A method for fabricating a radiation-resistant fault-tolerant trigger
By constructing a radiation-hardened fault-tolerant trigger based on D flip-flops, XOR gates, and selectors, the problems of area overhead and performance degradation in the prior art are solved, and the correct output of the trigger and efficient radiation resistance are achieved in a radiation environment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2021-02-22
- Publication Date
- 2026-05-26
AI Technical Summary
Existing radiation-hardened trigger design methods suffer from significant area overhead and performance degradation, especially triple-modulus redundancy and error-correcting code methods, which are difficult to effectively resist single-event transient pulse errors caused by radiation.
A radiation-resistant fault-tolerant trigger is constructed using three traditional D flip-flops, one XOR gate, one 2-to-1 selector, and two delay circuits. By using delay comparison and the selector to output correct data, the correct value is ensured to be output under radiation pulses.
It achieves correct output values of triggers in radiated environments, reduces area overhead and power consumption, and improves radiation resistance, which is superior to traditional triple redundancy schemes.
Smart Images
Figure CN114978116B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology and relates to a method for fabricating a radiation-hardened fault-tolerant trigger, specifically a circuit design method for a radiation-hardened fault-tolerant trigger based on a D flip-flop, an XOR gate, a selector, and a delay circuit. Background Technology
[0002] The prior art discloses that as the process size decreases, integrated circuits in chips are increasingly susceptible to errors caused by heavy particle or proton radiation in high space or near-Earth space. If the radiation occurs at the circuit node, it may cause a single-event transient pulse, which changes the logic state of the circuit node. The error value caused by the single-event transient pulse is transmitted to the memory and may be captured and stored. Therefore, the single-event transient pulse will change the logic state of the circuit node and may cause circuit function errors [1]. Therefore, it is necessary to propose a circuit design method that resists radiation.
[0003] The circuit design methods for radiation-hardened triggers mainly include multi-mode redundancy, error correction codes, and radiation-hardened memory cells. Multi-mode redundancy is represented by triple mode redundancy technology [2], which uses redundant circuit modules and majority voting circuits to shield the output of error circuit modules. Practice shows that this method will bring a large area overhead. Error correction code is represented by Hamming code [3], which locates the position of error bits by calculating the check value of the code. Radiation-hardened memory cell is represented by double interlocked memory cell [4], which adds extra transistors and intertwined interconnects on the basis of the basic memory cell structure to enhance the radiation resistance of sensitive nodes. Practice shows that both error correction codes and radiation-hardened memory cells will bring a large area overhead and reduce circuit performance.
[0004] Based on the current state of the technology, the inventors of this application intend to provide a method for preparing a radiation-hardened fault-tolerant trigger, and in particular a circuit design method for a radiation-hardened fault-tolerant trigger based on a D flip-flop, an XOR gate, a selector, and a delay circuit.
[0005] The following references are related to this invention:
[0006] [1]Baumann R.Soft Errors in Advanced Computer Systems[J],IEEETransactions on Device and Materials Reliability,2005,22(3),pp.258-266
[0007] [2]Oliveira R., Jagirdar A., Chakraborty TJ: A TMR Scheme for SEUMitigation in Scan Flip-Flops[C], in International Symposium onQualityElectronic Design,2007,pp.905–910
[0008] [3]Tausch HJSimplified Birthday Statistics and Hamming EDAC[J], IEEETransactions on Nuclear Science, 2009, 56(2), pp.474–478
[0009] [4]Calin T., Nicolaidis M., Velazco R.Upset hardened memory design for submicron CMOS technology[J], IEEE Transactions on Nuclear Science, 1996, 43(6), pp.2874–2878
[0010] [5] S. Yang. Logic Synthesis and Optimization Benchmarks User Guide, Research Triangle Park, NC: Microelectronics Center of North Carolina (MCNC), 1991. Summary of the Invention
[0011] The purpose of this invention is to address the current state of technology in the field of integrated circuits by providing a method for fabricating a radiation-hardened fault-tolerant trigger, and more particularly a circuit design method for a radiation-hardened fault-tolerant trigger based on a D flip-flop, an XOR gate, a selector, and a delay circuit.
[0012] The method for fabricating a radiation-hardened fault-tolerant trigger according to the present invention includes: constructing a radiation-hardened fault-tolerant trigger using three conventional D triggers, an XOR gate, a 2-to-1 selector, and two delay circuits; simultaneously writing input data to a primary D trigger and a backup D trigger; writing the input data to a third D trigger after a specified delay by the delay circuit, and then comparing it with the data stored in the primary D trigger; if they are the same, it indicates that the data stored in the primary D trigger is correct, and the 2-to-1 selector selects the data stored in the primary D trigger as the output data; if they are different, it indicates that the data stored in the primary D trigger is incorrect, and the 2-to-1 selector selects the data stored in the backup D trigger as the output data.
[0013] Specifically, the present invention comprises two steps, which are described in detail below.
[0014] Step 1: According to Figure 1 The circuit structure shown is designed using traditional integrated circuit design methods to create a radiation-resistant fault-tolerant trigger circuit.
[0015] according to Figure 1 Given the circuit structure shown, design a radiation-resistant fault-tolerant trigger circuit. Figure 1 It includes D flip-flops A1, A2, and A3, a 2-to-1 selector M1, an XOR gate B1, and a delay circuit composed of inverters. The D flip-flops A1, A2, and A3 are traditional storage circuit units. The data input port is I, the clock input port is C, the asynchronous reset port is R, and the data output port is O. When R is 1, O is 0; when R is 0, the I value is written to the D flip-flops on the rising edge of the clock input port C, and the O value is the data value stored in the D flip-flops. Figure 1 The D flip-flops A1, A2, and A3 are rising-edge clock triggers, but they can also be falling-edge clock triggers. The input ports of the 2-to-1 selector M1 are I1 and I2, the output port is O, and the selection port is S. In the 2-to-1 selector M1, when S is 0, O is the value of I1; when S is 1, O is the value of I2. An even number (e.g., 2, 4, 6, 8, ...) of inverters connected in series form a delay circuit. Figure 1The number of inverters connected in series in the delay circuit is 2, but it can also be other even numbers, such as 4, 6, 8, etc. The number of inverters connected in series in the delay circuit should ensure that the delay generated by these inverters is greater than the duration of the radiation pulse, so that the output port OUT of the radiation-hardened fault-tolerant trigger of this invention maintains the correct value. The data input port IN of the radiation-hardened fault-tolerant trigger is connected to the input port I of D flip-flops A1 and A2, and the delay circuit formed by connecting inverters in series is connected to the input port I of D flip-flop A3. The clock input port CLK of the radiation-hardened fault-tolerant trigger is connected to the clock input port C of D flip-flops A1 and A2, and the delay circuit formed by connecting inverters in series is connected to the clock input port C of D flip-flop A3. The asynchronous reset port RST of the radiation-hardened fault-tolerant trigger is connected to the asynchronous reset port R of D flip-flops A1, A2, and A3. The output port OUT of the radiation-hardened fault-tolerant trigger is connected to the output port O of the 2-to-1 selector M1.
[0016] Step 2: For Figure 1 Configure the asynchronous reset port RST of the radiation-resistant fault-tolerant trigger.
[0017] First, the asynchronous reset port RST value of the radiation-resistant fault-tolerant trigger of the present invention is set to 1, and the D flip-flops A1, A2, and A3 are asynchronously cleared. Then the selection port S value of the 2-to-1 selector M1 is 0, so the output port OUT of the radiation-resistant fault-tolerant trigger outputs the data stored in the D flip-flop A1.
[0018] Then, the asynchronous reset port RST value of the radiation-hardened fault-tolerant trigger of the present invention is set to 0. The value of the data input port IN is written to D flip-flops A1 and A2 on the rising edge of the clock input port CLK signal. The rising edges of IN and CLK signals are delayed by a delay circuit composed of inverters connected in series before being written to D flip-flop A3. The value stored in D flip-flop A1 and the value stored in D flip-flop A3 are compared through an XOR gate B1. If the output value of XOR gate B1 is 0, it indicates that the value stored in D flip-flop A1 is correct. The 2-to-1 selector M1 selects the value stored in D flip-flop A1, and the output port OUT of the radiation-hardened fault-tolerant trigger outputs the correct value. In the case where a radiation pulse can only cause an error in the value stored in one D flip-flop, if the output value of XOR gate B1 is 1, it indicates that the value stored in D flip-flop A1 is incorrect due to radiation. The 2-to-1 selector M1 selects the correct value stored in D flip-flop A2, and the output port OUT of the radiation-hardened fault-tolerant trigger still outputs the correct value. If a radiation pulse can only cause an error in the value stored in one D flip-flop, and the value stored in D flip-flop A2 becomes incorrect due to radiation, then because XOR gate B1 compares the value stored in D flip-flop A1 with the value stored in D flip-flop A3, and is independent of D flip-flop A2, the output port O of XOR gate B1 remains 0. The 2-to-1 selector M1 selects the value stored in D flip-flop A1, and the output port OUT of the radiation-hardened fault-tolerant flip-flop still outputs the correct value. Conversely, if a radiation pulse can only cause an error in the value stored in one D flip-flop, and the value stored in D flip-flop A3 becomes incorrect due to radiation, then the output port O of XOR gate B1 remains 1. The 2-to-1 selector M1 selects the correct value stored in D flip-flop A2, and the output port OUT of the radiation-hardened fault-tolerant flip-flop still outputs the correct value. In summary, when a radiation pulse can only cause an error in the value stored in one D flip-flop, regardless of which of D flip-flops A1, A2, or A3 becomes incorrect due to radiation, the output port OUT of the radiation-hardened fault-tolerant flip-flop will always output the correct value.
[0019] The present invention has the following advantages:
[0020] The present invention proposes a radiation-resistant fault-tolerant trigger circuit consisting of three conventional D flip-flops, an XOR gate, a 2-to-1 selector, and two delay circuits. Regardless of which of the D flip-flops causes the stored data to be incorrect due to radiation, the radiation-resistant fault-tolerant trigger circuit can still output the correct value. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of the radiation-resistant fault-tolerant trigger circuit of the present invention. Detailed Implementation
[0022] Example 1
[0023] Test experiments and results:
[0024] In the experiment, six reference test circuits bigkey,dsip,S38417,S13207.1,S15850.1,S38584.1[5] without radiation resistance were first implemented using the traditional standard circuit design method. Then, these reference test circuits were implemented using the triple redundancy scheme[2] and the present invention respectively, so that they had radiation resistance. The reference test circuits implemented by different schemes were randomly irradiated 1000 times. The number of errors, area and power consumption averages obtained from the test are shown in Table 1. The area and power consumption in Table 1 have been normalized and their values are multiples of the area and power consumption of the circuit implemented by the scheme of the present invention. The test results show that the present invention has the fewest errors, so it has the strongest radiation resistance. The area and power consumption of the present invention are close to the area and power consumption of the traditional triple redundancy radiation resistance scheme.
[0025] Table 1 Comparison of Area, Power Consumption, and Radiation Resistance
[0026] plan Number of errors area Power consumption Traditional standard design methods lacking radiation resistance 253 0.35 0.31 The radiation-resistant design method of the present invention 1 1 1 Triple redundancy radiation-hardened design method 4 1.14 1.09
Claims
1. A preparation method of a radiation-resistant and fault-tolerant flip-flop, characterized in that, The method is a circuit design method for a radiation-hardened fault-tolerant flip-flop based on D flip-flops, exclusive-OR gates, selectors, and delay circuits, and it includes the following steps: Step 1: Design a radiation-hardened fault-tolerant flip-flop circuit using traditional integrated circuit design methods; Step 2: Set the asynchronous reset port RST of the radiation-hardened fault-tolerant flip-flop; In Step 1, design a radiation-hardened fault-tolerant flip-flop circuit, which includes D flip-flops A1, A2, A3, a 2-to-1 selector M1, an exclusive-OR gate B1, and a delay circuit composed of inverters; the number of inverters connected in series in the delay circuit should ensure that the delay generated by the inverters is greater than the duration of the radiation pulse, so that the output port OUT of the radiation-hardened fault-tolerant flip-flop maintains the correct value; The data input port IN of the radiation-hardened fault-tolerant flip-flop is connected to the input port I of D flip-flops A1 and A2, and is connected to the input port I of D flip-flop A3 through a delay circuit composed of inverters connected in series; The clock input port CLK of the radiation-hardened fault-tolerant flip-flop is connected to the clock input port C of D flip-flops A1 and A2, and is connected to the clock input port C of D flip-flop A3 through a delay circuit composed of inverters connected in series; The asynchronous reset port RST of the radiation-hardened fault-tolerant flip-flop is connected to the asynchronous reset port R of D flip-flops A1, A2, and A3; The output port OUT of the radiation-hardened fault-tolerant flip-flop is connected to the output port O of the 2-to-1 selector M1; in the radiation-hardened fault-tolerant flip-flop circuit, the output port O of D flip-flop A1 is connected to the input port I1 of the 2-to-1 selector M1 and is connected to the input port I1 of the exclusive-OR gate B1; the output port O of D flip-flop A2 is connected to the input port I2 of the 2-to-1 selector M1; the output port 0 of D flip-flop A3 is connected to the input port I2 of the exclusive-OR gate B1; the output port O of the exclusive-OR gate B1 is connected to the input port S of the 2-to-1 selector M1; Step 2 includes: First, set the value of the asynchronous reset port RST of the radiation-hardened fault-tolerant flip-flop to 1, and asynchronously clear D flip-flops A1, A2, and A3, then the value of the selection port S of the 2-to-1 selector M1 is 0, so that the output port OUT of the radiation-hardened fault-tolerant flip-flop outputs the data stored in D flip-flop A1; Then, set the value of the asynchronous reset port RST of the radiation-hardened fault-tolerant flip-flop to 0, then the value of the data input port IN is written into D flip-flops A1 and A2 at the rising edge of the clock input port CLK signal; after the IN value and the rising edge of the CLK signal are delayed by a delay circuit composed of inverters connected in series, they are written into D flip-flop A3; Compare the value stored in D flip-flop A1 with the value stored in D flip-flop A3 through the exclusive-OR gate B1. If the value of the output port of the exclusive-OR gate B1 is 0, it means that the value stored in D flip-flop A1 is correct, and the 2-to-1 selector M1 selects the value stored in D flip-flop A1, and the output port OUT of the radiation-hardened fault-tolerant flip-flop outputs the correct value; When a radiation pulse can only cause an error in the value stored in one D flip - flop, if the value at the output port of the exclusive - OR gate B1 is 1, it indicates that the value stored in the D flip - flop A1 has an error due to radiation. The 2 - to - 1 selector M1 selects the correct value stored in the D flip - flop A2, and the output port OUT of the radiation - resistant fault - tolerant flip - flop still outputs the correct value. When a radiation pulse can only cause an error in the value stored in one D flip - flop, if the value stored in the D flip - flop A2 has an error due to radiation, since the exclusive - OR gate B1 compares the value stored in the D flip - flop A1 with the value stored in the D flip - flop A3 and has nothing to do with the D flip - flop A2, the value at the output port O of the exclusive - OR gate B1 remains 0. The 2 - to - 1 selector M1 selects the value stored in the D flip - flop A1, and the output port OUT of the radiation - resistant fault - tolerant flip - flop still outputs the correct value. When a radiation pulse can only cause an error in the value stored in one D flip - flop, if the value stored in the D flip - flop A3 has an error due to radiation, the value at the output port O of the exclusive - OR gate B1 is 1. The 2 - to - 1 selector M1 selects the correct value stored in the D flip - flop A2, and the output port OUT of the radiation - resistant fault - tolerant flip - flop still outputs the correct value.
2. The method according to claim 1, wherein When a radiation pulse can only cause an error in the value stored in one D flip - flop, no matter which one of the D flip - flops A1, A2, and A3 has an error in the stored data due to radiation, the output port OUT of the radiation - resistant fault - tolerant flip - flop can output the correct value.