Clockless linear equalizer and equalization method based on clockless linear equalizer

Abstract

This disclosure provides a clockless linear equalizer and an equalization method based on the clockless linear equalizer. The clockless linear equalizer includes: a first equalization circuit, a second equalization circuit, a delay circuit, a first load resistor, and a second load resistor. The first equalization circuit includes a first transistor and a second transistor, whose control terminal receives a first differential voltage signal, and whose second terminals serve as a first output node and a second output node, respectively. The delay circuit delays the first differential voltage signal to generate a second differential voltage signal. The second equalization circuit includes a third transistor and a fourth transistor, whose control terminal receives the second differential voltage signal, and whose second terminals are connected to a second output node and a first output node, respectively. The first load resistor and the second load resistor are connected to the first output node and the second output node. This disclosure employs a clockless design and does not require advanced CMOS processes, effectively achieving the frequency response characteristics of a feedforward equalizer (FFE).

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a clockless linear equalizer and an equalization method based on the clockless linear equalizer. Background Technology

[0002] With the advancement of 5G / 6G commercialization and the construction of AI computing centers, data transmission is developing towards ultra-high speeds, and multi-level modulation methods such as PAM-4 and PAM-8 have become mainstream due to their high bandwidth utilization. However, high-speed multi-level signals are prone to problems such as high-frequency component attenuation, gain unevenness, and excessive group delay deviation during transmission due to factors such as channel frequency-selective attenuation, skin effect, and parasitic effects. This leads to issues like closed or distorted eye diagrams at the receiver, increased bit error rate, and severely impacts transmission quality. Feedforward equalizers (FFEs), as feedback-free linear equalization devices, achieve signal pre-shaping and distortion compensation through multi-tap delay-weighted summation, and are the core circuit for solving channel distortion.

[0003] Currently, existing FFEs are mainly divided into digital FFEs and traditional linear analog FFEs, neither of which can meet the comprehensive requirements of ultra-high-speed transmission for clockless operation, linear equalization, low power consumption, and high integration. Among them, digital FFEs rely on high-speed clocks to drive digital components to implement FFE taps, which brings problems such as high power consumption, high complexity, and large chip area; and with the continuous increase in signal rates, the high mask cost of advanced CMOS processes has also become a limiting factor for high-speed digital circuits.

[0004] Analog FFE eliminates the strong dependence on high-speed clocks, thus greatly simplifying the circuitry and eliminating the need for advanced CMOS processes to reduce the latency and chip area of ​​digital circuits. However, it still has several technical drawbacks: First, some architectures do not achieve a completely clockless design; the introduction of a low-speed reference clock not only introduces synchronization deviations but also increases additional power consumption. Second, mass production and debugging of multi-tap circuits is difficult, as delay lines typically occupy a large area, making it difficult to balance linear performance, power consumption, and chip area. Third, most architectures have high coupling between delay and weighting modules, making circuit debugging difficult, resulting in low chip integration and failing to meet the miniaturization requirements of ultra-high-speed transmission.

[0005] Analog continuous-time linear equalizers (CTLEs) have the advantages of compact size and low power consumption, but their disadvantage is that they cannot achieve high-order equalization. A typical RC emitter-degraded or source-degraded CTLE is functionally only approximated by an FFE with a post-cursor tap.

[0006] Therefore, to address the aforementioned technical problems, it is necessary to provide a clockless linear equalizer and an equalization method based on the clockless linear equalizer. Summary of the Invention

[0007] The purpose of this disclosure is to provide a clockless linear equalizer and an equalization method based on the clockless linear equalizer, which can adopt a clockless design and get rid of the dependence on advanced CMOS process, and achieve the equivalent frequency response characteristics of a four-tap feedforward equalizer.

[0008] To achieve the above objectives, a specific embodiment of this disclosure provides a clockless linear equalizer, comprising: a first equalization circuit, a second equalization circuit, a delay circuit, a first load resistor, and a second load resistor; the first equalization circuit includes a first transistor and a second transistor, the control terminals of the first transistor and the second transistor receiving a first differential voltage signal, the first terminals of the first transistor and the second transistor being indirectly connected to ground potential, the second terminal of the first transistor serving as a first output node, and the second terminal of the second transistor serving as a second output node; the delay circuit receives the first differential voltage signal and delays the first differential voltage signal to generate a second differential voltage signal; the second equalization circuit includes a third transistor and a fourth transistor, the control terminals of the third transistor and the fourth transistor receiving the second differential voltage signal, the first terminals of the third transistor and the fourth transistor being indirectly connected to ground potential, the second terminal of the third transistor being connected to the second output node, and the second terminal of the fourth transistor being connected to the first output node; the first load resistor is connected between the power supply voltage and the first output node, and the second load resistor is connected between the power supply voltage and the second output node.

[0009] In one or more embodiments of this disclosure, the first equalization circuit further includes a first current source and a second current source, the first current source being connected between a first terminal of the first transistor and ground potential, and the second current source being connected between a first terminal of the second transistor and ground potential.

[0010] In one or more embodiments of this disclosure, the second equalization circuit further includes a third current source and a fourth current source, the third current source being connected between the first terminal of the third transistor and ground potential, and the fourth current source being connected between the first terminal of the fourth transistor and ground potential.

[0011] In one or more embodiments of this disclosure, the first equalization circuit further includes a first variable resistor unit, a first terminal of which is connected to a first terminal of the first transistor, and a second terminal of which is connected to a first terminal of the second transistor.

[0012] In one or more embodiments of this disclosure, the second equalization circuit further includes a second variable resistor unit, the first end of which is connected to the first end of the third transistor, and the second end of which is connected to the first end of the fourth transistor.

[0013] In one or more embodiments of this disclosure, the first equalization circuit further includes a first variable capacitor unit, a first terminal of which is connected to a first terminal of the first transistor, and a second terminal of which is connected to a first terminal of the second transistor. The second equalization circuit further includes a second variable capacitor unit, a first terminal of which is connected to a first terminal of the third transistor, and a second terminal of which is connected to a first terminal of the fourth transistor.

[0014] In one or more embodiments of this disclosure, the delay circuit includes an RC low-pass filter, an LC low-pass filter, a combination of multiple LC low-pass filters, or a transmission line.

[0015] In one or more embodiments of this disclosure, the delay circuit includes a first inductor, a second inductor, a first capacitor, a second capacitor, and a damping resistor. A first terminal of the first inductor and a first terminal of the second inductor receive a first differential voltage signal. A second terminal of the first inductor is connected to a first terminal of the first capacitor and a first terminal of the damping resistor. A second terminal of the second inductor is connected to a first terminal of the second capacitor and a second terminal of the damping resistor. The second terminals of the first capacitor and the second capacitor are connected to ground potential. The second terminals of the first inductor and the second terminal of the second inductor generate a second differential voltage signal.

[0016] In one or more embodiments of this disclosure, the first equalization circuit further includes a tap adjustment unit for controlling the output current of the first equalization circuit based on a third differential voltage signal to adjust the weight of the front vernier tap of the clockless linear equalizer.

[0017] In one or more embodiments of this disclosure, the tap adjustment unit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the first terminal of the fifth transistor is connected to the second terminal of the first transistor, and the second terminal is connected to a first output node; the first terminal of the sixth transistor is connected to the second terminal of the first transistor, and the second terminal is connected to a power supply voltage; the control terminals of the fifth and sixth transistors receive a third differential voltage signal; the first terminal of the seventh transistor is connected to the second terminal of the second transistor, and the second terminal is connected to a second output node; the first terminal of the eighth transistor is connected to the second terminal of the second transistor, and the second terminal is connected to a power supply voltage; the control terminals of the seventh and eighth transistors receive a third differential voltage signal.

[0018] In one or more embodiments of this disclosure, the second equalization circuit further includes a bias matching unit, which includes a ninth transistor and a tenth transistor. The first terminal of the ninth transistor is connected to the second terminal of the third transistor, and the second terminal is connected to the second output node. The first terminal of the tenth transistor is connected to the second terminal of the fourth transistor, and the second terminal is connected to the first output node. The control terminals of the ninth transistor and the tenth transistor receive a first voltage signal to make the bias point of the second equalization circuit consistent with the bias point of the first equalization circuit.

[0019] This disclosure also provides an equalization method based on a clockless linear equalizer, including:

[0020] The linearity required by the clockless linear equalizer is controlled by adjusting the resistance value of the second variable resistor unit, wherein the linearity is positively correlated with the resistance value of the second variable resistor unit; the maximum value of the second variable capacitor unit is designed according to the weight of the rear vernier tap required by the clockless linear equalizer, wherein the capacitance value of the second variable capacitor unit is positively correlated with the absolute value of the weight of the rear vernier tap; the tap spacing of the clockless linear equalizer is controlled by adjusting the delay time of the delay unit; the resistance value of the first variable resistor unit is designed according to the weight of the second front vernier tap required by the clockless linear equalizer, wherein the resistance value of the first variable resistor unit is positively correlated with the absolute value of the weight of the second front vernier tap; the high-frequency gain of the first equalization circuit is controlled by adjusting the capacitance value of the first variable capacitor; the weight of the front vernier tap of the clockless linear equalizer is controlled by adjusting the third differential voltage signal, wherein the voltage value of the third differential voltage signal is positively correlated with the absolute value of the weight of the front vernier tap; the ratio between the resistance value of the first load resistor and the resistance value of the second variable resistor unit is adjusted according to the gain required by the clockless linear equalizer, wherein the resistance values ​​of the first load resistor and the second load resistor are equal.

[0021] Compared with existing technologies, the clockless linear equalizer and the equalization method based on the clockless linear equalizer disclosed herein achieve the equivalent frequency response characteristics of a feedforward equalizer by combining a first equalization circuit, a second equalization circuit, and a single delay circuit. This can meet the requirements of ultra-high-speed multi-level transmission for clockless, linear equalization, low power consumption, high integration, and stable delay. This disclosure only requires the design of one delay circuit and does not require multiple sets of parallel amplification units, which greatly reduces the circuit area. In the equalization method disclosed herein, weight adjustment does not affect linearity and bandwidth, and high and low frequency equalization can be independently decoupled and controlled. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a circuit diagram of the clockless linear equalizer in Embodiment 1 of this disclosure;

[0024] Figure 2 This is a circuit diagram of a delay circuit in one embodiment of the present disclosure;

[0025] Figure 3 This is a circuit diagram of the clockless linear equalizer in Embodiment 2 of this disclosure;

[0026] Figure 4 This is a comparison chart of the equalization parameters and expected equalization results of the clockless linear equalizer in Embodiment 3 of this disclosure;

[0027] Figure 5 This is a simulation diagram of the gain and group delay characteristics of the ideal FFE in Embodiment 4 of this disclosure;

[0028] Figure 6 This is a simulation diagram of the gain and group delay characteristics of the clockless linear equalizer in Embodiment 4 of this disclosure;

[0029] Figure 7 This is a schematic eye diagram of an ideal FFE in Embodiment 4 of this disclosure;

[0030] Figure 8 This is a schematic eye diagram of the clockless linear equalizer in Embodiment 4 of this disclosure;

[0031] Figure 9 This is a simulation diagram comparing the gain and group delay characteristics of unequalized, ideal FFE and clockless linear equalizer in Embodiment 4 of this disclosure;

[0032] Figure 10 This is a schematic diagram comparing the eye diagrams of an unequalized, ideal FFE, and clockless linear equalizer in Embodiment 4 of this disclosure. Detailed Implementation

[0033] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0034] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0035] It should be noted that when an element is described as being "fixed to" another element, it can be directly attached to the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. In the embodiments shown in this disclosure, directional representations such as up, down, left, right, front, and back are relative and are used to explain the relative structure and movement of different components in this disclosure. These representations are appropriate when the components are in the positions shown in the figures. However, if the description of the component positions changes, then these representations are considered to change accordingly.

[0036] As mentioned in the background, digital FFE suffers from problems such as high-speed clock dependence, power consumption, and limited integration. Traditional linear analog FFE, on the other hand, faces challenges such as incomplete clocklessness, difficulty in implementing linear modules, and low integration. Neither can simultaneously meet the core technical requirements of ultra-high-speed multilevel transmission for clocklessness, linear equalization, low power consumption, high integration, and stable latency. Conventional CTLE, limited by its own equalization capabilities, struggles to achieve high-order equalization effects.

[0037] Based on the above understanding, this disclosure provides a clockless linear equalizer. The technical idea is to construct a CTLE+analog FFE fusion architecture, adopt a parallel minimalist topology with dual CTLE units and a single delay circuit, and realize the FFE tap function based on the frequency response characteristics of CTLE. Only one delay circuit is needed to achieve the equivalent four-tap equalization effect.

[0038] The present disclosure will be further described below with reference to specific embodiments.

[0039] Example 1:

[0040] like Figure 1 As shown, the clockless linear equalizer in this embodiment includes: a first equalization circuit 10, a second equalization circuit 20, a delay circuit 30, and a load circuit 40. The load circuit 40 includes a first load resistor R. L1 Second load resistor R L2 .

[0041] The first equalization circuit 10 includes a first transistor Q1, a second transistor Q2, and a first variable resistor unit R. PRE First variable capacitor unit C PRE First current source IBIASPRE1 Second current source IBIAS PRE2 .

[0042] The control terminals of the first transistor Q1 and the second transistor Q2 receive the first differential voltage signal INP-INN. The first terminal of the first transistor Q1 and the first terminal of the second transistor Q2 are indirectly connected to the ground potential GND. The second terminal of the first transistor Q1 serves as the first output node OUTP, and the second terminal of the second transistor Q2 serves as the second output node OUTN.

[0043] Furthermore, both the first transistor Q1 and the second transistor Q2 can be either NPN transistors or N-type metal-oxide-semiconductor field-effect transistors. When the first transistor Q1 and the second transistor Q2 are NPN transistors, the control terminal of the first transistor Q1 and the second transistor Q2 is the base, the first terminal is the emitter, and the second terminal is the collector. When the first transistor Q1 and the second transistor Q2 are N-type metal-oxide-semiconductor field-effect transistors, the control terminal of the first transistor Q1 and the second transistor Q2 is the gate, the first terminal is the source, and the second terminal is the drain.

[0044] First variable resistor unit R PRE The first terminal is connected to the first terminal of the first transistor Q1, and the second terminal is connected to the first terminal of the second transistor Q2. Specifically, the first variable resistor unit R PRE It can be implemented by voltage-controlled MOSFET devices or by digitally controlled resistor arrays. Variable resistors are well known in the prior art and will not be described in detail here. Any known or unknown variable resistors can be used without restriction.

[0045] First variable capacitor unit C PRE The first terminal is connected to the first terminal of the first transistor Q1, and the second terminal is connected to the first terminal of the second transistor Q2. Specifically, the first variable capacitor unit C PRE This can be achieved using a digitally controlled capacitor array. Variable capacitors are well known in the prior art and will not be described in detail here. Any known or unknown variable capacitors may be used without restriction.

[0046] First current source IBIAS PRE1 The second current source IBIAS is connected between the first terminal of the first transistor Q1 and ground potential. PRE2 It is connected between the first terminal of the second transistor Q2 and ground potential. First current source IBIAS PRE1 Second current source IBIAS PRE2 They are used to provide corresponding bias currents for the first transistor Q1 and the second transistor Q2, respectively, and the bias current values ​​provided by the two transistors are equal.

[0047] The delay circuit 30 receives the first differential voltage signal INP-INN and delays the first differential voltage signal INP-INN to generate the second differential voltage signal INP_MAIN-INN_MAIN.

[0048] Furthermore, the delay circuit 30 can be implemented by an RC low-pass filter (RC-LPF), an LC low-pass filter (LC-LPF), a combination of multiple LC low-pass filters (i.e., a stepped low-pass filter LC-LADDER-LPF), or a transmission line.

[0049] Please refer to Figure 2 As shown, exemplarily, the delay circuit includes a first inductor L1, a second inductor L2, a first capacitor C1, a second capacitor C2, and a damping resistor R. DAMP The first terminal of the first inductor L1 and the first terminal of the second inductor L2 respectively receive the first differential voltage signal INP-INN. The second terminal of the first inductor L1 is connected to the first terminal of the first capacitor C1 and the damping resistor R. DAMP The first terminal is connected, the second terminal of the second inductor L2 is connected to the first terminal of the second capacitor C2 and the damping resistor R. DAMP The second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 are connected to ground potential. The second terminals of the first inductor L1 and the second terminals of the second inductor L2 generate the second differential voltage signal INP_MAIN-INN_MAIN.

[0050] Under the same delay conditions, the bandwidth achievable by filters varies. This embodiment selects an LC-LPF as the delay circuit to meet the bandwidth requirement of over 50 Gbaud per channel without occupying excessive circuit area.

[0051] The second equalization circuit 20 includes a third transistor Q3, a fourth transistor Q4, and a second variable resistor unit R. MAIN Second variable capacitor unit C MAIN Third current source IBIAS MAIN1 and the fourth current source IBIAS MAIN2 .

[0052] The control terminals of the third transistor Q3 and the fourth transistor Q4 receive the second differential voltage signal INP_MAIN-INN_MAIN. The first terminal of the third transistor Q3 and the first terminal of the fourth transistor Q4 are indirectly connected to ground potential. The second terminal of the third transistor Q3 is connected to the second output node OUTN, and the second terminal of the fourth transistor Q4 is connected to the first output node OUTP.

[0053] The third transistor Q3 and the fourth transistor Q4 can both be NPN transistors or both be N-type metal-oxide-semiconductor field-effect transistors.

[0054] Second variable resistor unit R MAIN The first terminal is connected to the first terminal of the third transistor Q3, and the second terminal is connected to the first terminal of the fourth transistor Q4. The second variable resistor unit R... MAIN It can be implemented using voltage-controlled MOSFET devices or digitally controlled resistor arrays.

[0055] Second variable capacitor unit C MAIN The second variable capacitor unit C MAIN The first terminal is connected to the first terminal of the third transistor Q3, and the second terminal is connected to the first terminal of the fourth transistor Q4. The second variable capacitor unit C... MAIN This can be achieved using a digitally controlled capacitor array.

[0056] Third current source IBIAS MAIN1 The fourth current source IBIAS is connected between the first terminal of the third transistor Q3 and ground potential. MAIN2 It is connected between the first terminal of the fourth transistor Q4 and ground potential. The third current source IBIAS MAIN1 and the fourth current source IBIAS MAIN2 They are used to provide the corresponding bias currents, and the bias current values ​​provided by the two are equal.

[0057] First load resistor R L1 The second load resistor R is connected between the power supply voltage VDD and the first output node OUTP. L2 It is connected between the power supply voltage VDD and the second output node OUTN.

[0058] In this embodiment, both the first equalization circuit 10 and the second equalization circuit 20 are emitter-degraded CTLE circuits and employ a differential structure. In other alternative embodiments, the first equalization circuit 10 and the second equalization circuit 20 can also employ a single-ended structure. Both the first equalization circuit 10 and the second equalization circuit 20 output current, and the first load resistor R... L1 Second load resistor R L2 Based on the output current of the first equalization circuit 10 and the second equalization circuit 20, current-voltage conversion is completed at the first output node OUTP and the second output node OUTN to generate the corresponding output voltage.

[0059] This disclosure achieves the equivalent tap function of a feedforward equalizer through the first equalization circuit 10 and the second equalization circuit 20 of the CTLE structure, and only requires one delay circuit to achieve the equivalent frequency domain response characteristics of a 4-tap feedforward equalizer (including a main tap, one back vernier tap and two front vernier taps).

[0060] Specifically, the tap coefficient polarity of the four taps is not adjustable. The main tap MAIN has a positive tap coefficient polarity and does not directly increase or decrease bandwidth. The second front vernier tap PRE2 (i.e., the second-order front vernier tap) has a positive tap coefficient polarity and is used to introduce phase lead and amplitude suppression in the frequency domain, reducing the effective bandwidth of the system and offsetting the leading trailing ISI at more distant points. The first front vernier tap PRE1 (i.e., the first-order front vernier tap) has a negative tap coefficient polarity and is used to increase the effective bandwidth of the system. The rear vernier tap POST1 has a negative tap coefficient polarity and cancels the backward trailing of the main signal in the frequency domain, effectively increasing the effective utilization bandwidth of high-frequency components.

[0061] In this embodiment, the second variable resistor R can be adjusted according to the linearity requirements of the equalizer. MAIN The resistance value, linearity and the second variable resistor unit R MAIN The resistance value is positively correlated, meaning the linearity increases with the resistance of the second variable resistor unit R. MAIN The resistance increases as the resistance increases.

[0062] Design the second variable capacitor C based on the weight of the post-cursor tap POST1 required by the equalizer. MAIN The maximum value, where the second variable capacitor C MAIN The capacitance value is positively correlated with the absolute value of the weight of the subsequent vernier tap POST1. This is because the second equalization circuit 20 operates at gm / C. MAIN There exists a pole that limits the system bandwidth of the equalizer, and the transconductance gm of the third transistor Q3 and the fourth transistor Q4 is proportional to the bias current. Therefore, it is necessary to design the IBIAS to... MAIN1 / C MAIN The minimum value is greater than the system bandwidth required by a clockless linear equalizer.

[0063] Based on the required tap spacing (TAP) of the system, the delay time τ of the delay circuit is designed. It can be understood that the TAP spacing determines the compensation capability: the smaller the delay time τ, the stronger the high-frequency compensation capability and the weaker the low-frequency compensation capability of the first front vernier tap PRE1; conversely, the larger the delay time τ, the stronger the low-frequency compensation capability and the weaker the high-frequency compensation capability of the first front vernier tap PRE1.

[0064] Based on the weight of the second front vernier tap PRE2 required by the clockless linear equalizer, design the first variable resistor unit R. PRE The resistance value is affected by the low-frequency gain of the first equalization circuit 10 being controlled by the first variable resistor unit R. PRE Degradation, first variable resistor unit R PRE The resistance value is positively correlated with the absolute value of the weight of the second front vernier tap PRE2.

[0065] By adjusting the first variable capacitor C PRE The value of is used to give the first equalization circuit 10 a certain gain at high frequencies. Time alignment is then achieved through the delay circuit 30, effectively realizing the equalization compensation effect of the first front vernier tap PRE1 in FFE. Simultaneously, IBIAS is designed. PRE1 / C PRE The minimum value is greater than the system bandwidth required by a clockless linear equalizer.

[0066] Based on the gain required by the clockless linear equalizer, adjust the ratio (i.e., R) between the resistance value of the first load resistor and the resistance value of the second variable resistor unit RMAIN. L1 / R MAIN (where the resistance values ​​of the first load resistor and the second load resistor are equal).

[0067] As described above, the equalization function in this disclosure is deeply coupled with the active characteristics of CTLE: this disclosure achieves post-vernier tap equalization through the second equalization circuit 20, and achieves pre-vernier tap equalization through the first equalization circuit 10 combined with a delay circuit. The tap weights are directly adjusted based on the capacitance parameters, resistance parameters, and bias current of the first equalization circuit 10 and the second equalization circuit 20. Furthermore, the linearity, post-vernier equalization, pre-vernier equalization, bandwidth, and gain in this disclosure can be adjusted independently step by step, making mass production debugging less difficult.

[0068] In existing solutions, the CTLE pre-equalization and FFE post-equalization need to be designed as serial cascaded. This disclosure achieves the equivalent function of the FFE pre- and post-cursor taps by using two parallel CTLEs. In addition, this disclosure significantly reduces the number of delay circuits by adopting a modular combination of equalization circuits and delay circuits, thus solving the problems of large board area and high module coupling of traditional analog FFE delay lines.

[0069] Example 2:

[0070] Please refer to Figure 3 As shown, this embodiment differs from Embodiment 1 in that the first equalization circuit 10 further includes a tap adjustment unit 11, and the second equalization circuit 20 further includes a bias matching unit 21. The tap adjustment unit 11 controls the output current of the first equalization circuit 10 based on the third differential voltage signal VCP-VCN to adjust the weight of the front vernier tap of the clockless linear equalizer. The bias matching unit 21 ensures that the bias point of the second equalization circuit 20 is consistent with the bias point of the first equalization circuit 10.

[0071] Specifically, the tap adjustment unit 11 includes a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8. The first terminal of the fifth transistor Q5 is connected to the second terminal of the first transistor Q1, and the second terminal is connected to the first output node OUTP. The first terminal of the sixth transistor Q6 is connected to the second terminal of the first transistor Q1, and the second terminal is connected to the power supply voltage VDD. The control terminals of the fifth transistor Q5 and the sixth transistor Q6 receive a third differential voltage signal VCP-VCN. The first terminal of the seventh transistor Q7 is connected to the second terminal of the second transistor Q2, and the second terminal is connected to the second output node OUTN. The first terminal of the eighth transistor Q8 is connected to the second terminal of the second transistor Q2, and the second terminal is connected to the power supply voltage VDD. The control terminals of the seventh transistor Q7 and the eighth transistor Q8 receive the third differential voltage signal VCP-VCN. The fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 are synchronously controlled.

[0072] The weights of the front vernier taps (including the first front vernier tap PRE1 and the second front vernier tap PRE2) of the clockless linear equalizer can be controlled by adjusting the voltage value of the third differential voltage signal VCP-VCN. The voltage value of the third differential voltage signal VCP-VCN is positively correlated with the absolute value of the weights of the front vernier taps.

[0073] The tap adjustment unit 11 adopts a CASCODE structure. It adjusts the output current of the first equalization circuit 10 through the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 of the differential pair. This achieves flexible control of the front vernier tap weight (which can also be understood as the tap coefficient), and the adjustment process does not change the internal bias operating point of the first equalization circuit. When the third differential voltage signal VCP-VCN increases, the output current of the first equalization circuit increases. At this time, the weight of the front vernier tap increases relative to the weight of the main vernier tap.

[0074] The bias matching unit 21 includes a ninth transistor Q9 and a tenth transistor Q10. The first terminal of the ninth transistor Q9 is connected to the second terminal of the third transistor Q3, and the second terminal is connected to the second output node OUTN. The first terminal of the tenth transistor Q10 is connected to the second terminal of the fourth transistor Q4, and the second terminal is connected to the first output node OUTP. The control terminals of the ninth transistor Q9 and the tenth transistor Q10 receive a first voltage signal VCAS to make the bias point of the second equalization circuit consistent with or close to the bias point of the first equalization circuit.

[0075] Example 3:

[0076] Please combine Figure 4As shown, this embodiment provides an equalization method based on a clockless linear equalizer, used in the clockless linear equalizer provided in Embodiment 1 or 2. The design parameters of the clockless linear equalizer are equivalent to the design results in the FFE domain and analog domain, thus effectively realizing the frequency domain response characteristics of a 4-tap feedforward equalizer. The equalization method specifically includes:

[0077] By adjusting the second variable resistor unit R MAIN The resistance value controls the linearity required by the clockless linear equalizer, where the linearity is related to the second variable resistor unit R. MAIN The resistance value is positively correlated.

[0078] Based on the weights of the back vernier taps required by the clockless linear equalizer, design the second variable capacitor unit C. MAIN The maximum value, where the second variable capacitor unit C MAIN The capacitance value is positively correlated with the absolute value of the weight of the subsequent vernier tap. Specifically, due to the second equalization circuit 20 at gm / C MAIN There exists a pole that limits the system bandwidth of the equalizer, and the transconductance gm of the third transistor Q3 and the fourth transistor Q4 is proportional to the bias current. Therefore, it is necessary to design the IBIAS to... MAIN1 / C MAIN The minimum value is greater than the system bandwidth required by a clockless linear equalizer.

[0079] The tap spacing of the clockless linear equalizer is controlled by adjusting the delay time of the delay unit. Specifically, the delay time τ of the delay circuit is designed according to the required tap spacing (TAP) of the system. It can be understood that the TAP spacing determines the compensation capability: the smaller the delay time τ, the stronger the high-frequency compensation capability and the weaker the low-frequency compensation capability of the first front vernier tap PRE1; conversely, the larger the delay time τ, the stronger the low-frequency compensation capability and the weaker the high-frequency compensation capability of the first front vernier tap PRE1.

[0080] Based on the weights of the second front vernier tap required by the clockless linear equalizer, design the first variable resistor unit R. PRE The resistance value, wherein the first variable resistor unit R PRE The resistance value is positively correlated with the absolute value of the weight of the second front vernier tap.

[0081] By adjusting the first variable capacitor C PRE The capacitance value controls the high-frequency gain of the first equalization circuit 10. Specifically, this is achieved by adjusting the first variable capacitor C. PRE The value of is used to give the first equalization circuit 10 a certain gain at high frequencies. Time alignment is then achieved through the delay circuit 30, effectively realizing the equalization compensation effect of the first front vernier tap PRE1 in FFE. Simultaneously, IBIAS is designed. PRE1 / C PRE The minimum value is greater than the system bandwidth required by a clockless linear equalizer.

[0082] The weight of the front vernier tap in the clockless linear equalizer is controlled by adjusting the third differential voltage signal VCP-VCN. The voltage value of the third differential voltage signal VCP-VCN is positively correlated with the absolute value of the weight of the front vernier tap. When the third differential voltage signal VCP-VCN increases, the output current of the first equalization circuit increases, and the weight of the front vernier tap increases relative to the weight of the main vernier tap.

[0083] Adjust the value of the first load resistor and the second variable resistor unit R according to the gain required by the clockless linear equalizer. MAIN The ratio between the resistance values, wherein the resistance values ​​of the first load resistor and the second load resistor are equal.

[0084] The equalization method disclosed herein is a decoupled parameter design method, in which linearity, back vernier equalization, front vernier equalization, bandwidth, and gain can be adjusted independently step by step, thus reducing the difficulty of mass production debugging.

[0085] Example 4:

[0086] This embodiment verifies through experimental simulation that the clockless linear equalizer and ideal FFE provided in this disclosure can reduce group delay variation and ultimately obtain a clear eye diagram while increasing the original system bandwidth.

[0087] This example is a comparison of equalization simulation under Global Foundries' 0.13um SiGe 8XP process, with simulation conditions including: 53Gbaud PAM4=106Gbps.

[0088] Please refer to Figure 5 and Figure 6 As shown, Figure 5 and Figure 6 Simulation diagrams show the gain and group delay characteristics of an ideal FFE and a clockless linear equalizer, respectively. Simulation settings: The fixed tap coefficients for the ideal FFE are PRE2=0.05, PRE1=-0.2, and MAIN=1. The variables are designed as the back vernier tap coefficients, controlling the back vernier tap coefficients to scan within the range of -0.3 to 0 (including w_post1=0, -0.1, -0.2, -0.3 in the diagram). Simultaneously, the remaining parameters of the clockless linear equalizer provided in this disclosure are tuned to approximately match the front vernier tap state of the FFE, using the second variable capacitor unit C... MAIN The capacitance value is used as a variable to control the second variable capacitor unit C. MAIN The capacitance value was scanned within the range of 0~200fF (C is included in the figure). MAIN =0fF, 50fF, 100fF, 200fF).

[0089] Figure 5 and Figure 6 In the diagram, p_light represents the link gain from input to output, gd_o represents the link group delay, and w_post1 represents the weight of the post-cursor tap; a negative value indicates a reduction in low-frequency components to increase bandwidth. Simulation trends show that the link gain and group delay characteristics can be improved by increasing the weight of the post-cursor tap or by increasing the weight of the second variable capacitor unit C. MAIN The capacitance value achieves similar frequency domain and time domain equalization effects.

[0090] Please refer to Figure 7 and Figure 8 As shown, the eye diagram comparison between the ideal FFE and the clockless linear equalizer also demonstrates the similarity of their equalization effects.

[0091] Please combine Figure 9 , Figure 10 As shown in Table 1, the simulation results of unequalized, ideal FFE and clockless linear equalizer show that the clockless linear equalizer and ideal FFE of this disclosure can reduce group delay variation and finally obtain a clear eye diagram while increasing the original system bandwidth.

[0092] Table 1

[0093]

[0094] As can be seen from the above technical solutions, this disclosure has the following beneficial effects:

[0095] Clockless design, adapted for ultra-high-speed transmission: It abandons the high-speed clock drive of traditional digital FFE and the low-speed reference clock configuration of some analog FFE, eliminates the clock synchronization deviation problem, and avoids the drawbacks of high power consumption and high complexity brought by ultra-high frequency clocks, which can meet the balanced requirements of ultra-high-speed data transmission of 50Gbaud and above.

[0096] The hybrid architecture enhances integration and commercial viability: Based on the modular combination of the first equalization circuit, the second equalization circuit, and the delay circuit, the number of delay circuits is significantly reduced, solving the problems of large board area and high module coupling of traditional analog FFE delay lines, realizing highly integrated circuit design and reducing the difficulty of chip mass production debugging.

[0097] Low power consumption and no need for advanced CMOS process: Inheriting the core advantages of CTLE's compact area and low power consumption, it also gets rid of the dependence on advanced CMOS process and avoids the problem of high photomask cost, achieving cost control of circuit design and production while ensuring balanced performance.

[0098] Advanced equalization capabilities for superior compensation: By integrating the technical advantages of CTLE and analog FFE, it breaks through the limitation of traditional CTLE only being able to achieve low-order equalization. It can effectively compensate for high-frequency attenuation, high-frequency gain unevenness, and group delay deviation in high-speed signal transmission, improve the eye diagram quality of the receiver signal, reduce the bit error rate, and adapt to the precise equalization requirements of multi-level modulation scenarios such as PAM-4 and PAM-8.

[0099] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0100] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A clockless linear equalizer, characterized in that, include: First equalization circuit, second equalization circuit, delay circuit, first load resistor and second load resistor; The first equalization circuit includes a first transistor and a second transistor. The control terminals of the first transistor and the second transistor receive a first differential voltage signal. The first terminals of the first transistor and the second transistor are indirectly connected to ground potential. The second terminal of the first transistor serves as a first output node, and the second terminal of the second transistor serves as a second output node. The delay circuit receives the first differential voltage signal and delays the first differential voltage signal to generate a second differential voltage signal; The second equalization circuit includes a third transistor and a fourth transistor. The control terminals of the third transistor and the fourth transistor receive the second differential voltage signal. The first terminals of the third transistor and the fourth transistor are indirectly connected to ground potential. The second terminal of the third transistor is connected to the second output node, and the second terminal of the fourth transistor is connected to the first output node. The first load resistor is connected between the power supply voltage and the first output node, and the second load resistor is connected between the power supply voltage and the second output node.

2. The clockless linear equalizer according to claim 1, characterized in that, The first equalization circuit further includes a first current source and a second current source, wherein the first current source is connected between a first terminal of the first transistor and ground potential, and the second current source is connected between a first terminal of the second transistor and ground potential; and / or, The second equalization circuit further includes a third current source and a fourth current source. The third current source is connected between the first terminal of the third transistor and the ground potential, and the fourth current source is connected between the first terminal of the fourth transistor and the ground potential.

3. The clockless linear equalizer according to claim 1, characterized in that, The first equalization circuit further includes a first variable resistor unit, wherein a first terminal of the first variable resistor unit is connected to a first terminal of the first transistor, and a second terminal is connected to a first terminal of the second transistor; and / or, The second equalization circuit further includes a second variable resistor unit, the first end of which is connected to the first end of the third transistor, and the second end of which is connected to the first end of the fourth transistor.

4. The clockless linear equalizer according to claim 1, characterized in that, The first equalization circuit further includes a first variable capacitor unit, wherein a first terminal of the first variable capacitor unit is connected to a first terminal of the first transistor, and a second terminal is connected to a first terminal of the second transistor; and / or, The second equalization circuit further includes a second variable capacitor unit, the first end of which is connected to the first end of the third transistor, and the second end of which is connected to the first end of the fourth transistor.

5. The clockless linear equalizer according to claim 1, characterized in that, The delay circuit includes an RC low-pass filter, an LC low-pass filter, a combination of multiple LC low-pass filters, or a transmission line.

6. The clockless linear equalizer according to claim 1, characterized in that, The delay circuit includes a first inductor, a second inductor, a first capacitor, a second capacitor, and a damping resistor. The first end of the first inductor and the first end of the second inductor receive a first differential voltage signal. The second end of the first inductor is connected to the first end of the first capacitor and the first end of the damping resistor. The second end of the second inductor is connected to the first end of the second capacitor and the second end of the damping resistor. The second ends of the first capacitor and the second capacitor are connected to ground potential. The second ends of the first inductor and the second end of the second inductor generate a second differential voltage signal.

7. The clockless linear equalizer according to claim 1, characterized in that, The first equalization circuit further includes a tap adjustment unit, which is used to control the output current of the first equalization circuit based on a third differential voltage signal to adjust the weight of the front vernier tap of the clockless linear equalizer.

8. The clockless linear equalizer according to claim 7, characterized in that, The tap adjustment unit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The first terminal of the fifth transistor is connected to the second terminal of the first transistor, and the second terminal is connected to the first output node. The first terminal of the sixth transistor is connected to the second terminal of the first transistor, and the second terminal is connected to the power supply voltage. The control terminals of the fifth transistor and the sixth transistor receive the third differential voltage signal. The first terminal of the seventh transistor is connected to the second terminal of the second transistor, and the second terminal is connected to the second output node. The first terminal of the eighth transistor is connected to the second terminal of the second transistor, and the second terminal is connected to the power supply voltage. The control terminals of the seventh transistor and the eighth transistor receive the third differential voltage signal.

9. The clockless linear equalizer according to claim 1, characterized in that, The second equalization circuit further includes a bias matching unit, which includes a ninth transistor and a tenth transistor. The first terminal of the ninth transistor is connected to the second terminal of the third transistor, and the second terminal is connected to the second output node. The first terminal of the tenth transistor is connected to the second terminal of the fourth transistor, and the second terminal is connected to the first output node. The control terminals of the ninth transistor and the tenth transistor receive a first voltage signal to make the bias point of the second equalization circuit consistent with the bias point of the first equalization circuit.

10. An equalization method based on a clockless linear equalizer, wherein the clockless linear equalizer is based on any one of claims 1 to 9, characterized in that, The equilibrium method includes: The linearity required by the clockless linear equalizer is controlled by adjusting the resistance value of the second variable resistor unit, wherein the linearity is positively correlated with the resistance value of the second variable resistor unit. Based on the weight of the back vernier tap required by the clockless linear equalizer, the maximum value of the second variable capacitor unit is designed, wherein the capacitance value of the second variable capacitor unit is positively correlated with the absolute value of the weight of the back vernier tap. The tap spacing of the clockless linear equalizer is controlled by adjusting the delay time of the delay unit. Based on the weight of the second front vernier tap required by the clockless linear equalizer, the resistance value of the first variable resistor unit is designed, wherein the resistance value of the first variable resistor unit is positively correlated with the absolute value of the weight of the second front vernier tap. The high-frequency gain of the first equalization circuit is controlled by adjusting the capacitance of the first variable capacitor. The weight of the front vernier tap of the clockless linear equalizer is controlled by adjusting the third differential voltage signal. The voltage value of the third differential voltage signal is positively correlated with the absolute value of the weight of the front vernier tap. The ratio between the resistance value of the first load resistor and the resistance value of the second variable resistor unit is adjusted according to the gain required by the clockless linear equalizer, wherein the resistance values ​​of the first load resistor and the second load resistor are equal.

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