Hybrid clamped dc-dc converter based on si-c indirect series connection

Abstract

The application discloses a hybrid clamp DC-DC converter based on SiC indirect series connection, comprising: a direct-current power supply, first and second bus capacitors, first, second, third and fourth switch tubes, a flying capacitor, first and second diodes, a load inductor, a load capacitor and a load resistor; the first and second diodes and the flying capacitor form a clamping circuit for clamping half bus voltage; the first, second, third and fourth switch tubes are connected in series to form a half-bridge circuit composed of low-voltage single-tube devices in series connection; the drain electrode of the first switch tube is connected to the positive electrode of the power supply, and the source electrode of the fourth switch tube is connected to the negative electrode of the power supply; the first bus capacitor and the flying capacitor form a first switch capacitor loop when the first switch tube is turned on; and the second bus capacitor and the flying capacitor form a second switch capacitor loop when the fourth switch tube is turned on. The application realizes simplified topology structure and effective modulation strategy, and solves the problem of poor adaptability of voltage balance analysis of existing converters under different quasi-two-level modulation strategies.

Description

Technical Field

[0001] This invention relates to the field of power electronics, and in particular to a hybrid clamping DC-DC converter based on SiC indirect series connection and its clamping circuit design method. Background Technology

[0002] With the continuous development of wide bandgap semiconductor technology, SiC devices can significantly improve the efficiency and power density of medium-voltage DC-DC converters in applications such as photovoltaic power generation, energy storage systems, and electric vehicle charging. However, high-voltage SiC MOSFETs have high manufacturing costs, and the mainstream applications in the market are currently 1.2kV and 1.7kV devices. To balance performance and cost, SiC series technology has become a feasible solution for medium-voltage hybrid clamped DC-DC converters. The core challenge is to achieve static and dynamic voltage balance between devices to avoid local device overvoltage breakdown.

[0003] Existing voltage equalization solutions are mainly divided into three categories: voltage equalization based on passive buffer circuits, voltage equalization based on gate drive, and voltage equalization based on topology. Among them, the topology-based voltage equalization solution can reduce the power and size of the clamping circuit by using quasi-two-level modulation, resulting in a simple structure and high engineering application value. In the topology-based voltage equalization solution based on quasi-two-level modulation, diode clamping topology and flying capacitor topology can achieve voltage equalization through simple clamping circuits, but an additional voltage control loop is required, increasing control complexity. Hybrid clamping DC-DC converters achieve voltage self-balancing without an additional voltage control loop by introducing a switched capacitor loop into the clamping circuit, but the analysis of its voltage balancing mechanism is currently limited to specific quasi-two-level modulation strategies, without providing general voltage balancing conditions, and cannot explain the voltage self-balancing situation under different quasi-two-level modulation strategies. Furthermore, to achieve voltage self-balancing under all operating conditions, two additional diodes are added to assist the hybrid clamping DC-DC converter in voltage self-balancing, which increases the system complexity.

[0004] For hybrid clamped DC-DC converters based on SiC indirect series connection, existing topologies suffer from complex structures due to the need for voltage self-balancing, and lack suitable voltage balancing modulation methods and a unified analysis system. This makes it difficult to ensure the stability of device voltage balance under diverse operating conditions, limiting the widespread application of such converters and SiC series technology in medium-voltage scenarios. Therefore, a simplified design scheme for hybrid clamped DC-DC converters based on SiC indirect series connection is needed, along with a quasi-two-level voltage balancing modulation method to improve the converter's operational stability and adaptability to various operating conditions. This provides a simple, efficient, and engineering-friendly design and modulation scheme for medium- and high-voltage SiC series converters. Summary of the Invention

[0005] The purpose of this invention is to provide a hybrid clamping DC-DC converter based on SiC indirect series and its clamping circuit design method, which simplifies the topology and provides an effective modulation strategy, solving the problem of poor adaptability of existing converter voltage balance analysis under different quasi-two-level modulation strategies.

[0006] To achieve the above objectives, the technical solution provided by this invention is as follows: a hybrid clamped DC-DC converter based on SiC indirect series connection, comprising: a DC power supply, a first bus capacitor, a second bus capacitor, a first switch, a second switch, a third switch, a fourth switch, a flying capacitor, a first diode, a second diode, a load inductor, a load capacitor, and a load resistor; the first diode, the second diode, and the flying capacitor form a clamping circuit for clamping the half-bus voltage; the first switch, the second switch, the third switch, and the fourth switch are connected end-to-end to form a half-bridge circuit composed of low-voltage single-transistor devices connected in series; the drain of the first switch is connected to the positive terminal of the DC power supply, and the source of the fourth switch is connected to the negative terminal of the DC power supply; the first bus capacitor and the flying capacitor are connected in series in the first... When one switching transistor is turned on, it forms the first switched capacitor circuit; when the fourth switching transistor is turned on, the second bus capacitor and the flying capacitor form the second switched capacitor circuit; the first bus capacitor and the second bus capacitor are connected in series to the positive and negative terminals of the DC power supply; the two ends of the flying capacitor are respectively connected to the source of the first switching transistor and the source of the third switching transistor; the anode of the first diode is connected to the first bus capacitor and the second bus capacitor, and its cathode is connected to the source of the first switching transistor; the cathode of the second diode is connected to the first bus capacitor and the second bus capacitor, and its anode is connected to the source of the third switching transistor; the load capacitor and the load resistor are connected in parallel, one end of which is connected to the negative terminal of the DC power supply, and the other end is connected to one end of the load inductor, and the other end of the load inductor is connected to the source of the second switching transistor.

[0007] Furthermore, the clamping circuit follows a lightweight design with low loss and small size under quasi-two-level voltage balance modulation; the selection of the first diode and the second diode is based on the rated voltage and rated current, with the rated voltage being 70% higher than the bus voltage and the rated current being 10% of the load current; the selection of the flying capacitor is based on the rated voltage and capacitance value, with the rated voltage being 70% higher than the bus voltage and the capacitance value being selected according to the voltage ripple requirements to ensure that the capacitor voltage ripple is less than 20%.

[0008] Furthermore, the quasi-two-level voltage balance modulation is based on the following principle: the driving voltages of the first and third switches are complementary, and the driving voltages of the second and fourth switches are complementary; in the intermediate mode where only the first or second switch is on, the intermediate level time of the output voltage of the half-bridge circuit is... , Limited to 200~400 nanoseconds, due to the extremely short intermediate mode time, the output voltage of the half-bridge circuit approximately exhibits the standard two-level output characteristics. The output voltage of the half-bridge circuit composed of low-voltage single-transistor devices in series is equivalent to the output voltage of the half-bridge circuit composed of high-voltage single-transistor devices, and is the same in form as the series circuit.

[0009] The quasi-two-level voltage balance modulation includes the following four modulation strategies:

[0010] The first modulation strategy is as follows: the first switch turns on ahead of the second switch, and the lead time is equal to the intermediate level time. The first switch leads the second switch to turn off, and the lead time is the intermediate level time. ;

[0011] The second modulation strategy is as follows: the second switch turns on before the first switch, and the lead time is equal to the intermediate level time. The first switch leads the second switch to turn off, and the lead time is the intermediate level time. ;

[0012] The third modulation strategy is as follows: the first switch turns on ahead of the second switch, and the lead time is equal to the intermediate level time. The second switch leads the first switch from being turned off by the intermediate level time. ;

[0013] The fourth modulation strategy is as follows: the second switch turns on ahead of the first switch, and the lead time is equal to the intermediate level time. The second switch leads the first switch from being turned off by the intermediate level time. .

[0014] Furthermore, for any modulation strategy, when the voltage of the hybrid clamped DC-DC converter is unbalanced, the intermediate level time of the quasi-two-level voltage balance modulation is adjusted accordingly. and This allows the hybrid clamped DC-DC converter to restore voltage self-balancing; wherein, the voltage imbalance refers to the situation where, during operation, the voltage across the flyby capacitor drops to 0 or rises to the DC power supply voltage. Nearby; the intermediate level time and The adjustment is based on the calculation of the total charge of the flying capacitor in one cycle.

[0015] Furthermore, the total charge of the flying capacitor in one cycle consists of two parts: the charge of the flying capacitor due to the load current and the charge of the flying capacitor due to the junction capacitance of the switching device.

[0016] Furthermore, the voltage self-balancing factors affecting hybrid clamped DC-DC converters can be categorized into three parts:

[0017] Part 1: The impact of the switched capacitor circuit introduced by the hybrid clamp DC-DC converter; The hybrid clamp DC-DC converter introduces a first switched capacitor circuit and a second switched capacitor circuit, so that after the first or fourth switch is turned on, the first bus capacitor and the second bus capacitor have a circuit to charge the flying capacitor, so that the voltage of the flying capacitor will not be lower than the voltage of the first bus capacitor and the voltage of the second bus capacitor after charging, preventing the voltage of the flying capacitor from dropping continuously. This process is a charging process, and there is no discharging process.

[0018] Part Two: The Influence of Load Current on Charging and Discharging in the Quasi-Two-Level Intermediate Mode; The charging and discharging of the flying capacitor by the load current only occurs in the intermediate mode of the quasi-two-level mode. Therefore, the charging and discharging of the flying capacitor by the load current depends on the switching sequence of the first and second switching transistors and the direction of the load current. This process involves both a discharge process and a charging process.

[0019] Part Three: The Influence of Junction Capacitance of Switching Devices on Charging and Discharging During Switching; During mode switching, the junction capacitance of the switching device will generate charging and discharging behavior, and this process may introduce the charging and discharging path of the flying capacitor, which will affect the charging and discharging of the flying capacitor. Its charging and discharging is related to the junction capacitance, voltage, and the switching sequence of the first and second switching transistors. Therefore, this process involves both a discharging process and a charging process.

[0020] Furthermore, under different modulation strategies, the amount of charge generated by the load current on the flying capacitor is calculated as follows:

[0021] ;

[0022] In the formula, since the intermediate mode is extremely short, the load current is assumed to remain constant during the intermediate mode. , , , These represent the amount of charge applied to the flying capacitor by the load current under the first, second, third, and fourth modulation strategies, respectively. and This is the intermediate level time. for The corresponding load current value, for The corresponding load current value.

[0023] Furthermore, under different modulation strategies, the amount of charge generated by the junction capacitance of the switching device relative to the flying capacitor is calculated as follows:

[0024] ;

[0025] ;

[0026] ;

[0027] ;

[0028] In the formula, , , , These represent the charge amount generated by the junction capacitance of the switching device relative to the flying capacitor under the first, second, third, and fourth modulation strategies, respectively. This is the junction capacitance value of the first switching transistor. This is the junction capacitance value of the second switching transistor. This is the junction capacitance value of the third switching transistor. This is the junction capacitance value of the fourth switching transistor. Here is the junction capacitance value of the first diode. This is the junction capacitance value of the second diode. This is the DC power supply voltage.

[0029] Furthermore, the voltage self-balancing condition of the hybrid clamped DC-DC converter is divided into voltage self-balancing condition under ideal switching devices and voltage self-balancing condition under non-ideal switching devices.

[0030] The voltage self-balancing condition for an ideal switching device is:

[0031] ;

[0032] The voltage self-balancing condition for non-ideal switching devices is:

[0033] ;

[0034] In the formula, The total charge of the flying capacitor in one cycle. This represents the amount of charge applied to the flying capacitor by the load current. The amount of charge generated by the junction capacitance of the switching device relative to the flying capacitor. and This is the intermediate level time. for The corresponding load current value, for The corresponding load current value; This is to provide a margin to balance the charging charge on the flying capacitor through the first and second switched capacitor circuits of the first and second bus capacitors. Pick k1 and k2 are respectively and The charging and discharging direction coefficients during the period.

[0035] Furthermore, the quasi-two-level voltage balance modulation of the hybrid clamp DC-DC converter is specifically as follows:

[0036] First, if Hybrid clamp DC-DC converters can achieve voltage self-balancing, reducing the output intermediate level time. and The corresponding load current value; if Then it is necessary to adjust the intermediate level time. and Make adjustments to meet The condition is then used to output the intermediate level time. and The corresponding load current value;

[0037] Second, intermediate level time and The adjustment takes two points into consideration:

[0038] 1) Combining The determination of positive and negative values ​​affects the intermediate level time. and Make adjustments, with an adjustment step size of T. C This is to increase the discharge time of the flying capacitor and shorten the charging time of the flying capacitor;

[0039] 2) Intermediate level time and The time should be no less than 200ns. The switching time of the switching device must be taken into account to avoid interference with the switching process.

[0040] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0041] 1. By eliminating the two redundant diodes required to maintain voltage self-balancing, the SiC series hybrid clamp topology is simplified, significantly reducing system complexity from a hardware perspective and improving structural simplicity and engineering implementation efficiency.

[0042] 2. While reducing the number of components, it can still stably achieve voltage self-balancing, taking into account both performance and cost advantages, reducing losses and size, and adopting a low-loss, small-size lightweight clamping design under quasi-two-level voltage balance modulation, further simplifying circuit implementation.

[0043] 3. By analyzing the voltage self-balancing mechanism and its key influencing factors, the core constraints of topology parameters and voltage balance are clarified, the modulation logic is optimized, and stable and accurate voltage self-balancing control is achieved.

[0044] 4. The proposed modulation optimization has good strategy adaptability and can be flexibly applied to various quasi-two-level modulation strategies, ensuring the efficient and safe operation of the converter under different operating conditions, and improving the overall system stability and engineering practical value.

[0045] In summary, compared to existing technologies, this invention eliminates the need for two additional diodes to maintain voltage self-balancing, removes redundant hardware design, and optimizes the core structure of the SiC series hybrid clamping topology, significantly reducing structural complexity at the hardware level. Simultaneously, it achieves stable voltage self-balancing even without the two diodes, preserving core functionality while reducing engineering application costs and improving the convenience and feasibility of practical applications. Furthermore, unlike the clamping circuit design under three-level modulation, the clamping circuit design under quasi-two-level modulation follows a lightweight design principle of low loss and small size, further simplifying the circuit structure. This invention addresses the problems of poor adaptability and inadequate voltage balance control in existing quasi-two-level modulation strategies. By analyzing the influencing factors of voltage self-balancing, clarifying the topology parameters and core voltage balance conditions, and proposing a targeted modulation logic optimization scheme, it can flexibly adapt to various quasi-two-level modulation strategies, effectively achieving stable voltage self-balancing of the converter, ensuring efficient and safe operation of the converter, improving its operational stability and adaptability, and possessing practical application value, making it worthy of promotion. Attached Figure Description

[0046] Figure 1 This is a topology diagram of a hybrid clamped DC-DC converter with SiC indirect series connection.

[0047] Figure 2 This is a schematic diagram of four modulation strategies.

[0048] Figure 3 A flowchart for quasi-two-level voltage balance modulation.

[0049] Figure 4 The simulation waveform diagram before the improvement of the fourth modulation strategy (i.e., modulation 4) is shown. , =400ns).

[0050] Figure 5 The simulation waveform diagram is for the improved fourth modulation strategy (i.e., modulation 4). =500ns, =300ns). Detailed Implementation

[0051] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0052] See Figure 1 As shown, this embodiment discloses a hybrid clamped DC-DC converter based on SiC indirect series connection, including: a DC power supply V in First bus capacitor C1, second bus capacitor C2, first switch S1, second switch S2, third switch S3, fourth switch S4, flying capacitor C3, first diode D1, second diode D2, load inductor L L Load capacitor C L and load resistance R L The first diode D1, the second diode D2, and the flying capacitor C3 form a clamping circuit to clamp the half-bus voltage; the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are connected end-to-end to form a half-bridge circuit composed of low-voltage single-transistor devices in series; the drain of the first switch S1 is connected to the DC power supply V. in The positive terminal of the fourth switch S4 is connected to the DC power supply V. in The negative terminal; the first bus capacitor C1 and the flying capacitor C3 form the first switched capacitor circuit when the first switch S1 is turned on; the second bus capacitor C2 and the flying capacitor C3 form the second switched capacitor circuit when the fourth switch S4 is turned on; the first bus capacitor C1 and the second bus capacitor C2 are connected in series to the DC power supply V. in The positive and negative terminals of the load capacitor C3 are respectively connected to the source of the first switch S1 and the source of the third switch S3; the anode of the first diode D1 is connected to the first bus capacitor C1 and the second bus capacitor C2, and its cathode is connected to the source of the first switch S1; the cathode of the second diode D2 is connected to the first bus capacitor C1 and the second bus capacitor C2, and its anode is connected to the source of the third switch S3; the load capacitor C L and load resistance R L After parallel connection, one end is connected to the DC power supply V. in The negative terminal is connected to the load inductor L. L At one end, the load inductor L L The other end is connected to the source of the second switch S2.

[0053] The following is the clamping circuit design method for the hybrid clamping DC-DC converter based on SiC indirect series connection described in this embodiment. The specific details are as follows:

[0054] The clamping circuit follows a lightweight design with low loss and small size under quasi-two-level voltage balance modulation; the selection of the first diode D1 and the second diode D2 is based on the rated voltage and rated current, with the rated voltage being 70% higher than the bus voltage and the rated current being 10% of the load current; the selection of the flying capacitor C3 is based on the rated voltage and capacitance value, with the rated voltage being 70% higher than the bus voltage and the capacitance value being selected according to the voltage ripple requirements to ensure that the capacitor voltage ripple is less than 20%.

[0055] Specifically, the quasi-two-level voltage balance modulation is based on the following principle: the driving voltages of the first switch S1 and the third switch S3 are complementary, and the driving voltages of the second switch S2 and the fourth switch S4 are complementary; in the intermediate mode where only the first switch S1 or the second switch S2 is turned on, the intermediate level time of the output voltage of the half-bridge circuit is... , Limited to 200~400 nanoseconds, due to the extremely short intermediate mode time, the output voltage of the half-bridge circuit approximately exhibits the characteristics of a standard two-level output. The output voltage of the half-bridge circuit composed of series low-voltage single-transistor devices is equivalent to the output voltage of the half-bridge circuit composed of high-voltage single-transistor devices, and is the same in form as the series circuit.

[0056] Specifically, the quasi-two-level voltage balance modulation includes the following four modulation strategies:

[0057] The first modulation strategy is as follows: the first switch S1 turns on ahead of the second switch S2, and the lead time is the intermediate level time. The first switch S1 leads the second switch S2 to turn off, and the lead time is the intermediate level time. ;

[0058] The second modulation strategy is as follows: the second switch S2 turns on ahead of the first switch S1, and the lead time is equal to the intermediate level time. The first switch S1 leads the second switch S2 to turn off, and the lead time is the intermediate level time. ;

[0059] The third modulation strategy is as follows: the first switch S1 turns on ahead of the second switch S2, and the lead time is the intermediate level time. The second switch S2 leads the first switch S1 by turning it off, and the lead time is the intermediate level time. ;

[0060] The fourth modulation strategy is as follows: the second switch S2 turns on ahead of the first switch S1, and the lead time is the intermediate level time. The second switch S2 leads the first switch S1 by turning it off, and the lead time is the intermediate level time. .

[0061] See Figure 2 As shown, the driving voltage V of the first switch S1 and the second switch S2 is illustrated. GS and the output voltage V of the half-bridge circuit M The relationship between time T and the relationship between the two; where, This is the DC power supply voltage. This is the intermediate level voltage.

[0062] Specifically, for any modulation strategy, when the voltage of the hybrid clamped DC-DC converter is unbalanced, the intermediate level time of the quasi-two-level voltage balance modulation is adjusted accordingly. and This allows the hybrid clamped DC-DC converter to restore voltage self-balancing; wherein, the voltage imbalance refers to the voltage across the flying capacitor C3 dropping to 0 or rising to the DC power supply voltage during the operation of the hybrid clamped DC-DC converter. Nearby; the intermediate level time and The adjustment is based on the calculation of the total charge of the flying capacitor C3 in one cycle; the total charge of the flying capacitor C3 in one cycle consists of two parts, namely the charge of the load current on the flying capacitor C3 and the charge of the junction capacitance of the switching device on the flying capacitor C3.

[0063] Specifically, the voltage self-balancing factors affecting hybrid clamped DC-DC converters can be categorized into three parts:

[0064] Part 1: The impact of the switched capacitor circuit introduced by the hybrid clamp DC-DC converter; The hybrid clamp DC-DC converter introduces a first switched capacitor circuit and a second switched capacitor circuit, so that after the first switch S1 or the fourth switch S4 is turned on, there is a circuit for the first bus capacitor C1 and the second bus capacitor C2 to charge the flying capacitor C3. This causes the voltage of the flying capacitor C3 to not be lower than the voltage of the first bus capacitor C1 and the voltage of the second bus capacitor C2 after charging, preventing the voltage of the flying capacitor C3 from continuously dropping. This process is a charging process, and there is no discharging process.

[0065] Part Two, Load Current I load The influence of quasi-two-level intermediate mode charging and discharging; load current I load The charging and discharging of the flying capacitor C3 only occurs in the intermediate mode of the quasi-two-level circuit; therefore, the load current I... load The charging and discharging of the flying capacitor C3 depends on the switching sequence of the first switch S1 and the second switch S2, as well as the load current I. load In this process, there is both a discharge process and a charging process;

[0066] Part Three: The Influence of Junction Capacitance of Switching Devices on Charging and Discharging During Switching; During mode switching, the junction capacitance of the switching device will generate charging and discharging behavior, and this process may introduce the charging and discharging path of the flying capacitor C3, which will affect the charging and discharging of the flying capacitor C3. Its charging and discharging is related to the junction capacitance, voltage, and the switching sequence of the first switch S1 and the second switch S2. Therefore, this process involves both a discharging process and a charging process.

[0067] Specifically, under different modulation strategies, the load current I load The charge amount for the flying capacitor C3 is calculated as follows:

[0068] ;

[0069] In the formula, since the intermediate mode is extremely short, the load current I is assumed to be... load It remains unchanged during the intermediate mode. , , , These represent the load current I under the first, second, third, and fourth modulation strategies, respectively. load The amount of charge applied to the flying capacitor C3; and This is the intermediate level time. for The corresponding load current value, for The corresponding load current value.

[0070] Specifically, under different modulation strategies, the amount of charge generated by the junction capacitance of the switching device relative to the flying capacitor C3 is calculated as follows:

[0071] ;

[0072] ;

[0073] ;

[0074] ;

[0075] In the formula, , , , These represent the amount of charge generated by the junction capacitance of the switching device relative to the flying capacitor C3 under the first, second, third, and fourth modulation strategies, respectively. This is the junction capacitance value of the first switching transistor S1. This is the junction capacitance value of the second switch S2. This is the junction capacitance value of the third switch S3. This is the junction capacitance value of the fourth switch S4. This is the junction capacitance value of the first diode D1. This is the junction capacitance value of the second diode D2. This is the DC power supply voltage.

[0076] Specifically, the voltage self-balancing conditions of the hybrid clamped DC-DC converter are divided into voltage self-balancing conditions under ideal switching devices and voltage self-balancing conditions under non-ideal switching devices.

[0077] The voltage self-balancing condition for an ideal switching device is:

[0078] ;

[0079] The voltage self-balancing condition for non-ideal switching devices is:

[0080] ;

[0081] In the formula, The total charge of the flying capacitor C3 in one cycle. The load current applies to the amount of charge applied to the flying capacitor C3. The junction capacitance of the switching device is the amount of charge applied to the flying capacitor C3. and This is the intermediate level time. for The corresponding load current value, for The corresponding load current value; As a margin, to balance the charging charge on the flying capacitor C3 through the first bus capacitor C1 and the second bus capacitor C2 via the first and second switched capacitor circuits. Pick k1 and k2 are respectively and The charging and discharging direction coefficients during the period.

[0082] Specifically, the quasi-two-level voltage balance modulation of the hybrid clamp DC-DC converter is as follows:

[0083] First, if Hybrid clamp DC-DC converters can achieve voltage self-balancing, reducing the output intermediate level time. and The corresponding load current value; if Then it is necessary to adjust the intermediate level time. and Make adjustments to meet The condition is then used to output the intermediate level time. and The corresponding load current value;

[0084] Second, intermediate level time and The adjustment takes two points into consideration:

[0085] 1) Combining The determination of positive and negative values ​​affects the intermediate level time. and Make adjustments, with an adjustment step size of T. C This is to increase the discharge time of the flying capacitor C3 and shorten the charging time of the flying capacitor C3.

[0086] 2) Intermediate level time and The time should be no less than 200ns. The switching time of the switching device must be taken into account to avoid interference with the switching process.

[0087] Figure 3 A flowchart of quasi-two-level voltage balance modulation is given, in which, for or k i It is k1 or k2, i.e., i=1,2.

[0088] Below, we will take the fourth modulation strategy (i.e., modulation 4) as an example to conduct an experimental analysis of modulation 4 before and after the improvement. The experimental circuit and modulation strategy are as follows: Figure 1 As shown in Table 1, the specific parameters are as follows.

[0089] Table 1 Experimental Analysis Parameters

[0090]

[0091] Given an initial , At a ns = 400 ns, its output current I load Waveform, upper bus voltage V C1 Flying capacitor voltage V C3 Waveform as Figure 4 As shown. It can be seen that V C3 It has deviated from V C1 and to DC power supply voltage Approximation reveals that the hybrid clamping structure topology's voltage self-balancing is not maintained. Theoretical analysis indicates that, under modulation case 4, =9.4A, =10A, load current to the charging charge of the flying capacitor Therefore, voltage self-balancing of the hybrid clamping structure topology cannot be maintained.

[0092] Using voltage self-balancing modulation , Adjustments were made, and the adjusted version is as follows: =500ns, =300ns, and the experimental results are as follows Figure 5 As shown. It can be seen that V C3 In V C1 Nearby fluctuations maintained the voltage self-balancing of the hybrid clamping structure topology. Theoretically, by adjusting... , The load current affects the charging charge of the flying capacitor. Therefore, the voltage self-balancing of the hybrid clamping structure topology is maintained.

[0093] In summary, the hybrid clamped DC-DC converter based on SiC indirect series proposed in this paper clarifies the parameter design, ensures voltage self-balancing capability under different modulations, and verifies the consistency with theoretical analysis and the recovery of voltage self-balancing capability by the improved modulation strategy through experimental analysis. It has practical application value and is worth promoting.

[0094] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the embodiments described above. Any changes, modifications, or simplifications made without departing from the spirit and principle of the present invention are included within the protection scope of the present invention.

Claims

1. A hybrid clamped DC-DC converter based on SiC indirect series connection, characterized in that, include: DC power supply (V) in ), First bus capacitor (C1), Second bus capacitor (C2), First switch transistor (S1), Second switch transistor (S2), Third switch transistor (S3), Fourth switch transistor (S4), Flying capacitor (C3), First diode (D1), Second diode (D2), Load inductor (L) L ), load capacitance (C) L ) and load resistance (R) L The first diode (D1), the second diode (D2), and the flying capacitor (C3) form a clamping circuit to clamp the half-bus voltage; the first switch (S1), the second switch (S2), the third switch (S3), and the fourth switch (S4) are connected end-to-end to form a half-bridge circuit composed of low-voltage single-transistor devices in series; the drain of the first switch (S1) is connected to a DC power supply (V). in The positive terminal of the fourth switch (S4) is connected to the positive terminal of the DC power supply (V). in The negative terminal of the first bus capacitor (C1) and the flying capacitor (C3) form a first switched capacitor circuit when the first switch (S1) is turned on; the second bus capacitor (C2) and the flying capacitor (C3) form a second switched capacitor circuit when the fourth switch (S4) is turned on; the first bus capacitor (C1) and the second bus capacitor (C2) are connected in series to the DC power supply (V). in The positive and negative terminals of the load capacitor (C3) are connected to the first and third switching transistors (S1 and S3), respectively; the anode of the first diode (D1) is connected to the first bus capacitor (C1) and the second bus capacitor (C2), respectively, and its cathode is connected to the source of the first switching transistor (S1); the cathode of the second diode (D2) is connected to the first bus capacitor (C1) and the second bus capacitor (C2), respectively, and its anode is connected to the source of the third switching transistor (S3); the positive and negative terminals of the load capacitor (C3) are connected to the first switching transistor (S1) and the second bus capacitor (C2), respectively, and its cathode is connected to the source of the first switching transistor (S1); the cathode of the second diode (D2) is connected to the first bus capacitor (C1) and the second bus capacitor (C2), respectively, and its anode is connected to the source of the third switching transistor (S3); the positive and negative terminals of the load capacitor (C3) are connected to the first bus capacitor (S1) and the second bus capacitor (C2), respectively, and its cathode is connected to the source of the third switching transistor (S3); the positive and negative terminals of the load capacitor (C3) are connected to the first switching transistor (S1) and the second bus capacitor (C2), respectively, and its cathode is connected to the source of the first switching transistor (S1); the negative terminals of the load capacitor (C3) are connected to the first switching transistor (S1) and the second bus capacitor (C2), respectively, and its cathode is connected to the source of the third switching transistor (S3); the negative terminals of the load capacitor (C3) are connected to the first switching transistor (S1) and the second bus capacitor (C2), respectively, and its cathode is connected to the source of ... third switching L ) and load resistance (R) L After being connected in parallel, one end is connected to a DC power supply (V). in The negative terminal is connected to the load inductor (L). L One end of the load inductor (L) L The other end of the transistor is connected to the source of the second switching transistor (S2).

2. The clamping circuit design method for a hybrid clamping DC-DC converter based on SiC indirect series connection as described in claim 1, characterized in that, The clamping circuit follows a lightweight design with low loss and small size under quasi-two-level voltage balance modulation; the selection of the first diode (D1) and the second diode (D2) is based on the rated voltage and rated current, with the rated voltage being 70% higher than the bus voltage and the rated current being 10% of the load current; the selection of the flying capacitor (C3) is based on the rated voltage and capacitance value, with the rated voltage being 70% higher than the bus voltage and the capacitance value being selected according to the voltage ripple requirements to ensure that the capacitor voltage ripple is less than 20%.

3. The clamping circuit design method for a hybrid clamping DC-DC converter based on SiC indirect series connection according to claim 2, characterized in that, The quasi-two-level voltage balance modulation is based on the following principle: the driving voltages of the first switch (S1) and the third switch (S3) are complementary, and the driving voltages of the second switch (S2) and the fourth switch (S4) are complementary; in the intermediate mode where only the first switch (S1) or the second switch (S2) is turned on, the intermediate level time of the output voltage of the half-bridge circuit is... , Limited to 200~400 nanoseconds, due to the extremely short intermediate mode time, the output voltage of the half-bridge circuit approximately exhibits the standard two-level output characteristics. The output voltage of the half-bridge circuit composed of low-voltage single-transistor devices in series is equivalent to the output voltage of the half-bridge circuit composed of high-voltage single-transistor devices, and is the same in form as the series circuit. The quasi-two-level voltage balance modulation includes the following four modulation strategies: The first modulation strategy is as follows: the first switch (S1) turns on ahead of the second switch (S2), and the lead time is the intermediate level time. The first switch (S1) leads the second switch (S2) to turn off, and the lead time is the intermediate level time. ; The second modulation strategy is as follows: the second switch (S2) turns on ahead of the first switch (S1), and the lead time is the intermediate level time. The first switch (S1) leads the second switch (S2) to turn off, and the lead time is the intermediate level time. ; The third modulation strategy is as follows: the first switch (S1) turns on ahead of the second switch (S2), and the lead time is the intermediate level time. The second switch (S2) turns off before the first switch (S1), and the lead time is equal to the intermediate level time. ; The fourth modulation strategy is as follows: the second switch (S2) turns on ahead of the first switch (S1), and the lead time is the intermediate level time. The second switch (S2) turns off before the first switch (S1), and the lead time is equal to the intermediate level time. .

4. The clamping circuit design method for a hybrid clamping DC-DC converter based on SiC indirect series connection according to claim 3, characterized in that, For any modulation strategy, when the voltage of the hybrid clamped DC-DC converter is unbalanced, the intermediate level time of the quasi-two-level voltage balance modulation is adjusted accordingly. and This allows the hybrid clamped DC-DC converter to restore voltage self-balancing; wherein, the voltage imbalance refers to the voltage across the flying capacitor (C3) dropping to 0 or rising to the DC supply voltage during operation of the hybrid clamped DC-DC converter. Nearby; the intermediate level time and The adjustment is based on the calculation of the total charge of the flying capacitor (C3) in one cycle.

5. The clamping circuit design method for a hybrid clamping DC-DC converter based on SiC indirect series connection according to claim 4, characterized in that, The total charge of the flying capacitor (C3) in one cycle consists of two parts: the charge of the load current on the flying capacitor (C3) and the charge of the junction capacitance of the switching device on the flying capacitor (C3).

6. The clamping circuit design method for a hybrid clamping DC-DC converter based on SiC indirect series connection according to claim 4, characterized in that, The voltage self-balancing factors affecting hybrid clamp DC-DC converters can be categorized into three parts: Part 1: The impact of the switched capacitor circuit introduced in the hybrid clamp DC-DC converter; The hybrid clamp DC-DC converter introduces a first switched capacitor circuit and a second switched capacitor circuit, so that after the first switch (S1) or the fourth switch (S4) is turned on, there is a circuit between the first bus capacitor (C1) and the second bus capacitor (C2) to charge the flying capacitor (C3). This causes the voltage of the flying capacitor (C3) to not be lower than the voltage of the first bus capacitor (C1) and the voltage of the second bus capacitor (C2) after charging, preventing the voltage of the flying capacitor (C3) from continuously dropping. This process is a charging process, and there is no discharging process. Part Two, Load Current (I) load The influence of charging and discharging in the intermediate mode of the quasi-two-level circuit; Load current (I) load The charging and discharging of the flying capacitor (C3) only occurs in the intermediate mode of the quasi-two-level circuit; therefore, the load current (I) load The charging and discharging of the flying capacitor (C3) depends on the switching sequence of the first switch (S1) and the second switch (S2) and the load current (I). load The direction of the discharge process and the charging process are both involved in this process. Part Three: The Influence of Junction Capacitance of Switching Devices on Charging and Discharging During Switching; During mode switching, the junction capacitance of the switching device will generate charging and discharging behavior, and this process may introduce the charging and discharging path of the flying capacitor (C3), which will affect the charging and discharging of the flying capacitor (C3). Its charging and discharging is related to the junction capacitance, voltage, and the switching sequence of the first switch (S1) and the second switch (S2). Therefore, there is both a discharging process and a charging process in this process.

7. The clamping circuit design method for a hybrid clamping DC-DC converter based on SiC indirect series connection according to claim 5, characterized in that, Under different modulation strategies, the load current (I) load The calculation of the charging charge of the flying capacitor (C3) is as follows: ； In the formula, since the intermediate mode is extremely short, the load current (I) is considered to be... load It remains unchanged during the intermediate modes. , , , These represent the load currents (I) under the first, second, third, and fourth modulation strategies, respectively. load The amount of charge applied to the flying capacitor (C3); and This is the intermediate level time. for The corresponding load current value, for The corresponding load current value.

8. The clamping circuit design method for a hybrid clamping DC-DC converter based on SiC indirect series connection according to claim 5, characterized in that, Under different modulation strategies, the amount of charge generated by the junction capacitance of the switching device relative to the flying capacitor (C3) is calculated as follows: ； ； ； ； In the formula, , , , These represent the amount of charge generated by the junction capacitance of the switching device relative to the flying capacitor (C3) under the first, second, third, and fourth modulation strategies, respectively. This is the junction capacitance value of the first switching transistor (S1). This is the junction capacitance value of the second switching transistor (S2). This is the junction capacitance value of the third switch (S3). This is the junction capacitance value of the fourth switch (S4). Here is the junction capacitance value of the first diode (D1). This is the junction capacitance value of the second diode (D2). This is the DC power supply voltage.

9. The clamping circuit design method for a hybrid clamping DC-DC converter based on SiC indirect series connection according to claim 4, characterized in that, The voltage self-balancing conditions of the hybrid clamped DC-DC converter are divided into voltage self-balancing conditions under ideal switching devices and voltage self-balancing conditions under non-ideal switching devices. The voltage self-balancing condition for an ideal switching device is: ； The voltage self-balancing condition for non-ideal switching devices is: ； In the formula, The total charge of the flying capacitor (C3) over one cycle. This represents the amount of charge applied to the flying capacitor (C3) by the load current. The amount of charge applied to the junction capacitance of the switching device relative to the flying capacitor (C3). and This is the intermediate level time. for The corresponding load current value, for The corresponding load current value; To provide a margin, in order to balance the charging charge of the first bus capacitor (C1) and the second bus capacitor (C2) on the flying capacitor (C3) through the first and second switched capacitor circuits, Pick k1 and k2 are respectively and The charging and discharging direction coefficients during the period.

10. The clamping circuit design method for a hybrid clamping DC-DC converter based on SiC indirect series connection according to claim 9, characterized in that, The quasi-two-level voltage balance modulation of the hybrid clamp DC-DC converter is as follows: First, if Hybrid clamp DC-DC converters can achieve voltage self-balancing, reducing the output intermediate level time. and The corresponding load current value; if Then it is necessary to adjust the intermediate level time. and Make adjustments to meet The condition is then used to output the intermediate level time. and The corresponding load current value; Second, intermediate level time and The adjustment takes two points into consideration: 1) Combining The determination of positive and negative values ​​affects the intermediate level time. and Make adjustments, with an adjustment step size of T. C This is to increase the discharge time of the flying capacitor (C3) and shorten the charging time of the flying capacitor (C3); 2) Intermediate level time and The time should be no less than 200ns. The switching time of the switching device must be taken into account to avoid interference with the switching process.

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