A variable gain double-loop control method for three-phase PFC rectifier in discontinuous conduction mode

Abstract

The application discloses a variable gain double-loop control method of a three-phase PFC rectifier in discontinuous conduction mode, and relates to the technical field of power supply systems. The method comprises the following steps: firstly, determining an input-output variable ratio according to an input voltage, and calculating a proportional coefficient initial value under a load resistance based on a system cutoff frequency, and combining the variable ratio to determine a minimum load resistance and a corresponding integral coefficient; secondly, calculating a competitive gain coefficient through a DC side inductor and the variable ratio; then, fusing the gain coefficient, the initial value proportional coefficient and a traditional double-loop proportional coefficient to obtain a target proportional coefficient; combining a steady-state inductor current, the variable ratio and the integral coefficient to determine a target integral coefficient. Finally, the target PI parameter is used for a voltage loop, and the output thereof is multiplied by the competitive gain coefficient, and then, a minimum value is taken with a current loop output to generate a final control signal of the rectifier. The method improves the transient and steady-state performance of the three-phase PFC rectifier in discontinuous conduction mode under a wide range of variable load working conditions.

Description

Technical Field

[0001] This application relates to the field of power system technology, and in particular to a variable gain dual-loop control method for a three-phase PFC rectifier in intermittent conduction mode. Background Technology

[0002] With the rapid development of power electronics technology, three-phase power factor correction (PFC) rectifiers, as core modules for power conversion, have been widely used in various critical power supply scenarios. Current applications place stringent requirements on power modules: they must be adaptable to a wide load range from extremely light to heavy loads, cope with rapid load switching conditions, and simultaneously ensure stable output voltage, rapid dynamic response, and excellent power factor.

[0003] Three-phase Buck PFC rectifiers are the preferred choice due to their advantages such as simple topology, high conversion efficiency, and low input harmonics. However, under wide load conditions, their operating mode switches between Continuous Current Mode (CCM) and Discontinuous Current Mode (DCM). Under heavy load, the system operates in CCM mode, where the traditional voltage-current dual closed-loop control strategy can meet the steady-state requirements. However, under extremely light load / no-load conditions, the discontinuous DC-side inductor current causes the system to enter DCM mode. In this mode, the circuit exhibits strong nonlinear characteristics, resulting in incomplete vector synthesis and difficulties in averaging state variables, making the traditional dual closed-loop control inadequate. For a long time, research on the control of three-phase PFC rectifiers has focused primarily on CCM mode, with insufficient attention and in-depth exploration of DCM mode. Early applications featured gradual load changes, a low proportion of extremely light load conditions, and relaxed requirements for dynamic performance, lacking application needs for high load abrupt changes and wide-range switching. At the same time, the operating modes in DCM mode are complex, and the design of nonlinear modeling and control algorithms is difficult. Existing methods are unable to solve problems such as insufficient bandwidth, weak anti-interference, and large start-up overshoot under light load conditions, resulting in poor transient steady-state performance under wide-range variable load conditions. Summary of the Invention

[0004] Therefore, it is necessary to provide a variable gain dual-loop control method for a three-phase PFC rectifier in intermittent conduction mode to address the aforementioned technical problems.

[0005] The following technical solution is adopted in this specification: This manual provides a variable gain dual-loop control method for a three-phase PFC rectifier in intermittent conduction mode, including: Obtain the input voltage of the three-phase power factor correction rectifier, and determine the input-output ratio of the three-phase power factor correction rectifier based on the input voltage; Based on the system cutoff frequency of the three-phase power factor correction rectifier in discontinuous conduction mode, calculate the proportional coefficient of the single-voltage loop PI controller under the load resistance value, and determine the minimum load resistance value based on the input-output ratio and the load resistance value, and calculate the integral coefficient of the single-voltage loop PI controller under the minimum load resistance. The competing gain coefficient is determined based on the DC-side inductance and input-output ratio of the three-phase power factor correction rectifier. The target proportional coefficient is determined based on the competitive gain coefficient, the proportional coefficient of the single voltage loop PI controller under the load resistance value, and the proportional coefficient of the voltage loop PI controller of the three-phase power factor correction rectifier under dual-loop control. The competitive gain coefficient is determined based on the steady-state inductor current value and the input-output ratio. The target integral coefficient is determined based on the competitive gain coefficient and the integral coefficient. The target proportional coefficient and target integral coefficient are used as the control coefficients of the current voltage loop PI controller to determine the control output of the current voltage loop. The control output of the current voltage loop is then multiplied by the competing gain coefficient to determine the target control output of the current voltage loop. The minimum value between the target control output of the current voltage loop and the control output of the current current loop is determined as the control signal for the three-phase power factor correction rectifier.

[0006] Optionally, the input-output turns ratio of the three-phase power factor correction rectifier is determined based on the input voltage, including: Determine the equivalent input voltage amplitude under steady state based on the input voltage; The target output voltage of the three-phase power factor correction rectifier is determined based on the equivalent input voltage amplitude. The ratio of the target output voltage to the equivalent input voltage amplitude is determined as the input-output ratio. The formula for calculating the target output voltage is as follows: ; in, For the target output voltage, This represents the equivalent input voltage amplitude.

[0007] Optionally, based on the system cutoff frequency of the three-phase power factor correction rectifier in intermittent conduction mode, the proportional gain of the single-voltage loop PI controller under the load resistance value is calculated, including: Calculate the cutoff frequency of the low-pass filter based on the system cutoff frequency; Based on the equivalent input voltage amplitude and input-output ratio, determine the system gain of the single-voltage-loop PI controller under the load resistance value, and based on the input-output ratio and load resistance value, determine the poles of the single-voltage-loop PI controller under the load resistance value. Based on the system gain, poles, and cutoff frequency of the low-pass filter, determine the scaling factor for the load resistance value.

[0008] Optionally, the formula for calculating the cutoff frequency of the low-pass filter is: ; in, The system cutoff frequency, This is the cutoff frequency of the low-pass filter; System gain and extreme points The calculation formula is: ; in, The equivalent input voltage amplitude, For input-output ratio, In order to adjust the system, For output capacitor, Choose the value for the load resistor; proportionality coefficient The calculation formula is: .

[0009] Optionally, the integral coefficient of the single-voltage-loop PI controller at the minimum load resistance is calculated, including: Calculate the system gain of a single-voltage-loop PI controller at the minimum load resistance. Based on the cutoff frequency of the low-pass filter and the system gain of the single-voltage-loop PI controller at the minimum load resistance, determine the integral coefficient of the single-voltage-loop PI controller at the minimum load resistance; integral coefficient The calculation formula is: ; Minimum load resistance The calculation formula is: ; in, For DC side inductance, This refers to the switching frequency.

[0010] Optionally, the formula for calculating the competition gain coefficient is: .

[0011] Optionally, the target scaling factor of the current voltage loop The calculation formula is: ; in, This refers to the proportional gain of the voltage loop in a three-phase power factor correction rectifier under dual-loop control. This represents the absolute value of the error in a single voltage loop. and All are thresholds. , This is the control output of the current voltage loop. This is the control output of the current current loop.

[0012] Optionally, the target integral coefficient of the current voltage loop The calculation formula is: .

[0013] This specification provides a variable gain dual-loop control device for a three-phase PFC rectifier in intermittent conduction mode, including: The acquisition module is used to acquire the input voltage of the three-phase power factor correction rectifier and determine the input-output ratio of the three-phase power factor correction rectifier based on the input voltage. The first calculation module is used to calculate the proportional coefficient of the single voltage loop PI controller under the load resistance value based on the system cutoff frequency of the three-phase power factor correction rectifier in the intermittent conduction mode, and to determine the minimum load resistance value based on the input-output ratio and the load resistance value, and to calculate the integral coefficient of the single voltage loop PI controller under the minimum load resistance. The second calculation module is used to determine the competing gain coefficient based on the DC-side inductance and input-output ratio of the three-phase power factor correction rectifier. The third calculation module is used to determine the target proportional coefficient based on the competitive gain coefficient, the proportional coefficient of the single voltage loop PI controller under the load resistance value, and the proportional coefficient of the voltage loop PI controller of the three-phase power factor correction rectifier under dual-loop control; and to determine the competitive gain coefficient based on the steady-state inductor current value and the input-output ratio; and to determine the target integral coefficient based on the competitive gain coefficient and the integral coefficient. The fourth calculation module is used to use the target proportional coefficient and the target integral coefficient as the control coefficients of the current voltage loop PI controller, determine the control output of the current voltage loop, and multiply the control output of the current voltage loop by the competing gain coefficient to determine the target control output of the current voltage loop. The determination module is used to determine the minimum value between the target control output of the current voltage loop and the control output of the current current loop as the control signal for the three-phase power factor correction rectifier.

[0014] This specification provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for variable gain dual-loop control of a three-phase PFC rectifier under intermittent conduction mode.

[0015] This specification provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the above-described method for variable gain dual-loop control of a three-phase PFC rectifier under intermittent conduction mode.

[0016] The above-mentioned technical solutions adopted in this specification can achieve the following beneficial effects: This method, through a dynamically calculated "competitive gain coefficient" and a "minimum value" competition strategy, can automatically and smoothly switch between dual-loop control and equivalent single-voltage loop control based on the continuity of inductor current. This effectively solves the hard impact and oscillation problem of traditional methods during the critical switching of DCM / CCM, achieving smooth mode switching and avoiding hard impact. Furthermore, a target integral coefficient and target proportional coefficient are specifically designed and dynamically integrated for DCM mode, ensuring that the control law remains optimal over a wide load range. Combined with the aforementioned competition mechanism, it can quickly constrain current and stabilize voltage during startup and load abrupt changes, significantly suppressing light-load startup overshoot and accelerating the recovery process during load switching. The key parameters of this method (such as input / output ratio, PI coefficient, and competitive gain coefficient) are all calculated or adjusted online based on real-time input voltage and load boundaries, enabling the controller to adapt to wide input voltage and wide load range variations. This ensures steady-state accuracy, power factor correction capability, and dynamic adjustment capability under all operating conditions, improving the transient steady-state performance under wide-range variable load conditions.

[0017] In addition, this invention innovatively adapts the gain of the original voltage loop output through a "competitive gain coefficient", enabling it to function as a single voltage loop under DCM without the need to construct an additional independent loop. This method achieves the functionality of the traditional three-loop scheme with a simpler algorithm structure, reducing computational complexity and implementation cost. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 This document provides a flowchart illustrating a variable gain dual-loop control method for a three-phase PFC rectifier under intermittent conduction mode. Figure 2 This specification provides a schematic diagram of a three-phase Buck-type PFC rectifier topology. Figure 3 This specification provides a vector modulation principle and a schematic diagram of the first large sector vector modulation sequence; wherein, (a) shows the basic structure of vector modulation and the division of large and small sectors, and (b) shows the subdivision of the first large sector into smaller sectors and the distribution of the vector sequence; Figure 4 This specification provides the DC-side inductor voltage for different regions (Area1~Area4) under DCM conditions. u Ld With inductor current i Ld Characteristic curves; where (a) corresponds to Area 1, (b) corresponds to Area 2, (c) corresponds to Area 3, and (d) corresponds to Area 4; Figure 5 This specification provides a circuit diagram of four core operating modes under DCM conditions; wherein, (a) is an active vector I 6. Operational modes; (b) The figure shows the active vector. I 1. Operating modes; (c) The figure shows the mode in which the inductor current drops to zero under zero vector; (d) The figure shows the mode in which the inductor current remains at zero under zero vector; Figure 6 This specification provides a δ The Fourier decomposition results of (t) are compared; (a) shows the decomposition results of N=0 (constant term only), (b) shows the decomposition results of N=1, and (c) shows the decomposition results of N=2. Figure 7 This specification provides a comparison diagram of the AC side response of an original switch topology and a three-phase system model; wherein, (a) is the bridge arm terminal voltage. u mx ( x A comparison of the transient and steady-state waveforms of (a, b, c) is shown in Figure (b), which shows the current of the AC-side filter inductor. i Lx ( x Waveform comparison of (a, b, c); Figure 8 This specification provides a different simplified model compared to the original switch topology. i Ld (DC-side inductor current) and u o (Output voltage) Waveform comparison diagrams; among them, (a), (d) and (g) are full-process waveforms, (b), (e) and (h) are transient waveforms, and (c), (f) and (i) are steady-state waveforms; Figure 9 A different one provided in this specification G Value reduction system M Input-output ratio M v Relationship curve diagram; Figure 10 This document provides a comparison of Bode plots for different DCM system models; (a) Figure shows a 10W load ( Rd =4000Ω) working condition, (b) figure shows 50W load ( R d Under the condition of 800Ω, the frequency domain characteristics of the fourth-order system, the second-order system and the double-pole system are shown respectively. Figure 11 This specification provides a normalized value for the scaling factor under DCM mode. K p_D / ω r Normalized values ​​of integral coefficients K i_D / ω r With equivalent input voltage E n Load resistance R d The relationship curve; where, (a) shows the relationship curve. K p_D / ω r Follow E n , R d The changing trend is shown in Figure (b). K i_D / ω r The changing trend; Figure 12 This specification provides a K p_D , K i_D A schematic diagram illustrating the effect of the selected values ​​on the correction effect of the transfer function; wherein, Figure (a) shows... K p_D The impact of the changes is shown in Figure (b). K i_D The impact of the changes; Figure 13 This document provides a schematic diagram of a zero-state response operation of a dual closed-loop control architecture; wherein, (a) shows the operation result of heavy-load CCM, and (b) shows the operation result of extremely light-load DCM. Figure 14 A voltage loop proportionality factor provided in this specification K p A schematic diagram of the variable structure value taking logic curve; Figure 15 This document provides an overall architecture diagram of a variable gain dual-loop control algorithm. Figure 16The waveforms comparing the dynamic responses of the traditional dual-loop and variable-gain dual-loop competition strategies under three different operating conditions provided in this manual are shown. Among them, (a), (b) and (c) correspond to operating condition 1, (d), (e) and (f) correspond to operating condition 2, and (g), (h) and (i) correspond to operating condition 3. Figure 17 This document provides a schematic diagram of a computer device for implementing a variable gain dual-loop control method for a three-phase PFC rectifier in intermittent conduction mode. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in this specification without creative effort are within the scope of protection of this application.

[0021] With the continuous improvement of power supply dynamic performance requirements in related fields, wide load adaptability and stable operation with rapid switching have become core requirements. The metastable performance of traditional control algorithms under wide range of variable load conditions is not satisfactory. For example, when faced with problems such as hard impacts during switching between DCM and CCM modes, overshoot of startup voltage under light load, and dynamic response defects and transient oscillations caused by large load shearing, they can no longer meet the requirements of practical applications.

[0022] Existing technologies urgently need a new control algorithm to achieve smooth switching between two modes under a wide load range, suppress transient voltage fluctuations, improve the system's dynamic adjustment capability and steady-state stability, and adapt to the high-performance requirements of harsh scenarios.

[0023] From an implementation perspective, for control under wide load conditions, the current main approaches are voltage and current dual closed-loop control or current feedforward control.

[0024] Existing technology presents a research on control strategies for a three-phase current-source PWM rectifier. This research analyzes the grid-side current distortion and output voltage runaway problems caused by traditional PWM under light load, and proposes a multi-objective PWM method. Based on the equal area method and volt-second balance, it derives the duty cycle expressions for symmetrical / asymmetrical DCM, replacing the traditional duty cycle to optimize current and voltage characteristics. However, this research only derives the state-space equations under CCM, and in terms of voltage output level, it only focuses on Buck-Buck voltage mode, not covering other voltage modes, and does not address the transient impact of switching between DCM and CCM.

[0025] Another existing technology addresses the input current distortion and output voltage ripple issues of three-phase Buck rectifiers under light-load DCM (Distributed Current Management). It analyzes the DC-side current ripple characteristics, determines the CCM / DCM boundary, derives the DCM small-signal model, proposes an SS-III modulation scheme (ensuring current continuity in the active vector phase), and a digital feedforward compensation method. Simulation and experimental verification demonstrate its effectiveness in reducing current THD and voltage ripple. However, this study does not provide a universal expression for the entire sector, only analyzing specific sectors; it does not derive the system-level transfer function, nor does it conduct controller design based on the model. The control strategy focuses only on duty cycle compensation, lacking systematic optimization, and still employs a dual-loop voltage and current strategy, neglecting dynamic performance.

[0026] Another existing technology addresses the voltage boost and harmonic distortion issues under light-load DCM with CSI by proposing a multi-objective PWM method. This method considers the load impedance and the reactive current of the output filter capacitor, derives the duty cycle expression for adapting to DCM, and designs mode transition logic to achieve seamless switching between DCM and CCM. However, this paper does not optimize controller parameters based on the model; the optimization strategy focuses on the modulation level and neglects dynamic performance improvement.

[0027] Therefore, based on the application requirements of wide load adaptability and fast switching of three-phase Buck PFC rectifiers under the rapid development of power electronics technology, and addressing the problems of hard impact during DCM and CCM mode switching, large overshoot during light load start-up, and dynamic response defects during large load shearing, this invention provides a variable gain dual-loop control method for three-phase PFC rectifiers under intermittent conduction mode. This method achieves metastable performance optimization under wide-range variable load conditions through modal analysis, modeling optimization, dedicated controller design, and dual-loop competition strategy construction. This includes steady-state control under DCM, smooth switching between DCM and CCM modes, and suppression of voltage fluctuations during load shearing, thereby improving the overall system performance.

[0028] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0029] Figure 1 This is a flowchart illustrating a variable gain dual-loop control method for a three-phase PFC rectifier in intermittent conduction mode, as described in this specification. The method includes the following steps: S101: Obtain the input voltage of the three-phase power factor correction rectifier, and determine the input-output ratio of the three-phase power factor correction rectifier based on the input voltage.

[0030] In one embodiment, determining the input-output ratio of a three-phase power factor correction rectifier based on the input voltage includes: determining the equivalent input voltage amplitude in steady state based on the input voltage; determining the target output voltage of the three-phase power factor correction rectifier based on the equivalent input voltage amplitude; and determining the ratio of the target output voltage to the equivalent input voltage amplitude as the input-output ratio.

[0031] Among them, according to the input voltage e x ( x =a,b,c), and its amplitude can be obtained. E m Thus, the equivalent input voltage is obtained. The equivalent input voltage amplitude under steady state is E n .

[0032] The formula for calculating the target output voltage is: (1) in, For the target output voltage, This represents the equivalent input voltage amplitude.

[0033] S102, based on the system cutoff frequency of the three-phase power factor correction rectifier in discontinuous conduction mode, calculate the proportional coefficient of the single-voltage loop PI controller under the load resistance value, and determine the minimum load resistance value based on the input-output ratio and the load resistance value, and calculate the integral coefficient of the single-voltage loop PI controller under the minimum load resistance value.

[0034] In one embodiment, the proportional gain of a single-voltage-loop PI controller under different load resistance values ​​is calculated based on the system cutoff frequency of the three-phase power factor correction rectifier in discontinuous conduction mode. This includes: calculating the cutoff frequency of a low-pass filter based on the system cutoff frequency; determining the system gain of the single-voltage-loop PI controller under different load resistance values ​​based on the equivalent input voltage amplitude and the input-output ratio; determining the poles of the single-voltage-loop PI controller under different load resistance values ​​based on the input-output ratio and the load resistance value; and determining the proportional gain under different load resistance values ​​based on the system gain, poles, and the cutoff frequency of the low-pass filter.

[0035] The formula for calculating the cutoff frequency of the low-pass filter is as follows: (2) in, The system cutoff frequency, This is the cutoff frequency of the low-pass filter.

[0036] System gain and extreme points The calculation formula is: (3) in, The equivalent input voltage amplitude, For input-output ratio, In order to adjust the system, For output capacitor, The value is determined for the load resistance.

[0037] Substituting the load resistance value into formula (3) yields the system gain of the single-voltage-loop PI controller under the specified load resistance value.

[0038] In one embodiment, calculating the integral coefficient of the single-voltage-loop PI controller at the minimum load resistance includes: calculating the system gain of the single-voltage-loop PI controller at the minimum load resistance ( Based on the cutoff frequency of the low-pass filter and the system gain of the single-voltage-loop PI controller at the minimum load resistance, determine the integral coefficient of the single-voltage-loop PI controller at the minimum load resistance.

[0039] The proportional gain of a single-voltage-loop PI controller and integral coefficient The calculation formula is: (4) Minimum load resistance The calculation formula is: (5) in, For DC side inductance, This refers to the switching frequency.

[0040] S103 determines the competing gain coefficient based on the DC-side inductance and input-output ratio of the three-phase power factor correction rectifier.

[0041] The formula for calculating the competition gain coefficient is: (6) S104. Based on the competitive gain coefficient, the proportional coefficient of the single-voltage loop PI controller under the load resistance value, and the proportional coefficient of the voltage loop PI controller of the three-phase power factor correction rectifier under dual-loop control, determine the target proportional coefficient. Based on the steady-state inductor current value and the input-output ratio, determine the competitive gain coefficient. Based on the competitive gain coefficient and the integral coefficient, determine the target integral coefficient.

[0042] The target scaling factor for the current voltage loop The calculation formula is: (7) in, This refers to the proportional gain of the voltage loop in a three-phase power factor correction rectifier under dual-loop control. This represents the absolute value of the error in a single voltage loop. and All are thresholds. , This is the control output of the current voltage loop. This is the control output of the current loop. It should be noted that in digital control, the control outputs of the voltage loop and current loop in formula (7) can be the control outputs of the voltage loop and current loop in the previous discrete control cycle.

[0043] The target integral coefficient of the current voltage loop The calculation formula is: (8) S105: Use the target proportional coefficient and target integral coefficient as the control coefficients of the current voltage loop PI controller to determine the control output of the current voltage loop, and multiply the control output of the current voltage loop by the competing gain coefficient to determine the target control output of the current voltage loop.

[0044] S106 determines the minimum value between the target control output of the current voltage loop and the control output of the current current loop as the control signal for the three-phase power factor correction rectifier.

[0045] (9) in, This is the final output of the control loop of the three-phase power factor correction rectifier, i.e., the control signal.

[0046] To verify the effectiveness of the method of the present invention, the method will be described in further detail below.

[0047] 1. Analyze the operating modes of the system under DCM: Three-phase Buck PFC rectifier topology as follows: Figure 2 As shown. Let the three-phase input phase voltage and current be respectively... , , The amplitudes are respectively and The DC side inductor current is The output voltage is For an input AC CLC filter, ignoring the grid-side input line impedance, it can be equivalent to an LC filter, such as... Figure 2 As shown. Among them For AC side filter inductance, For AC side filter capacitor, For DC side inductance, and These are the parasitic resistances of AC and DC inductors, Decoupling capacitor for rectifier output, This is the load resistance.

[0048] Among them, such as Figure 3 As shown, the basic principle of vector modulation method is as follows: Figure 3 Figure (a) shows the active vector and the zero vector. The active vector... I 1~ I 6. The bridge arm output voltages corresponding to these states are as follows: u ab , u ac , u bc , u ba , u ca , u cb The dashed circle in the diagram represents the target vector trajectory. Based on the volt-second balance principle, vector points within different sectors are synthesized using their corresponding vectors. There are a total of 6 large sectors, each of which can be further divided into 2 smaller sectors, resulting in a total of 12 smaller sectors. Ignoring losses, the input-output transformation ratio Mv is defined as follows:

[0049] (10) in, and These represent the DC-side inductor current amplitude and the output voltage, respectively. The output voltage is the average output voltage. This represents the voltage amplitude at the bridge arm.

[0050] When the system is in CCM mode, all active vectors and zero vectors effectively participate in the synthesis of the target vector. Therefore, the control output quantity, i.e., the modulation index, is input to the modulation stage. m and M v equal.

[0051] When the system is in DCM state, the DC inductor current iLd will drop to 0. At this time, there may be situations where active vectors or zero vectors cannot effectively participate in the synthesis of the target vector. Therefore, the control quantity adjustment... m and M v They are not equal. For the specific vector sequence selection in the DCM state, symmetric modulation can satisfy this topology. m s The operating conditions are within the range of 0 to 0.97, which meets engineering requirements. The delay of the LC filter is not considered, and the input AC terminal voltage is not assumed. uma , u mb , u mc They are respectively:

[0052] (11) Taking the first large sector as an example to illustrate the vector modulation sequence, such as... Figure 3 In diagram (b), the vectors corresponding to the three vertices are the source vectors. I 1, I 6 and I 0, further divided into two smaller sectors. Bridge arm voltage u ab The bridge arm voltage dropped from 1.732Vm to 0.866Vm. u ac The voltage dropped from 0.866Vm to 1.732Vm. Small sector 12 satisfies the requirement. u ab > u ac The corresponding vector sequence is I 0- I 6- I 1- I 6- I 0; Small sector 12 satisfies u ab < u ac The corresponding vector sequence is I 0- I 1- I 6- I 1- I 0. . That is, the vector sequence is set to start and end as zero vectors within one switching cycle, the second and fourth symmetrically executed vectors are vectors corresponding to higher line voltages, and the vector executed in the middle is another active vector.

[0053] Consider the execution time, or modulation index, of each specific vector. Let the modulation function for each phase be... m a , m b , m c They are respectively:

[0054] (12) It is not hard to see that u mx ( x =a,b,c) and m x ( x =a,b,c) satisfy: (13) For each switching cycle of different sectors, the duty cycle corresponding to the voltage at each bridge arm is... d a , d b , d c As shown in Table 1, the relationship between duty cycle and modulation function satisfies... d x =| m x | ( x =a,b,c).

[0055] Table 1. Duty cycle expressions for three-phase bridge arms in each sector Taking the first major sector as an example, let's analyze the operating status under DCM. First, regarding the division of the region, let's further consider the output voltage. u o The relationship with the line voltage at the bridge arm endpoints. The operating condition is set as the output voltage. u o Between 0.866 and 1.500 U m Between, such as Figure 3 As shown in Figure (b), it can be determined according to u ab , u ac and u o The size relationship between them can divide a large sector into four regions, Area1 to Area4.

[0056] Secondly, the operation of the DCM under different Area states is analyzed within each switching cycle, such as... Figure 4 As shown. There are a total of 4 operating modes within each switching cycle, such as... Figure 5 As shown. Let the switching period be... T s The peak current is i pk The following is a detailed analysis.

[0057] When the switching cycle is in Area 1, the DC-side inductor voltage u Ld With inductor current i Ld The characteristic curves are as follows Figure 4 As shown in Figure (a). During the initial phase of this cycle, when entering the first zero-vector state, due to the inductor current... i Ld=0, according to the differential relationship between inductor voltage and current, the DC side inductor voltage u Ld =0, corresponding to Figure 5 The operating mode is shown in diagram (d). Then it enters the first active vector... I 6. During the operation phase, the inverter output line voltage is... u ab Higher than the load output voltage u o Based on the circuit topology, we can derive the following: u Ld = u ab - u o When the value is greater than 0, the inductor current shows an increasing trend, and the effective duration of this vector is 0.5 seconds. d b T s ,correspond Figure 5 The mode is shown in Figure (a). It then proceeds to the second active vector. I 1. Operational stage, during which the line voltage... u ac < u o , making u Ld = u ac - u o When the current is less than 0, the inductor current begins to decrease, and its duration is... d c T s Operating modes such as Figure 5 As shown in Figure (b). Then the third active vector switches again. I 6. At this time u Ld = u ab - u o The inductor current remains positive and resumes its rising phase, with a duration of 0.5 seconds. d b T s When the switching cycle enters the subsequent zero-vector state, a - is first applied across the inductor. u o Under the influence of a reverse voltage, the inductor current gradually decreases to zero. Let the time of this phase be t. d 2 T s ,correspond Figure 5 The mode shown in Figure (c); when the inductor current drops to zero,u Ld =0, system maintains Figure 5 The mode shown in Figure (d) operates until the end of the current switching cycle. In summary, neglecting losses, the differential equations for the inductor voltage and current over one switching cycle satisfy:

[0058] (14) Suppose the total time of the source vector action is d 1. It is not difficult to see at this time d 1. Satisfy (15) We can obtain: (16) When the switching cycle is in the Area2 region u Ld and i Ld The characteristic curves are as follows Figure 4 As shown in Figure (b). Similar to the initial stage of Area 1, in the first zero vector state due to i Ld =0, therefore u Ld =0, corresponding to Figure 5 The mode is shown in diagram (d). The first active vector. I When 6 is in effect, u ab > u o lead to u Ld = u ab - u o If the value is greater than 0, the inductor current increases, and the effective duration is 0.5 seconds. d b T s Operating modes such as Figure 5 As shown in Figure (a). Entering the second active vector. I During the first operational phase, although the line voltage satisfies... u ac < u ab But still maintain u ac > u o The relationship at this time u Ld = u ac - u o >0, the inductor current continues to rise, but becauseu ac Amplitude less than u ab The current rise slope compared to the previous active vector I The duration of the 6th phase of action is reduced, and the duration of this phase is... d c T s ,correspond Figure 5 The mode is shown in Figure (b). Subsequently, the third active vector switches to... I 6, u ab The high amplitude makes u Ld = u ab - u o If the current is greater than 0, the inductor current continues to rise with an increasing slope, and the duration of action is 0.5 seconds. d b T s The operating characteristics of the subsequent zero-vector phase of the switching cycle remain consistent with Area 1: first, a - vector is applied across the inductor. u o Voltage, i Ld Descending to zero (duration is) d 2 T s ,correspond Figure 5 (c) diagram mode), then i Ld =0 and u Ld =0, the system uses Figure 5 The mode shown in Figure (d) operates until the end of this switching cycle. The inductor state equation for this interval is consistent with formula (16).

[0059] When the switching cycle is in Area 3 and Area 4, the operating modes are similar to those in Area 2 and Area 1, respectively, with only the active vector changing. I 1. I 6. The order of their corresponding line voltages. Ignoring losses, the differential equations for inductor voltage and current in Area 3 and Area 4 over one switching cycle satisfy:

[0060] (17) The result is consistent with formula (16). Due to symmetry, formula (16) can be generalized to the entire operating cycle. For d 1. Extending this to the entire operational cycle, it is not difficult to obtain...

[0061] (18) in δ ( t )for: (19) 2. System Modeling, Analysis, and Simplification under DCM The above analysis of the KVL differential equations of the inductor element was based on modal decomposition and the state-space averaging method. Next, the voltage and current differential equations of the capacitor element were analyzed and extended to the entire system.

[0062] It should be noted that the core limitation of the state-space averaging method under DCM is that this method only averages the system matrix parameters, and does not necessarily perform averaging operations on the state variables themselves. Based on the above modal analysis, i Ld exist Figure 5 The value is 0 in mode (d) and is not related to capacitance. C d and load R d This forms a loop, and the duration of this mode is 1- d 1- d 2. If the state-space averaging method is used to compose the KCL equations, we can obtain:

[0063] (20) However, the value of the average inductor current at this point depends on the combined effect of system parameters and duty cycle. Under CCM, the product term... d · i Ld The product of the average value and the average values ​​of all variables is equal, therefore the solution results of the state-space averaging method and the formal averaging method of circuit equations are consistent; conversely, in the DCM mode, the product term ( d 1 +d 2)· i Ld The product of the average value and the average values ​​of all variables differs significantly, causing the calculation results of the two averaging methods to be no longer equivalent. Therefore, it is necessary to characterize the state within the zero-state interval of the zero vector.

[0064] analyze Figure 4 Connect the points with blue dashed lines. d 0 T s / 2, 0) and (( d 0 / 2+ d 1) T s , i pkDue to geometric symmetry, the area formed by the blue dashed line and the inductor current waveforms above it is equal to the area formed by the inductor current waveforms below it. Therefore, the average current... i Ld exist T s The area of ​​the rectangle enclosed over time, and the point ( d 0 T s / 2, i pk ), (( d 0 / 2+ d 1) T s , i pk )and(( d 0 / 2+ d 1+ d 2) T s The triangles formed by , 0) have equal areas, that is... i Ld and i pk The relationship is:

[0065] (twenty one) Consider a general scenario: when the topology is in an active vector working state and a zero vector state. d 2. Interval (time interval is) t ∈[ d 0 T s / 2, ( d 0 / 2+ d 1+ d 2) T s ]),capacitance C d With inductance L d A valid electrical connection is formed, at which point the current flows into the capacitor. C d The current at point A is not necessarily equal to the average inductor current. Given the rapid dynamic change of the inductor current during a switching cycle, a current-voltage relationship equation for the capacitor needs to be constructed based on the law of charge conservation, and then averaged. In this scenario, the total charge transferred from the inductor to the capacitor during one switching cycle is equal to the current at point B. d 0 T s / 2, i pk ) 、(( d 0 / 2+ d 1) Ts , i pk )and(( d 0 / 2+ d 1) T s Area of ​​the triangle formed by (0, 0):

[0066] (twenty two) Consider load R d Then the net charge delivered to the capacitor is (twenty three) Combining equation (21), we obtain the differential equation of capacitance current KCL that satisfies the charge conservation condition: (twenty four) Comparing formulas (20) and (24), we can see that, based on the state-space averaging equation, for i Ld Multiplied by gain 1 / ( d 1+ d 2). More generally, the actual average charging current of the capacitor connected to the inductor differs from the average current as described above. Due to these differences, the response expected to be defined by the original state-space average model (Equation (20)) will not match the actual average response of the converter. Therefore, modifications are needed to correct this mismatch. That is, for all discontinuous inductor currents occurring throughout the system, multiply by 1 / ( d 1+ d 2) The gain coefficient. Therefore, neglecting inductor line losses and capacitor parasitic resistance, the original equation can be written as:

[0067] (25) The model is reduced in order, that is, the newly added variables are processed. d 2. If volt-second balancing is used to process the input and output voltages... d 1, d The relationship between 2, that is

[0068] (26) This will cause the equations to degenerate, and the dynamic characteristics of the inductor current will disappear. This is because it is assumed here that... d 2 will follow d 1. Based on the current voltage relationship, a corresponding linear change occurs, but... d 2 itself exhibits a nonlinear response process, which is ignored here. Therefore, a substitution is needed to establish... d 2 and i Ld The relationship.

[0069] Further analysis Figure 4 Peak inductor current i pk satisfy: (27) Combining formula (20), we can obtain: (28) Therefore, the original system equations can be simplified to: (29) By using the state-space averaging method, the system state equations under CCM satisfy the following: (30) Throughout the entire system operation process, regardless of whether it's in a zero state, zero input, or any other initial state, the response is not always in a DCM or CCM state. The two states switch only when critical conditions are met. i Ld Does the magnitude satisfy the continuous conduction state? The system equations for the entire system throughout the entire process can be described as:

[0070] (31) Condition switching function ξ satisfy: (32) Considering the basic characteristics of a three-phase PFC, since its power factor PF is essentially 1.0, meaning the reactive power component approaches 0, and in a two-phase rotating coordinate system, the q-axis reactive component itself exhibits high stability, and the gain coefficient of the q-axis-d-axis coupling term is very low, its equivalent single-phase DC-DC model can be derived based on the dynamic characteristics of the d-axis active power component. Its system equations can be derived as follows: (33) Where the equivalent input voltage e n Filter inductor current i Ln Bridge arm terminal voltage u m satisfy: (34) AC filter equivalent parameters L fn , C fn Converted to: (35) Condition switching function ξ satisfy: (36) Because formula (19) describes δ ( t Given that the system is an explicit time function, the state equations under DCM (Dynamic Management Communication) exhibit characteristics of a periodically driven, non-autonomous, nonlinear system with piecewise smooth time. Direct analysis of this system is too complex and unsuitable for engineering applications; therefore, a different approach is considered. δ ( t Fourier decomposition is performed, and by converting it into a constant or a polynomial, the system of formula (30) is transformed into an autonomous system or a continuously differentiable non-autonomous system, and its rationality is verified.

[0071] Assume the starting point of time is sin( ωt The zero point of ) can be obtained δ ( t ) is a period of 6 ω The even function, its Fourier decomposition is: (37) in: (38) Set the highest level number N The transformation effect is as follows: (The numbers are 0, 1, and 2.) Figure 6 As shown.

[0072] Substitute it into the full-condition process system described by formulas (34) and (35) for comparison, and build the following in Simulink: ① PFC switch topology model based on ideal device SVPWM modulation; ②The three-phase system model described in formula (31) retains δ ( t Piecewise smooth non-autonomous systems; ③The equivalent DC-DC Buck model described in formula (33) retains δ ( t Piecewise smooth non-autonomous systems; ④ Formula (33) is equivalent to the DC-DC Buck model, where... δ ( t ) converted to N =1 Fourier decomposition, the system is a non-autonomous system that contains explicit time functions but is continuously differentiable; ⑤ Formula (33) is equivalent to the DC-DC Buck model, where... δ ( t ) converted to N =2Fourier decomposition, the system is a non-autonomous system that contains explicit time functions but is continuously differentiable; ⑥ Formula (33) is equivalent to the DC-DC Buck model, where... δ (t ) converted to N =0 Fourier decomposition, i.e. constant term, the system is an autonomous system that does not contain explicit time functions; The operating parameters are set as shown in Table 2 below, and the DC-side load is configured. R d It is 4000Ω.

[0073] Table 2 System Topology Parameter Given Table The response comparison conditions are set as follows. Due to the zero-input response... m When the input is 0, the system behaves as a discharge process of the energy storage element, which is no different from the CCM state; therefore, zero-input response is not considered. Set the control quantity. m Given settings:

[0074] (1) 0.00s, zero-state response, m Set the step size to 0.0 → 0.2; (2) 0.05s, full response, m Set the step size to 0.2 → 0.3 upwards; (3) 0.05s, full response, m Set the step size to 0.2 → 0.3.

[0075] The simulation results of the observed system are as follows: First, compare the results of the original switch topology ① with the three-phase system model ② on the AC side, such as... Figure 7 Figures (a) and (b) show the following respectively: u mx ( x =a,b,c) and i Lx ( x =a,b,c), and its transient and steady-state results are basically consistent.

[0076] Compare the results of the original switch topology ①, the three-phase system model ②, and the equivalent Buck ③ and its further simplified models ④~⑥ on the AC side.

[0077] like Figure 8 Figures (a), (b), and (c) show the following: m Operating Condition Setting (1) i Ld and u o Throughout the entire process, including transient and steady-state waveforms, it can be observed that the zero-state response first enters the CCM state, and then enters the DCM state when the voltage rises to around 95V. The waveforms of models ② to ⑥ are basically consistent with the output of topology ①, with a voltage error of no more than 0.53%.

[0078] like Figure 8 Figures (d), (e), and (f) show the following figures respectively: m Operating Condition Setting (2) i Ld and u o The entire process of DCM, transient and steady-state waveforms, the waveforms of model ②-⑥ are basically consistent with the output of topology ①, and the voltage error does not exceed 0.04%.

[0079] like Figure 8 Figures (g), (h), and (i) show the following: m Operating condition setting (3) i Ld and u o The entire process of DCM, transient and steady-state waveforms, the waveforms of model ②-⑥ are basically consistent with the output of topology ①, and the voltage error does not exceed 0.06%.

[0080] Based on the above model analysis, the inductor current of the autonomous system in Model ⑥ lacks AC information at the sixth harmonic on the power frequency scale. However, its response throughout the entire process is basically consistent with the other non-autonomous models, meaning that the explicit time function of the non-autonomous system has little impact on the system's response. The transient step process curve of Model ⑥ basically reflects the characteristics of the original system. i Ld The steady-state value has an error of no more than 0.1% compared to the RMS values ​​of the other waveforms. Therefore, according to formula (38), we can take... δ ( t constant term a 0 / 2 = 3 / π, formula (33) describes the DCM part of the system as transforming it into an autonomous nonlinear system:

[0081] (39) Let the state vector be x =[ i Ln , u m , i Ld , u o ] T Input vector u =[ e n , m ] T Solve for the steady-state operating point =0. Let the steady-state values ​​of the state variable and the input be respectively... U m , I Ln , ILd , U o , E n , M The input-output ratio is obtained as follows:

[0082] (40) Among them, the coefficients related to the operating conditions G for: (41) like Figure 9 The following are the different G Value M and M v The relationship curve. When M v and M exist M There are intersections within the range of values ​​(0,1). M c When, greater than the intersection point M c Then it becomes the CCM state.

[0083] It is easy to see that for a given G , M c satisfy: (42) Therefore G When the value is less than (2-6 / π)≈0.0901, the system will always be in the DCM state.

[0084] The remaining steady-state quantities are: (43) set up u m and i Ld Integral function f um , f iLd for: (44) By performing small-signal linearization on the nonlinear system near the steady-state point shown in equation (43), the disturbance state vector can be obtained. =[ , , , ] T Input vector =[ , ]T satisfy: (45) The state matrix A n With input matrix B n They are respectively: (46) (47) in f um The steady-state partial derivative is: (48) f iLd The steady-state partial derivative is: (49) Ignore input voltage disturbances ,Will B n Matrix transformation only about input matrix B n_m have to: (50) Solving for the disturbance of the adjustment system exist s Domain to output The transfer function can be set as follows: the output matrix is... C n Its transfer function general solution is: (51) In the formula I It is an identity matrix.

[0085] Specifically, for the system corresponding to the parameters in Table 2, the front-end LC filter circuit is designed for a 200kHz switching frequency, and its resonant frequency range is 0.1 to 0.2 times the switching frequency (i.e., 20kHz to 40kHz). This resonant frequency is still in the high-frequency range, and its frequency domain characteristics show a significant resonant peak at the resonant frequency, while its influence on other high and low frequency ranges is negligible. Therefore, when constructing the DC equivalent model of this system, a direct order reduction can be performed: only the characterization of the inductor current is retained. i Ld With output voltage u o The system equations are derived using a state matrix. A n With input matrix B n_m submatrix An [3,4;3,4] and B n_m [3,4] Perform modeling calculations and output the matrix. C n The dimension is reduced accordingly.

[0086] For the dimensionality-reduced model, let C n =[0,1], solving equation (40) simultaneously yields the modulation disturbance. To output voltage disturbance transfer function G um ( s )for: (52) It is easy to verify that, for this topology, assuming reasonable parameter and operating condition design, the following assumptions hold: (53) Therefore, based on this assumption, the original transmission function can be further reduced to: (54) System gain K n ,pole ω p1 As shown in formula (3), the poles ω p2 for: (55) like Figure 10 Bode plots representing the fourth-order system of formula (51), the second-order system of formula (52), and the double-pole system of formula (54) are given, with the relevant parameters set according to Table 2 and the output voltage set to 200V. Figure 10 In Figure (a), the power is set to 10W, corresponding to a load of 4000Ω; Figure 10 In graph (b), the power is set to 50W, corresponding to a load of 800Ω. The three curves show a good match, meeting expectations. This is easily verified under DCM conditions. ω p2 >> ω p1 Therefore, in the mid-to-low frequency region, it approximately exhibits characteristics dominated by the dominant pole. ω p1 The first-order system represented.

[0087] 3. Design of PI controller under DCM A compensation controller design is carried out for a three-phase PFC rectifier under DCM. As the above analysis shows, the open-loop transfer function bandwidth from the modulation scheme to the output voltage in DCM mode is significantly lower, much smaller than the transfer function bandwidth of the three-phase PFC rectifier under CCM. If the voltage-current dual closed-loop control strategy is used, the bandwidth of the three-phase PFC rectifier will be further reduced, resulting in significantly insufficient anti-interference capability; furthermore, the actual system's equation (19) characterizes… δ (t) The presence of a time-dependent term makes it impossible to obtain a constant average current command within each control cycle. Furthermore, electromagnetic interference is more severe in DCM mode, leading to a decrease in sampling accuracy. In summary, for DCM operation under extremely light load or no-load conditions, using only single-voltage-loop compensation control can better meet the design requirements.

[0088] First, a compensation controller is designed to address disturbances near the steady-state operating point. The transfer function shown in equation (54) is corrected according to a typical second-order open-loop system. Let the corrected open-loop transfer function of the system be:

[0089] (56) in K r For gain coefficient, ω r To configure the poles, its closed-loop system is as follows: (57) in ω n The resonant frequency of the closed-loop second-order system. ξ Let be the damping ratio. Select the optimal second-order system damping ratio. ξ =1 / =0.707, at this point we can obtain:

[0090] (58) Therefore, formula (56) can be transformed into: (59) Assume the system cutoff frequency is ω c Let Abs( G r (j ω ))=1, which can be solved to get ω c and ω r The relationship satisfies formula (2).

[0091] Considering only the dominant pole ω p1 By combining equations (54) and (59), the correction controller can be obtained.G c (s) is: (60) By designing the corrected system G r (s) System bandwidth, i.e., adjustable cutoff frequency ω c Thus, the control expression satisfying the optimal second-order system can be obtained (Formula (60)). It can be regarded as a combination of a PI controller and a low-pass filter (LPF), where the zeros of the PI controller are used to cancel the large inertia element of the original system, and the LPF is used to suppress the disturbance in the high-frequency part after the cutoff frequency. In summary, under DCM, the cutoff frequency of LPF is ω r Single voltage loop PI controller K p_D , K i_D As shown in formula (4).

[0092] proportionality coefficient K p With integral coefficient K i This is a function dependent on the steady-state input and output voltages, system topology parameters, and load parameters. The steady-state input and output voltages can be obtained through sampling and pre-setting, while the system topology parameters can be determined experimentally. However, in actual operating conditions, the load parameters... R d It is difficult to detect directly; it requires the steady-state inductor current. I Ld Indirect estimation, i.e., based on the derivation of Ohm's law. R d = U o / I Ld The load resistance is calculated. However, this estimation method has clear constraints: first, the system must reach steady state before parameter calculation; second, the calculation period and rate of change of the load parameters must be sufficiently slow to reduce disturbances to the system's nonlinear stability. Before the system reaches steady state and the load parameters are estimated, a set of general initial parameters needs to be set to cover the initial adjustment process under all operating conditions. Therefore, a systematic analysis for different load conditions is required to provide theoretical support for the optimized design of the general initial parameters.

[0093] First, according to formula (42), in determining E n and U o That is, to determine Mv In the case of a DCM state, the intersection point M c Must be greater than or equal to M v , can be obtained R d Minimum value of the range of values R d_min As shown in formula (5).

[0094] Let the effective value of the AC input phase voltage be... V rms The range is 85~140V (rated 115V), corresponding to the equivalent DC model input voltage range. E n The voltage is 180~297V (rated 244V), and the output voltage is set as shown in formula (1).

[0095] By combining formulas (40), (41), (1), (4), and (5), we can obtain K p_D , K i_D and E n , R d Relationship such as Figure 11 As shown in Figure (a), K p_D / ω r Follow E n , R d The changing trend is shown in Figure (b). K i_D / ω r The changing trend is shown in the figure. K p_D , K i_D Divided by bandwidth correlation coefficient ω r This only reflects the correlation trend between voltage and load changes. It can be seen that as the load increases, K p_D / ω r rise, K i_D / ω r The voltage decreases; while as the input voltage increases, K p_D / ω r decline, K i_D / ω r Rise. Consider the specified voltage. K p_D , K i_D The effect of changes on transfer function correction, such as Figure 12 As shown, (a) demonstrates K p_D The impact of the changes is shown in Figure (b). K i_D The impact of change.

[0096] Depend on Figure 12 We can obtain, K p_D Setting it too large will decrease the phase margin (PM), while setting it too small will result in insufficient bandwidth. Therefore, for any voltage level, a value of [value missing] can be considered. R d =around 2000-4000Ω K p_D As the initial value. And for K i_D Its reduction will lead to a decrease in DC gain, therefore it can be directly taken as... R d_min time K i As initial parameters. In fact, for projects with less stringent response requirements, the initial parameters are generally sufficient to meet the design needs.

[0097] 4. Design of Variable Gain Dual-Loop Control Algorithm under Wide-Range DCM & CCM Operating Conditions Figure 13 This is a schematic diagram of a zero-state response operation of a dual-closed-loop control architecture; where (a) shows the operation result of heavy-load CCM and (b) shows the operation result of extremely light-load DCM. The controller is designed for the entire operating condition and process under a wide range, including extremely light-load startup and switching between heavy and light loads. For the system represented by formula (32), it is clear that using a voltage-current dual-closed-loop control is more suitable under CCM conditions, such as... Figure 13 As shown in Figure (a). Based on the preceding reasoning, it is proven that using a single voltage loop for control compensation under DCM is more suitable. However, there are issues with loop output selection and critical switching between the two approaches.

[0098] If three loops are executed simultaneously, namely the voltage and current loop under CCM and the voltage loop under DCM, and then switched according to formula (36), the calculation load will be too large and a hard shear impact will occur.

[0099] In fact, at the initial stage of zero-state response, the system operates in CCM mode, such as... Figure 13 In Figure (b), 0~t As shown in stage 1, if only a single voltage loop control is used in this stage, it is difficult to effectively suppress the current surge during startup; and given that the load parameters are unknown during startup, a voltage-current dual closed-loop control strategy should be prioritized. For a dual closed-loop system in CCM mode, the voltage loop output is the DC-side inductor current loop command. i ref Under ideal operating conditions, this command should be related to the steady-state inductor current. I Ld Towards consensus.

[0100] When the system is under extremely light load conditions (i.e., high load resistance) R d > R d_min When ), the output capacitor C d With load resistance R d The inertial loop has a large time constant, and the voltage loop cannot raise the output voltage to the target value in a short time. U ref This leads to a current command. i ref It increases significantly and tends to saturate. Although i ref The value is high, but the extremely light load characteristics make it difficult for the actual inductor current to reach the commanded value, which in turn affects the controller output modulation. m Entering a saturated state, such as Figure 13 In Figure (b) t 1~ t As shown in stage 2.

[0101] When the output voltage is close to or exceeds U ref At that time, the voltage loop output i ref It will drop rapidly from the saturation value to 0, and then gradually converge to the steady-state value in the subsequent process. I Ld At this time, the steady-state current I Ld The current has become consistent with the actual inductor current, resulting in a slow decrease in the current loop output, such as... Figure 13 In Figure (b) t 2~ t As shown in the three stages. Combined Figure 9 As can be seen from the characteristic curve, under DCM steady-state conditions, the modulation index M required to achieve the specified turns ratio Mv is less than the required value under CCM mode with the same turns ratio. Therefore, before the current drops to 0 or is less than the command value during this stage, the output voltage will continue to rise until the current and control quantity return to the normal operating range.

[0102] From a frequency domain perspective, the above research shows that the voltage loop itself has a low bandwidth. Introducing the current loop is equivalent to connecting a low-pass filter in series in the control link, further reducing the overall system bandwidth. The voltage drop process mainly depends on the output capacitor. C d With load resistance R d The energy is consumed by the output impedance, and the voltage drop slope is gradual and the duration is relatively long.

[0103] In summary, based on dual-loop control, a method is proposed to multiply the output of the voltage loop by a specific competing gain coefficient. K m The output of the single voltage loop is directly used as the output of the voltage loop, and compared with the output of the voltage and current loops to determine the smaller value, thus obtaining the reconstructed variable gain dual-loop competition algorithm. Let the proportional-integral coefficients of the voltage loop in dual-loop control be... K p_C , K i_C The output is Out_U ; proportional-integral coefficient of current loop K p_I , K i_I The output is Out_I The final output of the control loop... m This is shown in formula (9).

[0104] There are three main technical issues in this regard: First, the competition gain coefficient. K m How to adapt to the separation critical point of CCM and DCM, and how to solve the critical oscillation problem; second, the voltage loop... K p , K i How to coordinate variable gain between CCM and DCM states; third, how to further improve the current loop to optimize dynamic performance during the switching between CCM and DCM, especially during the switching between no-load and full-load conditions under extreme operating conditions.

[0105] Regarding the first technical issue, when the voltage loop output... Out_U When used as an input to the current loop, its physical meaning is the current command value. i ref In steady state, it is the steady-state inductor current value. I Ld When used as the output of a single voltage loop, its value represents the modulation index, specifically its steady-state value. M The input-output ratio is adapted according to formula (40). M v The critical point is when... Rd equal R d_min time I Ld After multiplying by the gain K m It satisfies the condition of formula (5), that is:

[0106] (61) achievable K m The expression is shown in formula (6).

[0107] The critical point of inductor current is easily obtained. I Ld = M v / K m .

[0108] Regarding the critical oscillation problem in formula (9), where the voltage and current loop outputs are very close, the values ​​will repeatedly enter different states at the critical point. This can be solved by hysteresis comparison. That is, set a hysteresis threshold γ. When the system is determined to be in CCM state, if... K m · Out_U≤ ( Out_I-γ ), determine if the system is in DCM state; when the system is determined to be in DCM state, if K m · Out_U> ( Out_I+γ ), determines whether to enter CCM.

[0109] Regarding the second technical issue, when determining the voltage loop correction parameters in the dual-loop configuration, it is advisable to set its integral coefficient. K i_C = K i_D / K m The system response under CCM condition was verified to be as expected. Thus, in the single voltage loop, its integral coefficient is equivalent to the previously designed... K i_D Parameters. This way, only the scaling factor needs to be adjusted. K p Process it.

[0110] In the dual-loop configuration, to reduce the outer loop bandwidth and increase the phase margin, the voltage loop gain coefficient is... K p_C The coefficient is relatively small, while in a single-ring configuration, it is used to increase the bandwidth of the DCM system. K p_D The voltage loop proportionality coefficient is relatively large; therefore, the following voltage loop proportionality coefficient can be designed. Kp A schematic diagram of the variable structure value retrieval logic curve, as shown below. Figure 14 As shown: When the system operates in current loop mode, i.e., dual voltage and current closed-loop operation, the voltage loop... K p Equal to K p_C When the system has a single voltage loop output, if the absolute value of the error is less than the threshold... ε 1, K p is taken as K p_D This also satisfies the design range for local linearization; if the absolute value of the error exceeds the threshold... ε 2, K p Take as K p_C The middle part represents a transitional state. K p The value satisfies formula (7).

[0111] Regarding the third technical issue, since the current loop has no output behavior in DCM single-voltage loop control, continued operation will lead to output instability when switching back to voltage and current dual-loop control. As discussed earlier, the current loop output is the modulation index in CCM state, which is always equal to... M v Therefore, when using a single voltage loop output, the current loop integral term and the output term can be kept constant. M v This is to accelerate the response speed of DCM and CCM switching, especially during load shearing.

[0112] Furthermore, for operating conditions switching from light load to heavy load, after switching back to the current loop output, the voltage loop bandwidth is low at this time, while the actual current is large due to the load input. Therefore, the target value for the current loop will be lower than the actual current for a certain period, which will affect the output modulation. m This decrease leads to a voltage drop. Therefore, the magnitude of the current loop integral coefficient can be adjusted according to the polarity of the current loop input error to make the error less than 0. K i_I Reduce the voltage drop to minimize its extent.

[0113] The overall control architecture of this invention is as follows: Figure 15 As shown, the operating logic is as follows: (1) For a full topology system such as Figure 2 As shown, the sampled input voltage e x ( x =a,b,c), and its amplitude can be obtained. E mThe equivalent input voltage can be obtained according to formula (34). e n In steady state, it is E n The target output voltage can be calculated according to formula (1). U o The ideal ratio can be obtained according to formula (40). M v (Input / output ratio).

[0114] (2) Preset cutoff frequency under DCM ω c According to formula (2), the LPF cutoff frequency can be obtained, which is the open-loop pole configuration of the target system. ω r Calculate the preset value of PI parameter under DCM: Let... R d =2000~4000Ω, 3500Ω can be selected, combined with E n and M v Calculated using formula (3) R d System gain at 3500Ω K n With the extreme point ω p1 The control coefficients of the PI controller are calculated using formula (4). K P_D ; calculated using formula (5) R d Minimum value of the range of values R d_min , combined E n and M v Calculated using formula (3) R d = R d_min Below K n and ω p1 The control coefficients of the PI controller are calculated using formula (4). K i_D .

[0115] (3) Sample the DC side output voltage u o and DC side inductor current i Ld The current voltage loop proportional coefficient is calculated using formula (7). Kp The default initial stage is CCM. K m · Out_U>Out_I ; through form K i_C = K i_D / K m Calculate the target integral coefficient K i ,pass M v A certain margin (e.g., 0.08) is added to set the voltage loop's anti-integral saturation value and output limiting. The voltage loop PI output serves as the current loop input, and the aforementioned mechanism determines whether the current loop's integral and output values ​​need to be maintained. The voltage loop PI output passes through a cutoff frequency of... ω r The low-pass filter, multiplied by the competition coefficient K m To obtain the single voltage loop output K m · Out With current loop output Out_I Following the aforementioned mechanism, a hysteresis comparison is performed, and the smaller value is taken as the final control loop output.

[0116] In one embodiment, the present invention also provides a variable gain dual-loop control method for a three-phase PFC rectifier in intermittent conduction mode. This method is applied to aerospace airborne power supplies, marine special power supplies, industrial modular power supplies, and server power supply systems. It aims to solve problems such as hard impact during DCM and CCM mode switching of three-phase Buck-type PFC rectifiers, large overshoot during light load start-up, insufficient dynamic response during high load shearing, and voltage transient oscillation. This embodiment includes the following steps: S1. Refined analysis of DCM operating modes and simplified modeling: Decompose the four operating modes within the DCM switching cycle, divide the region according to the relationship between bridge arm line voltage and output voltage, and derive the differential equations of inductor voltage and current; improve the state-space averaging method and combine it with Fourier decomposition, introduce the gain coefficient to correct the capacitor current equation, and combine Fourier decomposition to transform the non-autonomous system into an autonomous system to simplify the modeling, so as to achieve accurate and simplified modeling of the nonlinear system of DCM mode, and provide a reliable theoretical basis for subsequent control strategy design.

[0117] S2. Based on a typical optimal second-order model, a dedicated compensation controller for DCM is designed. The compensation controller includes a PI controller and a low-pass filter. The zero point of the PI controller is used to cancel the large inertial element of the system, and the low-pass filter is used to suppress high-frequency disturbances after the cutoff frequency, so as to achieve the cancellation of the large inertial element and the suppression of high-frequency disturbances in DCM mode. The correlation expressions between the controller parameters and the input voltage and load are derived, and the general initial parameter selection principle is determined to ensure effective regulation before steady state.

[0118] S3 proposes a variable gain dual-loop competitive control strategy: a competitive gain coefficient Km and hysteresis comparison mechanism are designed, and a variable gain dual-loop competitive control algorithm framework is constructed, enabling the CCM voltage loop output to pass through... K m After adaptation, it competes with the current loop output for a smaller value, thus achieving an equivalent replacement of the DCM single voltage loop function without the need to construct an additional loop; hysteresis threshold is configured. γ This addresses the oscillations in critical operating conditions and avoids hard shear shocks.

[0119] S4 optimizes the parameter matching of the voltage loop and current loop, and solves the critical oscillation problem by configuring a hysteresis switching mechanism: the voltage loop adopts a variable structure Kp design, and takes the value during dual closed-loop operation. K p_C When operating in a single voltage loop, the error threshold is used. K p_C and K p_D Intermittent transition; in DCM mode, the integral term and output term of the current loop are kept constant, and dynamically adjusted according to the polarity of the current loop error. K i_I To achieve coordinated adaptation of parameters between CCM and DCM modes, suppressing voltage overshoot under extremely light load startup, as well as voltage overshoot or drop during load switching. A variable proportional coefficient structure design for the voltage loop, optimized integral coefficient adaptation for the current loop, and an integral and output hold strategy in DCM mode are employed to achieve wide-condition adaptive control.

[0120] S5 integrates the above technologies to build a full-condition adaptive control architecture. It combines modal analysis, model simplification, dedicated controllers and dual-loop competition strategy to build a control architecture that covers all operating conditions from ultra-light load start-up to load switching. Through mode switching logic and parameter adaptive adjustment, it achieves seamless connection between DCM and CCM to achieve full operating condition coverage from ultra-light load start-up to load switching, and adapts to wide input voltage and load change requirements.

[0121] Compared with the prior art, the present invention has the following advantages: 1) The disturbance observation feedforward compensation control method for three-phase PFC rectifiers under wide frequency conversion input proposed in this invention effectively solves the problem of complex nonlinear modeling in DCM mode, transforms the non-autonomous system into a simple autonomous system, and provides accurate and practical theoretical guidance for the controller design of three-phase PFC rectifiers in DCM mode.

[0122] 2) The disturbance observation feedforward compensation control method for three-phase PFC rectifiers with wide frequency conversion input proposed in this invention significantly reduces the amount of calculation compared with the traditional multi-loop scheme, while significantly improving dynamic performance, effectively suppressing the start-up overshoot under extremely light load and the hard impact of mode switching, and optimizing the response performance during load switching.

[0123] 3) The disturbance observation feedforward compensation control method for three-phase PFC rectifiers under wide frequency conversion input proposed in this invention is adapted to the wide input voltage and load change requirements, and solves the problem that traditional control is difficult to cover the full range of operating conditions from extremely light load to heavy load, thus ensuring the steady-state stability and dynamic adjustment capability of the system under a wide range of operating conditions.

[0124] In one embodiment, the method of the present invention is further verified by simulation. The simulation is built in Simlulink, and the system topology parameters and three sets of simulation conditions are given in the following table: Table 3 System Topology Parameter Given Table The control parameters, after calculation and adjustment, are given as follows: Table 4 System Control Parameter Setpoint Table The three operating conditions in Table 3 were simulated using traditional dual-loop and dual-loop competition methods, respectively. The tests were conducted sequentially at different voltage levels for very light load start-up, light-to-heavy load switching, and heavy-to-light load switching, and the waveforms were recorded as follows: Figure 16 As shown, Figure 16 The waveforms show the dynamic response comparison of the traditional dual-loop and variable-gain dual-loop competition strategies under three different operating conditions. Figures (a), (b), and (c) correspond to operating condition 1; figures (d), (e), and (f) correspond to operating condition 2; and figures (g), (h), and (i) correspond to operating condition 3. These figures respectively demonstrate the competition between the traditional dual-loop and dual-loop strategies during light-load start-up, light-to-heavy-load switching, and heavy-to-light-load switching. u o and i Ld The differences, and the relationship between the output control quantities of the dual-loop competing loop.

[0125] Table 5 shows the relevant data, indicating that the improved "dual-loop competition" method significantly outperforms the traditional dual-loop method in dynamic regulation performance under all operating conditions. During light-load startup, the voltage overshoot amplitude is reduced from 5.79~30.86V to 1.31~1.55V, a decrease of 77%~95%; the settling time is optimized from 90.2~312.3ms to 52.3~56.3ms, a reduction of 38%~83%. During load switching, the absolute value of the voltage overshoot during light-to-heavy switching decreases by 77%~90%, and the recovery time is compressed by 57%~64%; the voltage overshoot during heavy-to-light switching decreases by 49%~59%, and the recovery time is shortened by 83%~86%. Therefore, this method significantly suppresses voltage fluctuations, accelerates dynamic response, and greatly improves system robustness, fully meeting the stringent requirements of converters for voltage stability and response rate.

[0126] Table 5 Comparison and Analysis of Results In summary, this invention addresses the control challenges of three-phase Buck PFC rectifiers under a wide range of DCM and CCM operating conditions. By refining the analysis of DCM operating modes, improving the state-space averaging method, and combining Fourier decomposition to simplify system modeling, it proposes a control strategy based on variable gain dual-loop competition. Through designing competitive gain coefficients, the outer voltage loop output of the voltage and current dual closed loops, after gain adaptation, effectively replaces the function of the single voltage loop that originally required separate configuration. This eliminates the need to construct an additional single voltage loop, significantly reducing computational load compared to the original three-loop competition scheme. Simultaneously, it adapts to the wide operating conditions of varying input voltage and load. Combined with a hysteresis switching mechanism and current loop parameter optimization strategy, it effectively solves problems such as hard impact during mode switching, overshoot at light load startup, and response defects under wide-range load shearing in traditional dual-loop control. This significantly improves the system's dynamic response and steady-state stability, providing a feasible technical path for efficient control of similar power electronic converters under wide operating conditions.

[0127] When applying the three-phase PFC rectifier variable gain dual-loop control method in intermittent conduction mode provided in this manual, it is not necessary to follow the... Figure 1 The steps shown are executed in sequence. The specific execution order of each step can be determined as needed, and this manual does not impose any restrictions on it.

[0128] The above describes one or more embodiments of a three-phase PFC rectifier variable gain dual-loop control method in intermittent conduction mode provided in this specification. Based on the same idea, this specification also provides a corresponding three-phase PFC rectifier variable gain dual-loop control device in intermittent conduction mode, which includes: The acquisition module is used to acquire the input voltage of the three-phase power factor correction rectifier and determine the input-output ratio of the three-phase power factor correction rectifier based on the input voltage. The first calculation module is used to calculate the proportional coefficient of the single voltage loop PI controller under the load resistance value based on the system cutoff frequency of the three-phase power factor correction rectifier in the intermittent conduction mode, and to determine the minimum load resistance value based on the input-output ratio and the load resistance value, and to calculate the integral coefficient of the single voltage loop PI controller under the minimum load resistance. The second calculation module is used to determine the competing gain coefficient based on the DC-side inductance and input-output ratio of the three-phase power factor correction rectifier. The third calculation module is used to determine the target proportional coefficient based on the competitive gain coefficient, the proportional coefficient of the single voltage loop PI controller under the load resistance value, and the proportional coefficient of the voltage loop PI controller of the three-phase power factor correction rectifier under dual-loop control; and to determine the competitive gain coefficient based on the steady-state inductor current value and the input-output ratio; and to determine the target integral coefficient based on the competitive gain coefficient and the integral coefficient. The fourth calculation module is used to use the target proportional coefficient and the target integral coefficient as the control coefficients of the current voltage loop PI controller, determine the control output of the current voltage loop, and multiply the control output of the current voltage loop by the competing gain coefficient to determine the target control output of the current voltage loop. The determination module is used to determine the minimum value between the target control output of the current voltage loop and the control output of the current current loop as the control signal for the three-phase power factor correction rectifier.

[0129] Specific limitations regarding the three-phase PFC rectifier variable gain dual-loop control device in intermittent conduction mode can be found in the above description of the limitations of the three-phase PFC rectifier variable gain dual-loop control method in intermittent conduction mode, and will not be repeated here. Each module in the aforementioned three-phase PFC rectifier variable gain dual-loop control device in intermittent conduction mode can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in a computer device, or stored in software in the memory of a computer device, so that the processor can call and execute the corresponding operations of each module.

[0130] This specification also provides a computer-readable storage medium storing a computer program that can be used to execute the above-described... Figure 1 A variable gain dual-loop control method for a three-phase PFC rectifier in intermittent conduction mode is provided.

[0131] This instruction manual also provides Figure 17 The schematic diagram of the computer device shown is as follows: Figure 17 At the hardware level, the computer device includes a processor, internal bus, network interface, memory, and non-volatile memory, and may also include other hardware required for business operations. The processor reads the corresponding computer program from the non-volatile memory into memory and then runs it to achieve the above-mentioned functions. Figure 1 A variable gain dual-loop control method for a three-phase PFC rectifier in intermittent conduction mode is provided.

[0132] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0133] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A variable gain double-loop control method for a three-phase PFC rectifier in discontinuous conduction mode, characterized in that, include: Obtain the input voltage of the three-phase power factor correction rectifier, and determine the input-output ratio of the three-phase power factor correction rectifier based on the input voltage; Based on the system cutoff frequency of the three-phase power factor correction rectifier in discontinuous conduction mode, calculate the proportional coefficient of the single-voltage loop PI controller under the load resistance value, and determine the minimum load resistance value based on the input-output ratio and the load resistance value, and calculate the integral coefficient of the single-voltage loop PI controller under the minimum load resistance. The competing gain coefficient is determined based on the DC-side inductance and input-output ratio of the three-phase power factor correction rectifier. The target proportional coefficient is determined based on the competitive gain coefficient, the proportional coefficient of the single voltage loop PI controller under the load resistance value, and the proportional coefficient of the voltage loop PI controller of the three-phase power factor correction rectifier under dual-loop control. The competitive gain coefficient is determined based on the steady-state inductor current value and the input-output ratio. The target integral coefficient is determined based on the competitive gain coefficient and the integral coefficient. The target proportional coefficient and target integral coefficient are used as the control coefficients of the current voltage loop PI controller to determine the control output of the current voltage loop. The control output of the current voltage loop is then multiplied by the competing gain coefficient to determine the target control output of the current voltage loop. The minimum value between the target control output of the current voltage loop and the control output of the current current loop is determined as the control signal for the three-phase power factor correction rectifier.

2. The method of claim 1, wherein, Based on the input voltage, determine the input and output turns ratios of the three-phase power factor correction rectifier, including: Determine the equivalent input voltage amplitude under steady state based on the input voltage; The target output voltage of the three-phase power factor correction rectifier is determined based on the equivalent input voltage amplitude. The ratio of the target output voltage to the equivalent input voltage amplitude is determined as the input-output ratio. The formula for calculating the target output voltage is as follows: ； wherein, Vtarget is the target output voltage, Veq is the equivalent input voltage amplitude.

3. The method according to claim 2, characterized in that, Based on the system cutoff frequency of the three-phase power factor correction rectifier in intermittent conduction mode, calculate the proportional gain of the single-voltage loop PI controller for different load resistance values, including: Calculate the cutoff frequency of the low-pass filter based on the system cutoff frequency; Based on the equivalent input voltage amplitude and input-output ratio, determine the system gain of the single-voltage-loop PI controller under the load resistance value, and based on the input-output ratio and load resistance value, determine the poles of the single-voltage-loop PI controller under the load resistance value. Based on the system gain, poles, and cutoff frequency of the low-pass filter, determine the scaling factor for the load resistance value.

4. The method according to claim 3, characterized in that, The formula for calculating the cutoff frequency of a low-pass filter is: ； in, The system cutoff frequency, This is the cutoff frequency of the low-pass filter; System gain and extreme points The calculation formula is: ； in, The equivalent input voltage amplitude, For input-output ratio, In order to adjust the system, For output capacitor, Choose the value for the load resistor; proportionality coefficient The calculation formula is: 。 5. The method according to claim 4, characterized in that, Calculate the integral coefficient of the single-voltage-loop PI controller at the minimum load resistance, including: Calculate the system gain of a single-voltage-loop PI controller at the minimum load resistance. Based on the cutoff frequency of the low-pass filter and the system gain of the single-voltage-loop PI controller at the minimum load resistance, determine the integral coefficient of the single-voltage-loop PI controller at the minimum load resistance; integral coefficient The calculation formula is: ； Minimum load resistance The calculation formula is: ； in, For DC side inductance, This refers to the switching frequency.

6. The method according to claim 5, characterized in that, The formula for calculating the competition gain coefficient is: 。 7. The method according to claim 6, characterized in that, The target scaling factor for the current voltage loop The calculation formula is: ； in, This refers to the proportional gain of the voltage loop in a three-phase power factor correction rectifier under dual-loop control. This represents the absolute value of the error in a single voltage loop. and All are thresholds. , This is the control output of the current voltage loop. This is the control output of the current current loop.

8. The method according to claim 6, characterized in that, The target integral coefficient of the current voltage loop The calculation formula is: 。

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