Latch circuit and sense amplifier

Abstract

The present disclosure provides a latch circuit and a sense amplifier. The latch circuit includes: a first, a second, a third and a fourth current source; a first, a second, a third, a fourth, a fifth, a sixth, a seventh and an eighth transistor. The first and the third current source are coupled to the first output node. The second and the fourth current source are coupled to the second output node. The control ends of the first and the second transistors are coupled to the second output node. The control ends of the third and the fourth transistors are coupled to the first output node. The first and the fifth transistors are coupled in series between the power supply terminal and the first output node. The sixth and the second transistors are coupled in series between the first output node and the ground terminal. The third and the seventh transistors are coupled in series between the power supply terminal and the second output node. The eighth and the fourth transistors are coupled in series between the second output node and the ground terminal. The fifth, the sixth, the seventh and the eighth transistors are turned on or off based on a clock signal.

Description

Technical Field

[0001] The present disclosure relates to a latch circuit and a sense amplifier, and more particularly to a latch circuit and a sense amplifier with better performance. Background Art

[0002] With the development of circuit technology, latch circuits and sense amplifiers have been applied to various circuit systems. However, some latch circuits in related technologies may generate short current when switching. In addition, some sense amplifiers in related technologies may also have kickback noise problems. Summary of the invention

[0003] Some embodiments of the present disclosure relate to a latch circuit. The latch circuit includes a first current source, a second current source, a third current source, a fourth current source, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first current source and the third current source are coupled to a first output node. The second current source and the fourth current source are coupled to a second output node. The control end of the first transistor and the control end of the second transistor are coupled to the second output node. The control end of the third transistor and the control end of the fourth transistor are coupled to the first output node. The first transistor and the fifth transistor are coupled in series between a power supply terminal and the first output node. The sixth transistor and the second transistor are coupled in series between the first output node and a ground terminal. The third transistor and the seventh transistor are coupled in series between the power supply terminal and the second output node. The eighth transistor and the fourth transistor are coupled in series between the second output node and the ground terminal. The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are turned on or off based on a clock signal.

[0004] Some embodiments of the present disclosure relate to a sense amplifier. The sense amplifier includes a first comparison circuit, a logic circuit, and a latch circuit. The first comparison circuit is used to generate a first comparison signal and a second comparison signal based on a first input signal, a second input signal, and a first clock signal. The logic circuit is used to generate a first control signal, a second control signal, a third control signal, and a fourth control signal based on the first clock signal, the first comparison signal, and the second comparison signal. The latch circuit includes a first current source, a second current source, a third current source, a fourth current source, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first current source and the third current source are coupled to a first output node. The first control signal is used to control the first current source, and the third control signal is used to control the third current source. The second current source and the fourth current source are coupled to a second output node. The second control signal is used to control the second current source, and the fourth control signal is used to control the fourth current source. The control end of the first transistor and the control end of the second transistor are coupled to the second output node. The control end of the third transistor and the control end of the fourth transistor are coupled to the first output node.

[0005] In summary, in the present disclosure, the latch circuit can be prevented from generating a short-circuit current when switching, and the sensing amplifier can be improved in performance through kickback noise. Thus, the latch circuit and the sensing amplifier of the present disclosure can have better performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understood, the following are the descriptions of the accompanying drawings:

[0007] Figure 1 is a schematic diagram of a latch circuit according to some embodiments of the present disclosure;

[0008] Figure 2 is a schematic diagram of a sense amplifier according to some embodiments of the present disclosure;

[0009] Figure 3 According to some embodiments of the present disclosure Figure 2 Waveform diagrams of multiple signals in ;

[0010] Figure 4A is a schematic diagram of two comparison circuits and two logic circuits in a sense amplifier according to some embodiments of the present disclosure;

[0011] Figure 4B According to some embodiments of the present disclosure Figure 4A A schematic diagram of a latch circuit in a sense amplifier;

[0012] Figure 5According to some embodiments of the present disclosure Figure 4A as well as Figure 4B Waveform diagrams of multiple signals in ;

[0013] Figure 6 is a waveform diagram of two output voltages according to some related technologies and some embodiments of the present disclosure; and

[0014] Figure 7 It is a schematic diagram of data, corresponding analog signals and corresponding eye diagrams according to some embodiments of the present disclosure.

[0015] Explanation of symbols

[0016] 100: Latch circuit

[0017] 200, 400: Sense amplifier

[0018] 220, 420_1, 420_2: Comparison circuit

[0019] 240, 440_1, 440_2: Logic circuit

[0020] 260, 460: Latch circuit

[0021] CS1, CS2, CS3, CS4, CS5, CS6, CS7, CS8: Current sources

[0022] M1, M2, M3, M4, M5, M6, M7, M8: transistors

[0023] S1, S2, S3, S4, S5, S6, S7, S8: Switch

[0024] OUTN, OUTP: output nodes

[0025] VOUTN, VOUTP: output voltage

[0026] T1: Power supply end

[0027] VDD: power supply voltage

[0028] T2: Ground

[0029] VSS: Ground voltage

[0030] CLK, CLK_E, CLK_O: clock signal

[0031] CLKB, CLK_EB: inverted clock signals

[0032] IN1, IN2: input signal

[0033] SEB_P1, REB_P1, SEB_N1, REB_N1, SEB_P1, REB_P1, SEB_N1, REB_N1: Control signals

[0034] L1, L2, L3, L4, L5, L6, L7, L8: logic gates

[0035] T1, T2, T3, T4, T5, T6, T7, T8, T9: time points

[0036] DATA: Data

[0037] AS: Analog signal

[0038] EYE: Eye diagram DETAILED DESCRIPTION

[0039] As used herein, the term “coupled” may also refer to “electrically coupled”, and the term “connected” may also refer to “electrically connected.” “Coupled” and “connected” may also refer to two or more elements cooperating or interacting with each other.

[0040] refer to Figure 1 . Figure 1 1 is a schematic diagram of a latch circuit 100 according to some embodiments of the present disclosure. The latch circuit 100 includes current sources CS1-CS4 and transistors M1-M8, wherein the current sources CS1-CS4 are implemented by switches S1-S4, respectively, but the present disclosure is not limited thereto.

[0041] by Figure 1 For example, transistors M1, M3, M5 and M7 are P-type transistors, while transistors M2, M4, M6 and M8 are N-type transistors. Switches S1 and S2 are P-type switches (eg, P-type transistors), while switches S3 and S4 are N-type switches (eg, N-type transistors).

[0042] Current source CS1 and current source CS3 are coupled to output node OUTN. Output voltage VOUTN is generated at output node OUTN. Current source CS2 and current source CS4 are coupled to output node OUTP. Output voltage VOUTP is generated at output node OUTP. Control end of transistor M1 and control end of transistor M2 are coupled to output node OUTP. Control end of transistor M3 and control end of transistor M4 are coupled to output node OUTN. Transistor M1 and transistor M5 are coupled in series between power supply end T1 and output node OUTN. Power supply end T1 is used to receive power supply voltage VDD. Transistor M6 and transistor M2 are coupled in series between output node OUTN and ground end T2. Ground end T2 is used to receive ground voltage VSS. Transistor M3 and transistor M7 are coupled in series between power supply end T1 and output node OUTP. Transistor M8 and transistor M4 are coupled in series between output node OUTP and ground end T2.

[0043] The switch S1 is turned on or off by the control signal SEB_P1. The switch S2 is turned on or off by the control signal REB_P1. The switch S3 is turned on or off by the control signal SEB_N1. The switch S4 is turned on or off by the control signal REB_N1.

[0044] The transistors M5, M6, M7 and M8 are turned on or off based on the clock signal CLK. For example, the control terminals of the transistors M5 and M7 are used to receive the clock signal CLK to be turned on or off according to the clock signal CLK. The control terminals of the transistors M6 and M8 are used to receive the inverted clock signal CLKB to be turned on or off according to the inverted clock signal CLKB.

[0045] In some related technologies, the latch circuit does not include the transistors M5-M8 disclosed in the present invention. Accordingly, during the signal transition (e.g., from a high potential to a low potential) of these latch circuits, specific transistors in these latch circuits (e.g., transistors corresponding to the transistor M1 and transistor M2 disclosed in the present invention) are slightly turned on for a short period of time. Accordingly, a short-circuit current is generated in the paths of these specific transistors. The same problem also occurs in the paths of the corresponding specific transistors (e.g., transistors corresponding to the transistors M3 and transistor M4 disclosed in the present invention).

[0046] In addition, in some related technologies, during the transition of the output voltage (e.g., the output voltage VOUTP corresponding to the present disclosure changes from a high potential to a low potential and the output voltage VOUTN changes from a low potential to a high potential), a specific current source (e.g., the current source CS1 and the current source CS4 corresponding to the present disclosure) will be turned on first, and a short-circuit current will be generated on the path of a specific transistor (e.g., the transistor M2 and the transistor M3 corresponding to the present disclosure). Then, when the output voltage successfully transitions, the specific transistor (e.g., the transistor M2 and the transistor M3 corresponding to the present disclosure) will be turned off.

[0047] Compared to the above-mentioned related technologies, the latch circuit 100 of the present disclosure is provided with transistors M5-M8. Accordingly, when the clock signal CLK is at a high potential (the inverted clock signal CLKB is at a low potential), the control signal controls the current source to start conducting to control the signal transition. At this time, since the transistors M5-M8 are all in the off state, there will be no short-circuit current. When the clock signal CLK is at a low potential (the inverted clock signal CLKB is at a high potential), the control signal controls the current source to turn off. At this time, since the transistors M5-M8 are all in the on state, the latch stage will be entered.

[0048] It is particularly noted here that, in some other embodiments, the position of transistor M1 can be interchanged with the position of transistor M5, the position of transistor M2 can be interchanged with the position of transistor M6, the position of transistor M3 can be interchanged with the position of transistor M7, or the position of transistor M4 can be interchanged with the position of transistor M8.

[0049] refer to Figure 2 . Figure 2 FIG. 2 is a schematic diagram of a sense amplifier 200 according to some embodiments of the present disclosure. Figure 2 For example, the sense amplifier 200 includes a comparison circuit 220, a logic circuit 240, and a latch circuit 260. In some embodiments, the sense amplifier 200 can operate in a full-rate mode.

[0050] The comparison circuit 220 operates according to the clock signal CLK_E, the input signal IN1 , the input signal IN2 , the power voltage VDD and the ground voltage VSS to generate a comparison signal SE1 and a comparison signal RE1 .

[0051] For example, when the clock signal CLK_E experiences a falling phase and has a logic value of 0, the comparison circuit 220 is in a reset state. At this time, the comparison signal SE1 and the comparison signal RE1 have a logic value of 1. When the clock signal CLK_E experiences a rising phase and has a logic value of 1, the comparison circuit 220 is in a comparison state and can compare the input signal IN1 and the input signal IN2. If the input signal IN1 is greater than the input signal IN2, the comparison signal SE1 has a logic value of 0 and the comparison signal RE1 has a logic value of 1.

[0052] The logic circuit 240 is used to generate the control signal SEB_P1, the control signal REB_P1, the control signal SEB_N1 and the control signal REB_N1 based on the clock signal CLK_E, the clock signal CLK_O, the comparison signal SE1 and the comparison signal RE1. As mentioned above, the sense amplifier 200 can operate in the full rate mode. When the sense amplifier 200 operates in the full rate mode, the clock signal CLK_O has a logic value of 0.

[0053] by Figure 2 For example, the logic circuit 240 includes a logic gate L1, a logic gate L2, a logic gate L3, and a logic gate L4, wherein the logic gate L1 and the logic gate L2 are NAND gates, and the logic gate L3 and the logic gate L4 are NOR gates. The logic gate L1 is used to perform a NAND operation on the clock signal CLK_E and the comparison signal SE1 from the comparison circuit 220 to generate the control signal SEB_P1. The logic gate L2 is used to perform a NAND operation on the clock signal CLK_E and the comparison signal RE1 from the comparison circuit 220 to generate the control signal REB_P1. The logic gate L3 is used to perform a NOR operation on the clock signal CLK_O and the comparison signal SE1 from the comparison circuit 220 to generate the control signal SEB_N1. The logic gate L4 is used to perform a NOR operation on the clock signal CLK_O and the comparison signal RE1 from the comparison circuit 220 to generate the control signal REB_N1. Figure 2 The example is not intended to limit the present disclosure. As mentioned above, in some embodiments (for example, when the sense amplifier 200 operates in full-rate mode), the logic gate L3 can be replaced by an inverter to receive the comparison signal SE1 from the comparison circuit 220, and the logic gate L4 can be replaced by an inverter to receive the comparison signal RE1 from the comparison circuit 220.

[0054] Figure 2 The latch circuit 260 in the embodiment is implemented similarly to Figure 1 The latch circuit 100 ( Figure 2 The clock signal CLK_E and the inverted clock signal CLK_EB correspond to Figure 1The control signals SEB_P1, REB_P1, SEB_N1 and REB_N1 generated by the logic circuit 240 are used to control the switches S1, S2, S3 and S4 in the latch circuit 260, respectively.

[0055] refer to Figure 3 . Figure 3 According to some embodiments of the present disclosure Figure 2 Waveform diagram of multiple signals in .

[0056] Before the time point T1, as described above, when the clock signal CLK_E has a logic value of 0, the comparison circuit 220 is in a reset state and the comparison signal SE1 and the comparison signal RE1 have a logic value of 1. At this time, the control signal SEB_P1 and the control signal REB_P1 have a logic value of 1. Accordingly, the switch S1 and the switch S2 are turned off. As described above, when the sense amplifier 200 operates in the full rate mode, the clock signal CLK_O has a logic value of 0. Since the clock signal CLK_O has a logic value of 0 and the comparison signal SE1 and the comparison signal RE1 have a logic value of 1, the control signal SEB_N1 and the control signal REB_N1 have a logic value of 0. Accordingly, the switch S3 and the switch S4 are also turned off. At this time, the latch circuit 260 latches the data.

[0057] At time point T1, if the clock signal CLK_E undergoes a rising phase and turns to have a logic value of 1, the comparison circuit 220 enters a comparison state and the comparison signal SE1 and the comparison signal RE1 still have a logic value of 1. At this time, the control signal SEB_P1 and the control signal REB_P1 have a logic value of 0. Accordingly, the switch S1 and the switch S2 are turned on. The control signal SEB_N1 and the control signal REB_N1 still have a logic value of 0. Accordingly, the switch S3 and the switch S4 are still turned off. Since the switch S1 and the switch S2 are turned on and the switch S3 and the switch S4 are turned off, the output voltage VOUTN and the output voltage VOUTP are pulled up by the power supply voltage VDD.

[0058] After a period of comparison time, the comparison signal SE1 generated by the comparison circuit 220 has a logic value of 0 and the comparison signal RE1 has a logic value of 1. At this time (time point T2), the control signal SEB_P1 has a logic value of 1 and the control signal REB_P1 has a logic value of 0. Accordingly, the switch S1 is turned off and the switch S2 is still turned on. The control signal SEB_N1 has a logic value of 1 and the control signal REB_N1 has a logic value of 0. Accordingly, the switch S3 is turned on and the switch S4 is still turned off. In other words, the output voltage VOUTN is pulled down by the ground voltage VSS, and the output voltage VOUTP is still pulled up by the power supply voltage VDD.

[0059] Next (time point T3), the clock signal CLK_E goes through a falling phase again and turns to have a logic value of 0, the comparison circuit 220 enters the reset state again and the comparison signal SE1 still has a logic value of 0, and the comparison signal RE1 still has a logic value of 1. At this time, the control signal SEB_P1 and the control signal REB_P1 have a logic value of 1. Accordingly, the switch S1 is still turned off and the switch S2 is turned off. After a reset time, the comparison signal SE1 and the comparison signal RE1 generated by the comparison circuit 220 have a logic value of 1. At this time (time point T4), the control signal SEB_N1 and the control signal REB_N1 have a logic value of 0. Accordingly, the switch S3 is turned off and the switch S4 is still turned off, and the latch circuit 260 enters the latch state.

[0060] Generally speaking, the sensing amplifier in the prior art has the problem of kickback noise. In some related arts, in order to avoid kickback noise, a multi-stage (e.g., two-stage) inverter is provided to generate the control signal of the current source. However, the multi-stage inverter introduces too much delay into the signal. In addition, the control signal of the current source in some related arts needs to wait for a reset time before the switch in the current source is turned off.

[0061] Compared to the above-mentioned related art, the sense amplifier 200 of the present disclosure utilizes NAND gates and NOR gates to generate control signals of current sources CS1-CS4. In this way, the kickback noise can be turned into a capability to improve performance without introducing too much delay into the signal. Furthermore, in the present disclosure, when the clock signal CLK_E is in the falling phase (e.g., time point T3), the level of the control signal REB_P1 is immediately pulled high, so the switch S2 in the current source CS2 can be immediately turned off without waiting for the reset time.

[0062] refer to Figure 4A as well as Figure 4B . Figure 4A FIG. 4 is a schematic diagram of comparison circuits 420_1 and 420_2 and logic circuits 440_1 and 440_2 in a sense amplifier 400 according to some embodiments of the present disclosure. Figure 4B According to some embodiments of the present disclosure Figure 4A FIG. 4 is a schematic diagram of a latch circuit 460 in a sense amplifier 400 of FIG. 4. In some embodiments, the sense amplifier 400 can be operated in a half-rate mode. When the sense amplifier 400 is operated in the half-rate mode, the clock signal CLK_O is the inversion of the clock signal CLK_E.

[0063] by Figure 4A as well as Figure 4BFor example, the implementation of the comparison circuit 420_1 and the logic circuit 440_1 is the same as Figure 2 The implementation of the comparison circuit 220 and the logic circuit 240 is not described herein and will not be further elaborated.

[0064] The comparison circuit 420_2 is arranged to operate according to the clock signal CLK_O, the input signal IN1 , the input signal IN2 , the power voltage VDD and the ground voltage VSS to generate a comparison signal SE2 and a comparison signal RE2 .

[0065] The logic circuit 440_2 is configured to generate the control signal SEB_P2 , the control signal REB_P2 , the control signal SEB_N2 , and the control signal REB_N2 based on the clock signal CLK_E, the clock signal CLK_O, the comparison signal SE2 , and the comparison signal RE2 .

[0066] For example, the logic circuit 440_2 includes a logic gate L5, a logic gate L6, a logic gate L7, and a logic gate L8, wherein the logic gate L5 and the logic gate L6 are NAND gates, and the logic gate L7 and the logic gate L8 are NOR gates. The logic gate L5 is used to perform a NAND operation on the clock signal CLK_O and the comparison signal SE2 from the comparison circuit 420_2 to generate the control signal SEB_P2. The logic gate L6 is used to perform a NAND operation on the clock signal CLK_O and the comparison signal RE2 from the comparison circuit 420_2 to generate the control signal REB_P2. The logic gate L7 is used to perform a NOR operation on the clock signal CLK_E and the comparison signal SE2 from the comparison circuit 420_2 to generate the control signal SEB_N2. The logic gate L8 is used to perform a NOR operation on the clock signal CLK_E and the comparison signal RE2 from the comparison circuit 420_2 to generate the control signal REB_N2.

[0067] Figure 4B The latch circuit 460 and Figure 2 The main difference between the latch circuit 260 in FIG. 4 is that the latch circuit 460 further includes current sources CS5-CS8. The current sources CS5 and CS7 are coupled to the output node OUTN, while the current sources CS6 and CS8 are coupled to the output node OUTP. Figure 4B For example, current sources CS5-CS8 are implemented by switches S5-S8, respectively. Switch S5 and switch S6 are P-type switches (e.g., P-type transistors), and switch S7 and switch S8 are N-type switches (e.g., N-type transistors). Switch S5 is turned on or off by control signal SEB_P2. Switch S6 is turned on or off by control signal REB_P2. Switch S7 is turned on or off by control signal SEB_N2. Switch S8 is turned on or off by control signal REB_N2.

[0068] In some embodiments, Figure 4A The clock signal CLK_E and the clock signal CLK_O in the output are ORed together to obtain Figure 4B In addition, the clock signal CLK can be Figure 4A The clock signal CLK_E and the clock signal CLK_O in the clock are obtained by performing a NOR operation. Figure 4B The inverted clock signal CLKB in.

[0069] refer to Figure 5 . Figure 5 According to some embodiments of the present disclosure Figure 4A as well as Figure 4B Waveform diagram of multiple signals in .

[0070] Figure 5 The operation of the control signal REB_P1, the control signal REB_N1, the control signal SEB_P1 and the control signal SEB_N1 from the time point T5 to the time point T6 is similar to Figure 3 The control signals REB_P1 , REB_N1 , SEB_P1 , and SEB_N1 are operated from the time point T1 to the time point T3 . Figure 5 The operation of the control signal REB_P2, the control signal REB_N2, the control signal SEB_P2 and the control signal SEB_N2 from the time point T8 to the time point T9 is also similar to Figure 3 The control signals REB_P1 , REB_N1 , SEB_P1 , and SEB_N1 are operated from the time point T1 to the time point T3 .

[0071] in addition, Figure 5 The operation of the control signal REB_P1, the control signal REB_N1, the control signal SEB_P1 and the control signal SEB_N1 from the time point T7 to the time point T8 is similar to Figure 5 The control signals SEB_P2, SEB_N2, REB_P2, and REB_N2 are operated from the time point T6 to the time point T7.

[0072] In some related technologies, control signals of some current sources need to wait for a reset time before being turned off.

[0073] Compared to the above-mentioned related art, in the present disclosure, when the clock signal CLK_E is in the falling phase and CLK_O is in the rising phase (for example, time point T6), the level of the control signal REB_P1 is immediately pulled high and the level of the control signal SEB_N1 is immediately pulled low, so Figure 4BThe switch S3 in the current source CS3 and the switch S2 in the current source CS2 can be turned off immediately without waiting for the reset time. In addition, when the clock signal CLK_E is in the rising phase and CLK_O is in the falling phase (for example, time point T7), the level of the control signal REB_N2 is immediately pulled low and the level of the control signal SEB_P2 is immediately pulled high, so Figure 4B The switch S8 in the current source CS8 and the switch S5 in the current source CS5 can be turned off immediately without waiting for the reset time.

[0074] refer to Figure 6 . Figure 6 1 is a waveform diagram of an output voltage VOUTP and an output voltage VOUTN according to some related technologies and some embodiments of the present disclosure.

[0075] In some embodiments, the output voltage VOUTP and the output voltage VOUTN are input into the next stage sense amplifier, and the next stage sense amplifier can use NMOS transistors as input elements. Accordingly, when the output voltage VOUTP and the output voltage VOUTN drop to equal to or less than 0.5 volts, the next stage sense amplifier will not operate normally (the NMOS transistor will be turned off). In addition, assuming that the output signal has a logic value of 1, when the output voltage VOUTP is less than the output voltage VOUTN, the direction of the charge amount continuously accumulated by the next stage sense amplifier will be opposite, which may cause the next stage sense amplifier to fail to operate normally.

[0076] by Figure 6 For example, in Related Art 1, when the clock signal rises, the voltage of the output voltage VOUTP drops from 1 V, and the voltage of the output voltage VOUTN rises from 0 V. The time when the output voltage VOUTP has a voltage difference with the output voltage VOUTN is the same as the time when the next stage can operate.

[0077] In Related Art 2, when the clock signal rises, the voltage of the output voltage VOUTP drops from 1 V, while the voltage of the output voltage VOUTN remains at 0 V. The time during which the next stage can operate normally is shorter than the time during which there is a voltage difference between the output voltages VOUTP and VOUTN.

[0078] In the present disclosure, as described above, when the clock signal rises and after a period of comparison time, the output voltage VOUTN will be pulled down by the ground voltage VSS, while the output voltage VOUTP is still pulled up by the power supply voltage VDD. When the clock signal rises next time, the output voltage VOUTP remains at 1 volt and the voltage of the output voltage VOUTN starts to rise from 0 volts. Accordingly, the NMOS transistor of the next stage of the sense amplifier is turned on, so that the voltage difference between the output voltage VOUTP and the output voltage VOUTN can continue to accumulate. Figure 6 For example, in the present disclosure, the time during which the next stage can operate normally is longer than the time during which there is a voltage difference between the output voltage VOUTP and the output voltage VOUTN, and is longer than the time during which the next stage can operate normally in the related art 1 and the related art 2. In addition, compared with the related art 2, the end time point of the present disclosure is earlier.

[0079] refer to Figure 7 . Figure 7 1 is a schematic diagram of data DATA, a corresponding analog signal AS, and a corresponding eye diagram EYE according to some embodiments of the present disclosure. Figure 2Take the sense amplifier 200 in FIG. 2 as an example (assuming that the output voltage VOUTP of the previous data is a logic value of 0 and the output voltage VOUTN is a logic value of 1), when the next clock signal CLK_E rises and enters the comparison stage, the control signal SEB_P1 and the control signal REB_P1 will first be reduced to a logic value of 0, and accordingly, the switch S1 and the switch S2 will be turned on, causing the output voltage VOUTP to be pulled up. Based on the kickback noise, VOUTP is pulled up and causes the control signal REB_P1 and the control signal REB_N1 to be pulled up (affected by the switch S2 and the switch S4). The rise of the control signal REB_P1 and the control signal REB_N1 will cause the comparison signal RE1 to be pulled up (affected by the logic gate L2 and the logic gate L4). When the comparison signal RE1 is pulled up, the comparison signal SE1 finally generated by the comparison circuit 220 will tend to approach the logic value 0 and the comparison signal RE1 will tend to approach the logic value 1. When the comparison signal SE1 tends to approach the logic value 0 and the comparison signal RE1 tends to approach the logic value 1, the control signal SEB_P1 output by the logic gate L1 and the control signal SEB_N1 output by the logic gate L3 tend to approach the logic value 1, and the control signal REB_P1 output by the logic gate L2 and the control signal REB_N1 output by the logic gate L4 tend to approach the logic value 0. In this way, the switches S2 and S3 are more likely to be turned on, so that the output voltage VOUTP tends to approach the logic value 1 and VOUTN tends to approach the logic value 0, so that the final output data tends to be opposite to the previous one (the output voltage VOUTP of the previous data is the logic value 0 and the output voltage VOUTN is the logic value 1). Accordingly, the eye width of the part of the eye diagram EYE corresponding to the transition of the data DATA can be enlarged to improve the discernibility of the eye diagram EYE.

[0080] In summary, in the present disclosure, the latch circuit can be prevented from generating a short-circuit current when switching, and the sensing amplifier can be improved in performance through kickback noise. Thus, the latch circuit and the sensing amplifier of the present disclosure can have better performance.

[0081] Various functional elements and blocks have been disclosed herein. For those of ordinary skill in the art, the functional blocks may be implemented by circuits (whether dedicated circuits or general purpose circuits operating under the control of one or more processors and coded instructions), which generally include transistors or other circuit elements for controlling the operation of electrical circuits corresponding to the functions and operations described herein. It is further understood that the specific structure and interconnection of circuit elements generally may be determined by a compiler, such as a Register Transfer Language (RTL) compiler. The RTL compiler operates on scripts that are quite similar to assembly language code, compiling the scripts into a form used to lay out or fabricate the final circuit.

[0082] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Any ordinary technician in the field can make various changes and modifications without departing from the concept and scope of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on what is defined in the claims.

Claims

1. A latch circuit, comprising: a first current source; a second current source; a third current source; a fourth current source, wherein the first current source and the third current source are coupled to a first output node, and the second current source and the fourth current source are coupled to a second output node; a first transistor and a second transistor, wherein a control terminal of the first transistor and a control terminal of the second transistor are coupled to the second output node; a third transistor and a fourth transistor, wherein a control terminal of the third transistor and a control terminal of the fourth transistor are coupled to the first output node; a fifth transistor and a sixth transistor, wherein the first transistor and the fifth transistor are coupled in series between a power supply terminal and the first output node, wherein the sixth transistor and the second transistor are coupled in series between the first output node and a ground terminal; and a seventh transistor and an eighth transistor, wherein the third transistor and the seventh transistor are coupled in series between the power supply terminal and the second output node, wherein the eighth transistor and the fourth transistor are coupled in series between the second output node and the ground terminal, The fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are turned on or off based on a clock signal, The fifth transistor is used to receive the clock signal, and the sixth transistor is used to receive an inverted clock signal corresponding to the clock signal. The first current source receives a control signal and is controlled by the received control signal. The control signal is generated by performing a logic operation on the clock signal and a comparison signal. The comparison signal is generated by a comparison circuit according to a plurality of input signals and the clock signal.

2. The latch circuit as described in claim 1, wherein the fifth transistor is used to receive the clock signal, and the sixth transistor is used to receive an inverted clock signal corresponding to the clock signal, wherein the first transistor and the fifth transistor are P-type transistors, and the second transistor and the sixth transistor are N-type transistors, wherein the seventh transistor is used to receive the clock signal, and the eighth transistor is used to receive the inverted clock signal, wherein the third transistor and the seventh transistor are P-type transistors, and the fourth transistor and the eighth transistor are N-type transistors.

3. A sense amplifier comprising: a first comparison circuit for generating a first comparison signal and a second comparison signal according to a first input signal, a second input signal and a first clock signal; a logic circuit for generating a first control signal, a second control signal, a third control signal and a fourth control signal based on the first clock signal, the first comparison signal and the second comparison signal; and A latch circuit comprising: a first current source; a second current source; a third current source; a fourth current source, wherein the first current source and the third current source are coupled to a first output node, wherein the first control signal is used to control the first current source, and the third control signal is used to control the third current source, wherein the second current source and a fourth current source are coupled to a second output node, wherein the second control signal is used to control the second current source, and the fourth control signal is used to control the fourth current source; a first transistor and a second transistor, wherein a control terminal of the first transistor and a control terminal of the second transistor are coupled to the second output node; and a third transistor and a fourth transistor, wherein a control terminal of the third transistor and a control terminal of the fourth transistor are coupled to the first output node.

4. The sense amplifier of claim 3 , wherein the logic circuit comprises: a first logic gate, configured to generate the first control signal according to the first clock signal and the first comparison signal; a second logic gate, configured to generate the second control signal according to the first clock signal and the second comparison signal; a third logic gate, configured to generate the third control signal according to the first comparison signal; and A fourth logic gate is used to generate the fourth control signal according to the second comparison signal.

5. The sense amplifier as claimed in claim 4, wherein the third logic gate is further used to generate the third control signal according to a second clock signal and the first comparison signal, wherein the fourth logic gate is further used to generate the fourth control signal according to the second clock signal and the second comparison signal, wherein the first logic gate and the second logic gate are NAND gates, and the third logic gate and the fourth logic gate are NOR gates, wherein the first current source and the second current source each include a P-type switch, and the P-type switch is turned on or off according to the first control signal and the second control signal, respectively, wherein the third current source and the fourth current source each include an N-type switch, and the N-type switch is turned on or off according to the third control signal and the fourth control signal, respectively. 6 . The sense amplifier of claim 5 , wherein the second clock signal has a first logic value when the sense amplifier operates in a full rate mode.

7. The sense amplifier of claim 5, further comprising: a second comparison circuit for generating a third comparison signal and a fourth comparison signal according to the first input signal, the second input signal and the second clock signal, wherein the logic circuit is further used to generate a fifth control signal, a sixth control signal, a seventh control signal and an eighth control signal based on the first clock signal, the second clock signal, the third comparison signal and the fourth comparison signal, The latch circuit further comprises: a fifth current source; a sixth current source; a seventh current source; an eighth current source, wherein the fifth current source and the seventh current source are coupled to the first output node, wherein the fifth control signal is used to control the fifth current source, and the seventh control signal is used to control the seventh current source, wherein the sixth current source and the eighth current source are coupled to the second output node, wherein the sixth control signal is used to control the sixth current source, and the eighth control signal is used to control the eighth current source.

8. The sense amplifier of claim 7, wherein the logic circuit comprises: a fifth logic gate, configured to generate the fifth control signal according to the second clock signal and the third comparison signal; a sixth logic gate, configured to generate the sixth control signal according to the second clock signal and the fourth comparison signal; a seventh logic gate, configured to generate the seventh control signal according to the first clock signal and the third comparison signal; as well as an eighth logic gate, configured to generate the eighth control signal according to the first clock signal and the fourth comparison signal, The fifth logic gate and the sixth logic gate are NAND gates, and the seventh logic gate and the eighth logic gate are NOR gates. 9 . The sense amplifier of claim 7 , wherein when the sense amplifier operates in a half-rate mode, the second clock signal is an inversion of the first clock signal.

10. The sense amplifier of claim 3, wherein the latch circuit further comprises: a fifth transistor and a sixth transistor, wherein the first transistor and the fifth transistor are coupled in series between a power supply terminal and the first output node, wherein the sixth transistor and the second transistor are coupled in series between the first output node and a ground terminal; and a seventh transistor and an eighth transistor, wherein the third transistor and the seventh transistor are coupled in series between the power supply terminal and the second output node, wherein the eighth transistor and the fourth transistor are coupled in series between the second output node and the ground terminal, The fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are turned on or off according to the first clock signal.

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