Output circuit and input / output circuit

Abstract

An output circuit 1 comprises: three P-type transistors (P1, P2, P3) connected in series between a first power supply and an output terminal (OUT); three N-type transistors (N1, N2, N3) connected in series between the output terminal (OUT) and a fourth power supply; and an N-type transistor (N4) and a P-type transistor (P4) connected in series between a second power supply and a third power supply. The output circuit (1) outputs an output signal (OUT) that changes in accordance with an input signal (IN).

Description

Output and input / output circuits

[0001] The present disclosure relates to an output circuit and an input / output circuit of an IO cell that outputs a signal to the outside of a semiconductor device (LSI (Large Scale Integration)).

[0002] Conventional semiconductor devices have been available with thick-gate transistors (high-voltage transistors) and thin-gate transistors (low-voltage transistors) that have a lower voltage resistance than thick-gate transistors. Generally, high-voltage transistors have a high tolerable voltage stress (voltage resistance) and are used in IO cells that communicate high-voltage signals with the outside of the LSI. Low-voltage transistors are used in internal cells (memory cells, standard cells, etc.) that handle relatively low-voltage signals.

[0003] In recent years, semiconductor devices without high-voltage transistors have been considered due to manufacturing reasons associated with the miniaturization of transistors. As it is likely that relatively high-voltage signals (such as 1.8 V) will be used in communication in the future, I / O cells that handle high-voltage signals using only low-voltage transistors are being considered.

[0004] For example, Patent Document 1 discloses an output circuit of an IO cell that outputs a voltage signal several times higher than the withstand voltage of a transistor.

[0005] U.S. Patent No. 9,214,933

[0006] However, it is expected that the transistor breakdown voltage will further decrease as miniaturization progresses, and that the operating voltage will decrease accordingly, but there is no output circuit that can flexibly and easily adapt to these changes.

[0007] In view of the above problems, the present disclosure aims to solve the above problems.

[0008] In one aspect of the present disclosure, there is provided an output circuit that receives an input signal and outputs an output signal that changes in response to the input signal, the output circuit including: an output terminal that outputs the output signal; a first P-type transistor having a source connected to a first power supply, a drain connected to a first node, and a gate that receives a signal that changes in response to the input signal; a second P-type transistor having a source connected to the first node, a drain connected to a second node, and a gate connected to a second power supply having a power supply voltage lower than that of the first power supply; a third P-type transistor having a source connected to the second node, a drain connected to the output terminal, and a gate connected to a third node; and a fourth P-type transistor having a drain connected to the output terminal, a source connected to a fourth node, and a gate connected to the third node. a second N-type transistor having a drain connected to the fourth node, a source connected to a fifth node, and a gate connected to a third power supply having a power supply voltage lower than that of the second power supply; a third N-type transistor having a drain connected to the fifth node, a source connected to a fourth power supply having a power supply voltage lower than that of the third power supply, and having a gate receiving a signal that changes in response to the input signal; a fourth N-type transistor having a drain connected to the second power supply, a source connected to the third node, and a gate connected to the second node; and a fourth P-type transistor having a source connected to the third node, a drain connected to the third power supply, and a gate connected to the fourth node.

[0009] According to this embodiment, the gate voltages of P-type transistor P3 and N-type transistor N3 are controlled in accordance with the characteristics of the output signal, which vary depending on the breakdown voltage and operating voltage of the transistors. As a result, the voltages between the terminals of the first to third P-type transistors and the first to third N-type transistors are maintained at or below the breakdown voltage of the transistors while the output circuit is in operation. This makes it possible to more accurately prevent deterioration over time of the transistors (the first to third P-type transistors and the first to third N-type transistors) that make up the output circuit, compared to conventional techniques.

[0010] According to the present disclosure, the voltage across each terminal of each transistor is maintained at or below the breakdown voltage of the transistor while the output circuit is in operation, thereby making it possible to reliably prevent deterioration of each transistor over time.

[0011] 1. Circuit configuration diagram of an output circuit according to the first embodiment. 1. Diagram showing an example of the operating state of the output circuit of FIG. 1. 2. Waveform diagram showing the operation of the output circuit of FIG. 1. 3. Circuit configuration diagram of an input / output circuit according to a modification of the first embodiment and a diagram showing an example of the operating state. 4. Diagram showing another example of the operating state of the input / output circuit of FIG. 5. 5. Circuit configuration diagram of an output circuit according to the second embodiment. 6. Circuit configuration diagram of an input / output circuit according to a modification of the second embodiment.

[0012] Hereinafter, embodiments will be described with reference to the drawings.

[0013] In this disclosure, the term "connection" broadly encompasses electrical connection, including direct connection as well as indirect electrical connection via passive elements, etc. The circuit diagrams shown below are simplified and focus on the components relevant to this disclosure. Therefore, for example, components illustrated as being directly connected may in fact have other components interposed between them in the actual circuit configuration, resulting in an indirect connection. Furthermore, in this disclosure, the term "terminal" is used to refer to a current inlet or outlet provided for connecting an electrical circuit. For example, there is no intention to limit the term to a specific configuration such as a semiconductor pad; wiring or vias connecting circuits or elements may also correspond to terminals.

[0014] In the following description, the nodes and terminals of a circuit and the signals passing through those nodes and terminals may be described using common symbols or names, and the names of power supplies and the power supply voltages of those power supplies may be described using common symbols. The voltage of a terminal or node may be described using only a symbol indicating the voltage, such as "(terminal name or node name) = (symbol indicating voltage)". Specifically, for example, if the voltage of the output terminal OUT is VDD (the voltage of the power supply VDD), it may be described as "OUT = VDD".

[0015] First Embodiment FIG. 1 is a circuit diagram of an output circuit according to a first embodiment. The output circuit 1 in FIG. 1 receives an input signal IN and outputs an output signal OUT that varies in response to the input signal IN. The output circuit 1 is a circuit using low-voltage transistors and outputs a voltage signal approximately three times the transistor's voltage resistance. The output circuit 1 is provided, for example, in an IO cell (signal output section) of an LSI. In this case, the output pad of the LSI corresponds to the output terminal OUT. The input signal IN transitions between VSS and VDD, and the output signal OUT transitions between VSS and 3VDD. Note that VDD is the power supply voltage of the power supply VDD (corresponding to the third power supply), 2VDD is the power supply voltage of the power supply 2VDD (corresponding to the second power supply), 3VDD is the power supply voltage of the power supply 3VDD (corresponding to the first power supply), and VSS is the power supply voltage of ground VSS (corresponding to the fourth power supply). The magnitude relationship between the power supply voltages is "VSS<VDD<2VDD<3VDD". For example, VDD is a low voltage less than 1.0 V, and typically decreases as transistors become smaller. For example, 2VDD is twice the voltage of VDD, and 3VDD is three times the voltage of VDD.

[0016] 1, the output circuit 1 includes an output driver 10, a control circuit 20, and a buffer circuit 30. Note that each transistor described below is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, there is no intention to limit the transistors to MOSFETs, and alternative transistors or switching elements may be used.

[0017] - Output Driver - The output driver 10 is a circuit that outputs to an output terminal OUT an output signal OUT (amplitude: VSS to 3VDD) that changes in response to an input signal IN (amplitude: VSS to VDD) input to an input terminal IN. The specific operation of the output driver 10 will be described later.

[0018] The output driver 10 includes P-type transistors P1, P2, and P3 connected in series between a power supply 3 VDD and an output terminal OUT, and N-type transistors N3, N2, and N1 connected in series between the output terminal OUT and ground VSS. The P-type transistors P1, P2, P3, and P4 (described below) and the N-type transistors N1, N2, N3, and N4 (described below) are so-called low-voltage transistors, and in the following description, when no distinction is made between them, these transistors may be collectively referred to simply as "low-voltage transistors." In this example, the low-voltage transistors are transistors that, when viewed individually, have a breakdown voltage of VDD+α, where α is, for example, a value approximately equal to the threshold voltage of the transistor.

[0019] The P-type transistor P1 (corresponding to the first P-type transistor) has a source connected to the power supply 3VDD and a drain connected to a node n1 (corresponding to the first node). The gate of the P-type transistor P1 is connected to the output 31 of the buffer circuit 30 via a node n6, and receives a signal from the buffer circuit 30 that varies in accordance with the input signal IN. The P-type transistor P2 (corresponding to the second P-type transistor) has a source connected to the node n1, a drain connected to a node n2 (corresponding to the second node), and a gate connected to the power supply 2VDD. The P-type transistor P3 (corresponding to the third P-type transistor) has a source connected to the node n2, a drain connected to the output terminal OUT, and a gate connected to a node n3 (corresponding to the third node).

[0020] The N-type transistor N3 (corresponding to the first N-type transistor) has a drain connected to the output terminal OUT, a source connected to a node n4 (corresponding to the fourth node), and a gate connected to a node n3. The N-type transistor N2 (corresponding to the second N-type transistor) has a drain connected to the node n4, a source connected to a node n5 (corresponding to the fifth node), and a gate connected to a power supply VDD. The N-type transistor N1 (corresponding to the third N-type transistor) has a drain connected to the node n5 and a source connected to ground VSS. The gate of the N-type transistor N1 is connected to the output 32 of the buffer circuit 30 via a node n7, and receives a signal from the buffer circuit 30 that changes in response to the input signal IN.

[0021] -Control Circuit- The control circuit 20 is a circuit that controls the voltage of the gates of the P-type transistor P3 and the N-type transistor N3, ie, the voltage amplitude of the node n3, within the range of VDD to 2VDD in accordance with the operation of the output driver 10.

[0022] The control circuit 20 includes an N-type transistor N4 (corresponding to a fourth N-type transistor) and a P-type transistor P4 (corresponding to a fourth P-type transistor) connected in series between the power supply 2VDD and the power supply VDD. The N-type transistor N4 has a drain connected to the power supply 2VDD, a source connected to a node n3, and a gate connected to a node n2. The P-type transistor P4 has a source connected to the node n3, a drain connected to the power supply VDD, and a gate connected to a node n4.

[0023] - Buffer Circuit - The buffer circuit 30 propagates a signal that changes in response to an input signal to nodes n6 and n7. Specifically, the buffer circuit 30 propagates a signal that changes between 3 VDD and 2 VDD as an output 31 to node n6 in response to a change in the input signal from VSS to VDD. In other words, the buffer circuit 30 shifts (boosts) the input signal that changes between VSS and VDD to a signal that changes between 3 VDD and 2 VDD and propagates the signal to node n6. Furthermore, the buffer circuit 30 propagates a signal that changes between VDD and VSS as an output 32 to node n7 in response to a change in the input signal from VSS to VDD.

[0024] With the above configuration, the voltage between the terminals of each of the P-type transistors P1, P2 and the N-type transistors N1, N2 is maintained below the breakdown voltage.

[0025] [Operation of Output Circuit] The operation of the output circuit 1 will be described below, focusing on the voltages between the terminals of the P-type transistor P3 and the N-type transistor N3. In the following description, the gate-drain voltage |Vgd| of a transistor will be simply referred to as Vgd. Similarly, the gate-source voltage |Vgs| will be simply referred to as Vgs, and the drain-source voltage |Vds| will be simply referred to as Vds. Furthermore, the threshold voltage of a P-type transistor will be referred to as Vtp, and the threshold voltage of an N-type transistor will be referred to as Vtn.

[0026] --Operation Example 1-1: When IN=VSS, OUT=VSS-- Figure 2 shows the voltage of each node and the on / off state of each transistor for operation when IN=VSS, OUT=VSS, that is, operation when a low signal is input to the input terminal IN of the output circuit 1 and a low signal is output from the output terminal OUT.

[0027] When IN=VSS, n7=VDD, N-type transistors N1 and N2 turn on, and n4=VSS. Then, P-type transistor P4 turns on, n3=VDD, and N-type transistor N3 turns on, and OUT=VSS.

[0028] When IN=VSS, n6=3VDD, and the P-type transistor P1 is turned off. As described above, n3=VDD, so n2=VDD+Vtp. VDD+Vtp<2VDD, and the N-type transistor N4 is turned off.

[0029] Here, Vgd of P-type transistor P3 and N-type transistor N3 is the voltage between node n3 and output terminal OUT, and Vgd = VDD. This is below the breakdown voltage of the low-voltage transistor. Furthermore, Vgs of P-type transistor P3 is Vgs = (VDD + Vtp) - VDD = Vtp, and Vds is Vds = (VDD + Vtp) - VSS = VDD + Vtp, so both are below the breakdown voltage of the low-voltage transistor. Similarly, Vgs of N-type transistor N3 is Vgs = VDD - VSS = VDD, and Vds is Vds = VSS - VSS = 0 [V], so both are below the breakdown voltage of the low-voltage transistor.

[0030] --Operation Example 1-2: When IN=VDD, OUT=3VDD-- Figure 3 shows the voltage of each node and the on / off state of each transistor for the operation of the output circuit 1 when IN=VDD, OUT=3VDD, that is, when a high signal is input to the input terminal IN and a high signal is output from the output terminal OUT.

[0031] When IN=VDD, n6=2VDD, and the P-type transistors P1 and P2 turn on, so that n2=3VDD. Then, the N-type transistor N4 turns on, so that n3=2VDD, and the P-type transistor P3 turns on, so that OUT=3VDD.

[0032] When IN=VDD, n7=VSS, and the N-type transistor N1 is turned off. As described above, n3=2VDD, so n4=2VDD-Vtn. 2VDD-Vtn>VDD, and the P-type transistor P4 is turned off.

[0033] Here, Vgd of P-type transistor P3 and N-type transistor N3 is the voltage between node n3 and output terminal OUT, and is Vgd = 3VDD - 2VDD = VDD. This is below the breakdown voltage of the low-voltage transistor. Furthermore, Vgs of P-type transistor P3 is Vgs = 3VDD - 2VDD = VDD, and Vds is Vds = 3VDD - 3VDD = 0 [V], so both are below the breakdown voltage of the low-voltage transistor. Similarly, Vgs of N-type transistor N3 is Vgs = 2VDD - (2VDD - Vtn) = Vtn, and Vds is Vds = 3VDD - (2VDD - Vtn) = VDD + Vtn, so both are below the breakdown voltage of the low-voltage transistor.

[0034] --Operation Example 1-3: When IN=VSS→VDD, OUT=VSS→3VDD-- The left side of FIG. 4 shows the operation when IN=VSS→VDD, OUT=VSS→3VDD, that is, the waveforms when the input signal IN of the output circuit 1 transitions from low to high and the output signal OUT changes from low to high.

[0035] When the input signal IN transitions from low to high, the on / off state of each transistor transitions from the state in "Operation Example 1-1" described above to the state in "Operation Example 1-2." Here, the operation related to the voltage between the terminals of the P-type transistor P3 and the N-type transistor N3 will be described.

[0036] When the input signal IN transitions from low to high, the P-type transistors P1, P2, and P3 turn on, and the voltages of the output signal OUT and node n2 rise toward 3VDD. As the voltages of the output signal OUT and node n2 rise, the N-type transistor N4 turns on, and the voltage of node n3 rises from VDD toward 2VDD.

[0037] At this time, the start of the rise in the voltage at node n3 is delayed from the start of the rise in the output signal OUT by the time T1 (see FIG. 4) it takes for N-type transistor N4 to turn on. Therefore, the Vgd of P-type transistor P3 and N-type transistor N3 is maintained below VDD, and is below the breakdown voltage of the low-voltage transistor, even while the output signal OUT is changing from low to high. The same is true for Vgs and Vds of P-type transistor P3 and N-type transistor N3, which are maintained at voltages below the breakdown voltage of the low-voltage transistor, even while the output signal OUT is changing from low to high.

[0038] --Operation Example 1-4: When IN=VDD→VSS, OUT=3VDD→VSS-- The right side of FIG. 4 shows the operation when IN=VDD→VSS and OUT=3VDD→VSS, that is, the waveforms when the input signal IN of the output circuit 1 transitions from High to Low and the output signal OUT changes from High to Low.

[0039] When the input signal IN transitions from High to Low, the on / off state of each transistor transitions from the state in "Operation Example 1-2" described above to the state in "Operation Example 1-1." Here, the operation related to the voltage between the terminals of the P-type transistor P3 and the N-type transistor N3 will be described.

[0040] When the input signal IN transitions from high to low, the N-type transistors N1, N2, and N3 turn on, and the voltages of the output signal OUT and node n4 fall toward VSS. As the voltages of the output signal OUT and node n4 fall, the P-type transistor P4 turns on, and the voltage of node n3 falls from 2VDD toward VDD.

[0041] At this time, the start of the fall of the voltage at node n3 is delayed from the start of the fall of output signal OUT by the time T2 (see FIG. 4) it takes for P-type transistor P4 to turn on. Therefore, Vgd of P-type transistor P3 and N-type transistor N3 is maintained below VDD, and is below the breakdown voltage of the low-voltage transistor, even while output signal OUT is changing from High to Low. The same is true for Vgs and Vds of P-type transistor P3 and N-type transistor N3, which are maintained at voltages below the breakdown voltage of the low-voltage transistor, even while output signal OUT is changing from High to Low.

[0042] [Operation and Effects of First Embodiment] According to this embodiment, the control circuit 20 controls the gate voltages of the P-type transistor P3 and the N-type transistor N3 in accordance with the characteristics of the output signal, which vary depending on the breakdown voltage and operating voltage of the transistors. As a result, the Vgd, Vgs, and Vds of the P-type transistors P1, P2, and P3 and the N-type transistors N1, N2, and N3 are maintained at or below the breakdown voltages of the low-voltage transistors while the output circuit 1 is in operation. This makes it possible to more accurately prevent deterioration of the P-type transistor P3 and the N-type transistor N3 over time, compared to the prior art.

[0043] Furthermore, the control circuit 20 according to this embodiment has a very simple configuration consisting of only two transistors, which makes it possible to simplify the design of the output circuit 1 and reduce the circuit area.

[0044] <Modification of First Embodiment> FIG. 5 is a circuit configuration diagram of an input / output circuit according to a modification of the first embodiment. In FIG. 5, components corresponding to those in FIG. 1 are assigned common reference numerals. The following description will focus on differences from the first embodiment. Note that there is no intention to limit the configurations and various design parameters / process parameters, etc., of blocks and elements (e.g., transistors) assigned the same reference numerals in FIGS. 1 and 5 to those elements. In other words, the technical scope of the present disclosure includes configurations in which the various parameters of elements assigned the same reference numerals in FIGS. 1 and 5 differ from each other. The same applies to the relationships between the other drawings.

[0045] [Configuration of Input / Output Circuit] The input / output circuit 2 of Figure 5 includes the output circuit 1 of Figure 1 and an input buffer 40. The output terminal OUT of the output circuit 1 is connected to the input / output terminal INOUT. The input terminal 41 of the input buffer 40 is connected to the input / output terminal INOUT. The specific circuit configuration of the input buffer 40 is not particularly limited, and a conventionally known buffer circuit configured by combining transistors can be applied. In this example, the input / output pad of the LSI corresponds to the input / output terminal INOUT. The output node connecting the output of the output driver 10 and the input / output terminal INOUT corresponds to the output terminal OUT of the output circuit 1.

[0046] Furthermore, the input / output circuit 2 has a mode switching terminal EN for switching between input and output modes. The input / output circuit 2 is switched, by a mode switching signal EN input from the mode switching terminal EN, between operating in an input mode in which the input signal IN2 is received from the input / output terminal INOUT and operating in an output mode in which the output signal OUT of the output circuit 1 is output from the input / output terminal INOUT.

[0047] [Operation of Input / Output Circuit] The operation of the input / output circuit 2 in Fig. 5 will be described below. The operation when the input / output circuit 2 is in the output mode is the same as that in the above-described embodiment 1. Here, the operation when the input / output circuit 2 is in the input mode will be described.

[0048] --Operation Example 1-5: When INOUT=VSS→3VDD--Here, we will explain the operation when INOUT=VSS→3VDD, that is, the operation when the mode switching signal EN is set to input mode and the input signal IN2 of the input / output terminal INOUT transitions from low to high. Figure 5 shows the voltage of each node and the on / off state of each transistor in this operation example.

[0049] When the mode switching signal EN is set to the input mode, n7=VSS. The voltages of the other nodes are the same as those in the "Operation Example 1-1" of the first embodiment described above.

[0050] As the input signal IN2 transitions from low to high (from VSS to 3VDD), the P-type transistor P3 turns on, causing the voltage at node n2 to rise toward 3VDD. During this transition, the N-type transistor N4 turns on, causing the voltage at node n3 to rise from VDD toward 2VDD. Furthermore, the N-type transistor N3 and the P-type transistor P4 turn off. Here, as in the first embodiment, the start of the rise in the voltage at node n3 is delayed from the start of the rise in the input signal IN2 by the time T1 (see FIG. 4 ) it takes for the N-type transistor N4 to turn on. Therefore, as in the first embodiment, the Vgd of the P-type transistor P3 and the N-type transistor N3 is maintained below VDD and is below the breakdown voltage of the low-voltage transistor, even while the input signal IN2 is transitioning from low to high. The same is true for the Vgs and Vds of the P-type transistor P3 and the N-type transistor N3, which are maintained at a voltage equal to or lower than the breakdown voltage of the low-voltage transistors even while the input signal IN2 is changing from low to high.

[0051] --Operation Example 1-6: When INOUT=3VDD→VSS--Here, we will explain the operation when INOUT=3VDD→VSS, that is, the operation when the mode switching signal EN is set to input mode and the input signal IN2 of the input / output terminal INOUT transitions from high to low. Figure 6 shows the voltage of each node and the on / off state of each transistor in this operation example.

[0052] When the mode switching signal EN is set to the input mode, n6 becomes 3VDD. The voltages of the other nodes are the same as those in the "Operation Example 1-2" of the first embodiment described above.

[0053] As the input signal IN2 transitions from High to Low (from 3VDD to VSS), the N-type transistor N3 turns on, causing the voltage at node n4 to drop toward VSS. During this transition, the P-type transistor P4 turns on, causing the voltage at node n3 to drop from 2VDD toward VDD. Furthermore, the P-type transistor P3 and the N-type transistor N4 turn off. Here, as in the first embodiment, the start of the fall of the voltage at node n3 is delayed from the start of the fall of the input signal IN2 by the time T2 (see FIG. 4 ) it takes for the P-type transistor P4 to turn on. Therefore, as in the first embodiment, the Vgd of the P-type transistor P3 and the N-type transistor N3 is maintained below VDD, even while the input signal IN2 is changing from High to Low, and is below the breakdown voltage of the low-voltage transistor. The same is true for the Vgs and Vds of the P-type transistor P3 and the N-type transistor N3, which are maintained at a voltage equal to or lower than the breakdown voltage of the low-voltage transistors even while the input signal IN2 changes from High to Low.

[0054] [Operation and Effects of the Modification of the First Embodiment] According to this modification, the same effects as those of the first embodiment can be obtained, for example, even when the input / output circuit 2 operates in conjunction with the input signal IN2 from outside the LSI. Specifically, while the input / output circuit 2 is operating, the Vgd, Vgs, and Vds of the P-type transistors P1, P2, and P3 and the N-type transistors N1, N2, and N3 are maintained at or below the breakdown voltages of the low-voltage transistors. This makes it possible to more accurately prevent deterioration over time of the P-type transistor P3 and the N-type transistor N3 than in the prior art.

[0055] Furthermore, since there is no wiring directly connecting the control circuit 20 and the input / output terminal INOUT, no leakage current (such as transistor leakage current) occurs between the outside of the LSI and the control circuit 20, and the control circuit 20 does not affect the quality of the input signal IN2.

[0056] 7 and 8 are circuit diagrams of an output circuit according to a second embodiment. In Fig. 7 and Fig. 8, components corresponding to those in Fig. 1 are given the same reference numerals. The following description will focus on the differences from the first embodiment.

[0057] [Configuration of Output Circuit] The output circuit 1 in Figures 7 and 8 differs from the output circuit 1 in Figure 1 in the internal configuration of the control circuit 20. Like Figure 1, the control circuit 20 in Figures 7 and 8 is a circuit that controls the voltages of the gates of P-type transistor P3 and N-type transistor N3, i.e., the voltage amplitude of node n3, within the range of VDD to 2VDD in accordance with the operation of the output driver 10.

[0058] 7 includes, in addition to the configuration of FIG. 1, an N-type transistor N5 (corresponding to a fifth N-type transistor) and a P-type transistor P5 (corresponding to a fifth P-type transistor) connected in series between the power supply 2VDD and the power supply VDD. The N-type transistor N5 has a drain connected to the power supply 2VDD and a source and gate connected to a node n3. The P-type transistor P5 has a source and gate connected to the node n3 and a drain connected to the power supply VDD. The P-type transistor P5 and the N-type transistor N5 are the low-voltage transistors described above.

[0059] 8 includes, in addition to the configuration of FIG. 1, a P-type transistor P5 (corresponding to a fifth P-type transistor) and an N-type transistor N5 (corresponding to a fifth N-type transistor) connected in series between the power supply 2VDD and the power supply VDD. The source and gate of the P-type transistor P5 are connected to the power supply 2VDD, and the drain is connected to a node n3. The drain of the N-type transistor N5 is connected to the node n3, and the source and gate are connected to the power supply VDD.

[0060] When the output signal OUT from the output terminal OUT transitions, the voltage of node n3 may fluctuate unexpectedly due to the coupling of parasitic capacitance occurring between the output terminal OUT and node n3. For example, the voltage of node n3 may exceed 2VDD or fall below VDD. As shown in Figures 7 and 8, by providing a P-type transistor P5 and an N-type transistor N5, this voltage fluctuation can be suppressed. Note that, because the parasitic capacitance fluctuates depending on factors such as the proximity of wiring within the circuit, both the P-type transistor P5 and the N-type transistor N5 may be provided, or either the P-type transistor P5 or the N-type transistor N5 may be provided.

[0061] [Operation of Output Circuit] In this embodiment, the basic operation of the output circuit 1 as a whole is the same as that of the above-mentioned "Operation Example 1-1," "Operation Example 1-2," "Operation Example 1-3," and "Operation Example 1-4." Here, the explanation will be centered on the newly added configurations in FIGS. 7 and 8.

[0062] 7, when the voltage at node n3 rises above 2VDD, N-type transistor N5 turns on in the process, acting to lower the voltage at node n3 to 2VDD. In the output circuit 1 of FIG. 7, when the voltage at node n3 falls below VDD, P-type transistor P5 turns on in the process, acting to raise the voltage at node n3 to VDD.

[0063] In the output circuit 1 of Fig. 8, when the voltage of node n3 rises above 2VDD, P-type transistor P5 turns on in the process, acting to lower the voltage of node n3 to 2VDD. In the output circuit 1 of Fig. 8, when the voltage of node n3 falls below VDD, N-type transistor N5 turns on in the process, acting to raise the voltage of node n3 to VDD.

[0064] According to the present embodiment, even when the voltage of the parasitic capacitance coupling node n3 exceeds 2VDD or falls below VDD during operation of the output circuit 1, the Vgd, Vgs, and Vds of the P-type transistors P1, P2, and P3 and the N-type transistors N1, N2, and N3 are maintained at or below the breakdown voltages of the low-voltage transistors. This makes it possible to more reliably prevent deterioration over time of the P-type transistor P3 and the N-type transistor N3 than in the prior art.

[0065] Furthermore, the control circuit 20 according to this embodiment has a very simple configuration consisting of four transistors, which makes it possible to simplify the design of the output circuit 1 and reduce the circuit area.

[0066] <Modification of Second Embodiment> Figures 9 and 10 are circuit configuration diagrams of an input / output circuit according to a modification of the second embodiment. In Figures 9 and 10, components corresponding to those in Figures 7 and 8 are assigned the same reference numerals. The following description will focus on the differences from the second embodiment.

[0067] [Configuration of Input / Output Circuit] The input / output circuit 2 of FIG. 9 includes the output circuit 1 of FIG. 7 and an input buffer 40. The output terminal OUT of the output circuit 1 is connected to the input / output terminal INOUT. The input terminal 41 of the input buffer 40 is connected to the input / output terminal INOUT. The input / output circuit 2 of FIG. 10 includes the output circuit 1 of FIG. 8 and an input buffer 40. The output terminal OUT of the output circuit 1 is connected to the input / output terminal INOUT. The input terminal 41 of the input buffer 40 is connected to the input / output terminal INOUT. Note that in FIGS. 9 and 10, the specific circuit configuration of the input buffer 40 is not particularly limited, and a conventionally known buffer circuit configured by combining transistors can be applied.

[0068] 9 and 10, the input / output circuit 2 further includes a mode switching terminal EN for switching between input and output modes. The input / output circuit 2 is switched, by a mode switching signal EN input from the mode switching terminal EN, between operating in an input mode in which the input signal IN2 is received from the input / output terminal INOUT and operating in an output mode in which the output signal OUT of the output circuit 1 is output from the input / output terminal INOUT.

[0069] [Operation of Input / Output Circuit] The input / output circuit 2 of FIG. 9 operates by combining the output circuit 1 of the second embodiment (see FIG. 7) and the input / output circuit 2 of the modified example of the first embodiment (see FIG. 5). That is, as a basic operation, in the output mode, the operation is the same as in the above-mentioned "Operation Example 1-1," "Operation Example 1-2," "Operation Example 1-3," and "Operation Example 1-4," and in the input mode, the operation is the same as in the above-mentioned "Operation Example 1-5" and "Operation Example 1-6." Furthermore, when the voltage of node n3 rises above 2VDD, N-type transistor N5 turns on in the process, acting to lower the voltage of node n3 to 2VDD. When the voltage of node n3 falls below VDD, P-type transistor P5 turns on in the process, acting to raise the voltage of node n3 to VDD.

[0070] The input / output circuit 2 of FIG. 10 operates by combining the output circuit 1 of the second embodiment (see FIG. 8) and the input / output circuit 2 of the modified example of the first embodiment (see FIG. 5). That is, as a basic operation, in the output mode, the operation is the same as in the above-mentioned "Operation Example 1-1," "Operation Example 1-2," "Operation Example 1-3," and "Operation Example 1-4," and in the input mode, the operation is the same as in the above-mentioned "Operation Example 1-5" and "Operation Example 1-6." Furthermore, when the voltage of node n3 rises above 2VDD, P-type transistor P5 turns on in the process, acting to lower the voltage of node n3 to 2VDD. In the input / output circuit 2 of FIG. 10, when the voltage of node n3 falls below VDD and drops, N-type transistor N5 turns on in the process, acting to raise the voltage of node n3 to VDD.

[0071] [Operation and Effects of the Modification of the Second Embodiment] According to this modification, as with the modification of the first embodiment, the same effects as those of the first embodiment can be obtained, for example, even when the input / output circuit 2 operates in conjunction with an input signal from outside the LSI. Specifically, during operation of the input / output circuit 2, the Vgd, Vgs, and Vds of the P-type transistors P1, P2, and P3 and the N-type transistors N1, N2, and N3 are maintained at or below the breakdown voltages of the low-voltage transistors. This makes it possible to more accurately prevent deterioration over time of the P-type transistor P3 and the N-type transistor N3 than with conventional techniques.

[0072] Furthermore, since there is no wiring directly connecting the control circuit 20 and the input / output terminal INOUT, no leakage current (such as transistor leakage current) occurs between the outside of the LSI and the control circuit 20, and the control circuit 20 does not affect the quality of the input signal IN2.

[0073] Furthermore, similarly to the second embodiment, even when the voltage at the parasitic capacitance coupling node n3 exceeds 2VDD or falls below VDD during operation of the output circuit 1, the Vgd, Vgs, and Vds of the P-type transistors P1, P2, and P3 and the N-type transistors N1, N2, and N3 are maintained at or below the breakdown voltages of the low-voltage transistors. This makes it possible to more reliably prevent deterioration over time of the P-type transistor P3 and the N-type transistor N3 than in the prior art.

[0074] Furthermore, the control circuit 20 according to this embodiment has a very simple configuration consisting of four transistors, which makes it possible to simplify the design of the output circuit 1 and reduce the circuit area.

[0075] Other Embodiments The technology of the present disclosure is not limited to the configurations described in the above embodiments, and many modifications, such as changes, substitutions, additions, and omissions, are possible by a person of ordinary skill in the art within the technical spirit of the present disclosure. Furthermore, new embodiments can be created by combining the components described in the above embodiments.

[0076] For example, in the above embodiment, the power supply voltage of the power supply 3VDD is not limited to a voltage three times VDD. In other words, the voltage amplitude of the output signal is not limited to three times VDD. For example, by adjusting the voltage of each node, it is possible to output from the output circuit 1 or input from the input buffer 40 a voltage that is more than three times VDD or less than three times VDD.

[0077] The present disclosure can reliably prevent deterioration of transistors over time, and is therefore useful as an output circuit or an input / output circuit of an LSI.

[0078] 1 Output circuit 40 Input buffer 41 Input terminal IN Input signal INOUT Input / output terminal N1 N-type transistor (third N-type transistor) N2 N-type transistor (second N-type transistor) N3 N-type transistor (first N-type transistor) N4 N-type transistor (fourth N-type transistor) N5 N-type transistor (fifth N-type transistor) P1 P-type transistor (first P-type transistor) P2 P-type transistor (second P-type transistor) P3 P-type transistor (third P-type transistor) P4 P-type transistor (fourth P-type transistor) P5 P-type transistor (fifth P-type transistor) OUT Output terminal, output signal VDD Power supply (third power supply) 2VDD Power supply (second power supply) 3VDD Power supply (first power supply) VSS Ground (fourth power supply) n1 First node n2 Second node n3 3rd node n4 4th node n5 5th node

Claims

1. An output circuit that receives an input signal and outputs an output signal that varies in accordance with the input signal, comprising: an output terminal that outputs the output signal; a first P-type transistor having a source connected to a first power supply and a drain connected to a first node, and having a gate that receives a signal that varies in accordance with the input signal; a second P-type transistor having a source connected to the first node, a drain connected to a second node, and a gate that is connected to a second power supply having a power supply voltage lower than that of the first power supply; a third P-type transistor having a source connected to the second node, a drain connected to the output terminal, and a gate that is connected to a third node; a first N-type transistor having a drain connected to the output terminal, a source connected to a fourth node, and a gate that is connected to the third node; a second N-type transistor having a drain connected to the fourth node, a source connected to a fifth node, and a gate that is connected to a third power supply having a power supply voltage lower than that of the second power supply; and a third N-type transistor having a drain connected to the fifth node, a source connected to a fourth power supply having a power supply voltage lower than that of the third power supply, and having a gate that receives a signal that varies in accordance with the input signal. an output circuit comprising: a fourth N-type transistor having a drain connected to the second power supply, a source connected to the third node, and a gate connected to the second node; and a fourth P-type transistor having a source connected to the third node, a drain connected to the third power supply, and a gate connected to the fourth node.

2. An output circuit according to claim 1, comprising: a fifth N-type transistor having a drain connected to the second power supply and a source and gate connected to the third node; and a fifth P-type transistor having a source and gate connected to the third node and a drain connected to the third power supply.

3. An output circuit according to claim 1, comprising: a fifth P-type transistor having a source and a gate connected to the second power supply and a drain connected to the third node; and a fifth N-type transistor having a drain connected to the third node and a source and a gate connected to the third power supply.

4. An input / output circuit comprising: an output circuit according to claim 1; an input / output terminal to which said output terminal is connected; and an input buffer having an input terminal connected to said input / output terminal.

5. An input / output circuit comprising: an output circuit according to claim 2; an input / output terminal to which said output terminal is connected; and an input buffer having an input terminal connected to said input / output terminal.

6. An input / output circuit comprising: an output circuit according to claim 3; an input / output terminal to which said output terminal is connected; and an input buffer having an input terminal connected to said input / output terminal.

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