Circuit element with programmable impedance, method for designing same, and method for operating same

Abstract

A programmable impedance element includes a plurality of nominally identical two-port elements, each two-port element having an impedance element and two switches. The two-port elements are arranged in a chain with a structured switch group such that a certain range of impedances can be obtained from each unit by dynamically changing the connections between the impedance elements in the unit. A common unit is constructed by connecting the nominally identical two-port impedance elements in such a way that the number of possible combinations of impedance elements is reduced to a subset of all possible combinations using the minimum possible number of connections. This structure allows the use of industry-standard devices to generate matching impedances. The connections between the impedance elements are switches, which can be "field programmable", i.e., they can be set on the chip after manufacturing and configured during the operation of the circuit or can be mask programmable.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority of Provisional Application No. 62 / 813,121, filed on March 3, 2019, the entire content of which is incorporated herein by reference. Technical field

[0003] The present invention generally relates to analog integrated circuits, and more particularly to such circuits that include elements having impedance. Background art

[0004] As artificial intelligence (AI) becomes increasingly prevalent and useful, designers are looking for better ways to implement the mathematical operations required for neural networks used in AI to function. In some cases, AI networks can be implemented in an analog computer rather than a digital computer. There are commercial reasons for this, as analog circuits can generally have higher speed and lower power consumption than their digital equivalents.

[0005] As is known in the art, the common layer operation in a neural network is given by:

[0006] Y i = σ(A ij ·X j + C i ) (Equation 1)

[0007] Where A ij is a two - dimensional array, and X j is a vector of input quantities (there is an implicit summation over repeated indices, in this case a summation over j, i.e., Einstein notation). The activation function σ is typically, for example, the hyperbolic tangent function, and C i is the activation threshold.

[0008] One of the challenges in the analog implementation of neural networks is the multiplication operation required in each neuron of the layer, i.e., the multiplication of A*X in Equation 1 above. Additionally, each multiplication operation may require different weights for the input values. Solutions such as R - 2R ladder networks, memristors, and charge storage devices have been proposed to implement the multiplication operation. For various reasons, none of these are ideal.

[0009] For example, R-2R ladder networks and charge storage devices that operate in an analog manner (i.e., produce a nominally continuous variation of channel conductance with a certain resolution) require a "probe current" to access values; thus, in order to observe the channel conductance or the R-2R ladder setting, a certain current must flow, which generates a certain voltage, and the resistance value is the voltage divided by the current (V / I). Since useful networks constructed based on these principles may have, for example, one million components, even a small probe current of 100 nanoamperes (nA) in each component may cause a total current consumption of 100 milliamperes (mA).

[0010] Using weights in the analog implementation of neural networks is particularly challenging, which often limits the applicability of analog circuits in AI. There are implementation techniques that consider adaptable weights, such as capacitors, floating-gate transistors, charge-coupled devices (CCDs), etc. However, these techniques all face various problems, such as process parameter variations across the entire chip during manufacturing, limited storage times (i.e., volatility of information), and lack of compatibility with standard very-large-scale integration (VLSI) processing technologies.

[0011] Resistors are easy to represent weights and have long been considered a possible solution for the adjustable weights required in neural networks. For example, Figure 1 is a diagram of a so-called T-model analog neuron proposed as a unit in a T-model network 20 years ago. As shown in Figure 1, the T-model analog neuron relies on variable resistors Ti1 to Tii-1 to obtain the necessary adjustable weights.

[0012] However, after a circuit chip containing resistors is manufactured, the resistors are not yet suitable. Therefore, a chip made of fixed components (such as resistors) can only perform one aspect of a more general AI solution with two stages. In the first stage, the AI network learns through various means well-known to those skilled in the emerging field of AI methods. This is called "training". Once the learning has been carried out, new data is provided to the AI network, and the learned values are applied to this new data. This second stage is called "inference".

[0013] Training requires incremental adjustment of the components of the network to find a specific set of values that minimizes a specified error. During training, the components are constantly changing: fixed values are clearly incompatible with this process. However, once the training is complete, these values are known, and a device can be constructed using these fixed values. Therefore, fixed-value devices are generally capable of performing the second inference stage.

[0014] However, practical problems may prevent a fixed-value network from performing the second inference stage; the required network may be so large that it is impractical to fabricate all fixed elements. A common solution for very large systems is to use "time-division multiplexing" (TDM); however, this solution is not possible with fixed weights, and thus adjustable weights are again required for the elements. In this case, TDM is used to implement a subset of the complete AI inference machine with limited resources: the weights of this subset are loaded into adjustable elements instead of fixed elements. The AI then performs a part of the complete solution corresponding to the subset weights and stores its results in some type of memory. The adjustable weights are then updated to represent the next small part of the complete AI, and the results of the first subset are applied from the memory; this is repeated until all weights have been used.

[0015] When time-division multiplexing with such limited resources is employed, there will be many weight adjustments. For example, if the inference runs at one million operations per second and only one-tenth of the entire machine can be implemented, the weights will change 100 million times per second. It is known in the art that such rapid changes in programmable weights cannot be at low power, but rather consume a certain amount of computable power when changing the weights.

[0016] Adjustable weights provide additional advantages. If the AI inference machine is small enough to be mounted on a chip, having adjustable weights has a huge commercial advantage: upon power-up, the weights are loaded into the adjustable elements only once, and thereafter no power is consumed to change the weights. There is no need to change the weights because the entire AI inference machine is represented by this on-chip set of weights and time-division multiplexing is not required. Thus, one chip serves many tasks and is programmed once after fabrication.

[0017] For at least these reasons, using variable resistors in an analog computer is not feasible in terms of readability. It would be desirable to have a simple way to fabricate variable impedance elements in an analog integrated circuit without the disadvantages of the above prior art solutions.

[0018] In addition, many other analog circuits also use devices with impedance, and thus, without a doubt, there are other cases where it would be desirable to be able to adjust the impedance of such elements during the operation of the circuit. SUMMARY OF THE INVENTION

[0019] This application describes a simple circuit with programmable impedance and a method for its design.

[0020] One embodiment describes a circuit element with programmable impedance, comprising: a first two-port element, the first two-port element including a unified impedance element having two ends, a first switch connected to a first of the two ends of the unified impedance element and having an open position and a closed position, a second switch connected to a second of the two ends of the unified impedance element and having an open position and a closed position; a plurality of additional two-port elements, each additional two-port element being nominally identical to the first two-port element, the two-port elements being connected in a chain such that: a first of the two ends of the unified impedance element in each additional two-port element is connected to a switch connected to a second of the two ends of the unified impedance element in a previous two-port element, and a second of the two ends of the unified impedance element in each additional two-port element is connected to a switch connected to a first of the two ends of the unified impedance element in an immediately previous two-port element; an input port connected to the first two-port element, configured to receive an input signal; an output port connected to the last two-port element, configured to output a signal from the circuit element; and a control port configured to receive a control signal that sets the switches of the first two-port element and the additional two-port elements to a selected configuration of an open position and a closed position.

[0021] Another embodiment describes a method of designing a circuit element with programmable impedance, comprising: 2 The invention further comprises selecting N nominally identical two-port elements at a desired ratio of 1 to 1, each of the two-port elements comprising a unified impedance element having two ends, a first switch connected to a first end of the two ends of the unified impedance element and having an open position and a closed position, and a second switch connected to a second end of the two ends of the unified impedance element and having an open position and a closed position; and a plurality of additional two-port elements, each of the additional two-port elements being nominally identical to the first two-port element, the two-port elements being connected in a chain such that: the first end of the two ends of the unified impedance element in each additional two-port element is connected to the switch connected to the second end of the two ends of the unified impedance element in the previous two-port element, and the unified impedance element in each additional two-port element is connected to the switch connected to the second end of the two ends of the unified impedance element in the previous two-port element. a second end of the two ends of an impedance element connected to a switch connected to a first end of the two ends of the unified impedance element in the immediately preceding two-port element; connected to an input port of a first two-port element; connected to an output port of a last two-port element; and a control port configured to receive a control signal that sets the switches of the first two-port element and the additional two-port element to a selected configuration of an open position and a closed position; select a value for each unified impedance element based on a desired maximum impedance value and / or a minimum impedance value of a circuit; determine all possible available impedance values ​​using N two-port elements each having an impedance of R and determine a switch position corresponding to each available impedance value.

[0022] Another embodiment describes a method of operating a circuit element having a programmable impedance. The circuit element includes: a first two-port element including a uniform impedance element having two ends, a first switch connected to a first end of the two ends of the uniform impedance element and having an open position and a closed position, and a second switch connected to a second end of the two ends of the uniform impedance element and having an open position and a closed position; a plurality of additional two-port elements, each additional two-port element being nominally the same as the first two-port element, the two-port elements being connected in a chain such that: a first end of the two ends of the uniform impedance element in each additional two-port element is connected to a switch connected to a second end of the two ends of the uniform impedance element in the previous two-port element, and a second end of the two ends of the uniform impedance element in each additional two-port element is connected to a switch connected to a first end of the two ends of the uniform impedance element in the immediately preceding two-port element; an input port connected to the first two-port element; an output port connected to the last two-port element; and a control port configured to receive a control signal that sets the switches of the first two-port element and the additional two-port elements to a selected configuration of open and closed positions. The method includes: applying a control signal to the control port that sets the switches to a configuration that gives the circuit element a selected impedance value; applying an input signal to the input port; and receiving an output signal from the output port. In another embodiment, applying the control signal to the control port further includes: determining a desired impedance value of the circuit element; selecting an impedance value from a plurality of possible impedance values of the circuit element that is closest to the desired impedance value; and configuring the control signal to set the switches to positions that give the circuit element the selected impedance value. Description of the Drawings

[0023] FIG. 1 is a diagram of a T-model analog neuron known in the prior art.

[0024] Figure 2 is a diagram of a two-port element known in the prior art.

[0025] Figures 3 to 5 is a diagram of a common unit having a programmable impedance according to one embodiment.

[0026] Figure 6 is a schematic representation of a common unit according to another embodiment.

[0027] Figure 7 is a diagram of a common unit having a programmable impedance according to another embodiment.

[0028] Figure 8Graphs showing the values of the common unit of six impedance elements, and graphs showing the values of the common unit of 16 impedance elements.

[0029] Figure 9 Is a schematic diagram of a common unit according to another embodiment.

[0030] Figure 10 Is a flowchart of a method for selecting values of multiple programmable impedances according to one embodiment. Detailed Description

[0031] A simple circuit with programmable impedance and a method for designing the circuit are described herein. The method described herein uses a "common cell" composed of multiple nominally identical two-port elements, each two-port element having a unified impedance element and two switches. The two-port elements are arranged in a specific chain manner together with a subset of structured switches such that a certain range of impedances can be obtained from each cell by dynamically changing the connections between the impedance elements in the cell. The common cell is constructed by connecting the nominally identical two-port elements in such a way that the number of possible combinations of the impedance elements is reduced to a subset of all possible combinations that uses the minimum possible number of connections.

[0032] The resulting circuit according to the present method enables the generation of matching impedance using industrial standard devices. In addition, the connections between the impedance elements can be "field programmable" switches, i.e., switches that can be set on the chip after manufacturing and configured during the operation of a circuit (such as an analog computer) that contains the impedance elements; or alternatively, the connections can be mask programmable switches.

[0033] Figure 2 Is a diagram of a two-port element 200 known in the prior art and can be used in the present method described herein. The two-port element 200 has an impedance element 202 and two switches 204, one switch 204 is connected to one end of the impedance element 202, and the other switch 204 is connected to the other end of the impedance element 202.

[0034] It is known that series and / or parallel arrangements of nominally identical two-port elements such as element 200 can be set up to create an equivalent two-port element with adjustable impedance. For example, see U.S. Patent No. 9,361,419 ("the '419 patent"), where multiple nominally equal two-port elements in a cell can be connected in various ways to achieve different impedances. As described herein, the method of the '419 patent has certain advantages, such as allowing for process variations between multiple cells on a semiconductor chip, a large number of possible impedance values for each cell (assuming a sufficiently large number of impedance elements), etc. For example, 16 two-port elements in a cell can be connected in different ways to obtain over 600,000 different impedance values.

[0035] However, the method of the '419 patent also has certain limitations. In this method, the configuration of the two-port elements within a block can only be selected once and then "hard-wired", i.e., connected in a permanent manner such that it cannot be changed later. Additionally, if the connections of the impedance elements are on a chip containing the cells, the method of the '419 patent requires determining how the connections to each two-port element can be positioned outside the cells on the chip, which is a process known as "placement and routing". (An alternative method is to position the connections of the two-port elements of the cell outside the chip itself, but these connections would be hard-wired and thus unchangeable).

[0036] Multiple nominally identical two-port elements such as Figure 2 element 200 can be configured in a specific array to create a common cell that results in certain limitations on the number of possible combinations of the elements within the cell, such that only a subset of all possible combinations is available. The array is a chain of two-port elements where each two-port element can only be connected to the other elements in the chain in a specific way, such that the number of possible connections between the two-port elements is at its minimum. This method enables some of the benefits of the method of the '419 patent to be obtained without the disadvantages of this existing method.

[0037] Figure 3 Such a common cell 300 including an array of two-port elements according to the present method is shown, where each impedance element 202 is now a resistor 302. As shown, the common cell 300 contains eight resistors 302 and 16 switches 304. It is assumed that the resistors 302 have the same uniform value and that the switches 304 can be opened and closed by a digital device after chip construction.

[0038] In Figure 3 all the switches 304 are shown as open, so the array 300 in Figure 3 is open-circuited and has a virtually infinite resistance (and thus impedance). (Note that opening Figure 2The two switches 204 in [it] will isolate the component 200 from the next component; thus, disconnecting any two switches 304 associated with the same impedance component 302 will also result in an open circuit and infinite impedance.)

[0039] Note that although resistors are used in this figure and the following figures, the present method is not limited to resistors as impedance components. For example, the physical size of a field effect transistor (FET) connected and operating in its resistive region on an advanced chip may be much smaller than that of a resistor with an equal impedance. Therefore, in the case where resistors are shown in the figures herein, those skilled in the art will understand that a FET or any other impedance component with a nominal linear resistance may be substituted, as long as all components have a uniform impedance. For example, in addition to resistors or FETs, the repeating impedance components may be inductors, capacitors, memristors, or complex devices such as diodes, varactors, or coupled inductors that are biased over a specific range of conditions to represent these linear components.)

[0040] Figure 4 A common unit 400 is shown, which is similar to the Figure 3 common unit 300 except for the switch configuration. In the common unit 400, the upper switch 404a after the first resistor 402 is open, while the lower switch 404b after the first resistor 402 is closed. Conversely, the upper switch 404c after the second resistor 402 is closed, while the lower switch 404d after the second resistor 402 is open. Therefore, it is obvious that the current from the input port A must flow to the first resistor 402 of the common unit 400 and then through the second resistor 402, and these resistors are thus in series. The switches in the common unit 400 alternate in this way so that the current must flow through all eight resistors 402 in the common unit 400, i.e., all the resistors 402 are in series. If each resistor has a value of R, the total resistance of the common unit 400 is 8R because there are eight resistors. As those skilled in the art will understand, this is the maximum resistance that can be obtained from a common unit with eight resistors.)

[0041] Figure 5 A common unit 500 is shown, which is also similar to the Figure 3 and Figure 4The common units 300 and 400 therein. In the common unit 500, all switches in the switches 504 are closed except for the last upper switch 504a. As a result, any current is divided among all the resistors in the resistor 502, that is, the resistors 502 are in parallel, so the common unit 500 has an effective resistance of R / 8. Moreover, as those skilled in the art will understand, this is the minimum resistance that can be obtained from an array with eight resistors. (If the switch 504a in the common unit 500 is closed, the result is that there is no effective resistance between point A and point B, and the common unit 500 will be short-circuited).

[0042] Therefore, ignoring the effectively infinite resistance of an open circuit or the effectively zero resistance of a short circuit (which is of less concern in many applications and can be obtained in a simpler way than this method), for example Figures 3 to 5 the common unit shown can have a resistance between 8R and R / 8, where R is also the resistance of each resistor, depending on how the switches are configured and thus on how the resistors are connected in series and / or in parallel. This effectively ranges from 64 to 1 between the maximum and minimum resistances of the array.

[0043] It will be obvious to those skilled in the art that the resistance R of each resistor can be adjusted to obtain the required absolute values of the maximum relative value 8R and / or the minimum relative value R / 8. Those skilled in the art will also recognize that an array constructed in this way does not need to contain resistors, but any impedance element can be used. In addition, such an array does not need to have only eight resistors or other impedance elements; rather, any number of two-port elements can be added as needed to obtain a larger range than 64 to 1 when needed.

[0044] Figure 6 As shown, for example Figures 3 to 5 a schematic diagram of the common unit 600 is shown. Here, the entire common unit is represented as a resistor; the value of the resistor shown will be the resistance of the common unit, which depends on the selected positions of the switches in the common unit as described above. The control signal D enters on the bus 602 to control the positions of the switches in the common unit, thus determining the impedance of the common unit.

[0045] Figure 7 is a diagram of another common unit 700 with programmable impedance according to one embodiment, which shows Figure 6 how the control signal D in it can operate. In this example, the common unit 700 has six impedance elements 702a to 702f.

[0046] A mapping is established by using numbers to represent the switch positions of each two-port impedance element in the common unit. For example, for a given impedance element, 1 can be used to indicate the "upper" switch, for example Figure 4Switch 404a in Figure 4 is closed, and -1 is used to indicate that a "lower" switch, for example

[0047] in Figure 7 is open, and 0 is used to indicate that both switches are closed. (As described above, if both switches of a given two-port element are open, the common cell is open.) Then, a list of these numbers can be used to indicate how the elements in the common cell are connected.

[0048] As Figure 7 shown, the lower switch 702g of impedance element 702a is closed, while the upper switch 702h of element 702a is open. Thus, according to the mapping described above, the switch position of impedance element 702a is represented by -1. Since both switches associated with each of impedance elements 702b, 702d, and 702e are closed, these switch positions are each represented by 0. The upper switch associated with impedance element 702c is closed while the lower switch is open, so that impedance element 702c is 1. Like impedance element 702a, impedance element 702f has an open upper switch and a closed lower switch, such that impedance element 702f is also represented by -1. Thus, using the 1, 0, and -1 mapping nomenclature described above for the six impedance elements 702a through 702f, the switch positions of common cell 700 can be represented by the following string:

[0049] [-1, 0, 1, 0, 0, -1]

[0050] As Figure 6 in, one way to digitally encode the control signal is to use two bits to represent each element of the string (since each element has 3 possible values), so a 12-bit string is to be input as control signal D to the common cell having six impedance elements.

[0051] In order to obtain an impedance value close to a particular desired value from a common unit, all possible combinations of the impedance elements in the common unit should be known. Although this can be done manually, clearly, more impedance elements in the common unit will result in a rapid increase in the number of possible values. This can be easily done with the aid of a computer; for example, attached as an appendix to this document is an example of LISP code that generates all possible values of the overall impedance of the common unit, corresponding to all possible switch configurations of any given number of impedance elements.

[0052] In practice, an equivalent of the example LISP code can be implemented in a controller on a chip or in a system containing the common unit. Alternatively, all possible impedance values can be calculated and then these values, along with the associated switch positions, can be stored in a table on the chip or in the system. Once the desired impedance value of a particular common unit is input, the closest available impedance of that common unit can be selected and the switches of the impedance elements can be placed in the positions corresponding to that closest available common unit impedance.

[0053] In the case of the common unit 700, given six impedance elements, there are 26 possible values for the overall impedance. If the nominal impedance of each impedance element is 1, then as described above, these values range from 1 / 6 to 6, with a ratio of 1 to 36, and their range is shown as follows:

[0054]

[0055]

[0056] (In this case, there are two different configurations that result in an impedance value of 2.333; however, this is not necessarily the case for other numbers of impedance elements).

[0057] Figure 8 Figure 802 shows the 26 values for the six-impedance-element common unit and Figure 804 shows approximately 800 values for the 16-impedance-element common unit. The Y-axis on each figure is logarithmic, and it can be seen that in both cases, the resulting curve of possible values is generally also logarithmic, and is smoother for Figure 804, which has more values from a common unit with a greater number of impedance elements. It is believed that a logarithmic distribution of available weights in an AI system is advantageous.

[0058] Note that the number of possible values for a common cell with 16 impedance elements using this method is much less than the approximately 650,000 possible values for a cell with 16 two-port elements in the method of the '419 patent. This is because the '419 patent allows the 32 available ports to be connected in any way, whereas in this method, how the two ports of each element are connected to the elements up and down the chain is restricted by how the other elements are interconnected. As described above, different from the connections in the '419 patent, in this method, the connections between elements, i.e., switches, are field programmable. Additionally, the locations of the connections between the two-port elements in this method are fixed by the chain configuration of the two-port elements, so a placement and routing process such as that in the case of the '419 patent is not required.

[0059] Figure 9 FIG. is a schematic diagram of a common cell 900 according to another embodiment where FETs are used as impedance elements. As described above, an FET has a nominal linear resistance in the resistive region and thus can replace the resistors shown and described herein; one advantage of replacing a resistor is that the physical size of an FET can be much smaller than that of a resistor with an equal impedance.

[0060] In the common cell 900, an FET (e.g., FET 902) having a gate connected to signal Bias is an impedance element; the impedance element is preferably a long and narrow device operating in its resistive region. An FET 904 having a gate connected to bus A is a switch; these switches are preferably short devices having a low resistance ("on-resistance") between the drain and the source when operating.

[0061] Figure 10 FIG.

[0059] is a flowchart of a method for selecting values of multiple programmable impedances according to one embodiment.

[0062] At step 1002, the number N of nominally identical two-port elements to be included in each common cell is selected based on the desired ratio of the maximum value to the minimum value for each common cell. This ratio will always be from N to 1 / N, i.e., in the range of N, as seen above in 2 (8 elements, 64-to-1 ratio) and Figure 3 (6 elements, 36-to-1 ratio). Figure 7

[0063] At step 1004, the impedance values of the impedance elements in the two-port elements are selected based on the desired maximum and minimum impedances desired in the circuit or system. As discussed above with respect to Figure 7 , if there are N elements according to step 1002 and the value selected for each impedance element is R, the range of available impedance values for each common cell will be N*R to R / N.

[0064] At step 1006, all impedance values available in each common cell are calculated based on the values of N and R from steps 1002 and 1004. As described above, this can be done by the controller during the operation of the circuit or system containing the common cell, or it can be done prior to such operation, and the results are stored on the chip or in the system as a table of available values, where the table has a corresponding switch position for each value.

[0065] Based on the design of the circuit or system in which the common cell will be used, there will be a desired impedance value for each common cell. For example, in an AI system that uses impedance elements for signal weighting, each such impedance element will have an expected value that reflects the desired signal weighting.

[0066] At step 1008, for each common cell that serves as an impedance element, an impedance value is selected as one of the available values that is closest to the expected value for that impedance element. The selected impedance value will have a corresponding pattern regarding how to set the switches in the common cell so that the common cell will have the selected impedance value. Then, when the circuit or system is in operation, the switch pattern can be implemented so that the common cell provides the selected impedance value. Then, as described above, an input signal is applied to the first two-port element of the common cell, and an output signal is received from the last two-port element of the common cell.

[0067] By combining these features, a programmable and variable impedance element can be constructed. Those skilled in the art will understand that programmable and variable impedances with any number of different values can be constructed according to these principles.

[0068] The disclosed system has been illustrated above with reference to several embodiments. Other embodiments will be apparent to those skilled in the art in light of the present disclosure. Certain aspects of the described methods and devices can be readily implemented using configurations different from those described in the embodiments above, or by combining elements different from those described above or in addition to those described above.

[0069] For example, as is well known to those skilled in the art, various alternatives will be apparent to those skilled in the art. Additionally, the illustration of transistors and resistors is exemplary; those skilled in the art will be able to select the appropriate number of resistors, transistors, and / or similar elements suitable for a particular application.

[0070] The present disclosure is intended to cover these and other variations of the embodiments, and the present disclosure is defined only by the appended claims.

[0071] Appendix

[0072] LISP code for generating all possible values of the total impedance of a common cell corresponding to all possible switch configurations for any number of cells.

[0073]

Claims

1. A circuit element with programmable impedance, comprising: First two-port element, comprising: A uniform impedance element having two ends, the uniform impedance element having an impedance value; A first switch connected to a first end of the two ends of the uniform impedance element and having an open position and a closed position; A second switch connected to a second end of the two ends of the uniform impedance element and having an open position and a closed position; A plurality of additional two-port elements, each additional two-port element being nominally the same as the first two-port element, wherein the uniform impedance element in each additional two-port element has the same impedance value as the uniform impedance element in the first two-port element; wherein the first two-port element and the plurality of additional two-port elements are connected in a chain such that: A first end of the two ends of the uniform impedance element in each additional two-port element is connected to the first switch connected to a first end of the two ends of the uniform impedance element in the previous two-port element; and A second end of the two ends of the uniform impedance element in each additional two-port element is connected to the second switch connected to a second end of the two ends of the uniform impedance element in the previous two-port element; An input port connected to the first two-port element, configured to receive an input signal; an output port connected to the last two-port element, configured to output a signal from the circuit element; and A control port configured to receive a control signal that sets the switches of the first two-port element and the additional two-port elements to a selected configuration of open and closed positions.

2. The circuit element according to claim 1, wherein, The uniform impedance element is a resistor.

3. The circuit element according to claim 1, wherein, The uniform impedance element is a field effect transistor.

4. The circuit element according to claim 1, wherein, The uniform impedance element is a capacitor.

5. The circuit element according to claim 1, wherein, The uniform impedance element is a memristor.

6. The circuit element according to claim 1, wherein, The uniform impedance element is a diode.

7. The circuit element according to claim 6, wherein, The diode is a varactor diode.

8. The circuit element according to claim 1, wherein, The uniform impedance element is a coupled inductor.

9. A method for designing a circuit element with programmable impedance, comprising: Based on the N from the maximum impedance value to the minimum impedance value of the circuit element 2 The circuit element comprises the N two-port elements, an input port, an output port, and a control port, wherein the N two-port elements comprise a first two-port element and a plurality of additional two-port elements, each of which comprises a uniform impedance element having two ends, a first switch connected to a first end of the two ends of the uniform impedance element and having an open position and a closed position, and a second switch connected to a second end of the two ends of the uniform impedance element and having an open position and a closed position; each of the additional two-port elements is nominally the same as the first two-port element, and each of the additional two-port elements comprises a first two-port element and a plurality of additional two-port elements, each of which comprises a uniform impedance element having two ends, a first switch connected to a first end of the two ends of the uniform impedance element and having an open position and a closed position, and a second switch connected to a second end of the two ends of the uniform impedance element and having an open position and a closed position. The unified impedance element in the first two-port element has the same impedance value as the unified impedance element in the first two-port element, and the first two-port element is connected to the plurality of additional two-port elements in a chain, so that: a first end of both ends of the unified impedance element in each additional two-port element is connected to a first switch connected to a first end of both ends of the unified impedance element in a previous two-port element, and a second end of both ends of the unified impedance element in each additional two-port element is connected to a second switch connected to a second end of both ends of the unified impedance element in the previous two-port element; the input port is connected to the first two-port element; and the output port is connected to the last two-port element; The control port is configured to receive a control signal that sets the switches of the first two-port element and the additional two-port elements to a selected configuration of open and closed positions; Select a value for each uniform impedance element based on the desired maximum impedance value and / or minimum impedance value of the circuit; And Determine all possible available impedance values using N two-port elements each having an R impedance and determine the switch positions corresponding to each available impedance value.

10. The method according to claim 9, further comprising storing the possible available impedance values and corresponding switch positions in a memory.

11. A method for operating a circuit element with programmable impedance, the circuit element comprising: First two-port element, the first two-port element comprising a uniform impedance element having two ends, a first switch connected to a first end of the two ends of the uniform impedance element and having an open position and a closed position, and a second switch connected to a second end of the two ends of the uniform impedance element and having an open position and a closed position; Multiple additional two-port elements, each additional two-port element being nominally identical to the first two-port element, the uniform impedance element in each additional two-port element having the same impedance value as the uniform impedance element in the first two-port element, the first two-port element being connected in a chain with the multiple additional two-port elements such that: a first end of the two ends of the uniform impedance element in each additional two-port element is connected to a first switch connected to a first end of the two ends of the uniform impedance element in the previous two-port element, and a second end of the two ends of the uniform impedance element in each additional two-port element is connected to a second switch connected to a second end of the two ends of the uniform impedance element in the previous two-port element; connected to the input port of the first two-port element; Connected to the output port of the last two-port element; a control port configured to receive a control signal setting the switches of the first two-port element and the additional two-port elements to a selected configuration of open and closed positions, the method comprising: Applying a control signal to the control port, the control signal setting the switches to a configuration that causes the circuit element to have a selected impedance value; Applying an input signal to the input port; and Receiving an output signal from the output port.

12. According to the method of claim 11, wherein, Applying a control signal to the control port further comprises: Determining a desired impedance value of the circuit element; Selecting an impedance value closest to the desired impedance value from among a plurality of possible impedance values of the circuit element; and Configuring the control signal to set the switches to a position that causes the circuit element to have the selected impedance value.

Images