Physically non-copyable function circuit and operation method thereof and semiconductor chip

Abstract

A physical non-copyable function circuit and its operation method and a semiconductor chip. The physical non-copyable function circuit includes a flash memory, a current comparator and a controller. The flash memory includes multiple memory cells. The method includes the controller setting these memory cells in an initial data state, the controller setting these memory cells between the initial data state and the adjacent initial data state of the initial data state, the current comparator reading a first current from the first area memory cells of these memory cells, the current comparator reading a second current from the second area memory cells of these memory cells, and the current comparator outputting random bits according to the first current and the second current.

Description

Technical Field

[0001] The present invention relates to data security, and in particular to an operation method of a physically non-copyable function circuit, a physically non-copyable function circuit and a semiconductor chip. Background Art

[0002] The physically unclonable function (PUF) circuit prevents data theft and ensures data security through the unique "digital fingerprint" of each semiconductor element. The PUF circuit in the related art sets the memory cell in a critical range near the read current level and uses the read current level to read the memory cell to generate random data. However, when the read current level is not in the center of the critical range, the randomness of the random data will be reduced, resulting in reduced data security. Summary of the invention

[0003] An embodiment of the present invention provides an operation method of a physical non-copyable function circuit. The physical non-copyable function circuit includes a flash memory, a current comparator and a controller. The flash memory includes multiple memory cells. The method includes the controller setting these memory cells in an initial data state, the controller setting these memory cells between the initial data state and the adjacent initial data state of the initial data state, the current comparator reading a first current from the first area memory cells of these memory cells, the current comparator reading a second current from the second area memory cells of these memory cells, and the current comparator outputting random bits based on the first current and the second current.

[0004] Another embodiment of the present invention provides a physical non-copyable function circuit, comprising a flash memory, a current comparator and a controller. The flash memory comprises a plurality of memory cells. The current comparator is coupled to the first zone memory cells and the second zone memory cells of the memory cells. The controller is coupled to the flash memory and the current comparator. The controller is used to set the memory cells in an initial data state, and to set the memory cells between the initial data state and the adjacent initial data state of the initial data state. The current comparator is used to read a first current from the first zone memory cells, read a second current from the second zone memory cells, and output a random bit according to the first current and the second current.

[0005] Another embodiment of the present invention provides a semiconductor chip, including a physical non-copyable function circuit and a key generator. The physical non-copyable function circuit includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. The current comparator is coupled to the first zone memory cells and the second row memory cells of these memory cells. The controller is coupled to the flash memory and the current comparator. The key generator is coupled to the physical non-copyable function circuit. The controller is used to set these memory cells in an initial data state, and to set these memory cells between the initial data state and the adjacent initial data state of the initial data state. The current comparator is used to read a first current from the first zone memory cells, read a second current from the second zone memory cells, and output a random bit based on the first current and the second current. The key generator generates a key based on the random bit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 The figure is a block diagram of a physically non-copyable function circuit in an embodiment of the present invention.

[0007] Figure 2 show Figure 1 Current distribution of the memory cell in .

[0008] Figure 3 for Figure 1 Flowchart of the operating method of the PUF circuit in FIG.

[0009] Figure 4 for Figure 1 A circuit diagram of a current comparator in FIG.

[0010] Figure 5 for Figure 1 Another circuit diagram of a current comparator in FIG.

[0011] Figure 6 The relationship between the weak erase voltage and the current difference between the first current and the second current is shown.

[0012] Figure 7 Shows the relationship between weak erase voltage and random bits.

[0013] Figure 8 is a block diagram of a semiconductor chip in an embodiment of the present invention.

[0014]

Main component symbol description

[0015] 1: PUF circuit

[0016] 10: Line decoder

[0017] 12: Flash memory

[0018] 121, 122: memory block

[0019] 14: Controller

[0020] 16: Current comparator

[0021] 300: Operation method

[0022] 410, 412, 440, 442, 510, 530: transistors

[0023] 414, 444, 500, 502, 540, 542: Current source

[0024] 420: Operational Amplifier

[0025] 440, 460, 520 and 522: Inverter

[0026] 70, 72: Simulation curve

[0027] 8: Semiconductor Chips

[0028] 80:Key Generator

[0029] 82:Codec

[0030] BL1(1) to BL1(M), BL2(1) to BL2(M): bit lines

[0031] D1, Dm, D0: Distribution

[0032] Din: Input data

[0033] Dout: output data

[0034] Kpb: Public key

[0035] Kprv: Private Key

[0036] L1, Lm, L0: current level

[0037] Dpuf: Random bits

[0038] I: Current

[0039] I1: First current

[0040] I2: Second current

[0041] Iref: reference current

[0042] M1(1,1) to M1(M,N), M2(1,1) to M2(M,N): memory cells

[0043] S302 to S310: Steps

[0044] VDD: supply voltage

[0045] VSS: Ground voltage

[0046] WL1(1) to WL1(N), WL2(1) to WL2(N): word lines DETAILED DESCRIPTION

[0047] Figure 1 1 is a block diagram of a physically unclonable function (PUF) circuit 1 in an embodiment of the present invention. The PUF circuit 1 may not use the read current level to generate the random bit Dpuf, thereby increasing the randomness of the random bit Dpuf. The random bit Dpuf may be a first logic value or a second logic value, and the probability that the random bit Dpuf is the first logic value and the probability that the random bit Dpuf is the second logic value may be substantially equal. The first logic value may be logic "0", and the second logic value may be logic "1", but the first logic value and the second logic value are not limited thereto.

[0048] The PUF circuit 1 may include a row decoder 10, a flash memory 12, a controller 14, and a current comparator 16. The flash memory 12 may be a NAND flash memory, and may include memory blocks 121 and 122. The memory block 121 may include memory cells M1(1, 1) to M1(M, N) arranged in N rows, and the N rows of memory cells of the memory block 121 may be coupled to the row decoder 10 via word lines WL1(1) to WL1(N), and may be coupled to the current comparator 16 via bit lines BL1(1) to BL1(M), where N is a positive integer greater than 1. The memory block 122 may include memory cells M2(1,1) to M2(M,N) arranged in N rows. The N rows of memory cells of the memory block 122 may be coupled to the row decoder 10 via word lines WL2(1) to WL2(N), and may be coupled to the current comparator 16 via bit lines BL2(1) to BL2(M). The memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) may be single-layer cells or multi-layer cells. The current comparator 16 may be a sense amplifier or a differential current comparator. The controller 14 may be coupled to the current comparator 16 and to the flash memory 12 via the row decoder 10.

[0049] The memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) can be set in an erased state, a lowest programming state or a random state. The random state can be between the erased state and the lowest programming state. During normal operation, each memory cell M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) will be set in an erased state or a lowest programming state and will not be set in a random state. When generating the random bit Dpuf, the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) will be set in a random state. The controller 14 can set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to a random state at factory or reset. Figure 2 The current distribution of the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) is shown, wherein the horizontal axis represents the current and the vertical axis represents the number of memory cells. When reading data, the controller 14 may apply a predetermined read voltage, such as 0V, to the control terminals of the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) via the row decoder 10, and the current comparator 16 may read the current flowing through the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to determine the state. According to the state of the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N), the read current I may form a distribution D1, Dm or D0. Distributions D1, Dm and D0 are the current distributions of the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) in the lowest programming state, random state and erased state, respectively. Current levels L1, Lm and L0 are the average values ​​of distributions D1, Dm and D0, respectively. For example, current levels L1, Lm and L0 may be 0μA, 10μA and 20μA, respectively. When setting a random state, the controller 14 may first erase the data in the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) (distribution D1), and then program the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to the lowest programming state (distribution D1), and then perform a weak erase procedure to set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to a random state (distribution Dm). In some embodiments, when setting a random state, the controller 14 may first erase the data in the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) (distribution D1), and then perform a weak programming procedure to set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to a random state (distribution Dm).

[0050] When it is necessary to generate a random bit Dpuf, the current comparator 16 can read a first current from one of the memory cells M1 (1, 1) to M1 (M, N), and read a second current from one of the memory cells M2 (1, 1) to M2 (M, N), and output the random bit Dpuf based on the first current and the second current. Specifically, the current comparator 16 can compare the first current and the second current to generate a comparison result, and generate the random bit Dpuf based on the comparison result. If the comparison result shows that the first current is greater than the second current, the current comparator 16 outputs the first logic value of the random bit Dpuf; if the comparison result shows that the first current is less than the second current, the current comparator 16 outputs the second logic value of the random bit Dpuf. Since the PUF circuit 1 outputs the random bit Dpuf based on the first current and the second current, the randomness of the random bit Dpuf is not affected by the read current level, which helps to increase the randomness of the random bit Dpuf. In addition, Figure 2 The distribution Dm of the random state is wider than the distribution D1 of the lowest programmed state and the distribution D0 of the erased state, so the difference between the first current and the second current may be larger, increasing the randomness of the random bit Dpuf and accelerating the generation of the random bit Dpuf.

[0051] Figure 3 3 is a flow chart of the operation method 300 of the PUF circuit 1. The control method 300 includes steps S302 to S310 for generating random bits Dpuf. Any reasonable technical changes or step adjustments fall within the scope of the present invention. The details of steps S302 to S310 are as follows:

[0052] Step S302: The controller 14 sets the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) in an initial data state;

[0053] Step S304: the controller 14 sets the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) in an initial data state and between the adjacent data states of the initial data state;

[0054] Step S306: the current comparator 16 reads a first current from the first region memory cells of the memory cells M1(1,1) to M1(M,N);

[0055] Step S308: the current comparator 16 reads a second current from the second region memory cells of the memory cells M2(1,1) to M2(M,N);

[0056] Step S310: The current comparator 16 outputs a random bit Dpuf according to the first current and the second current.

[0057] In step S302, the initial data state may be the lowest programmed state or the erased state. In step S304, if the initial data state is the lowest programmed state, the adjacent data state is the erased state, and the controller 14 applies a weak erase pulse to the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to a random state between the lowest programmed state and the erased state. Specifically, the controller 14 may apply a weak erase pulse to the control terminals of the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) through the word lines WL1(1) to WL1(N), WL2(1) to WL2(M), and apply a high voltage to the common P-type well of the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N). The weak erase pulse may be 7 to 8V. If the initial data state is the erase state, the adjacent data state is the lowest programming state, and the controller 14 applies a weak programming pulse to the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) in a random state between the erase state and the lowest programming state. Specifically, the controller 14 may apply a weak programming pulse to the control terminals of the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) via the word lines WL1(1) to WL1(N), WL2(1) to WL2(N), and apply a positive voltage to the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) via the bit lines BL1(1) to BL1(M), BL2(1) to BL2(M). The weak programming pulse may be 7 to 8V. In steps S306 and S308, the first region memory cells are memory cells in a specific range in the memory block 121, and the second region memory cells are memory cells in a specific range in the memory block 122. In some embodiments, the first region memory cells are the nth row of the memory block 121, and the second region memory cells are the nth row of the memory block 122. When a request to generate a random bit Dpuf is received, the controller 14 enables the nth row of the memory block 121 and the nth row of the memory block 122 via the word lines WL1(n) and WL2(n), respectively, so that the current comparator 16 reads the first current from the memory cell M1(m,n) in the nth row and the mth column of the memory block 121 and reads the second current from the memory cell M2(m,n) in the nth row and the mth column of the memory block 122, respectively, where n is a positive integer from 1 to N and m is a positive integer from 1 to M.In some embodiments, the first region memory cells are the n1th row of the memory block 121, and the second region memory cells are the n2th row of the memory block 122, where n1 and n2 are positive integers from 1 to N. The controller 14 can enable the n1th row of the memory block 121 and the n2th row of the memory block 122 via the word lines WL1 (n1) and WL2 (n2), respectively, so that the current comparator 16 reads the first current from the memory cell M1 (m, n1) in the n1th row and the mth column of the memory block 121 and reads the second current from the memory cell M2 (m, n2) in the n2th row and the mth column of the memory block 122, respectively, where m is a positive integer from 1 to M. In step S310, if the comparison result shows that the first current is greater than the second current, the current comparator 16 outputs the first logic value (logic "0") of the random bit Dpuf; if the comparison result shows that the first current is less than the second current, the current comparator 16 outputs the second logic value (logic "1") of the random bit Dpuf. In some embodiments, the current comparator 16 may also read multiple memory cells from the nth row of the memory block 121 and the nth row of the memory block 122 to generate k first currents and k second currents, and compare the k first currents and the k corresponding second currents to generate k random bits Dpuf, where k is a positive integer from 1 to M. Please refer to Table 1. The current comparator 16 reads the memory cell M1(m,n) of the word line WL1(n) to obtain 7 first currents and 7 second currents respectively, and compares the 7 first currents {8μA, 7μA, 12μA, 4μA, 15μA, 9μA, 9μA} and the 7 corresponding second currents {4μA, 12μA, 14μA, 5μA, 12μA, 3μA, 15μA} to generate 7 random bits Dpuf{0(8>4), 1(7<12), 1(12<14), 1(4<5), 0(15>12), 0(9>3), 1(9<15)}.

[0058] Table 1

[0059] WL1(n) WL2(n) DpU 8 4 0 7 12 1 12 14 1 4 5 1 15 12 0 9 3 0 9 15 1

[0060] The operation method 300 outputs the random bit Dpuf according to the first current and the second current. Therefore, the randomness of the random bit Dpuf is not affected by the read current level, which helps to increase the randomness of the random bit Dpuf.

[0061] Figure 4 is a circuit diagram of a current comparator 16. The current comparator 16 includes transistors 410, 412, 440 and 442, inverters 400 and 460, current sources 414 and 444 and an operational amplifier 420. The current comparator 16 can receive a first current I1 and a second current I2, and output a random bit Dpuf according to the first current I1 and the second current I2.

[0062] The transistor 410 includes a first terminal for receiving a power supply voltage VDD, a second terminal, and a control terminal coupled to the second terminal of the transistor 410. The transistor 412 includes a first terminal coupled to the second terminal of the transistor 410, a second terminal, and a control terminal. The current source 414 includes a first terminal coupled to the second terminal of the transistor 412, and a second terminal for receiving a ground voltage VSS. The inverter 400 includes a first terminal coupled to the first terminal of the current source 414, and a second terminal coupled to the control terminal of the transistor 412. The transistor 440 includes a first terminal for receiving a power supply voltage VDD, a second terminal, and a control terminal coupled to the control terminal of the transistor 410. The transistor 442 includes a first terminal coupled to the second terminal of the transistor 440, a second terminal, and a control terminal. The current source 444 includes a first terminal coupled to the second terminal of the transistor 442, and a second terminal for receiving a ground voltage VSS. The inverter 460 includes a first terminal coupled to the first terminal of the current source 444, and a second terminal coupled to the control terminal of the transistor 442. The operational amplifier 420 includes a first input terminal coupled to the second terminal of the transistor 412, a second input terminal coupled to the second terminal of the transistor 442, and an output terminal. The first input terminal of the operational amplifier 420 may be a positive input terminal, and the first input terminal of the operational amplifier 420 may be an inverting input terminal. The transistors 410 and 440 may be P-type transistors, and the transistors 412 and 442 may be N-type transistors.

[0063] Transistors 410 and 440 can be used as current mirrors. Transistors 412 and 442 can be used as current clamps. In an initial state, the first current I1 and the second current I2 are 0, and the control end of transistor 412 and the control end of transistor 442 can receive a fixed bias voltage, such as 0.8V, to clamp the voltage of the first input end and the voltage of the second input end of the operational amplifier 420. When generating the random bit Dpuf, if the first current I1 is greater than the second current I2, the current source 414 will increase the voltage of the first terminal of the current source 414 according to the first current I1, the inverter 400 will reduce the voltage of the second terminal of the inverter 400, and the transistor 412 will reduce the voltage of the first input terminal of the operational amplifier 420; similarly, the current source 444 will increase the voltage of the first terminal of the current source 444 according to the second current I2, the inverter 460 will reduce the voltage of the second terminal of the inverter 460, and the transistor 442 will reduce the voltage of the second input terminal of the operational amplifier 420; because the first current I1 is greater than the second current I2, the voltage of the first input terminal of the operational amplifier 420 will be lower than the voltage of the second input terminal, and the output terminal of the operational amplifier 420 will output a logic "0" as the random bit Dpuf. If the first current I1 is less than the second current I2, the voltage of the first input terminal of the operational amplifier 420 will be higher than the voltage of the second input terminal, and the output terminal of the operational amplifier 420 will output a logic "1" as the random bit Dpuf.

[0064] Figure 5 is a circuit diagram of another current comparator 16. The current comparator 16 includes current sources 500, 502, 540 and 542, transistors 510 and 530, and inverters 520 and 522. The current comparator 16 can receive the first current I1 and the second current I2, and output a random bit Dpuf according to the first current I1 and the second current I2.

[0065] The current source 500 includes a first terminal for receiving a power supply voltage VDD and a second terminal. The current source 502 includes a first terminal coupled to the second terminal of the current source 500 and a second terminal for receiving a ground voltage VSS. The transistor 510 includes a first terminal, a second terminal for receiving the ground voltage VSS, and a control terminal coupled to the second terminal of the current source 500 and the first terminal of the current source 502. The current source 540 includes a first terminal for receiving a power supply voltage VDD and a second terminal. The current source 542 includes a first terminal coupled to the second terminal of the current source 540 and a second terminal for receiving the ground voltage VSS. The transistor 530 includes a first terminal, a second terminal for receiving the ground voltage VSS, and a control terminal coupled to the second terminal of the current source 540 and the first terminal of the current source 542. The inverter 522 includes a first terminal coupled to the first terminal of the transistor 510 and a second terminal coupled to the first terminal of the transistor 530. The inverter 520 includes a first terminal coupled to the first terminal of the transistor 530, and a second terminal coupled to the first terminal of the transistor 510. The transistors 510 and 530 may be N-type transistors.

[0066] Current sources 500 and 540 may generate a reference current Iref. Current source 502 may generate a first current I1, and current source 503 may generate a second current I2. Inverters 520 and 522 may form a latch. In an initial state, the first current I1 and the second current I2 are 0, and the control terminal of transistor 510 and the control terminal of transistor 530 may receive a fixed bias voltage to establish substantially the same voltage at the first terminal of transistor 510 and the first terminal of transistor 530. When generating the random bit Dpuf, if the first current I1 is greater than the second current I2, the current sources 500 and 502 will establish a voltage at the control end of the transistor 510 according to the difference between the reference current Iref and the first current I1; the current sources 540 and 542 will establish a voltage at the control end of the transistor 530 according to the difference between the reference current Iref and the second current I2; since the first current I1 is greater than the second current I2, the voltage at the control end of the transistor 510 will be less than the voltage at the control end of the transistor 530, the voltage at the first end of the transistor 510 will be greater than the voltage at the first end of the transistor 530, and the latch will output a logic "0" as the random bit Dpuf. If the first current I1 is less than the second current I2, the voltage at the control end of the transistor 510 will be greater than the voltage at the control end of the transistor 530, the voltage at the first end of the transistor 510 will be less than the voltage at the first end of the transistor 530, and the latch will output a logic "1" as the random bit Dpuf.

[0067] Figure 6 The relationship between the weak erase voltage and the current difference between the first current and the second current is shown, where the horizontal axis represents the weak erase pulse and the vertical axis represents the current difference between the first current I1 and the second current I2. When the weak erase pulse is between 6V and 8V, the current difference between the first current I1 and the second current I2 has a normal distribution centered on 0. When the weak erase pulse increases from 6V to 8V, the current difference between the first current I1 and the second current I2 also expands from ±5μA to ±20μA. When the weak erase pulse is less than -7V, the current difference between the first current I1 and the second current I2 exceeds ±10μA. Therefore, the PUF circuit 1 can use a weak erase pulse between 7V and 8V to set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to random states.

[0068] Figure 7The relationship between the weak erase voltage and the random bit is shown, where the horizontal axis represents the weak erase pulse and the vertical axis represents the percentage. The simulation curve 70 indicates that the first current I1 is greater than the second current I2, and the random bit Dpuf is a percentage of the first logic value; the simulation curve 72 indicates that the first current I1 is less than the second current I2, and the random bit Dpuf is a percentage of the second logic value. When the weak erase pulse increases from 6V to 8V, the simulation curves 70 and 72 also gradually approach 50%. When the weak erase pulse is between 7V and 8V, the percentage of the random bit Dpuf as the first logic value and the percentage of the random bit Dpuf as the second logic value approach 50%. Therefore, the PUF circuit 1 can use a weak erase pulse between 7V and 8V to set the memory cells M1(1,1) to M1(M,N), M2(1,1) to M2(M,N) to a random state to enhance randomness.

[0069] Figure 8 8 is a block diagram of a semiconductor chip 8 in an embodiment of the present invention. The semiconductor chip 8 includes a PUF circuit 1, a key generator 80, and a codec 82. The PUF circuit 1, the key generator 80, and the codec 82 are coupled in sequence. The circuit configuration and operation of the PUF circuit 1 have been explained in the previous paragraphs and will not be repeated here.

[0070] When encoding / decoding, the PUF circuit 1 can receive a request to generate a random bit Dpuf, the key generator 80 can generate a public key Kpb and a secret key Kprv based on the random bit Dpuf, and the codec 82 can encode / decode the input data Din based on the secret key Kprv to generate the output data Dout. The input data Din can be pre-encoding data, pre-encoding address, encoded data, and / or encoded address. After encoding, the codec 82 can output the output data Dout to an external circuit, the key generator 80 can output the public key Kpb to the external circuit, and the external circuit can decode the output data Dout based on the public key Kpb to obtain the input data Din. Since the random bit Dpuf has enhanced randomness, the data security of the input data Din can be ensured.

[0071] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. An operating method of a physically non-copyable function circuit, the physically non-copyable function circuit comprising a flash memory, a current comparator and a controller, the flash memory comprising a plurality of memory cells, characterized in that: The method includes: The controller sets the plurality of memory cells in an initial data state; After the controller sets the plurality of memory cells in the initial data state, the controller sets the plurality of memory cells between the initial data state and an adjacent data state of the initial data state; The current comparator reads a first current from a first region memory cell of the plurality of memory cells; The current comparator reads a second current from a second region of memory cells of the plurality of memory cells; and The current comparator outputs a random bit according to the first current and the second current.

2. The method according to claim 1, characterized in that The current comparator generates the random bit according to the first current and the second current, which includes: if the first current is greater than the second current, the current comparator outputs the first logic value of the random bit.

3. The method according to claim 1, characterized in that The current comparator generates the random bit according to the first current and the second current, which includes: if the first current is smaller than the second current, the current comparator outputs the second logic value of the random bit.

4. The method according to claim 1, characterized in that: The initial data state is the lowest programming state, the adjacent data state is an erase state, and the controller sets the multiple memory cells between the initial data state and the adjacent data state of the initial data state, including: the controller applies a weak erase pulse to the multiple memory cells to set the multiple memory cells between the initial data state and the adjacent data state.

5. The method according to claim 1, characterized in that The initial data state is an erased state, the adjacent data state is a lowest programming state, and the controller sets the multiple memory cells between the initial data state and the adjacent data state of the initial data state, including: the controller applies a weak programming pulse to the multiple memory cells to set the multiple memory cells between the initial data state and the adjacent data state.

6. The method according to claim 1, characterized in that The current comparator is a sense amplifier.

7. The method according to claim 1, characterized in that The current comparator is a differential current comparator.

8. A physically non-copyable function circuit, characterized in that: Include: A flash memory comprising a plurality of memory cells; a current comparator coupled to the first region memory cells and the second region memory cells of the plurality of memory cells; and A controller coupled to the flash memory and the current comparator; wherein the controller is used to set the plurality of memory cells in an initial data state, and after the controller sets the plurality of memory cells in the initial data state, the plurality of memory cells are set between the initial data state and an adjacent data state of the initial data state; and The current comparator is used for reading a first current from the first area memory cell, reading a second current from the second area memory cell, and outputting a random bit according to the first current and the second current.

9. The physical non-copyable function circuit according to claim 8, characterized in that: If the first current is greater than the second current, the current comparator outputs a first logic value of the random bit.

10. The physical non-copyable function circuit according to claim 8, characterized in that: If the first current is less than the second current, the current comparator outputs the second logic value of the random bit.

11. The physical non-copyable function circuit according to claim 8, characterized in that: The initial data state is the lowest programming state, the adjacent data state is an erase state, and the controller is used to apply a weak erase pulse to the plurality of memory cells to set the plurality of memory cells between the initial data state and the adjacent data state.

12. The physical non-copyable function circuit according to claim 8, characterized in that: The initial data state is an erase state, the adjacent data state is a lowest programming state, and the controller is used to apply weak programming pulses to the plurality of memory cells to set the plurality of memory cells between the initial data state and the adjacent data state.

13. The physical non-copyable function circuit according to claim 8, characterized in that: The current comparator is a sense amplifier.

14. The physical non-copyable function circuit according to claim 8, characterized in that: The current comparator is a differential current comparator.

15. A semiconductor chip, characterized in that: Include: Physically non-copyable function circuits, including: A flash memory comprising a plurality of memory cells; The current comparator is coupled to The multiple a first region memory cell and a second region memory cell of the memory cell; and A controller coupled to the flash memory and the current comparator; and A key generator coupled to the physical non-copyable function circuit; The controller is used to The multiple The memory cells are set in an initial data state, and after the controller sets the plurality of memory cells in the initial data state, The multiple The memory cell is arranged between the initial data state and an adjacent data state of the initial data state; The current comparator is used to read a first current from the first region memory cell, read a second current from the second region memory cell, and output a random bit according to the first current and the second current; and The key generator generates a key according to the random bits.

16. The semiconductor chip according to claim 15, characterized in that If the first current is greater than the second current, the current comparator is used to output the first logic value of the random bit.

17. The semiconductor chip according to claim 15, characterized in that If the first current is smaller than the second current, the current comparator is used to output the second logic value of the random bit.

18. The semiconductor chip according to claim 15, characterized in that The initial data state is the lowest programming state, the adjacent data state is an erase state, and the controller is used to apply a weak erase pulse to the plurality of memory cells to set the plurality of memory cells between the initial data state and the adjacent data state.

19. The semiconductor chip according to claim 15, characterized in that The initial data state is an erase state, the adjacent data state is a lowest programming state, and the controller is used to apply weak programming pulses to the plurality of memory cells to set the plurality of memory cells between the initial data state and the adjacent data state.

20. The semiconductor chip according to claim 15, characterized in that The current comparator is a sense amplifier or a differential current comparator.

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