Pixel circuit, driving method thereof and flat panel detector

Abstract

The embodiment of the present application provides a pixel circuit, a driving method thereof and a flat panel detector. The pixel circuit comprises: a first thin film transistor, a gate of the first thin film transistor being connected with a reset voltage line, a source of the first thin film transistor being connected with a first end of a first capacitor, a first end of a second capacitor and a negative electrode of a photosensitive diode; a drain of the first thin film transistor being connected with a reference voltage line; a second end of the first capacitor being connected with a positive electrode of the photosensitive diode and a bias voltage line; a second end of the second capacitor being connected with a gate of a fourth thin film transistor and a source of a fifth thin film transistor; the source of the fourth thin film transistor being connected with the drain of the fifth thin film transistor, the drain of the fourth thin film transistor being connected with a source of a third thin film transistor; the drain of the third thin film transistor being connected with an output signal line; and a drain of a second thin film transistor being connected with the source of the fourth thin film transistor. The present application can avoid the influence of the threshold voltage of the source follower and its drift on the pixel circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel circuit and its driving method, and a flat panel detector. Background Technology

[0002] Currently, flat panel detectors used in various fields such as medical imaging, security inspection, and industrial detection mainly employ amorphous silicon (a-Si) thin-film transistor (TFT) technology. The pixel circuitry of a flat panel detector includes passive pixel sensor (PPS) and active pixel sensor (APS) structures. A PPS typically consists of a photodiode and a TFT switch, while an APS contains multiple TFT switches. Compared to PPS, the APS structure offers a better signal-to-noise ratio. Furthermore, in APS, the source follower operates in the saturation region, amplifying changes in the output current signal. Therefore, APS flat panel detectors require only a lower dose of X-rays to expose images.

[0003] Reference Figure 1 A 3T-APS provided for the prior art includes three thin-film transistors, as shown in the reference. Figure 2 Another 4T-APS provided by the prior art includes four thin-film transistors; wherein, the 3T-APS and 4T-APS are due to the source follower ( Figure 1 and Figure 2 The presence of T2 in the image causes the output signal Iout of the APS to be affected by the T2 threshold voltage and its drift, which in turn interferes with the image quality of the flat panel detector. Summary of the Invention

[0004] This invention provides a pixel circuit to solve the problem that existing pixel circuits interfere with the image quality of flat panel detectors due to the influence of the threshold voltage of the source follower.

[0005] The first aspect of the present invention provides a pixel circuit, which includes: a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, a fourth thin-film transistor, a fifth thin-film transistor, a first capacitor, a second capacitor, and a photodiode;

[0006] The gate of the first thin-film transistor is connected to the reset voltage line, the source of the first thin-film transistor is connected to the first terminal of the first capacitor, the first terminal of the second capacitor, and the negative terminal of the photodiode, respectively, and the drain of the first thin-film transistor is connected to the reference voltage line.

[0007] The second terminal of the first capacitor is connected to the positive terminal of the photodiode and the bias voltage line, respectively.

[0008] The second terminal of the second capacitor is connected to the gate of the fourth thin-film transistor and the source of the fifth thin-film transistor, respectively.

[0009] The source of the fourth thin-film transistor is connected to the drain of the fifth thin-film transistor, and the drain of the fourth thin-film transistor is connected to the source of the third thin-film transistor; the drain of the third thin-film transistor is connected to the output signal line.

[0010] The source of the second thin-film transistor is connected to the power supply, and the drain of the second thin-film transistor is connected to the source of the fourth thin-film transistor.

[0011] Optionally, the gate of the second thin-film transistor is connected to the first on-voltage signal line; the first on-voltage signal provided by the first on-voltage signal line controls the second thin-film transistor to be in an on or off state.

[0012] The gate of the third thin-film transistor is connected to the second on-voltage signal line; the second on-voltage signal provided by the second on-voltage signal line controls the third thin-film transistor to be in an on or off state.

[0013] The gate of the fifth thin-film transistor is connected to the third conduction voltage signal line; the third conduction voltage signal provided by the third conduction voltage signal line controls the fifth thin-film transistor to be in the conduction or off state.

[0014] Optionally, the reset voltage provided by the reset voltage line is used to control the first thin-film transistor to turn on, so that the voltage at the source of the first thin-film transistor is reset to the reference voltage.

[0015] Optionally, the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the fourth thin-film transistor, and the fifth thin-film transistor are N-type thin-film transistors or P-type thin-film transistors.

[0016] A second aspect of the present invention provides a driving method for a pixel circuit, applied to the pixel circuit described in any one of the preceding claims, the method comprising:

[0017] During the reset phase, the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, and the fifth thin-film transistor are turned on.

[0018] During the compensation phase, the first thin-film transistor, the third thin-film transistor, and the fifth thin-film transistor are turned on, and the second thin-film transistor is turned off.

[0019] During the integration phase, the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, and the fifth thin-film transistor are turned off, allowing the photodiode to integrate during exposure and charging the first capacitor and the second capacitor.

[0020] During the reading phase, the second and third thin-film transistors are turned on, and the first and fifth thin-film transistors are turned off, and the current value at the drain of the third thin-film transistor is read.

[0021] Optionally, during the reset phase, the potential of the source of the first thin-film transistor is the reference voltage provided by the reference voltage line, and the potentials of the drain of the second thin-film transistor and the second terminal of the second capacitor are both the power supply voltage provided by the power supply.

[0022] Optionally, during the compensation phase, the potential of the source of the first thin-film transistor is the reference voltage provided by the reference voltage line, and the potentials of the drain of the second thin-film transistor and the second terminal of the second capacitor are both the threshold voltage of the fourth thin-film transistor.

[0023] Optionally, during the integration phase, the potential of the source of the first thin-film transistor is the sum of the reference voltage provided by the reference voltage line and the voltage difference of the photodiode, and the potential of the second terminal of the second capacitor is the sum of the threshold voltage of the fourth thin-film transistor and the voltage difference of the photodiode.

[0024] Optionally, during the reading phase, the reading phase ends when the potential at the second terminal of the second capacitor reaches the threshold voltage.

[0025] A third aspect of the present invention provides a flat panel detector, including the pixel circuitry described in any one of the first aspects.

[0026] This invention provides a pixel circuit, comprising: a first thin-film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a first capacitor, a second capacitor, and a photodiode; wherein the gate of the first TFT is connected to a reset voltage line, the source of the first TFT is connected to a first terminal of the first capacitor, a first terminal of the second capacitor, and the negative terminal of the photodiode; the drain of the first TFT is connected to a reference voltage line; the second terminal of the first capacitor is connected to the positive terminal of the photodiode and a bias voltage line; the second terminal of the second capacitor is connected to the gate of the fourth TFT and the source of the fifth TFT; the source of the fourth TFT is connected to the drain of the fifth TFT, and the drain of the fourth TFT is connected to the source of the third TFT; the drain of the third TFT is connected to an output signal line; the source of the second TFT is connected to a power supply, and the drain of the second TFT is connected to the source of the fourth TFT. The pixel circuit provided in this embodiment of the invention uses five thin-film transistors. After the fifth thin-film transistor is turned on, the cathode of the photodiode maintains the threshold voltage of the source follower (fourth thin-film transistor) before exposure integration. Furthermore, it can actively subtract the threshold voltage during the readout stage to avoid the pixel circuit being affected by the threshold voltage of the source follower and its drift. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of a pixel circuit in the prior art;

[0029] Figure 2 This is a schematic diagram of another pixel circuit in the prior art;

[0030] Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of a pixel circuit driving method provided in an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of the reset stage of a pixel circuit provided in an embodiment of the present invention;

[0033] Figure 6This is a schematic diagram of the compensation stage of a pixel circuit provided in an embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram of the integration stage of a pixel circuit provided in an embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram of the reading stage of a pixel circuit provided in an embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Reference Figure 3 The diagram shows a pixel circuit provided in an embodiment of the present invention. The pixel circuit includes: a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, a fourth thin-film transistor T4, a fifth thin-film transistor T5, a first capacitor C1, a second capacitor C2, and a photodiode.

[0038] The gate of the first thin-film transistor T1 is connected to the reset voltage line Vrst, the source N1 of the first thin-film transistor T1 is connected to the first terminal N1 of C1, the first terminal N1 of the second capacitor C2, and the negative terminal N1 of the photodiode; the drain of the first thin-film transistor T1 is connected to the reference voltage line Vref.

[0039] The second terminal of the first capacitor C1 is connected to the positive terminal of the photodiode and the bias voltage line Vbias, respectively.

[0040] The second terminal N2 of the second capacitor C2 is connected to the gate of the fourth thin-film transistor T4 and the source N2 of the fifth thin-film transistor T5, respectively.

[0041] The source N3 of the fourth thin-film transistor T4 is connected to the drain N3 of the fifth thin-film transistor T5, and the drain of the fourth thin-film transistor T4 is connected to the source of the third thin-film transistor T3; the drain of the third thin-film transistor T3 is connected to the output signal line Iout.

[0042] The source of the second thin-film transistor T2 is connected to the power supply VDD+, and the drain N3 of the second thin-film transistor T2 is connected to the source N3 of the fourth thin-film transistor T4.

[0043] The source of the first thin-film transistor T1, the first terminal of the first capacitor C1, the first terminal of the second capacitor, and the negative terminal of the photodiode are connected at node N1; the second terminal of the second capacitor, the source of the fifth thin-film transistor, and the gate of the fourth thin-film transistor are connected at node N2; and the source of the fourth thin-film transistor, the drain of the fifth thin-film transistor, and the drain of the second thin-film transistor are connected at node N3.

[0044] In this embodiment of the invention, the first, second, third, fourth, and fifth thin-film transistors are either N-type or P-type thin-film transistors. Specifically, the N-type thin-film transistor is turned on by a high-level voltage signal and turned off by a low-level voltage signal; the P-type thin-film transistor is turned on by a low-level voltage signal and turned off by a high-level voltage signal.

[0045] Furthermore, the reset voltage provided by the reset voltage line Vrst is used to control the first thin-film transistor T1 to turn on, so that the voltage at the source of the first thin-film transistor T1 is reset to the reference voltage Vref.

[0046] In addition, the reset voltage line Vrst is connected to the gate of the first thin film transistor T1 and is used to control the conduction and turn-off of the first thin film transistor T1. When the first thin film transistor T1 is controlled to be turned on, the potential of the N1 node is the reference voltage Vref.

[0047] Specifically, when the first thin-film transistor T1 is an N-type thin-film transistor, the reset voltage line Vrst provides a high-level voltage signal to the first thin-film transistor T1 to turn it on, and a low-level voltage signal to turn it off; when the first thin-film transistor T1 is a P-type thin-film transistor, the reset voltage line Vrst provides a low-level voltage signal to the first thin-film transistor T1 to turn it on, and a high-level voltage signal to turn it off.

[0048] In this embodiment of the invention, reference is made to Figure 3 The gate of the second thin-film transistor T2 is connected to the first conduction voltage signal line Va; the first conduction voltage signal provided by the first conduction voltage signal line Va controls the second thin-film transistor T2 to be in the conduction or off state.

[0049] Specifically, when the second thin-film transistor T2 is an N-type thin-film transistor, the first conduction voltage signal line Va provides a high-level voltage signal to the second thin-film transistor T2 to turn it on, and a low-level voltage signal to turn it off; when the second thin-film transistor T2 is a P-type thin-film transistor, the first conduction voltage signal line Va provides a low-level voltage signal to the second thin-film transistor T2 to turn it on, and a high-level voltage signal to turn it off.

[0050] The gate of the third thin-film transistor T3 is connected to the second on-voltage signal line Vb; the second on-voltage signal provided by the second on-voltage signal line Vb controls the third thin-film transistor T3 to be in the on or off state.

[0051] Specifically, when the third thin-film transistor T3 is an N-type thin-film transistor, the second conduction voltage signal line Vb provides a high-level voltage signal to the third thin-film transistor T3 to turn it on, and a low-level voltage signal to turn it off; when the third thin-film transistor T3 is a P-type thin-film transistor, the second conduction voltage signal line Vb provides a low-level voltage signal to the third thin-film transistor T3 to turn it on, and a high-level voltage signal to turn it off.

[0052] The gate of the fifth thin-film transistor T5 is connected to the third conduction voltage signal line Vc; the third conduction voltage signal provided by the third conduction voltage signal line Vc controls the fifth thin-film transistor T5 to be in the conduction or off state.

[0053] Specifically, when the fifth thin-film transistor T5 is an N-type thin-film transistor, the third conduction voltage signal line Vc provides a high-level voltage signal to the fifth thin-film transistor T5 to turn it on, and a low-level voltage signal to turn it off; when the fifth thin-film transistor T5 is a P-type thin-film transistor, the third conduction voltage signal line Vc provides a low-level voltage signal to the fifth thin-film transistor T5 to turn it on, and a high-level voltage signal to turn it off.

[0054] The pixel circuit provided in this embodiment of the invention uses five thin-film transistors. After the fifth thin-film transistor is turned on, the cathode of the photodiode maintains the threshold voltage of the source follower (fourth thin-film transistor) before exposure integration. Furthermore, it can actively subtract the threshold voltage during the readout stage to avoid the pixel circuit being affected by the threshold voltage of the source follower and its drift.

[0055] Reference Figure 4 This illustrates an embodiment of the present invention providing a driving method for a pixel circuit, applicable to any of the pixel circuits described above, wherein... Figure 4 When the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, and the fifth thin-film transistor T5 are all N-type thin-film transistors, the method includes:

[0056] During the reset phase, the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, and the fifth thin-film transistor T5 are turned on.

[0057] Among them, reference Figure 5The diagram shows a pixel circuit during the reset phase. During the reset phase, the potential of the source N1 of the first thin-film transistor T1 is the reference voltage Vref provided by the reference voltage line Vref, and the potentials of the drain N3 of the second thin-film transistor T2 and the second terminal N2 of the second capacitor C2 are both the power supply voltage VDD provided by the power supply VDD+.

[0058] Specifically, the reset voltage line Vrst provides a reset voltage Vrst to the first thin-film transistor T1, turning it on. After the first thin-film transistor T1 is turned on, the potential at node N1 is the reference voltage Vref. After the first turn-on voltage signal line Va controls the second thin-film transistor T2 to turn on, the potential at node N3 is the power supply voltage VDD. After the third turn-on voltage signal line Vc controls the fifth thin-film transistor T5 to turn on, the potential at node N2 is the power supply voltage VDD. When the potential at node N2 is the power supply voltage VDD, the fourth thin-film transistor T4 is also in the turned-on state.

[0059] Furthermore, when the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, and the fifth thin-film transistor T5 are all N-type thin-film transistors, during the reset phase, the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, and the fifth thin-film transistor T5 remain at a high potential and are turned on. When the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, and the fifth thin-film transistor T5 are all P-type thin-film transistors, during the reset phase, the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, and the fifth thin-film transistor T5 remain at a low potential and are turned on.

[0060] During the compensation phase, the first thin-film transistor T1, the third thin-film transistor T3, and the fifth thin-film transistor T4 are turned on, and the second thin-film transistor is turned off.

[0061] Among them, reference Figure 6 The diagram shows a pixel circuit during the compensation phase. During the compensation phase, the potential of the source N1 of the first thin-film transistor T1 is the reference voltage Vref provided by the reference voltage line Vref, and the potentials of the drain N3 of the second thin-film transistor T2 and the second terminal N2 of the second capacitor C2 are both the threshold voltage Vth of the fourth thin-film transistor T4.

[0062] Specifically, after the second thin-film transistor T2 is turned off, the power supply voltage VDD cannot be obtained at node N3, and therefore node N2 also cannot obtain the power supply voltage VDD. The fourth thin-film transistor T4 is also turned off. Then the potential at node N2 is the threshold voltage Vth of the fourth thin-film transistor T4. Since the fifth thin-film transistor T5 is in the conducting state, the potential at node N3 is also the threshold voltage Vth, thus achieving early compensation for the threshold voltage Vth of the source follower (fourth thin-film transistor T4).

[0063] Furthermore, when the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, and the fifth thin-film transistor T5 are all N-type thin-film transistors, during the compensation phase, the first thin-film transistor T1, the second thin-film transistor T2, and the fifth thin-film transistor T5 remain at a high potential and are turned on, while the third thin-film transistor T3 remains at a low potential and is turned off. When the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, and the fifth thin-film transistor T5 are all P-type thin-film transistors, during the compensation phase, the first thin-film transistor T1, the second thin-film transistor T2, and the fifth thin-film transistor T5 remain at a low potential and are turned on, while the third thin-film transistor T3 remains at a high potential and is turned off.

[0064] During the integration phase, the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, and the fifth thin-film transistor T4 are turned off, so that the photodiode is exposed and integrated, and the first capacitor C1 and the second capacitor C2 are charged.

[0065] Among them, reference Figure 7 The diagram shows the pixel circuit during the integration phase. During the integration phase, the potential of the source N1 of the first thin-film transistor T1 is the sum of the reference voltage Vref provided by the reference voltage line Vref and the voltage difference Vpin of the photodiode (Vref+Vpin), and the potential of the second terminal N2 of the second capacitor C2 is the sum of the threshold voltage Vth of the fourth thin-film transistor T4 and the voltage difference Vpin of the photodiode (Vth+Vpin).

[0066] Furthermore, when the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, and the fifth thin-film transistor T5 are all N-type thin-film transistors, during the integration phase, the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, and the fifth thin-film transistor T5 remain at a low potential and are turned off; when the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, and the fifth thin-film transistor T5 are all P-type thin-film transistors, during the integration phase, the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, and the fifth thin-film transistor T5 remain at a high potential and are turned off.

[0067] During the reading phase, the second thin-film transistor T2 and the third thin-film transistor T3 are turned on, while the first thin-film transistor T1 and the fifth thin-film transistor T5 are turned off, and the current value Iout at the drain of the third thin-film transistor T3 is read.

[0068] Among them, reference Figure 8 The diagram shows a pixel circuit during the reading phase. During the reading phase, the reading phase ends when the potential of the second terminal N2 of the second capacitor C2 is equal to the threshold voltage Vth.

[0069] Specifically, the second thin-film transistor T2 and the third thin-film transistor T3 are kept at a high potential and turned on. At this time, the fourth thin-film transistor T4 is turned on, and the current starts to be output at Iout. When the voltage of the N2 node becomes the threshold voltage Vth of the fourth thin-film transistor T4, the source follower (the fourth thin-film transistor T4) is turned off, the reading is completed, and the voltage difference Vpin generated by the photodiode exposure integration is completely read.

[0070] During the readout phase, the current value at Iout is primarily read. This current value corresponds to the charge generated after photoconversion by the photodiode. Specifically, the conduction of the fifth thin-film transistor T5 maintains the threshold voltage Vth of the source follower (fourth thin-film transistor T4) at node N2 before exposure integration. During the readout phase, the threshold voltage Vth is actively subtracted (Vt). 输出 =Vpin+Vth-Vth=Vpin), change V 输出 =Vpin is converted into output current Iout for reading, avoiding the impact of the threshold voltage Vth drift of the source follower (fourth thin film transistor T4) on the accuracy of the output current Iout.

[0071] Furthermore, when the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, and the fifth thin-film transistor T5 are all N-type thin-film transistors, during the read phase, the second thin-film transistor T2 and the third thin-film transistor T3 remain at a high potential and are turned on, while the first thin-film transistor T1 and the fifth thin-film transistor T5 remain at a low potential and are turned off. When the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, and the fifth thin-film transistor T5 are all P-type thin-film transistors, during the read phase, the second thin-film transistor T2 and the third thin-film transistor T3 remain at a low potential and are turned on, while the first thin-film transistor T1 and the fifth thin-film transistor T5 remain at a high potential and are turned off.

[0072] The pixel circuit driving method provided in this embodiment of the invention drives five thin-film transistors. After the fifth thin-film transistor is turned on, the cathode of the photodiode maintains the threshold voltage of the source follower (fourth thin-film transistor) before exposure integration. Furthermore, it can actively subtract the threshold voltage during the readout phase to avoid the output current value of the pixel circuit being affected by the threshold voltage of the source follower and its drift.

[0073] This invention also provides a flat panel detector, including the pixel circuit described in any one of the above embodiments.

[0074] The flat panel circuit includes multiple pixel circuits, each corresponding to a pixel. The charge accumulated by the photodiode after illumination is converted into a voltage signal, which is then converted into a current value. After the flat panel detector reads the current value, it displays different grayscale values ​​according to the magnitude of the current value. Multiple pixel circuits correspond to multiple grayscale values. These grayscale values ​​are combined into a grayscale image for display, thus realizing the detection function of the flat panel detector.

[0075] Specifically, the size of the flat panel detector is 17 inches × 17 inches, or 14 inches × 17 inches, etc. The 17 inch × 17 inch flat panel detector consists of 3072 × 3072 pixels, corresponding to 3072 × 3072 pixel circuits. In this embodiment of the invention, the flat panel detector can also be of other sizes, and any number of pixel circuits can be set as needed; this is not limited here.

[0076] The flat panel detector provided in this embodiment of the invention can further improve the anti-interference capability of the flat panel detector, improve the signal-to-noise ratio, ensure image quality, and has high field-effect mobility, low off-state current, and good uniformity. It can also be applied to the manufacturing of large-size flat panel detectors.

[0077] The pixel circuit provided in this embodiment of the invention uses five thin-film transistors. After the fifth thin-film transistor is turned on, the cathode of the photodiode maintains the threshold voltage of the source follower (fourth thin-film transistor) before exposure integration. Furthermore, it can actively subtract the threshold voltage during the readout stage to avoid the pixel circuit being affected by the threshold voltage of the source follower and its drift.

[0078] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0079] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0080] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes: a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, a fourth thin-film transistor, a fifth thin-film transistor, a first capacitor, a second capacitor, and a photodiode; The gate of the first thin-film transistor is connected to the reset voltage line, the source of the first thin-film transistor is connected to the first terminal of the first capacitor, the first terminal of the second capacitor, and the negative terminal of the photodiode, respectively, and the drain of the first thin-film transistor is connected to the reference voltage line. The second terminal of the first capacitor is connected to the positive terminal of the photodiode and the bias voltage line, respectively, and the positive terminal of the photodiode is connected to the bias voltage line. The second terminal of the second capacitor is connected to the gate of the fourth thin-film transistor and the source of the fifth thin-film transistor, respectively. The source of the fourth thin-film transistor is connected to the drain of the fifth thin-film transistor, and the drain of the fourth thin-film transistor is connected to the source of the third thin-film transistor; the drain of the third thin-film transistor is connected to the output signal line. The source of the second thin-film transistor is connected to the power supply, and the drain of the second thin-film transistor is connected to the source of the fourth thin-film transistor. The reset voltage provided by the reset voltage line is used to control the first thin-film transistor to turn on, so that the voltage at the source of the first thin-film transistor is reset to the reference voltage.

2. The pixel circuit according to claim 1, characterized in that, The gate of the second thin-film transistor is connected to the first on-voltage signal line; the first on-voltage signal provided by the first on-voltage signal line controls the second thin-film transistor to be in an on or off state. The gate of the third thin-film transistor is connected to the second on-voltage signal line; the second on-voltage signal provided by the second on-voltage signal line controls the third thin-film transistor to be in an on or off state. The gate of the fifth thin-film transistor is connected to the third on-voltage signal line; the third on-voltage signal provided by the third on-voltage signal line controls the fifth thin-film transistor to be in the on or off state.

3. The pixel circuit according to claim 1, characterized in that, The first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the fourth thin-film transistor, and the fifth thin-film transistor are N-type thin-film transistors or P-type thin-film transistors.

4. A driving method for a pixel circuit, applied to the pixel circuit according to any one of claims 1-3, characterized in that, The method includes: During the reset phase, the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, and the fifth thin-film transistor are turned on. During the compensation phase, the first thin-film transistor, the third thin-film transistor, and the fifth thin-film transistor are turned on, and the second thin-film transistor is turned off. During the integration phase, the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, and the fifth thin-film transistor are turned off, allowing the photodiode to integrate during exposure and charging the first capacitor and the second capacitor. During the reading phase, the second and third thin-film transistors are turned on, and the first and fifth thin-film transistors are turned off, and the current value at the drain of the third thin-film transistor is read.

5. The driving method according to claim 4, characterized in that, During the reset phase, the potential of the source of the first thin-film transistor is the reference voltage provided by the reference voltage line, and the potentials of the drain of the second thin-film transistor and the second terminal of the second capacitor are both the power supply voltage provided by the power supply.

6. The driving method according to claim 5, characterized in that, During the compensation phase, the potential of the source of the first thin-film transistor is the reference voltage provided by the reference voltage line, and the potentials of the drain of the second thin-film transistor and the second terminal of the second capacitor are both the threshold voltage of the fourth thin-film transistor.

7. The driving method according to claim 6, characterized in that, During the integration phase, the potential of the source of the first thin-film transistor is the sum of the reference voltage provided by the reference voltage line and the voltage difference of the photodiode, and the potential of the second terminal of the second capacitor is the sum of the threshold voltage of the fourth thin-film transistor and the voltage difference of the photodiode.

8. The driving method according to claim 7, characterized in that, During the reading phase, the reading phase ends when the potential at the second terminal of the second capacitor reaches the threshold voltage.

9. A flat panel detector, characterized in that, Includes the pixel circuit as described in any one of claims 1-3.

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