Image sensing device

Abstract

An image sensing device includes a pixel array configured to include a plurality of pixel groups arranged continuously in a row direction and a column direction. Each pixel group includes a plurality of unit pixels, and each unit pixel includes a photoelectric conversion element configured to generate photocharges by conversion of incident light. Each pixel group outputs a first pixel signal corresponding to a photocharge generated by a single unit pixel and a second pixel signal corresponding to a sum of photocharges generated by two or more unit pixels.

Description

Technical Field

[0001] Technologies and implementations disclosed in this patent document generally relate to image sensing devices. Background Art

[0002] Image sensing devices are used in electronic devices to convert optical images into electrical signals. With the recent developments in the automotive, medical, computer and communication industries, the demand for highly integrated, higher performance image sensors has increased rapidly in various electronic devices such as digital cameras, camcorders, personal communication systems (PCS), video game consoles, surveillance cameras, medical micro cameras, robots, etc. Summary of the invention

[0003] Various embodiments of the disclosed technology relate to an image sensing device capable of acquiring all pixel signals (eg, single pixel signals and SUM pixel signals) of multiple modes using only one exposure.

[0004] According to an embodiment of the disclosed technology, an image sensing device may include a pixel array configured to include a plurality of pixel groups arranged continuously in row and column directions. Each pixel group may include a plurality of unit pixels, and each unit pixel may include a photoelectric conversion element configured to generate photocharges by conversion of incident light. Each pixel group may output a first pixel signal corresponding to a photocharge generated by a single unit pixel and a second pixel signal corresponding to the sum of photocharges generated by two or more unit pixels.

[0005] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description considered in conjunction with the accompanying drawings.

[0007] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0008] Figure 2 Some implementations based on the disclosed technology are illustrated. Figure 1 A schematic diagram of an example of a layout structure of pixel groups included in a pixel array shown.

[0009] Figure 3 Some implementations based on the disclosed technology are illustrated. Figure 2 A schematic diagram of an example of a planar structure of any pixel group shown.

[0010] Figure 4 is an example of some implementations based on the disclosed technology. Figure 3 A circuit diagram showing an example of a circuit structure corresponding to a pixel group shown.

[0011] Figure 5 Some implementations based on the disclosed technology are illustrated. Figure 1 A schematic diagram of another example of a layout structure of pixel groups included in a pixel array shown.

[0012] Figure 6 Some implementations based on the disclosed technology are illustrated. Figure 5 A schematic diagram of an example of a planar structure of any pixel group shown.

[0013] Figure 7 is an example of some implementations based on the disclosed technology. Figure 6 A circuit diagram showing an example of a circuit structure corresponding to a pixel group shown. DETAILED DESCRIPTION

[0014] This patent document provides implementations and examples of image sensing devices, and the disclosed features can be implemented to achieve one or more advantages in more applications. Some implementations of the disclosed technology propose designs of image sensing devices that can acquire all pixel signals (e.g., single pixel signals and SUM pixel signals) of several modes using only one exposure.

[0015] The present invention will now be described in detail with reference to specific embodiments, examples of which are shown in the accompanying drawings. As much as possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. In the following description, detailed descriptions of related known structures or functions incorporated herein will be omitted to avoid confusing the subject matter.

[0016] Figure 1 is a block diagram illustrating an image sensing device according to an embodiment of the disclosed technology.

[0017] Reference Figure 1 , the image sensing device may include a pixel array 100, a row driver 200, a correlated double sampler (CDS) 300, an analog-to-digital converter (ADC) 400, an output buffer 500, a column driver 600, and a timing controller 700. The present invention is discussed only by way of example. Figure 1 The components of the image sensing device shown, and this patent document encompasses many other variations, substitutions, variations, changes, and modifications.

[0018] The pixel array 100 may include a plurality of pixel groups (PXGs) arranged in rows and columns. In one example, the plurality of pixel groups (PXGs) may be arranged as a two-dimensional (2D) pixel array including rows and columns. In another example, the plurality of pixel groups (PXGs) may be arranged as a three-dimensional (3D) pixel array.

[0019] Each of the pixel groups (PXG) may include a plurality of unit pixels that generate photocharges by converting light signals into electrical signals and a pixel transistor that outputs a pixel signal corresponding to the photocharges generated by the unit pixels. The unit pixels included in the same pixel group (PXG) may receive light of the same color. For example, the unit pixels included in the same pixel group (PXG) may include a color filter disposed above a substrate, each color filter allowing light of the same color to pass through and transmitting the light to a corresponding photoelectric conversion element. The pixel transistor of each pixel group (PXG) may output a pixel signal (i.e., a single pixel signal) corresponding to the photocharge generated by only one unit pixel included in the corresponding pixel group (PXG), or may output a pixel signal (i.e., a 2-SUM pixel signal or a 4-SUM pixel signal) corresponding to the photocharges generated by a plurality of unit pixels included in the corresponding pixel group (PXG). In this case, a 2-SUM pixel signal may refer to a pixel signal corresponding to the sum of the photocharges generated by two unit pixels, and a 4-SUM pixel signal may refer to a pixel signal corresponding to the sum of the photocharges generated by four unit pixels.

[0020] The pixel array 100 may receive a driving signal (e.g., a row selection signal, a pixel reset signal, a transmission (or transfer) signal, and a pass signal) from the row driver 200. Upon receiving the driving signal, the unit pixels and pixel transistors in the pixel array 100 may be activated to perform operations corresponding to the transmission signal, the pass signal, the row selection signal, and the pixel reset signal.

[0021] The row driver 200 can activate the pixel array 100 based on a control signal provided by a controller circuit such as a timing controller 700 to perform a specific operation on the unit pixel in the corresponding row. In some implementations, the row driver 200 can select one or more pixel groups arranged in one or more rows of the pixel array 100. The row driver 200 can generate a row selection signal to select one or more rows from a plurality of rows. The row driver 200 can sequentially enable a pixel reset signal, a transmission signal, and a pass signal for the pixel group arranged in the selected row. The pixel signals (i.e., a single pixel signal, a 2-SUM pixel signal, and a 4-SUM pixel signal) generated by the pixel group arranged in the selected row can be output to a correlated double sampler (CDS) 300.

[0022] The correlated double sampler (CDS) 300 can remove the undesired offset value of the unit pixel using correlated double sampling. In one example, the correlated double sampler (CDS) 300 can remove the undesired offset value of the unit pixel by comparing the output voltage of the pixel signal obtained before and after the photocharge generated by the incident light is accumulated in the sensing node (i.e., the floating diffusion node). As a result, the CDS 300 can obtain the pixel signal generated only by the incident light without causing noise. In some implementations, once the clock signal is received from the timing controller 700, the CDS 300 can sequentially sample and hold the voltage level of the reference signal and the pixel signal provided to each of the plurality of column lines from the pixel array 100. That is, the CDS 300 can sample and hold the voltage level of the reference signal and the pixel signal corresponding to each column of the pixel array 100. In some implementations, the CDS 300 can transmit the reference signal and the pixel signal of each column as a correlated double sampling (CDS) signal to the ADC 400 based on the control signal from the timing controller 700.

[0023] The ADC 400 is used to convert the analog CDS signal received from the CDS 300 into a digital signal. In some implementations, the ADC 400 may be implemented as a ramp comparison type ADC. The analog-to-digital converter (ADC) 400 may compare the ramp signal received from the timing controller 700 with the CDS signal received from the CDS 300, and thus may output a comparison signal indicating a comparison result between the ramp signal and the CDS signal. The analog-to-digital converter (ADC) 400 may count the level transition time of the comparison signal in response to the ramp signal received from the timing controller 700, and may output a count value indicating the counted level transition time to the output buffer 500.

[0024] The output buffer 500 may temporarily store the column-based image data provided from the ADC 400 based on the control signal of the timing controller 170. The image data received from the ADC 400 may be temporarily stored in the output buffer 500 based on the control signal of the timing controller 700. The output buffer 500 may provide an interface to compensate for a data rate difference or a transmission rate difference between the image sensing device and other devices.

[0025] The column driver 600 may select a column of the output buffer 500 upon receiving a control signal from the timing controller 700, and sequentially output the image data temporarily stored in the selected column of the output buffer 500. In some implementations, upon receiving an address signal from the timing controller 700, the column driver 600 may generate a column selection signal based on the address signal, may select a column of the output buffer 500 using the column selection signal, and may control the image data received from the selected column of the output buffer 500 to be output as an output signal.

[0026] The timing controller 700 may generate signals for controlling the operation of the row driver 200, the ADC 400, the output buffer 500, and the column driver 600. The timing controller 700 may provide the row driver 200, the column driver 600, the ADC 400, and the output buffer 500 with clock signals required for the operation of the various components of the image sensing device, control signals for timing control, and address signals for selecting rows or columns. In some implementations, the timing controller 700 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0027] Figure 2 Some implementations based on the disclosed technology are illustrated. Figure 1 FIG. 1 is a schematic diagram of an example of a layout structure of pixel groups included in the pixel array 100 shown.

[0028] Reference Figure 2 , the pixel array 100 may include a plurality of pixel groups PXG_R, PXG_G, and PXG_B arranged continuously in the row direction and the column direction. Each of the pixel groups PXG_R, PXG_G, and PXG_B may include a plurality of unit pixels PX1 to PX16 configured to receive light of the same color. For example, the pixel group PXG_R may include a plurality of unit pixels that receive red visible light and generate photocharges corresponding to the red visible light, the pixel group PXG_G may include a plurality of unit pixels that receive green visible light and generate photocharges corresponding to the green visible light, and the pixel group PXG_B may include a plurality of unit pixels that receive blue visible light and generate photocharges corresponding to the blue visible light. Each of the pixel groups PXG_R, PXG_G, and PXG_B may include 16 unit pixels PX1 to PX16 arranged adjacent to each other in a (4×4) matrix array. The pixel groups PXG_R, PXG_G, and PXG_B may be continuously arranged in a Bayer pattern in the pixel array 100 .

[0029] Each of the pixel groups PXG_R, PXG_G, and PXG_B can output different types of pixel signals depending on how many unit pixels are used to generate the photocharge corresponding to each pixel signal. The different types of pixel signals include a first pixel signal corresponding to the photocharge generated by a single unit pixel and a second pixel signal corresponding to the photocharge generated by a plurality of unit pixels (e.g., the sum of the photocharges generated by the unit pixels). For example, the pixel group PXG_G can output a single pixel signal corresponding to the photocharge generated by each of the unit pixels PX1, PX2, PX3, and PX4, a 2-SUM pixel signal corresponding to the photocharge generated by two unit pixels PX5-PX6 or PX7-PX8, and can output a 4-SUM pixel signal corresponding to the photocharge generated by four unit pixels PX9-PX12 or PX13-PX16.

[0030] In About Figure 2 In the description, each unit pixel for outputting a single pixel signal will be referred to as a single pixel 112a, 112b, 112c or 112d, a group of two unit pixels for outputting a 2-SUM pixel signal will be referred to as a 2-SUM pixel block 114a or 114b, and a group of four unit pixels for outputting a 4-SUM pixel signal will be referred to as a 4-SUM pixel block 116a or 116b.

[0031] Figure 3 Some implementations based on the disclosed technology are illustrated. Figure 2 A schematic diagram of an example of a planar structure of a pixel group is shown. Figure 4 is an example of some implementations based on the disclosed technology. Figure 3 The circuit diagram of an example of a circuit structure corresponding to a pixel group shown in FIG. Figure 3 and Figure 4 The structure of the pixel group PXG-G is shown, but the structure can be applied to Figure 2 Any pixel group PXG_R or PXG_B shown.

[0032] Reference Figure 3 and Figure 4 , the pixel group PXG_G may include a plurality of unit pixels PX1 to PX16 arranged continuously in the row direction and the column direction. For example, the pixel group PXG_G may include 16 unit pixels PX1 to PX16 arranged adjacent to each other in a (4×4) matrix array. Although the above implementation only exemplarily discloses the pixel group PXG_G corresponding to green, the pixel groups PXG_R, PXG_G, and PXG_B may also be formed to have the same structure.

[0033] In some implementations, the pixel group PXG_G may include unit pixels PX1 to PX16 , floating diffusion regions FD1 to FD5 , pass transistors TR1 to TR5 , and pixel transistors DX, SX, and RX.

[0034] The unit pixels PX1 to PX16 may include photoelectric conversion elements PD1 to PD16 for generating photocharges in response to incident light, respectively, and may include transfer transistors TX1 to TX16 for transferring the photocharges generated by the corresponding photoelectric conversion elements PD1 to PD16 to the floating diffusion areas FD1 to FD5, respectively, in response to transfer signals TS1 to TS16. In more detail, the unit pixel PX1 may include a photoelectric conversion element PD1 and a transfer transistor TX1, the unit pixel PX2 may include a photoelectric conversion element PD2 and a transfer transistor TX2, the unit pixel PX3 may include a photoelectric conversion element PD3 and a transfer transistor TX3, and the unit pixel PX4 may include a photoelectric conversion element PD4 and a transfer transistor TX4. The unit pixel PX5 may include a photoelectric conversion element PD5 and a transfer transistor TX5, the unit pixel PX6 may include a photoelectric conversion element PD6 and a transfer transistor TX6, the unit pixel PX7 may include a photoelectric conversion element PD7 and a transfer transistor TX7, and the unit pixel PX8 may include a photoelectric conversion element PD8 and a transfer transistor TX8. The unit pixel PX9 may include a photoelectric conversion element PD9 and a transfer transistor TX9, the unit pixel PX10 may include a photoelectric conversion element PD10 and a transfer transistor TX10, the unit pixel PX11 may include a photoelectric conversion element PD11 and a transfer transistor TX11, and the unit pixel PX12 may include a photoelectric conversion element PD12 and a transfer transistor TX12. The unit pixel PX13 may include a photoelectric conversion element PD13 and a transfer transistor TX13, the unit pixel PX14 may include a photoelectric conversion element PD14 and a transfer transistor TX14, the unit pixel PX15 may include a photoelectric conversion element PD15 and a transfer transistor TX15, and the unit pixel PX16 may include a photoelectric conversion element PD16 and a transfer transistor TX16. The unit pixels PX1 to PX16 may be classified into a group of single pixels 112a to 112d, 2-SUM pixel blocks 114a and 114b, and 4-SUM pixel blocks 116a and 116b.

[0035] In some implementations, each of the photoelectric conversion elements PD1 to PD16 may generate an electrical signal in response to received light and include, for example, a photodiode, a phototransistor, a photogate, or other photosensitive circuits capable of converting light into a pixel signal (e.g., charge, voltage, or current). When the photoelectric conversion element is implemented as including a photodiode, the photoelectric conversion elements PD1 to PD16 may be formed in a substrate. Each of the photoelectric conversion elements PD1 to PD16 may include a stacked structure in which impurity regions (i.e., P-type impurity regions and N-type impurity regions) having complementary conductivity are vertically stacked.

[0036] The transfer transistors TX1 to TX16 may be respectively coupled to the photoelectric conversion elements PD1 to PD16 and may be coupled to the corresponding floating diffusion areas FD1 to FD5. As a result, the transfer transistors TX1 to TX16 may transfer the photocharges generated by the corresponding photoelectric conversion elements PD1 to PD16 to the corresponding floating diffusion areas FD1 to FD5 in response to the transfer signals TS1 to TS16.

[0037] For example, the transfer transistors TX1, TX2, TX3, and TX4 belonging to the individual pixels 112a, 112b, 112d, and 112d, respectively, may transfer the photocharges generated by the corresponding photoelectric conversion elements PD1, PD2, PD3, and PD4 to the floating diffusion area FD1 in response to the transfer signals TS1, TS2, TS3, and TS4. The transfer transistors TX5 and TX6 included in the 2-SUM pixel block 114a may transfer the photocharges generated by the corresponding photoelectric conversion elements PD5 and PD6 to the floating diffusion area FD2 in response to the transfer signals TS5 and TS6. In more detail, the transfer transistor TX5 of the 2-SUM pixel block 114a may transfer the photocharges generated by the photoelectric conversion element PD5 to the floating diffusion area FD2 in response to the transfer signal TS5, and another transfer transistor TX6 of the 2-SUM pixel block 114a may transfer the photocharges generated by the photoelectric conversion element PD6 to the floating diffusion area FD2 in response to the transfer signal TS6. The transfer transistors TX7 and TX8 included in the 2-SUM pixel block 114b may transfer the photocharges generated by the corresponding photoelectric conversion elements PD7 and PD8 to the floating diffusion area FD3 in response to the transfer signals TS7 and TS8. In more detail, the transfer transistor TX7 of the 2-SUM pixel block 114b may transfer the photocharges generated by the photoelectric conversion element PD7 to the floating diffusion area FD3 in response to the transfer signal TS7, and another transfer transistor TX8 of the 2-SUM pixel block 114b may transfer the photocharges generated by the photoelectric conversion element PD8 to the floating diffusion area FD3 in response to the transfer signal TS8. The transfer transistors TX9 to TX12 included in the 4-SUM pixel block 116a may transfer the photocharges generated by the corresponding photoelectric conversion elements PD9 to PD12 to the floating diffusion area FD4 in response to the transfer signals TS9 to TS12. The transfer transistors TX13 to TX16 included in the 4-SUM pixel block 116 b may transfer photo charges generated by the corresponding photoelectric conversion elements PD13 to PD16 to the floating diffusion area FD5 in response to transfer signals TS13 to TS16 .

[0038] Each of the floating diffusion regions FD1 to FD5 may include an impurity region formed by injecting impurities (e.g., N-type impurities) into an upper portion of a substrate, and may store photocharges carried by transfer transistors TX1 to TX16. In more detail, the floating diffusion region FD1 may store photocharges received from transfer transistors TX1 to TX4, the floating diffusion region FD2 may store photocharges received from transfer transistors TX5 and TX6, the floating diffusion region FD3 may store photocharges received from transfer transistors TX7 and TX8, the floating diffusion region FD4 may store photocharges received from transfer transistors TX9 to TX12, and the floating diffusion region FD5 may store photocharges received from transfer transistors TX13 to TX16.

[0039] The floating diffusion area FD1 may be shared by the individual pixels 112a to 112d and may store photocharges received from any one of the transfer transistors TX1 to TX4. The transfer transistors TX1, TX2, TX3, and TX4 may be turned on in sequence in response to the transfer signals TS1, TS2, TS3, and TS4. The floating diffusion area FD1 may have a size (capacity) capable of storing photocharges generated by any one of the unit pixels.

[0040] The floating diffusion area FD2 may be shared by the unit pixels PX5 and PX6 included in the 2-SUM pixel block 114a, and may store the sum of the photocharges received from the transfer transistors TX5 and TX6. The transfer transistors TX5 and TX6 may be turned on sequentially in response to the transfer signals TS5 and TS6, or may be turned on simultaneously in response to the transfer signals TS5 and TS6.

[0041] The floating diffusion area FD3 may be shared by the unit pixels PX7 and PX8 included in the 2-SUM pixel block 114b and may store the sum of the photocharges received from the transfer transistors TX7 and TX8. The transfer transistors TX7 and TX8 may be turned on sequentially in response to the transfer signals TS7 and TS8, or may be turned on simultaneously in response to the transfer signals TS7 and TS8.

[0042] Each of the floating diffusion areas FD2 of the 2-SUM pixel block 114a and the floating diffusion areas FD3 of the 2-SUM pixel block 114b may be two or more times larger in photocharge storage capacity than the floating diffusion area FD1 shared by the single pixels 112a to 112d. In more detail, each of the floating diffusion areas FD2 and FD3 may have a size (capacity) capable of storing all photocharges generated by at least two unit pixels.

[0043] The floating diffusion area FD4 may be shared by the unit pixels PX9 to PX12 included in the 4-SUM pixel block 116a, and may store the sum of the photocharges received from the transfer transistors TX9 to TX12. The transfer transistors TX9 to TX12 may be turned on sequentially in response to the transfer signals TS9 to TS12, or may be turned on simultaneously in response to the transfer signals TS9 to TS12.

[0044] The floating diffusion area FD5 may be shared by the unit pixels PX13 to PX16 included in the 4-SUM pixel block 116b and may store the sum of the photocharges received from the transfer transistors TX13 to TX16. The transfer transistors TX13 to TX16 may be turned on sequentially in response to the transfer signals TS13 to TS16, or may be turned on simultaneously in response to the transfer signals TS13 to TS16.

[0045] Each of the floating diffusion areas FD4 of the 4-SUM pixel block 116a and the floating diffusion areas FD5 of the 4-SUM pixel block 116b may be two or more times larger in photocharge storage capacity than the floating diffusion areas FD2 or FD3 of the 2-SUM pixel block 114a or 114b. In more detail, each of the floating diffusion areas FD4 and FD5 may have a size (capacity) capable of storing all photocharges generated by at least four unit pixels.

[0046] The floating diffusion region FD1, FD2, FD3, FD4 or FD5 may be connected to one terminal (e.g., source or drain) of the corresponding pass transistor TR1, TR2, TR3, TR4 or TR5 through a conductive line (e.g., a metal line). Another terminal (e.g., drain or source) of the pass transistors TR1 to TR5 may be connected to a common node CL1. The common node CL1 may be connected to the gate of the source follower transistor DX and one terminal (e.g., source or drain) of the reset transistor RX.

[0047] The pass transistors TR1 to TR5 may be turned on or off in response to pass signals TRS1 to TRS5 , respectively.

[0048] For example, in order to connect the floating diffusion area FD1 shared by the individual pixels 112a to 112d to the gate of the source follower transistor DX, the pass signal TRS1 can be enabled (or activated) to a high level so that the pass transistor TR1 can be turned on. Therefore, the pass transistor TR1 can be turned on to output a single pixel signal corresponding to each of the individual pixels 112a to 112d. When the pass transistor TR1 is turned on, the other pass transistors TR2 to TR5 can be turned off.

[0049] In order to connect the floating diffusion area FD2 of the 2-SUM pixel block 114a to the gate of the source follower transistor DX, the pass signal TRS2 can be enabled (or activated) to a high level so that the pass transistor TR2 can be turned on. Therefore, the pass transistor TR2 can be turned on to output a 2-SUM pixel signal corresponding to the sum of the photocharges of the two unit pixels PX5 and PX6 included in the 2-SUM pixel block 114a. When the pass transistor TR2 is turned on, the other pass transistors TR1, TR3, TR4 and TR5 can be turned off.

[0050] In order to connect the floating diffusion area FD3 of the 2-SUM pixel block 114b to the gate of the source follower transistor DX, the pass signal TRS3 can be enabled (or activated) to a high level so that the pass transistor TR3 can be turned on. Therefore, the pass transistor TR3 can be turned on to output a 2-SUM pixel signal corresponding to the sum of the photocharges of the two unit pixels PX7 and PX8 included in the 2-SUM pixel block 114b. When the pass transistor TR3 is turned on, the other pass transistors TR1-TR2 and TR4-TR5 can be turned off.

[0051] In order to connect the floating diffusion area FD4 of the 4-SUM pixel block 116a to the gate of the source follower transistor DX, the pass signal TRS4 can be enabled (or activated) to a high level so that the pass transistor TR4 can be turned on. Therefore, the pass transistor TR4 can be turned on to output a 4-SUM pixel signal corresponding to the sum of the photocharges of the four unit pixels PX9 to PX12 included in the 4-SUM pixel block 116a. When the pass transistor TR4 is turned on, the other pass transistors TR1 to TR3 and TR5 can be turned off.

[0052] In order to connect the floating diffusion area FD5 of the 4-SUM pixel block 116b to the gate of the source follower transistor DX, the pass signal TRS5 can be enabled (or activated) to a high level so that the pass transistor TR5 can be turned on. Therefore, the pass transistor TR5 can be turned on to output a 4-SUM pixel signal corresponding to the sum of the photocharges of the four unit pixels PX13 to PX16 included in the 4-SUM pixel block 116b. When the pass transistor TR5 is turned on, the other pass transistors TR1 to TR4 can be turned off.

[0053] One terminal (e.g., source or drain) of source follower transistor DX may be coupled to a pixel voltage (VDD) node, and another terminal (e.g., drain or source) of source follower transistor DX may be coupled to one terminal (e.g., source or drain) of select transistor SX. Another terminal (e.g., drain or source) of select transistor SX may be coupled to an output node (OUT). Thus, source follower transistor DX and select transistor SX may be coupled in series between a pixel voltage (VDD) node and an output node (OUT).

[0054] The source follower transistor DX may generate a pixel signal (e.g., a single pixel signal, a 2-SUM pixel signal, or a 4-SUM pixel signal) corresponding to the size (amount) of the photocharges transmitted to the common node (CL1) by the transistors TR1 to TR5, and may output the generated pixel signal to the selection transistor SX. The selection transistor SX may transmit the pixel signal received from the source follower transistor DX to the output node (OUT) in response to the selection signal SS.

[0055] One terminal (e.g., source or drain) of the reset transistor RX may be coupled to the common node (CL1), and the other terminal (e.g., drain or source) of the reset transistor RX may be coupled to the pixel voltage (VDD) node. The reset transistor RX may initialize the common node CL1 to the pixel voltage (VDD) in response to a reset signal RS.

[0056] The active areas in which the pass transistors TR1 to TR5 and the pixel transistors DX, SX, and RX are formed, the active areas in which the transfer transistors TX1 to TX16 are formed, and the active areas in which the floating diffusion areas FD1 to FD5 are formed may be isolated by a device isolation structure. In this case, the device isolation structure may include a trench-shaped device isolation structure formed by etching a substrate or a junction isolation structure formed by injecting impurities (e.g., P-type impurities) into a substrate.

[0057] Transmission signals TS1 to TS16 , pass signals TRS1 to TRS5 , a selection signal SS, and a reset signal RS may be provided from the row driver 200 .

[0058] Figure 5 Some implementations based on the disclosed technology are illustrated. Figure 1 A schematic diagram of another example of a layout structure of pixel groups included in a pixel array shown.

[0059] Reference Figure 5, the pixel array 100 may include a plurality of pixel groups PXG_R, PXG_G, and PXG_B arranged continuously in the row direction and the column direction. Each of the pixel groups PXG_R, PXG_G, and PXG_B may include a plurality of unit pixels PX1 to PX16 configured to receive light of the same color. For example, the pixel group PXG_R may include a plurality of unit pixels that receive red visible light and generate photocharges corresponding to the red visible light, the pixel group PXG_G may include a plurality of unit pixels that receive green visible light and generate photocharges corresponding to the green visible light, and the pixel group PXG_B may include a plurality of unit pixels that receive blue visible light and generate photocharges corresponding to the blue visible light. Each of the pixel groups PXG_R, PXG_G, and PXG_B may include 16 unit pixels PX1 to PX16 arranged adjacent to each other in a (4×4) matrix array.

[0060] and Figure 2 The implementation shown in which the pixel group includes a single pixel outputting a single pixel signal, a 2-SUM pixel block outputting a 2-SUM pixel signal, and a 4-SUM pixel block outputting a 4-SUM pixel signal is different. Figure 5 A plurality of unit pixels included in each pixel group PXG_R, PXG_G, or PXG_B may be arranged such that four unit pixels form a sub-pixel group and each pixel group PXG_R, PXG_G, or PXG_B includes four sub-pixel groups.

[0061] Each pixel group PXG_R, PXG_G, or PXG_B may output different types of pixel signals including a first pixel signal corresponding to a photocharge generated by only one unit pixel (i.e., a single unit pixel) and a second pixel signal corresponding to a photocharge generated by a plurality of pixel signals. Figure 5 In the example of , the second pixel signal may be any one of a 2-SUM pixel signal corresponding to photo charges generated by two unit pixels to a 7-SUM pixel signal corresponding to photo charges generated by seven unit pixels.

[0062] Figure 6 Some implementations based on the disclosed technology are illustrated. Figure 5 A schematic diagram of an example of a planar structure of a pixel group is shown. Figure 7 is an example of some implementations based on the disclosed technology. Figure 6 The circuit diagram of an example of a circuit structure corresponding to a pixel group shown in FIG. Figure 6 and Figure 7 The structure of the pixel group PXG_G is shown, but the structure can be applied to Figure 5 Any pixel group PXG_R or PXG_B shown.

[0063] Reference Figure 6 and Figure 7 , the pixel group PXG_G may include a plurality of unit pixels PX1 to PX16 arranged continuously in the row direction and the column direction. For example, the pixel group PXG_G may include 16 unit pixels PX1 to PX16 arranged adjacent to each other in a (4×4) matrix array. Although the above implementation only exemplarily discloses the pixel group PXG_G corresponding to green, the pixel groups PXG_R, PXG_G, and PXG_B may also be formed to have the same structure.

[0064] In some implementations, the pixel group PXG_G may include unit pixels PX1 to PX16 , common connectors CC1 to CC4 , photo-charge storage circuits 122 , 124 , and 126 , and pixel transistors DX, SX, and RX.

[0065] The unit pixels PX1 to PX16 may include photoelectric conversion elements PD1 to PD16 for generating photocharges in response to incident light, respectively, and may include transfer transistors TX1 to TX16 for transferring the photocharges generated by the corresponding photoelectric conversion elements PD1 to PD16 to the common connectors CC1 to CC4 in response to transfer signals TS1 to TS16. In more detail, the unit pixel PX1 may include a photoelectric conversion element PD1 and a transfer transistor TX1, the unit pixel PX2 may include a photoelectric conversion element PD2 and a transfer transistor TX2, the unit pixel PX3 may include a photoelectric conversion element PD3 and a transfer transistor TX3, and the unit pixel PX4 may include a photoelectric conversion element PD4 and a transfer transistor TX4. The unit pixel PX5 may include a photoelectric conversion element PD5 and a transfer transistor TX5, the unit pixel PX6 may include a photoelectric conversion element PD6 and a transfer transistor TX6, the unit pixel PX7 may include a photoelectric conversion element PD7 and a transfer transistor TX7, and the unit pixel PX8 may include a photoelectric conversion element PD8 and a transfer transistor TX8. The unit pixel PX9 may include a photoelectric conversion element PD9 and a transfer transistor TX9, the unit pixel PX10 may include a photoelectric conversion element PD10 and a transfer transistor TX10, the unit pixel PX11 may include a photoelectric conversion element PD11 and a transfer transistor TX11, and the unit pixel PX12 may include a photoelectric conversion element PD12 and a transfer transistor TX12. The unit pixel PX13 may include a photoelectric conversion element PD13 and a transfer transistor TX13, the unit pixel PX14 may include a photoelectric conversion element PD14 and a transfer transistor TX14, the unit pixel PX15 may include a photoelectric conversion element PD15 and a transfer transistor TX15, and the unit pixel PX16 may include a photoelectric conversion element PD16 and a transfer transistor TX16.

[0066] Each of the photoelectric conversion elements PD1 to PD16 may include a photodiode. For example, the photoelectric conversion elements PD1 to PD16 may be formed in a substrate. Each of the photoelectric conversion elements PD1 to PD16 may include a stacked structure in which impurity regions (i.e., P-type impurity regions and N-type impurity regions) having complementary conductivity are vertically stacked.

[0067] The transmission transistors TX1 to TX16 may be respectively coupled to the photoelectric conversion elements PD1 to PD16 and may be coupled to the corresponding common connectors CC1 to CC4. As a result, the transmission transistors TX1 to TX16 may transmit the photocharges generated by the corresponding photoelectric conversion elements PD1 to PD16 to the corresponding common connectors CC1 to CC4 in response to the transmission signals TS1 to TS16.

[0068] For example, the transmission transistors TX1 to TX4 can transmit the photocharges generated by the corresponding photoelectric conversion elements PD1 to PD4 to the common connector CC1 in response to the transmission signals TS1 to TS4. The transmission transistors TX5 to TX8 can transmit the photocharges generated by the corresponding photoelectric conversion elements PD5 to PD8 to the common connector CC2 in response to the transmission signals TS5 to TS8. The transmission transistors TX9 to TX12 can transmit the photocharges generated by the corresponding photoelectric conversion elements PD9 to PD12 to the common connector CC3 in response to the transmission signals TS9 to TS12. The transmission transistors TX13 to TX16 can transmit the photocharges generated by the corresponding photoelectric conversion elements PD13 to PD16 to the common connector CC4 in response to the transmission signals TS13 to TS16.

[0069] Common connectors CC1 to CC4 may be commonly connected to a plurality of unit pixels (e.g., four unit pixels). For example, common connector CC1 may be commonly connected to four unit pixels PX1 to PX4, and common connector CC2 may be commonly connected to four unit pixels PX5 to PX8. In addition, common connector CC3 may be commonly connected to four unit pixels PX9 to PX12, and common connector CC4 may be commonly connected to four unit pixels PX13 to PX16. Common connectors CC1 to CC4 may be connected to one terminal (e.g., source or drain) of each of photocharge storage circuits 122, 124, and 126 via wires. Therefore, the photocharges transmitted to common connectors CC1 to CC4 may be directly transmitted to photocharge storage circuits 122, 124, and 126 via wires.

[0070] Each of the common connectors CC1 to CC4 may include an impurity region formed by implanting impurities (eg, N-type impurities) into an upper portion of the substrate. Figure 3Compared with the floating diffusion regions FD1, FD4 and FD5 shown, the common connectors CC1 to CC4 may be located at the same Figure 3 The floating diffusion regions FD1, FD4 and FD5 are located at the same positions as shown, but are configured to perform the same Figure 3 The floating diffusion regions FD1, FD4, and FD5 shown in FIG. 1 are operated differently. The common connectors CC1 to CC4 may be used as interconnection regions through which the unit pixels PX1 to PX16 are connected to the photocharge storage circuits 122, 124, and 126 by wires. Therefore, each of the common connectors CC1 to CC4 may be formed to have a predetermined size capable of being electrically connected to the wires, and may be smaller in size than each of the floating diffusion regions FD1, FD4, and FD5.

[0071] The photocharge storage circuits 122, 124, and 126 can store the photocharges generated by the unit pixels PX1 to PX16 in the floating diffusion areas FD1 to FD3 in response to the pass signals TRS11 to TRS32, and can output the photocharges stored in the floating diffusion areas FD1 to FD3 to the common node CL2. In this case, the floating diffusion areas FD1 to FD3 can be different in size (i.e., photocharge storage capacity) from each other.

[0072] For example, the photocharge storage circuit 122 may include pass transistors TR11 and TR12 connected in series with each other in the active region ACT1 and a floating diffusion region FD1 located between the gates of the pass transistors TR11 and TR12 in the active region ACT1. Therefore, the floating diffusion region FD1 may include an impurity region (e.g., a source or a drain) commonly connected to the pass transistors TR11 and TR12. In this case, the floating diffusion region FD1 may be formed to have a size (capacity) capable of storing photocharges generated by a single unit pixel.

[0073] Since the pass transistor TR11 is turned on and the pass transistor TR12 is turned off, the photocharge storage circuit 122 can store photocharges in the floating diffusion area FD1. In addition, since the pass transistor TR11 is turned off and the pass transistor TR12 is turned on, the photocharge storage circuit 122 can output the photocharges stored in the floating diffusion area FD1 to the common node CL2. The pass transistor TR11 can be turned on or off in response to the pass signal TRS11, and the pass transistor TR12 can be turned on or off in response to the pass signal TRS12.

[0074] The photocharge storage circuit 124 may include pass transistors TR21 and TR22 connected in series with each other in the active region ACT2 and a floating diffusion region FD2 located between the gates of the pass transistors TR21 and TR22 in the active region ACT2. Therefore, the floating diffusion region FD2 may include an impurity region (e.g., a source or a drain) commonly connected to the pass transistors TR21 and TR22. In this case, the floating diffusion region FD2 may be two or more times larger than the floating diffusion region FD1 of the photocharge storage circuit 122 in terms of photocharge storage capacity. Therefore, the floating diffusion region FD2 may be formed to have a size (capacity) capable of storing all photocharges generated by at least two unit pixels.

[0075] Since the pass transistor TR21 is turned on and the pass transistor TR22 is turned off, the photocharge storage circuit 124 can store photocharges in the floating diffusion area FD2. In this case, the photocharge storage circuit 124 can be designed in the following manner: the pass transistor TR21 remains turned on and the pass transistor TR22 remains turned off until the photocharges generated by the two unit pixels are continuously stored in the photocharge storage circuit 124. In addition, since the pass transistor TR21 is turned off and the pass transistor TR22 is turned on, the photocharge storage circuit 124 can output the photocharges stored in the floating diffusion area FD2 to the common node CL2. The pass transistor TR21 can be turned on or off in response to the pass signal TRS21, and the pass transistor TR22 can be turned on or off in response to the pass signal TRS22.

[0076] The photocharge storage circuit 126 may include pass transistors TR31 and TR32 connected in series with each other in the active region ACT3 and a floating diffusion region FD3 located between the gates of the pass transistors TR31 and TR32 in the active region ACT3. That is, the floating diffusion region FD3 may include an impurity region (e.g., a source or a drain) commonly connected to the pass transistors TR31 and TR32. In this case, the floating diffusion region FD3 may be two or more times larger in photocharge storage capacity than the floating diffusion region FD2 of the photocharge storage circuit 124. Therefore, the floating diffusion region FD3 may be formed to have a size (capacity) capable of storing all photocharges generated by at least four unit pixels.

[0077] Since the pass transistor TR31 is turned on and the pass transistor TR32 is turned off, the photocharge storage circuit 126 can store photocharges in the floating diffusion area FD3. In this case, the photocharge storage circuit 126 can be designed in the following manner: the pass transistor TR31 remains turned on and the pass transistor TR32 remains turned off until the photocharges generated by the four unit pixels are continuously stored in the photocharge storage circuit 126. For example, since the pass transistor TR31 is turned off and the pass transistor TR32 is turned on, the photocharge storage circuit 126 can output the photocharges stored in the floating diffusion area FD3 to the common node CL2. The pass transistor TR31 can be turned on or off in response to the pass signal TRS31, and the pass transistor TR32 can be turned on or off in response to the pass signal TRS32.

[0078] When any one of the photocharge storage circuits 122, 124, and 126 stores photocharges in the corresponding floating diffusion area FD1, FD2, or FD3, the remaining photocharge storage circuits may not operate. When the photocharge storage circuits 122, 124, and 126 output the photocharges stored in the corresponding floating diffusion areas FD1, FD2, and FD3 to the common node CL2, at least one of the photocharge storage circuits 122, 124, and 126 may operate in response to the pass signals TRS12, TRS22, and TRS32. In this case, information about which of the photocharge storage circuits will operate can be determined based on how many unit pixels will be used to output pixel signals corresponding to the sum of these photocharges.

[0079] The pixel group PXG_G may output a single pixel signal corresponding to a photocharge generated by a single unit pixel, a 2-SUM pixel signal corresponding to the sum of photocharges generated by two unit pixels, a 3-SUM pixel signal corresponding to the sum of photocharges generated by three unit pixels, a 4-SUM pixel signal corresponding to the sum of photocharges generated by four unit pixels, a 5-SUM pixel signal corresponding to the sum of photocharges generated by five unit pixels, a 6-SUM pixel signal corresponding to the sum of photocharges generated by six unit pixels, and a 7-SUM pixel signal corresponding to the sum of photocharges generated by seven unit pixels. Thus, the pixel group PXG_G may output a single pixel signal or a 2-SUM pixel signal to a 7-SUM pixel signal by combining the photocharges received from the photocharge storage circuits 122, 124, and 126.

[0080] For example, a single pixel signal may be generated using the photocharge received from photocharge storage circuit 122. A 2-SUM pixel signal may be generated using the photocharge received from photocharge storage circuit 124. A 3-SUM pixel signal may be generated by the sum of the photocharges received from photocharge storage circuits 122 and 124. A 4-SUM pixel signal may be generated using the photocharge received from photocharge storage circuit 126. A 5-SUM pixel signal may be generated by the sum of the photocharges received from photocharge storage circuits 122 and 126. A 6-SUM pixel signal may be generated by the sum of the photocharges received from photocharge storage circuits 124 and 126. A 7-SUM pixel signal may be generated by the sum of the photocharges received from photocharge storage circuits 122, 124, and 126.

[0081] Figure 6 and Figure 7 The source follower transistor DX, the select transistor SX and the reset transistor RX shown may be similar in structure and function to the Figure 3 and Figure 4 The structures and functions of the implementations shown in are basically similar, and the same description will be omitted. Figure 6 and Figure 7 In the implementation, since the gate of the source follower transistor DX is connected to the photocharge storage circuits 122, 124 and 126, a pixel signal corresponding to the size (amount) of the photocharge received from the photocharge storage circuits 122, 124 and 126 (i.e., a single pixel signal, a 2-SUM pixel signal or a 4-SUM pixel signal) can be generated, so that the resulting pixel signal can be output to the selection transistor SX.

[0082] Transmission signals TS1 to TS16 , pass signals TRS11 to TRS32 , a selection signal SS, and a reset signal RS may be provided from the row driver 200 .

[0083] As apparent from the above description, an image sensing device based on some implementations of the disclosed technology is able to acquire all pixel signals of several modes (eg, single pixel signals and SUM pixel signals) using only one exposure.

[0084] Although a number of exemplary embodiments have been described, modifications to the disclosed embodiments and other embodiments may be designed based on what is described and / or illustrated in this patent document.

[0085] CROSS-REFERENCE TO RELATED APPLICATIONS

[0086] This patent document claims priority to and the benefits of Korean Patent Application No. 10-2021-0021623, filed on February 18, 2021, the disclosure of which is incorporated herein by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: A pixel array including a plurality of pixel groups arranged continuously in a row direction and a column direction, Each of the plurality of pixel groups includes a plurality of unit pixels, each unit pixel includes a photoelectric conversion element, and the photoelectric conversion element generates photocharges by converting incident light. Each of the plurality of pixel groups outputs a first pixel signal corresponding to a photocharge generated by a single unit pixel and a second pixel signal corresponding to a sum of photocharges generated by two or more unit pixels, The sum of the photocharges generated by the single unit pixel and the photocharges generated by the two or more unit pixels are respectively transferred to the common node through different pass transistors connected between the plurality of unit pixels and the common node, and Wherein, each of the plurality of pixel groups further comprises: A source follower transistor has a gate terminal coupled to the common node and outputs the first pixel signal or the second pixel signal corresponding to the size of the photocharge transferred to the common node.

2. The image sensing device according to claim 1, wherein: Each of the plurality of pixel groups comprises: a plurality of first unit pixels, the plurality of first unit pixels outputting the first pixel signal and sharing a first floating diffusion area; a plurality of second unit pixels, the plurality of second unit pixels outputting the second pixel signal and sharing a second floating diffusion area; a first pass transistor coupled to the first floating diffusion region and transmitting photo charges stored in the first floating diffusion region to the common node based on a first pass signal; and A second pass transistor is coupled to the second floating diffusion region and transmits the photo charges stored in the second floating diffusion region to the common node based on a second pass signal.

3. The image sensing device according to claim 2, wherein: The first floating diffusion region has a storage capacity different from a storage capacity of the second floating diffusion region.

4. The image sensing device according to claim 2, wherein: The first floating diffusion region stores photocharges generated by any one of the first unit pixels, and The second floating diffusion area stores photo charges generated by all of the second unit pixels.

5. The image sensing device according to claim 2, wherein: Each of the plurality of pixel groups further comprises: a plurality of third unit pixels, the plurality of third unit pixels sharing a third floating diffusion area; and A third pass transistor is coupled to the third floating diffusion region and transmits the photo charges stored in the third floating diffusion region to the common node based on a third pass signal.

6. The image sensing device according to claim 5, wherein: The third floating diffusion region has a storage capacity greater than a storage capacity of the second floating diffusion region.

7. The image sensing device according to claim 5, wherein: The third floating diffusion region simultaneously stores photo charges generated by all of the third unit pixels.

8. The image sensing device according to claim 1, wherein: Each of the plurality of pixel groups comprises: first unit pixels, the first unit pixels being commonly coupled to a first common connector; second unit pixels, the second unit pixels being commonly coupled to a second common connector coupled to the first common connector; a first photocharge storage circuit coupled to the first common connector and the second common connector, storing photocharges generated by the first unit pixel or the second unit pixel based on a first pass signal, and outputting the stored photocharges to the common node based on a second pass signal; and A second photocharge storage circuit is connected to the first common connector and the second common connector, stores photocharges generated by the first unit pixel or the second unit pixel based on a third pass signal, and outputs the stored photocharges to the common node based on a fourth pass signal.

9. The image sensing device according to claim 8, wherein: The first photocharge storage circuit comprises: a first pass transistor that is turned on or off based on the first pass signal; a second pass transistor that is serially coupled to the first pass transistor and is turned on or off based on the second pass signal; and A first floating diffusion region is provided between the first pass transistor and the second pass transistor in such a manner that the first floating diffusion region is commonly coupled to the first pass transistor and the second pass transistor.

10. The image sensing device according to claim 9, wherein: The first floating diffusion region is formed to have a storage capacity corresponding to a size capable of storing photocharges generated by a single unit pixel.

11. The image sensing device according to claim 9, wherein: The first pass transistor, the second pass transistor, and the first floating diffusion region are formed in a first active region.

12. The image sensing device according to claim 8, wherein: The second photocharge storage circuit comprises: a third pass transistor which is turned on or off based on the third pass signal; a fourth pass transistor connected in series to the third pass transistor and turned on or off based on the fourth pass signal; and A second floating diffusion region is provided between the third pass transistor and the fourth pass transistor in such a manner that the second floating diffusion region is commonly coupled to the third pass transistor and the fourth pass transistor.

13. The image sensing device according to claim 12, wherein: The second floating diffusion region is formed to have a storage capacity corresponding to a size capable of simultaneously storing photo charges generated by two or more unit pixels.

14. The image sensing device according to claim 12, wherein: The third pass transistor, the fourth pass transistor, and the second floating diffusion region are formed in a second active region.

15. The image sensing device according to claim 1, wherein: The plurality of unit pixels included in each of the plurality of pixel groups include a color filter allowing light having the same color to pass therethrough.

16. The image sensing device according to claim 1, wherein: The plurality of pixel groups include a first pixel group that allows light having a first color to pass therethrough to be detected and a second pixel group that allows light having a second color different from the first color to pass therethrough to be detected.

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