System and method for determining time of flight using classification of both code and phase in a received signal

Abstract

A method for detecting a sounding signal with an estimated code delay and an estimated Doppler frequency comprises: (i) dividing a period of the sounding signal into parts each having a predetermined duration; (ii) assigning one of a plurality of code classes to each part, each code class indicating a signal pattern of the sounding signal within the part; and (iii) selecting a plurality of phase classes for a sinusoidal signal, each phase class indicating a phase range in the sinusoidal signal. Thereafter, the method comprises: (i) receiving a signal from which a sounding signal is to be detected; (ii) dividing the received signal into parts each having a predetermined duration; (iii) assigning a corresponding code class and a corresponding phase class to each part of the received signal based on the estimated code delay and the Doppler frequency, respectively; and (iv) individually accumulating the parts of the received signal according to the assigned code class and phase class of each part.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present invention relates to and claims priority to: (i) U.S. Provisional Patent Application Serial No. 62 / 846,240, filed on May 10, 2019, and entitled “System and Method For Time-of-Flight Determination Using Categorization of Code and Phase in Received Signal”; and (ii) U.S. Provisional Patent Application Serial No. 62 / 964,950, filed on January 23, 2020, and entitled “System and Method For Time-of-Flight Determination Using Categorization of Code and Phase in Received Signal”.

[0003] The present invention is also related to U.S. patent application Ser. No. 16 / 587,779, filed on Sep. 30, 2019, entitled “System and Method of Time of Flight Detection,” which is a continuation of U.S. patent application Ser. No. 16 / 359,315, filed on Mar. 20, 2019, entitled “System and Method of Time of Flight Detection,” now U.S. Patent No. 10,477,353, filed on Jul. 27, 2017, entitled “System and Method of Time of Flight Detection,” which is a continuation of U.S. patent application Ser. No. 16 / 359,315, filed on Mar. 20, 2019, entitled “System and Method of Time of Flight Detection,” now U.S. Patent No. 10,477,353, filed on Jul. 27, 2017, entitled “System and Method of Time of Flight Detection,” No. 15 / 661.477, entitled “System and Method of Time of Flight Detection,” filed on July 26, 2016, which is a continuation of U.S. patent application Ser. No. 15 / 220,360, entitled “System and Method of Time of Flight Detection,” filed on July 26, 2016, which is a continuation of U.S. patent application Ser. No. 9,723,444, entitled “System and Method of Time of Flight Detection,” filed on August 13, 2015, which is a continuation of U.S. patent application Ser. No. 14 / 826,128, entitled “System and Method of Time of Flight Detection,” filed on August 13, 2015, which is a continuation of U.S. patent application Ser. No. 9,439,040, entitled “System and Method of Time of Flight Detection,” filed on August 13, 2014, which is a continuation of The related application is incorporated herein by reference in its entirety. Technical Field

[0004] The present invention relates to processing a received signal to determine the distance to the signal source. In particular, the present invention relates to processing a direct sequence code division multiple access (CDMA) signal to determine the distance of a receiver from its signal source using both its code sequence and its phase. Background Art

[0005] The position of the signal receiver at any given time can be triangulated very accurately using signals received from multiple signal transmitting satellites, the positions of which are known to high accuracy at the time. Currently, satellites that can be used for position determination include those transmitted from Beidou, Glonass, GNSS and GPS systems. For example, each satellite in the GPS system transmits a "probe signal" that includes a 1575.42MHz carrier signal modulated by a 1023-chip pseudo-random (PRN) code and navigation data of 1.023MHz and 50bps, respectively. Based on the detected transmission time ("flight time" or "code delay") of the probe signal between the satellite and the receiver, the receiver can accurately determine its distance from the satellite. Detection of signals from multiple (e.g., 5 or more) satellites allows the receiver to accurately determine its position by triangulation. Summary of the invention

[0006] According to one embodiment of the present invention, a method for detecting a sounding signal with an estimated code delay and an estimated Doppler frequency comprises: (i) dividing a period of the sounding signal into parts each having a predetermined duration; (ii) assigning one of a plurality of code categories to each part, each code category indicating a signal pattern of the sounding signal within the part; and (iii) selecting a plurality of phase categories for a sinusoidal signal, each phase category indicating a phase range in the sinusoidal signal. Thereafter, the method comprises: (i) receiving a signal from which a sounding signal is to be detected; (ii) dividing the received signal into parts each having a predetermined duration; (iii) assigning a corresponding code category and a corresponding phase category to each part of the received signal based on the estimated code delay and the Doppler frequency, respectively; and (iv) separately accumulating the parts of the received signal according to the assigned code category and phase category of each part. In some embodiments, the predetermined duration of each part of the received signal or the sounding signal may be at most one chip, wherein each part of the received signal comprises a plurality of samples, each sample being represented by an in-phase component and an orthogonal component according to a predetermined sampling rate. The sounding signal may have a repeating cycle of a pseudo-random code modulated thereon.

[0007] According to one embodiment of the present invention, an integrated circuit for detecting a detection signal in a received signal comprises: (a) a memory circuit for storing one or more parts of the received signal, each part having a predetermined duration; (b) a plurality of processing circuits, each processing circuit comprising one or more independently addressable accumulators; and (c) a scheduling circuit, the scheduling circuit comprising: (i) a storage element for storing code categories, each code category being assigned to a corresponding part of a continuous part of the detection signal, each part of the detection signal having a predetermined duration, and each code category indicating a signal transition pattern of the detection signal within the corresponding part; and (ii) a code counter circuit, the code counter circuit mapping each part of the received signal to a corresponding code category in a code category in the storage element based on an estimated code delay between the detection signal and the received signal; and (iii) a phase counter circuit, the phase counter circuit mapping each part of the received signal to a corresponding phase category in a plurality of phase categories of a sinusoidal signal based on an estimated Doppler frequency between the received signal and the detection signal, wherein the scheduling circuit maps each part of the received signal to one of the addressable accumulators based on the corresponding code category and the corresponding phase category.

[0008] In one embodiment of the present invention, each accumulator in each processing unit separately accumulates the in-phase component and the orthogonal component of each sample, and the accumulator further includes a vector register for separate accumulation, a vector adder and a vector accumulation element.

[0009] In one embodiment of the present invention, the integrated circuit further includes a control circuit that causes the code category of the detection signal to be stored in a storage element. The control circuit provides overall control of the circuit elements in the integrated circuit and allocates resources (e.g., an accumulator circuit in each processing unit) for detection of the detection signal. The scheduling circuit may also include a code category generation circuit that determines the code category in the storage element based on a pseudo-random code specified by the control circuit. Alternatively, the code category may be generated by a control circuit that executes software or firmware. In addition, the scheduling circuit may also include a Gold code generator.

[0010] In one embodiment of the present invention, the control circuit may be provided by a microprocessor or a microcontroller in the form of a system on a chip.

[0011] According to one embodiment of the present invention, the scheduling circuit includes multiple groups of storage elements, code counter circuits, and phase counter circuits for detecting multiple detection signals, multiple estimated code delays, and multiple estimated Doppler frequencies.

[0012] The invention may be better understood from the following detailed discussion considered in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1Ais a block diagram showing a signal processing circuit 100 of a GPS receiver.

[0014] Figure 1B Shows Figure 1A An exemplary implementation 150 of each of the channels 103-1, 103-2, ..., and 103-n.

[0015] Figure 2A The samples of the exemplary 12-chip PRN code 603 are illustrated as being divided into portions in time.

[0016] Figure 2B shows the frequency f D The phase change (modulo 2π) of the sinusoidal signal 650 within 3 cycles.

[0017] Figure 3A A block diagram of a digital circuit 300 according to an embodiment of the present invention is shown, which includes an arithmetic logic unit 301, a scheduling circuit (or a class allocation circuit) 302, a memory circuit 303, and processing circuits 304-1, 304-2, ... 304-n.

[0018] Figure 3B A functional representation 315 of the partial accumulation period scheduling circuit 302 is shown.

[0019] Figure 3C An implementation 320 of an accumulator for supporting accumulation in any of the processing circuits 304 - 1 , 304 - 2 , . . . , and 304 - n is shown according to one embodiment of the present invention.

[0020] Figure 3D Data registers that may be provided in the scheduling circuit 302 to support the implementation of the functional representation 315 are shown.

[0021] Figure 4 Waveform 401 and waveform 402 are shown, where waveform 401 corresponds to the accumulated in-phase samples of a portion of the received signal (ie, the values ​​in the real part of the signal) and waveform 402 corresponds to the accumulated quadrature samples of the same portion of the received signal (ie, the values ​​in the imaginary part of the signal).

[0022] Figure 5 The relative size of the frequency search space in satellite acquisition is shown, showing the relative speed |v k The frequency search space 501 caused by the uncertainty of |-v| and the frequency search space 502 caused by the uncertainty of all Doppler components. DETAILED DESCRIPTION

[0023] Figure 1A FIG. 1 is a block diagram showing a signal processing circuit 100 of a GPS receiver. Figure 1AAs shown, antenna 101 receives satellite signal 120, which is down-converted to intermediate frequency (IF) (e.g., 4 MHz) signal 121 by mixing the received signal 120 with a signal 122 generated by a local oscillator in a radio frequency (RF) front-end circuit 102. The signal 122 generated by the local oscillator can be implemented, for example, by an oscillator 125 (e.g., a temperature compensated crystal oscillator ("TCXO")). This down-conversion can be implemented, for example, by mixing the received signal 120 with a locally generated signal 122 (e.g., a 1471.42 MHz signal) in an analog mixer in the RF front-end circuit 102. The present invention is applicable to processing signals from satellites of multiple constellations (e.g., GPS, GLONASS, Galileo, and BeiDou). Since the constellations use several different carrier frequencies, the IF signal 121 includes signals from different constellations modulated by slightly different intermediate frequencies.

[0024] The IF signal 121 is then sampled (e.g., at 32 MHz) in an analog-to-digital (ADC) circuit 103 to obtain a digitized signal 123, which is then provided to each of the channels 104-1, 104-2, ..., and 104-n for parallel detection. In many implementations, the digitized signal 123 is provided in complex form, i.e., in in-phase (I) and quadrature (Q) representations (e.g., 2 bits in each of the I component and the Q component). The movement of the satellite relative to the receiver results in a frequency shift f in the received signal 120. D (“Doppler frequency”). In many applications, the Doppler frequency is typically determined to be within ±5 KHz. Typically, at any given time, to detect received signal 120, channels 104-1, 104-2, ..., and 104-n each test hypotheses of both code delay and Doppler shift as estimates.

[0025] Figure 1B Shows Figure 1A An exemplary implementation 150 of each of the channels 104-1, 104-2, ..., and 104-n is shown. Figure 1B As shown, the channel implementation 150 includes a Doppler frequency removal circuit 151 and a matched filter circuit 152. The Doppler frequency removal circuit 151 multiplies the digitized received signal 123 by the digital samples of the sinusoidal signal of the estimated Doppler frequency to provide an input signal 124 with the Doppler frequency removed. The matched filter circuit 151 calculates a correlation value 125 between the input received signal with the Doppler frequency removed and a PRN code replica of the sounding signal at the estimated code delay. When the output value 125 of the matched filter circuit 152 is significantly greater than the background noise level, it is considered that a satellite is detected at the estimated code delay and the estimated Doppler frequency.

[0026] Figure 1AThe processor 180 can be used to process the detected satellite code delays to determine the receiver's position, velocity, and GPS time. The processor 180 can be implemented, for example, by any microprocessor (e.g., a microprocessor customized for signal processing or a general-purpose microprocessor) or any suitable host computer.

[0027] An efficient method for calculating correlation is disclosed in the related application, which is incorporated by reference above. The related application teaches a method, one of which is incorporated herein by reference. Figure 2A As shown, in this method, the samples of the exemplary 12-chip PRN code 603 are divided into parts according to time. (Of course, Figure 2A The PRN code 603 in FIG. 6 is constructed for illustration purposes only; any actual PRN code of any sounding signal, such as from a GPS satellite, has a relatively large number of chips (ie, code length). Figure 2A Also shown is a received signal 604 aligned with the PRN code 603 at the estimated code delay; the received signal 604 has been down-converted and the Doppler frequency removed. Section boundaries 601 are each set at the midpoint of a corresponding chip in the 12-chip PRN code of the sounding signal 603. Each section lasts for one chip time (t c ).like Figure 2A As shown, each section is classified according to the bit transitions in the PRN code 603 within the section. For example, adjacent section 602 is classified into categories "0" and "1". The categories of the remaining sections are similarly labeled. Figure 2A In the example, the category k of each part can be any one of the following four categories: (a) when all signal values ​​within the part are equal to +1 level, k=0; (b) when the signal value within the part once changes from +1 level to -1 level, k=1; (c) when all signal values ​​within the part are equal to -1 level, k=2; (d) when the signal value within the part changes from +1 level to -1 level, k=3.

[0028] In the disclosed method of the related application, samples in each portion of the received signal 604 are accumulated in an accumulator corresponding to the class of the portion. Figure 2A According to the classification scheme in FIG. 6 , four accumulators (each corresponding to one of the four categories) may be used to accumulate in parallel samples of a corresponding classified portion of the received signal 604. In each accumulator, the detected signal (i.e., the estimated code delay and the estimated Doppler frequency are close to the actual code delay and the actual Doppler frequency) causes the accumulated samples in each accumulator to conform to the waveform of the corresponding bit transitions in the PRN code within the portion.

[0029] The present invention extends the method of the related application to eliminate the need for a separate step of removing the Doppler frequency. Figure 2B shows the frequency fD The sinusoidal signal 650 is within 3 cycles (i.e., from time 0.0 to time 3.0 / f D The phase change (modulo 2π) between Figure 2B As shown, the phase of the sinusoidal signal 650 increases linearly from 0 to 2π over time in each signal cycle. Within each signal cycle, the phase of the sinusoidal signal 650 at any time can be assigned to one of any number of "phase categories". For example, Figure 2B , the phase of the sinusoidal signal 650 can all fall into one of four phase categories, namely, (i) between 0.0 and π / 2, indicated by interval 651, (ii) between π / 2 and π, indicated by interval 652, (iii) between π and 3π / 2, indicated by interval 653, and (iv) between 3π / 2 and 2π (i.e., 0.0), indicated by interval 653. Figure 2B The diagram shows the mapping of the phase change over time of each cycle of the sinusoidal signal to four phase categories, which is for illustrative purposes only. The phase change in each cycle of the sinusoidal signal can be mapped to any number of phase categories. For example, the phase category in each cycle of the sinusoidal signal can be mapped to eight phase categories, namely, (i) between 0.0 and π / 4, (ii) between π / 4 and π / 2, (iii) between π / 2 and 3π / 4, (iv) between 3π / 4 and π, (v) between π and 5π / 4, (vi) between 5π / 4 and 3π / 2, (vii) between 3π / 2 and 7π / 4, and (viii) between 7π / 4 and 2π.

[0030] According to one embodiment of the present invention, Figure 2A The received signal 604 can also be divided into parts in time, and the parts are not only classified into code categories, as described above in conjunction with Figure 2A As discussed above, the received signal 604 is classified into phase categories. In other words, a composite category (c, p) may be assigned to each portion of the received signal 604, where c is the code category and p is the phase category. As assigned, samples of each portion of the received signal 604 assigned to the composite category (c, p) may be accumulated in an accumulator assigned to the composite category. In each accumulator, the detected signal causes the accumulated samples in the accumulator to conform to the phase waveform and quadrature waveform of the corresponding down-converted detection signal at the estimated code delay and the estimated Doppler frequency. According to one embodiment of the present invention, using Figure 2A and 2BThe four code classes and four phase classes of the sixteen accumulators can be used to perform the corresponding accumulations in parallel. In GPS applications, the Doppler frequency is usually between ±5KHz, and the duration of each chip is 1.0 microseconds, and the phase class rarely changes within the code period. Therefore, according to one embodiment of the present invention, for GPS applications, the same 1-chip duration can be used to create signal parts, such as Figure 2A shown.

[0031] According to one embodiment of the present invention, the following method illustrates the detection of a probe signal at an estimated code delay and an estimated Doppler frequency:

[0032] (i) dividing a period of the detection signal into parts of predetermined duration;

[0033] (ii) assigning one of a plurality of code classes to each portion, each code class indicating a signal pattern of a probe signal within the portion;

[0034] (iii) selecting a plurality of phase categories for the sinusoidal signal, each phase category indicating a phase range in the sinusoidal signal;

[0035] (iv) receiving a signal from which a probe signal is to be detected;

[0036] (v) dividing the received signal into parts each having a predetermined duration;

[0037] (v) assigning a corresponding code class and a corresponding phase class to each portion of the received signal based on the estimated code delay and Doppler frequency, respectively; and

[0038] (vi) Accumulating portions of the received signal individually according to the assigned code class and phase class of each portion.

[0039] Step (vi) may be performed, for example, by providing an accumulator for each composite class (c, p), where c is the code class and p is the phase class. This arrangement takes advantage of parallelism to achieve high performance and efficiency.

[0040] According to one embodiment of the present invention, the method of the present invention may be performed in a dedicated digital circuit, such as Figures 3A-3C The digital circuit 300 is shown. Figure 3AA block diagram of a digital circuit 300 according to an embodiment of the present invention is shown, and the digital circuit 300 includes a central processing unit (CPU) 301, a scheduling circuit (or a class assignment circuit) 302, a memory circuit 303, and processing circuits 304-1, 304-2, ... 304-n. The digital circuit 300 can be used to search for multiple detection signals from multiple signal sources ("channels") at the same time. Data (e.g., digitized received signals, PRN codes, and output data) can be received into the digital circuit 300, distributed throughout the digital circuit 300, or sent out from the digital circuit 300 via a system bus 305. An internal bus 306 provides communication of internal data and control signals between circuits of the digital circuit 300.

[0041] In some embodiments, CPU 301 can be any general-purpose microprocessor or microcontroller (e.g., of ARM architecture), typically usable as a configurable circuit module that can be directly integrated into a customized "system on chip" integrated circuit. In some embodiments, CPU 301 can be a customized control circuit capable of performing selected arithmetic and logic functions. According to one embodiment of the present invention, CPU 301 configures and controls the operation of the circuits in digital circuit 300. In some embodiments, processing circuits 304-1, 304-2, ... and 304-n each include one or more accumulator circuits, each of which is suitable for accumulating samples in a portion of a received signal, as described in further detail below. CPU 301 can allocate, for example, each such accumulator for accumulating a portion of a received signal of a specified channel, a specified composite category, and a specified pair of estimated code delays and estimated Doppler frequencies at any given time.

[0042] The scheduling circuit 302 is a logic circuit that schedules each portion of the received signal to one or more accumulators designated therefor for accumulation. The digital circuit 300 can be used to search for detection signals from multiple channels, and each portion of the received signal can be scheduled to multiple accumulators. Initially, the CPU 301 can load one or more PRN codes into the scheduling circuit 302. The scheduling circuit 302 can divide the cycle of the PRN code into desired portions and classify each portion according to a predetermined code category. Alternatively, the CPU 301 can provide a code category for each portion of the PRN code cycle instead of providing the PRN code to the scheduling circuit 302. In some embodiments, a Gold code generator can be provided to the scheduling circuit, which can be configured to generate the desired PRN code. The scheduling circuit 302 includes a data register for storing data required to assign a portion of the received signal to a composite category of a designated detection signal based on a corresponding pair of estimated code delays and estimated Doppler frequencies, and for scheduling a portion of the received signal to one or more of the processing circuits 301-1, 301-2, ... and 301-n for further processing.

[0043] Figure 3B A functional representation 315 of the partial accumulation period scheduling circuit 302 is shown. Figure 3D 315. Data registers are shown that may be provided in the scheduling circuit 302 to support the implementation of the functional representation 315. Initially, in the data register 343 ( Figure 3D ) provides the code category of the PRN code cycle and the identifier of the corresponding search channel. Figure 3B As shown, samples 316 of each portion of the received signal may be retrieved from memory circuit 303 to scheduling circuit 302 (e.g., to Figure 3D 344 of the sample data portion of the register 344 of the received signal). For example, in a GPS application, at a 32 MHz sampling rate, 32 complex samples (i.e., both in-phase samples and quadrature samples) are provided in each portion of 1 chip duration. The scheduling circuit 302 schedules the received samples to an accumulator, which maps the address of the accumulator according to the search parameters 317 (i.e., the assigned channel, the estimated code delay, and the Doppler frequency (determining the transition of phase category over time)). Based on the estimated code delay, a portion of the received signal is mapped to the start of a cycle of the PRN code of the assigned channel. The offset counter 341 ( Figure 3D ) indicates an offset 318 of the current portion of the received signal relative to the start of the PRN code. Based on the offset, the scheduling circuit 302 determines the code class. A phase counter 342 based on the estimated Doppler frequency indicates the phase class of the received portion. The combination of channel, code class, and phase class allows the scheduling circuit 302 to determine the destination accumulator that has been assigned by the CPU 301 for accumulation. The accumulator can be set in register 344 ( Figure 3D) provides the identification or address of the destination accumulator in the accumulator address portion of the accumulator address. Figure 3A ) provides sample data and the accumulator address of register 344 to send samples of the received signal to the destination accumulator.

[0044] Figure 3C 3 shows an implementation 320 of an accumulator for supporting accumulation in any one of the processing circuits 304-1, 304-2, ..., and 304-n according to one embodiment of the present invention. Figure 3C As shown, the data bus 324 (which may be Figure 3A The samples of each part are provided on the internal data bus 306 of the receiving device 306). As described above, each sample of each part is provided with both in-phase and quadrature (e.g., 2 bits in each of the in-phase component and the quadrature component). The in-phase component and the quadrature component of the sample are received by vector registers 325-I and 325-Q, respectively. Each of the vector registers 325-I and 325-Q may include, for example, 32 2-bit sub-registers, each of which stores a corresponding one of the 32 samples in the part. Accumulator registers 327-I and 327-Q store the corresponding accumulated vector sums of the in-phase component and the quadrature component of the samples in the previously received part. Vector adders 326-I and 326-Q add the in-phase component and the quadrature component of the current part to the accumulated vector sums in the accumulator registers 327-I and 327-Q. Each in-phase component or quadrature component of each sample in accumulation registers 327-I and 327-Q may be, for example, 8 bits or 16 bits, as required, based in part on the expected length of the PRN code.

[0045] As described above, in each accumulator, the detected signal (ie, the estimated code delay and the estimated Doppler frequency are close to the actual code delay and the actual Doppler frequency) causes the accumulated samples in each accumulator to conform to the waveform of the corresponding bit transitions in the PRN code within that portion. Figure 4 Waveform 401 and waveform 402 are shown, where waveform 401 corresponds to the accumulated in-phase samples of a portion of the received signal (i.e., the values ​​in the real part of the signal), and waveform 402 corresponds to the accumulated quadrature samples of the same portion of the received signal (i.e., the values ​​in the imaginary part of the signal). Note that the waveform corresponding to Figure 4 The portion of the PRN code of the portion of the received signal in includes a signal transition (e.g., from -1 to +1 or from +1 to -1). Waveform 401 and waveform 402 are similar to a step function and its derivative (i.e., an impulse function), respectively. Figure 44 , waveform 402 has a peak (i.e., peak 403) that is before midpoint 404 of the signal transition in waveform 401. The inventors recognized that in this configuration, the received signal represents the superposition of signals arriving via multiple paths, and peak 403 in waveform 402 represents their earliest arrival time.

[0046] The distance ("pseudorange") between the receiver and the location of the received signal transmitted from the satellite can be measured by multiplying the measured code delay by the speed of light c. If the receiver receives the received signal at time t, then the satellite must have transmitted from the satellite at GPS time t-τ, where τ is the actual code delay. The position of the satellite at GPS time t-τ can be accurately estimated from its ephemeris. The receiver's position and velocity can be solved using the measured pseudoranges (of typically four or more satellites). The calculations involved can be, for example, described above. Figure 1A , is executed in the processor 180 shown in . For example, in Section 6.1 of the revised second edition of the book "Global Positioning System: Signals, Measurement and Performance" ("Misra") co-authored by P. Misra and P. Enge, Misra provides the measured pseudorange ρ of satellite k, 1≤k≤N, N≥4 k Model of (t,t-τ):

[0047]

[0048] where r(t,t-τ) is the actual pseudorange, δt r (t) and δt s (t-τ) are the clock biases of the receiver and the satellite, respectively, k (t) represents the atmospheric delay compensation factor and is a noise term, usually modeled as Gaussian zero-mean noise. In general, the pseudoranges form the pseudorange vector ρ(t), and their time derivatives form the pseudorange time derivative vector

[0049] The receiver position and velocity vectors x and v can be modeled as system state variables of a dynamic system, which can be expressed using the pseudorange vector ρ(t) and the pseudorange time derivative vector The satellite ephemeris and statistical analysis techniques known to those skilled in the art (e.g., Kalman filter) are used to solve. For example, see Section 6.2 of Misra.

[0050] The above equation (1) can be rewritten as:

[0051]

[0052] where |xk -x| is the actual pseudorange, here represented by the satellite position vector x k The Euclidean distance between the satellite velocity vector v and the receiver position vector x. The time derivative of equation (2) converts the satellite velocity vector v k Relate to the receiver velocity vector v:

[0053]

[0054] Therefore, for each satellite, the observed Doppler frequency (which is linearly related to the time rate of change of the pseudorange) is the relative velocity (v) along the line of sight between the satellite and the receiver. k -v), satellite and receiver clock deviation rate and and the atmospheric compensation factor rate Among these Doppler components, the receiver clock deviation rate and the relative line of sight velocity |v k -v|, satellite clock deviation rate and atmospheric compensation factor rate Typically small, assuming a high-quality clock in the satellite and a relatively slowly varying weather model. As mentioned above, IF signal 121 is the result of mixing the received signal with a fixed frequency signal generated by local oscillator 125 (usually TXCO). The stability of oscillator 125 is reflected in the receiver clock deviation rate Uncertainty in relative velocity |v k -v| is dominated by the satellite motion; this uncertainty is typically on the order of 100KHz. However, the receiver clock deviation rate The uncertainty may be much greater. Figure 5 The relative size of the frequency search space in satellite acquisition is shown, showing the relative speed |v k The frequency search space 501 caused by the uncertainty of |-v| and the frequency search space 502 caused by the uncertainty of all Doppler components. The code phase search space 503 is also Figure 5 Instructions.

[0055] To reduce the frequency search space 502, the prior art requires a high quality TXCO with a known limited drift, which adds additional cost to the receiver. However, this approach may make the receiver too expensive for possible applications, such as IoT applications. Observing that the uncertainty due to the TCXO in the receiver is common to all satellites, the method according to the present invention requires the full range of the frequency search space 502 only during the initial acquisition of the first satellite in a cold start or warm start. Once the first satellite is successfully acquired, the receiver clock bias δt r(t) and the receiver clock deviation rate The values ​​of , together with their respective variances (as determined during the initial acquisition of the first satellite) are used in all subsequent satellite acquisitions. By this method, uncertainties other than the uncertainty of the relative speed of the respective satellites are substantially removed, so that the frequency search space that may be required only covers the frequency search space 501. The method can be summarized as follows:

[0056] (i) Using the receiver position and velocity vectors x and v and the receiver clock bias δt r (t) and the receiver clock deviation rate The receiver position and velocity vectors x and v are initialized to the best initial estimates as the state variables of the system model;

[0057] (ii) Acquire the first satellite using a first frequency search space that covers the uncertainty due to the orbit of the first satellite and due to the receiver clock bias δt r (t) and the receiver clock deviation rate The uncertainty caused by both;

[0058] (iii) The receiver clock deviation δt r (t) and the receiver clock deviation rate The corresponding internal states are set to their respective estimates obtained during the acquisition of the first satellite;

[0059] (iv) acquiring a second satellite using a second frequency search space that substantially only covers the uncertainty due to the orbit of the second satellite.

[0060] In some embodiments of the invention, the Kalman filter implements a system model in which the receiver position and velocity vectors x and v and the receiver and satellite clock biases δt r (t) is a system state variable. In some embodiments, the satellite clock bias δt s (t-τ), atmospheric compensation factor A k (t) and other factors that affect the measured pseudorange can be provided as input variables, or processed separately. In the Kalman filter, the system state variables x and v, and the receiver clock bias δt r (t) and the receiver clock deviation rate and their covariances are predicted by their corresponding current estimates and noise models. The current estimates of these system variables and their covariances are in turn updated using their corresponding recent estimates and measurements of the pseudoranges and Doppler frequencies of the corresponding satellites. For example, the receiver clock bias rate The current estimate of can be updated by a linear function of its most recent estimate and the measured Doppler.

[0061] The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Many variations and modifications are possible within the scope of the present invention. The present invention is set forth in the following claims.

Claims

1. A method for detecting a probe signal with an estimated code delay and an estimated Doppler frequency, comprising: (i) dividing a period of the detection signal into parts each having a predetermined duration; (ii) assigning one of a plurality of code classes to each portion, each code class being indicative of a signal pattern of the detection signal within the portion; (iii) selecting a plurality of phase categories for the sinusoidal signal, each phase category indicating a phase range in the sinusoidal signal; (iv) receiving a signal from which the detection signal is to be detected; (v) dividing the received signal into parts each having said predetermined duration; (vi) assigning each portion of the received signal both a corresponding code class and a corresponding phase class based on the estimated code delay and the Doppler frequency, respectively; and (vii) individually summing portions of the received signal according to the assigned code class and phase class of each portion.

2. The method of claim 1, wherein: The predetermined duration is at most one chip.

3. The method of claim 1, wherein: Each portion of the received signal includes a plurality of samples.

4. The method of claim 3, wherein: Each sample includes an in-phase component and a quadrature component.

5. The method of claim 1, wherein: The probe signal has a repeating cycle of a pseudo-random code modulated thereon.

6. An integrated circuit for detecting a detection signal in a received signal, comprising: a memory circuit for storing one or more portions of the received signal, each portion having a predetermined duration; a plurality of processing circuits, each processing circuit including one or more independently addressable accumulators; as well as A scheduling circuit comprises: (i) a storage element for storing a plurality of code categories, each code category being assigned to a corresponding portion of a continuous portion of the detection signal, each portion of the detection signal having the predetermined duration, and each code category indicating a signal transition pattern of the detection signal within the corresponding portion; (ii) a code counter circuit, the code counter circuit mapping each portion of the received signal to a corresponding code category in the code categories in the storage element based on an estimated code delay between the detection signal and the received signal; and (iii) a phase counter circuit, the phase counter circuit mapping each portion of the received signal to a corresponding phase category in a plurality of phase categories of a sinusoidal signal based on an estimated Doppler frequency between the received signal and the detection signal, wherein the scheduling circuit maps each portion of the received signal to one of the addressable accumulators based on the corresponding code category and the corresponding phase category.

7. The integrated circuit of claim 6, further comprising a control circuit that causes the code category of the detection signal to be stored in the storage element.

8. The integrated circuit of claim 7, wherein: The scheduling circuit further includes a code class generation circuit that determines the code class in the storage element based on a pseudo-random code specified by the control circuit.

9. The integrated circuit of claim 8, wherein: The scheduling circuit also includes a Gold code generator circuit.

10. The integrated circuit of claim 7, wherein: The control circuit includes a microprocessor or a microcontroller.

11. The integrated circuit of claim 10, wherein: The microprocessor or the microcontroller is integrated into the integrated circuit in a system-on-chip manner.

12. The integrated circuit of claim 6, wherein: The scheduling circuit includes a plurality of groups of storage elements, a code counter circuit, and a phase counter circuit for detecting a plurality of detection signals, a plurality of estimated code delays, and a plurality of estimated Doppler frequencies.

13. The integrated circuit of claim 6, wherein: The predetermined duration is at most one chip.

14. The integrated circuit of claim 6, wherein: Each portion of the received signal includes a plurality of samples.

15. The integrated circuit of claim 14, wherein: Each sample includes an in-phase component and a quadrature component.

16. The integrated circuit of claim 15, wherein: Each accumulator separately accumulates the in-phase component and the quadrature component of each sample separately, and the accumulator further includes a vector register, a vector adder and a vector accumulation element for the separate accumulation.

17. The integrated circuit of claim 6, wherein: The probe signal has a repeating cycle of a pseudo-random code modulated thereon.

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