Photonic chip and method of manufacturing the same

Abstract

A method of fabricating a photonic chip. The method includes providing a wafer including a silicon substrate and a low refractive index layer on the silicon substrate; forming a first trench having a first height and a second trench having a second height by etching the low refractive index layer. The second height is greater than the first height, and the second trench has a bottom surface closer to a bottom surface of the substrate than a bottom surface of the first trench.

Description

Technical Field

[0001] This invention relates to the fabrication of photonic chips and waveguides on photonic chips. Background Technology

[0002] In the field of photonic chips, it is often necessary to provide waveguides of different sizes on the same photonic chip. These waveguides are suitable for different purposes, such as coupling to components of different sizes, such as optoelectronic devices or optical fibers.

[0003] Chips with waveguides of different sizes may be difficult to process later, for example, using chemical mechanical polishing (CMP), due to variations in the height of the top surface on the chip.

[0004] The present invention was designed based on the above considerations. Summary of the Invention

[0005] In a first aspect, the present invention provides a method for manufacturing a photonic chip, the method comprising: providing a wafer, a wafer substrate, and a low-refractive-index layer thereon; etching the low-refractive-index layer to form a first trench having a first height and a second trench having a second height greater than the first height, and the second trench having a bottom surface closer to the bottom surface of the substrate than the bottom surface of the first trench.

[0006] A low-refractive-index layer, due to its low refractive index, can confine light within a waveguide. In this application, the refractive index of the low-refractive-index layer may be lower than that of the waveguide material. The refractive index of the low-refractive-index layer may be lower than that of silicon. For example, the low-refractive-index layer may be less than 3.4 at wavelengths from 1200 nm to 8500 nm. The low-refractive-index material may be SiO2. Alternatively or additionally, any low-refractive-index layer in this application may be an insulating layer. Furthermore, when the term "insulating layer" is used in this application, such a layer may alternatively or additionally be a low-refractive-index layer.

[0007] The height of a layer, waveguide, or trench is measured in a direction away from the substrate. The top surface of a layer or waveguide is the surface furthest from the substrate, while the bottom surface of a layer or waveguide, or the bottom of a trench, is the surface closest to the substrate. For example, the height of a waveguide is measured from the bottom surface to the top surface of the waveguide in a direction orthogonal to the substrate surface. The width of a waveguide is measured in a direction perpendicular to its height and perpendicular to the direction of light propagation along the waveguide. The length of a waveguide is measured in a direction perpendicular to its height and parallel to the direction of light propagation along the waveguide.

[0008] The substrate can be a silicon substrate.

[0009] The height of the waveguide can range from 100 nm to 12 micrometers. The first height can be less than 550 nm, preferably between 100 nm and 500 nm, and more preferably 220 nm. The second height can be between 1 micrometer and 12 micrometers, preferably between 2 micrometers and 5 micrometers, and more preferably 3 micrometers. Optionally, the height of the second trench can be 10 micrometers or 12 micrometers.

[0010] The method may further include: etching the low-refractive-index layer to form one or more additional trenches having the same or different depths as the first trench or the second trench.

[0011] The first and second trenches can be etched using reactive ion etching (RIE). Due to a phenomenon known as RIE hysteresis, the wider the trench, the deeper the etching. Therefore, the trench width can be used to control the trench depth.

[0012] The second trench can be etched through the entire height of the low-refractive-index layer, such that the bottom of the trench is formed from the surface of the substrate. This allows the substrate to be used as a seed for the regrowth of silicon deposited in the second trench.

[0013] Etching the first trench and etching the second trench can occur simultaneously. "Simultaneously" can mean that the steps occur with the same start and end times, such that the time spent on each step completely overlaps. "Simultaneously" can also mean partial overlap in the duration of two simultaneous steps. A single process can be used to complete multiple simultaneous steps.

[0014] The width of the second trench may be greater than the width of the first trench. The width of the trench may be between 80 nm and 12 micrometers. The width of the first trench may be in the range of 80 nm to 3000 nm or 250 nm to 3000 nm, preferably 500 nm + / - 100 nm. The width of the second trench may be between 1 micrometer and 12 micrometers, preferably 3 micrometers.

[0015] Due to an effect known as RIE hysteresis, wider trenches will etch to a greater height under the same conditions when using RIE. Therefore, by etching trenches of different widths, a single RIE process can be used to etch trenches of multiple depths.

[0016] The method may further include: depositing a mask on a photonic chip and patterning the mask to define the location and width of trenches.

[0017] The method may further include: forming a first waveguide in a first trench. The method may further include: forming a second waveguide in a second trench. The first waveguide and / or the second waveguide may be formed of silicon. The formation of the first waveguide and the formation of the second waveguide may occur simultaneously. The width of the second waveguide may be greater than the width of the first waveguide. The method may further include: forming one or more additional waveguides in one or more additional trenches. The trench layout may be designed according to the application in which the waveguides will be used.

[0018] The first waveguide and / or the second waveguide may be epitaxially grown. Alternatively, the first waveguide and / or the second waveguide may be deposited by chemical vapor deposition (CVD), atomic layer deposition, evaporation, or sputtering. The first waveguide and / or the second waveguide may be deposited as a polycrystalline or amorphous material, and then subsequently thermally regrown to form a polycrystalline or single-crystal structure. The first waveguide and / or the second waveguide may be formed from polycrystalline silicon, amorphous silicon, or single-crystal silicon. The first waveguide and / or the second waveguide may be formed from silicon, germanium, or any combination of silicon nitride or oxynitride.

[0019] The step of forming the first waveguide may include filling the first trench with polycrystalline silicon, amorphous silicon, or monocrystalline silicon. The step of forming the second waveguide may include filling the second trench with polycrystalline silicon, amorphous silicon, or monocrystalline silicon.

[0020] The steps of forming the first waveguide and / or the second waveguide may include: epitaxially growing silicon in the respective first trench and / or second trench.

[0021] The steps of forming the first waveguide and the second waveguide may include: overfilling the first trench and the second trench such that silicon in the first trench is bonded to silicon in the second trench through excess silicon; and regrowing the silicon in the first trench and the second trench to form monocrystalline silicon. This means that a monocrystalline silicon waveguide can be provided even if the bottom of the waveguide is not in a substrate or another silicon layer. Furthermore, if the bottom of the second trench is formed by a substrate, the silicon in the first trench can be regrowed using the substrate as a seed crystal to form a monocrystalline waveguide even if the bottom of the first trench is not formed by silicon.

[0022] The steps of forming the first waveguide and the second waveguide may include: planarizing the silicon in the first trench and the second trench such that the top surface of the first waveguide is coplanar with the top surface of the second waveguide. Planarization may include chemical mechanical polishing. Making the top surfaces of the waveguides coplanar enables simpler subsequent processing of the chip, such as by CMP.

[0023] Alternatively, the top surfaces of the first and second waveguides may not be coplanar. The center height of the first waveguide may be coplanar with the center height of the second waveguide. The center height of each waveguide is equidistant from the bottom and top surfaces of the respective waveguide. This can be advantageous when guiding light between waveguides of different heights.

[0024] The height of the mode in the first waveguide can be coplanar with the height of the mode in the second waveguide. The height of the core of the first waveguide can be coplanar with the height of the core of the second waveguide. When multiple modes are formed in the second waveguide, the height of one or more of these modes can be aligned with the height of the mode in the first waveguide, and vice versa.

[0025] In this disclosure, surfaces with a height difference of less than 50 nm are considered coplanar because such height difference is negligible. Such height differences may be caused by manufacturing processes (such as CMP termination layers).

[0026] The steps of forming the first waveguide and / or the second waveguide may include: etching material in the respective first trench and / or second trench to form a ribbed waveguide. The first waveguide and / or the second waveguide may be a strip waveguide, a ribbed waveguide, or a slotted waveguide. Forming the first waveguide and / or the second waveguide may include: etching material in the respective first trench and / or second trench to form a strip waveguide, a ribbed waveguide, or a slotted waveguide.

[0027] The first waveguide and / or the second waveguide may be formed from a sequence of materials, and the sequence may be periodic. For example, one or more of the waveguides may be formed from alternating segments of silicon oxide and silicon, the sizes of which may be adjusted to select a desired refractive index for the waveguide. The segments may be sized such that their length is less than the wavelength of the light to pass through the waveguide. The steps of forming the first waveguide and / or the second waveguide may include depositing or growing a sequence of materials along the length of the waveguide. The sequence may be periodic. For example, one or more of the waveguides may be formed from alternating segments of silicon oxide and silicon, the sizes of which may be adjusted to select a desired refractive index for the waveguide. The segments may be sized such that their length is less than the wavelength of the light to pass through the waveguide. An example of a method for fabricating a waveguide using a sequence of materials is given in “Subwavelength waveguide grating for modeconversion and light coupling in integrated optics”, Vol. 14, No. 11, pp. 4695-4702, by Cheben P et al., Optics Letters, 2006.

[0028] The procedures described herein can be used in either or both of the first and / or second waveguides and / or in one or more other waveguides.

[0029] The wafer can be a silicon-on-insulator (SOI) wafer comprising a substrate formed of silicon, a low-refractive-index layer, and a silicon device layer. If SOI is used, etching the first trench and / or the second trench may include etching through the top device layer and into the low-refractive-index layer.

[0030] The wafer may be a double silicon-on-insulator (SOI) wafer, comprising a top silicon device layer, a low-refractive-index layer below the top silicon device layer, an intermediate device layer below the low-refractive-index layer, another low-refractive-index layer below the intermediate device layer, and a substrate below the other low-refractive-index layer. If a double SOI is used, etching the first trench and / or the second trench may include etching through the top silicon device layer, through the low-refractive-index layer, through the intermediate device layer, and into the other low-refractive-index layer. Additionally, the trench may be etched through the entire height of the other low-refractive-index layer, such that the bottom of the trench is formed by the surface of the substrate. Etching the first trench and / or the second trench may include etching through the top silicon device layer and into the low-refractive-index layer. Additionally, the trench may be etched through the entire height of the low-refractive-index layer, such that the bottom of the trench is formed by the surface of the intermediate device layer.

[0031] The method may further include: depositing a top layer of low-refractive-index material before etching the first trench and the second trench, and the step of etching the first trench and the second trench may include: etching through the top layer.

[0032] The method may further include: depositing or growing a low-refractive-index material on a substrate to form a low-refractive-index layer.

[0033] The first and second waveguides can be connected by a tapered waveguide, which may be adjacent to the first waveguide at a first end and / or adjacent to the second waveguide at a second end. The term "adjacent" means that the tapered waveguide intersects with the first / second waveguide at a boundary and may be adjacent to the first / second waveguide (e.g., the tapered waveguide may form a single crystal with the first / second waveguide) or may intersect with the first / second waveguide at an interface of the tapered waveguide's internal structure, and the first / second waveguides are not aligned (e.g., the tapered waveguide may be amorphous silicon, and the first / second waveguide may be single crystal, or the first / second waveguide and the tapered waveguide may be formed of different materials).

[0034] Using a tapered connection, light can be transmitted from a larger component (e.g., a waveguide or optical fiber) to a smaller component (e.g., a waveguide) via a tapered waveguide as follows: from the larger component through a second waveguide, from the second end through the tapered waveguide to the first end, into the first waveguide, and then into the smaller component. Alternatively, light can be transmitted from the smaller component to the larger component via a tapered waveguide as follows: from the smaller component through a first waveguide, from the first end through the tapered waveguide to the second end, into the second waveguide, and then into the larger component. By transmitting light through the first and second waveguides, as well as the tapered waveguide, optical loss between the smaller and larger components is reduced.

[0035] The width and / or height of the trench may vary continuously from the first end to the second end of the tapered waveguide to provide a smooth change in width and / or height along the length of the tapered waveguide. Alternatively, the width and / or height of the tapered waveguide may vary gradually along the length of the tapered waveguide. The step size may be at regular intervals along the length of the tapered waveguide.

[0036] In a second aspect, the present invention provides a photonic chip comprising a substrate and a low-refractive-index layer thereon, a first waveguide having a first height and a second waveguide having a second height greater than the first height, and a second trench having a bottom surface closer to the bottom surface of the substrate than the bottom surface of the first trench.

[0037] The substrate can be a silicon substrate.

[0038] The height of the waveguide can range from 100 nm to 12 micrometers. A first height can be less than 550 nm, preferably between 100 nm and 500 nm, and more preferably 220 nm. A second height can be between 1 micrometer and 12 micrometers, preferably between 2 micrometers and 5 micrometers, and more preferably 3 micrometers. Optionally, the second height can be 10 micrometers or 12 micrometers.

[0039] The photonic chip may also include one or more additional waveguides having the same or different heights as the first or second waveguide. These waveguides may be formed simultaneously using the same process as the first and second waveguides.

[0040] The width of the second waveguide can be greater than the width of the first waveguide. The width of the trench can be between 80 nm and 12 micrometers. The width of the first waveguide can be in the range of 80 nm to 3000 nm or 250 nm to 3000 nm, preferably 500 nm + / - 100 nm. The width of the second waveguide can be between 1 micrometer and 12 micrometers, preferably 3 micrometers.

[0041] The first waveguide and / or the second waveguide may be formed of polycrystalline silicon, amorphous silicon, or monocrystalline silicon. The first waveguide and / or the second waveguide may be formed of silicon, germanium, or any combination of silicon nitride or oxynitride.

[0042] The top surface of the first waveguide may be coplanar with the top surface of the second waveguide. Making the top surfaces of the waveguides coplanar allows for simpler subsequent processing of the chip, such as through CMP. When one or more additional waveguides are formed, all waveguides may have coplanar top surfaces.

[0043] Alternatively, the top surfaces of the first and second waveguides may not be coplanar. The center height of the first waveguide may be coplanar with the center height of the second waveguide. The center height of each waveguide is equidistant from the bottom and top surfaces of the respective waveguide. This can be advantageous when guiding light between waveguides of different heights.

[0044] The height of the mode in the first waveguide can be coplanar with the height of the mode in the second waveguide. The height of the core of the first waveguide can be coplanar with the height of the core of the second waveguide. When multiple modes are formed in the second waveguide, the height of one or more of these modes can be aligned with the height of the mode in the first waveguide, and vice versa.

[0045] The first waveguide and / or the second waveguide may be a strip waveguide, a rib waveguide, or a slot waveguide.

[0046] The first waveguide and / or the second waveguide may be formed from a sequence of materials, and the sequence may be periodic. For example, one or more of the waveguides may be formed from alternating segments of silicon oxide and silicon, the sizes of which may be adjusted to select a desired refractive index for the waveguide. The segments may be sized such that their length is less than the wavelength of the light to be transmitted through the waveguide. An example of a method for fabricating waveguides using a sequence of materials is given in “Subwavelength waveguide grating for mode conversion and light coupling in integrated optics”, Vol. 14, No. 11, pp. 4695-4702, by Cheben P et al., 2006, Optics Letters.

[0047] The procedures described herein can be used in either or both of the first and / or second waveguides and / or in one or more other waveguides.

[0048] The photonic chip may also include a silicon device layer situated above the low-refractive-index layer. A first waveguide may extend through the top device layer and into the low-refractive-index layer.

[0049] The photonic chip may include a top silicon device layer, a low-refractive-index layer below the top silicon device layer, an intermediate device layer below the low-refractive-index layer, another low-refractive-index layer below the intermediate device layer, and a substrate below the other low-refractive-index layer. A first waveguide and / or a second waveguide may extend through the top silicon device layer, through the low-refractive-index layer, through the intermediate device layer, and into the other low-refractive-index layer. They may be etched through the entire height of the other low-refractive-index layer, such that the bottom of the waveguide is formed by the surface of the substrate. The first waveguide and / or the second waveguide may extend through the top silicon device layer and into the low-refractive-index layer, such that the bottom of the waveguide is formed by the low-refractive-index layer. They may extend through the entire height of the low-refractive-index layer, such that the bottom of the waveguide is formed by the surface of the intermediate device layer.

[0050] The first and second waveguides can be connected via a tapered waveguide, which may be adjacent to the first waveguide at a first end and / or adjacent to the second waveguide at a second end. The term "adjacent" means that the tapered waveguide intersects with the first / second waveguide at a boundary and may be adjacent to the first / second waveguide (e.g., the tapered waveguide may form a single crystal with the first / second waveguide) or may intersect with the first / second waveguide at an interface of the tapered waveguide's internal structure, and the first / second waveguides are not aligned (e.g., the tapered waveguide may be amorphous silicon, and the first / second waveguide may be single crystal, or the first / second waveguide and the tapered waveguide may be formed of different materials). When forming one or more additional waveguides, any pair of waveguides of different sizes can be connected to each other in the same manner via tapered waveguides.

[0051] Using a tapered connection, light can be transmitted from a larger component (e.g., a waveguide or optical fiber) to a smaller component (e.g., a waveguide) via a tapered waveguide as follows: from the larger component through a second waveguide, from the second end through the tapered waveguide to the first end, into the first waveguide, and then into the smaller component. Alternatively, light can be transmitted from the smaller component to the larger component via a tapered waveguide as follows: from the smaller component through a first waveguide, from the first end through the tapered waveguide to the second end, into the second waveguide, and then into the larger component. By transmitting light through the first and second waveguides, as well as the tapered waveguide, optical loss between the smaller and larger components is reduced.

[0052] The width and / or height of the trench may vary continuously from the first end to the second end of the tapered waveguide to provide a smooth change in width and / or height along the length of the tapered waveguide. Alternatively, the width and / or height of the tapered waveguide may vary gradually along the length of the tapered waveguide. The step size may be at regular intervals along the length of the tapered waveguide.

[0053] The varying height of the tapered waveguide can be controlled by changing the width of the tapered waveguide in a manner similar to that described in this application for controlling the height of the waveguide.

[0054] The present invention includes combinations of the described aspects and preferred features, unless such combinations are obviously not permitted or explicitly avoided. Attached Figure Description

[0055] The embodiments and experiments illustrating the principles of the present invention will now be discussed with reference to the accompanying drawings, in which:

[0056] Figure 1 A cross-sectional view of a photonic chip with waveguides of four different heights is shown, all of which have a coplanar top surface.

[0057] Figure 2 A cross-sectional view of a photonic chip with four strip waveguides of different heights is shown, all of which have a coplanar top surface.

[0058] Figures 3A to 3F It shows Figure 2 A cross-sectional view of the steps in the manufacturing method of a photonic chip.

[0059] Figures 4A to 4F A cross-sectional view is shown of the steps in a method for fabricating photonic chips with waveguides of different heights on an SOI wafer.

[0060] Figures 5A to 5G A cross-sectional view is shown of the steps in a method for manufacturing a photonic chip with four waveguides of different heights. Detailed Implementation

[0061] Aspects and embodiments of the invention will now be discussed with reference to the accompanying drawings. Further aspects and embodiments will be apparent to those skilled in the art. All documents mentioned herein are incorporated by reference.

[0062] Figure 1 A photonic chip comprising a silicon substrate 1, a low-refractive-index layer 2 on top of the silicon substrate 1, and four waveguides 11, 12, 13, and 14 is shown. The first waveguide 11 has a first height from the bottom surface of the waveguide in the low-refractive-index layer 2 to the top surface of the waveguide. The second waveguide 12 has a second height from the bottom surface of the waveguide in the low-refractive-index layer 2 to the top surface of the waveguide. The second height is greater than the first height. The third waveguide 13 has a third height less than the first and second heights. The fourth waveguide 14 has a fourth height less than the third height.

[0063] Waveguides 11, 12, 13, and 14 all have coplanar top surfaces; therefore, the higher the waveguide, the closer its bottom surface is to the substrate. The second waveguide 12 has the greatest height, and therefore its bottom surface is closer to the substrate than the bottom surfaces of any other waveguide.

[0064] In other implementations, the top surfaces may be non-coplanar. For example, the center height of one waveguide may be coplanar with the center height of another waveguide. The center height of each waveguide is equidistant from the bottom and top surfaces of the respective waveguide. This can be advantageous when guiding light between waveguides of different heights.

[0065] For example, the height of one mode in a waveguide can be coplanar with the height of another mode in the waveguide. Similarly, the height of the core in one waveguide can be coplanar with the height of the core in another waveguide. In the case of multiple modes formed in a waveguide, the height of one or more of these modes can be aligned with the height of another mode in the waveguide.

[0066] Waveguides are depicted in order from the minimum height on the left side of the diagram to the maximum height on the right side. However, it should be understood that this is for illustrative purposes only, and the orientation and position of waveguides on the chip can be freely chosen to suit the application.

[0067] The waveguides are strip waveguides and fill the trenches in the low-refractive-index layer 2. The top surface of each of waveguides 11, 12, 13, and 14 is coplanar with the top surface of the low-refractive-index layer 2. In this example, the low-refractive-index layer 2 is SiO2.

[0068] Figure 2 Showing with Figure 1 Similar to photonic chips, but the waveguides do not fill the trenches in the low-refractive-index waveguides, and there are gaps between the trench walls and the waveguide on each side of each waveguide. This illustrates the possibility of etching one or more waveguides to form the width and shape desired for the application.

[0069] To form this photonic chip, etching is possible. Figure 1 Waveguides 11, 12, 13, and 14 are shown to form side trenches on each side of the waveguide. This can be achieved by depositing a mask on the top surface of the chip, patterning the mask to the desired waveguide width, and etching the waveguide to produce the desired shape.

[0070] Figure 3 illustrates the process from... Figure 3A The steps in a method for fabricating a photonic chip, starting with silicon (Si) wafer 1, are shown. Figure 3B In this example, a low-refractive-index layer 2 has been grown or deposited on the silicon substrate 1. In this example, the low-refractive-index layer 2 is formed of SiO2.

[0071] A mask can be provided above the low-refractive-index layer 2, and the mask can be patterned to the desired layout and width of the trenches in which the waveguide will later be formed. Trenches 11t, 12t, 13t, and 14t are etched into the low-refractive-index layer 2, as follows: Figure 3CAs shown in the figure, the four trenches illustrated illustrate the concept of simultaneously creating trenches of different heights. In other examples, this technique can be used to form any number of trenches with any desired height combination.

[0072] Figure 3C The example shown illustrates four trenches. The first trench 11t has a first height, extending from the bottom of the trench in the low-refractive-index layer 2 to the top surface of the low-refractive-index layer 2. The second trench 12t has a second height, also extending from the bottom of the trench in the low-refractive-index layer 2 to the top surface of the low-refractive-index layer 2. The second height is greater than the first height. The third waveguide 13 has a third height, less than the first height. The fourth waveguide 14 has a fourth height, less than the third height.

[0073] The bottom of all trenches is formed of a low-refractive-index layer 2. In other embodiments, the bottom of one or more trenches may be formed of a silicon substrate 1.

[0074] An example of a suitable etching process is inductively coupled plasma reactive ion etching (RIE). Here, the additional electromagnetically induced plasma enables high plasma density and allows control over the ionization of the argon and octafluorocyclobutane gas combination. The etching depth, dependent on the trench width, can be controlled by utilizing the physical effects of RIE hysteresis. This effect depends primarily on the gas flow ratio of argon and octafluorocyclobutane. Here, argon is used to control the ionization and plasma density, as well as the level of anisotropic etching, while octafluorocyclobutane controls the degree of polymerization. In this example, the chamber pressure is low, the ICP power is in the kilowatts range, and the RF power is in the hundreds of watts range. These parameters allow etching of silicon dioxide at etching rates between 1.5 nm / s and 6 nm / s. In a specific example, for a 3000 nm wide trench, approximately 2000 nm is etched into the silicon dioxide layer, while for a 250 nm wide trench, the etching depth into the silicon dioxide layer is only 200 nm.

[0075] exist Figure 3D In this example, the trench is filled with the material that will form the waveguide. In other examples, the material is silicon. In other examples, the waveguide may be formed from silicon, germanium, or any combination of silicon nitride or oxynitride.

[0076] Silicon can be deposited or grown and can be polycrystalline, amorphous, or monocrystalline. Waveguide materials can be deposited via chemical vapor deposition (CVD), atomic layer deposition, evaporation, or sputtering.

[0077] Silicon 11s, 12s, 13s, and 14s fill the trenches, and excess silicon 7 is deposited on the trenches and on the low-refractive-index layer 2.

[0078] Then, for example, CMP is used to planarize the silicon to form the planar top surface of the photonic chip, such as... Figure 3E As shown. This produces as Figure 1 The photonic chip shown.

[0079] Optionally, waveguides 11, 12, 13, and 14 can be etched to a desired width smaller than the width of trenches 11t, 12t, 13t, and 14t, such as... Figure 3F As shown.

[0080] Waveguides can be etched to form the shape desired for the application in which the photonic chip is to be used. One or more of waveguides 11, 12, 13, and 14 can be etched to form strip, rib, or groove waveguides. Waveguides can all have the same shape or can be etched differently from each other as needed.

[0081] Figures 4A to 4F This illustrates an alternative manufacturing process for forming photonic chips, but starting with an SOI wafer. The SOI wafer has a silicon substrate 1, a low-refractive-index layer 2, and a silicon device layer 3.

[0082] like Figure 4B As shown, SiO2 layer 4 is deposited on silicon device layer 3. SiO2 layer 4 serves as a termination layer for the subsequent planarization of the waveguide. Layer 4 allows for better control over the chip's polishing height, and therefore better control over the waveguide height. In other embodiments, SiO2 may be replaced by SiN or another suitable termination material. Alternatively, the termination layer may be omitted.

[0083] Trench 11t, 12t, 13t, and 14t are etched through the SiO2 layer 4 and through the silicon device layer 3, and into the low-refractive-index layer 2, as shown. Figure 4C As shown. An example of a suitable etching process is inductively coupled plasma reactive ion etching, as described above.

[0084] The four trenches illustrated in this figure demonstrate the concept of simultaneously creating trenches of different heights in the low-refractive-index layer 2. In other examples, this technique can be used to form any number of trenches with any desired combination of heights.

[0085] Figure 4C The example shown illustrates four trenches. The first trench 11t has a first height extending from the bottom of the trench in the low-refractive-index layer 2 to the top surface of the SiO2 layer 4. The second trench 12t has a second height extending from the bottom of the trench in the low-refractive-index layer 2 to the top surface of the SiO2 layer 4. The second height is greater than the first height. The third waveguide 13 has a third height less than the first height. The fourth waveguide 14 has a fourth height less than the third height.

[0086] The bottom of all trenches is formed of a low-refractive-index layer 2. In other embodiments, the bottom of one or more trenches may be formed of a silicon device layer 3 or a silicon substrate 1.

[0087] exist Figure 4DIn this example, the trench is filled with the material that will form the waveguide. In other examples, the material is silicon. In other examples, the waveguide may be formed from silicon, germanium, or any combination of silicon nitride or oxynitride.

[0088] Silicon can be deposited or grown and can be polycrystalline, amorphous, or monocrystalline. Waveguide materials can be deposited via chemical vapor deposition (CVD), atomic layer deposition, evaporation, or sputtering.

[0089] Silicon 11s, 12s, 13s, and 14s fill the trenches, and excess silicon 7 is deposited on the trenches and on the SiO2 layer 2.

[0090] Then, for example, CMP is used to planarize the silicon to form a planar top surface of the photonic chip at the height of the top surface of the SiO24 layer, such as... Figure 4E As shown. Optionally, waveguides 11, 12, 13, and 14 can be etched to a desired width smaller than the width of trenches 11t, 12t, 13t, and 14t, as shown. Figure 4F As shown.

[0091] Waveguides can be etched to form the shape desired for the application in which the photonic chip is to be used. One or more of waveguides 11, 12, 13, and 14 can be etched to form strip, rib, or groove waveguides. Waveguides can all have the same shape or can be etched differently from each other as needed.

[0092] The process described in Figure 4 can be modified to begin with a dual-SOI wafer. A dual-SOI wafer includes a top silicon device layer, a low-refractive-index layer below the top silicon device layer, a silicon intermediate device layer below the low-refractive-index layer, another low-refractive-index layer below the intermediate device layer, and a substrate below the other low-refractive-index layer. If dual-SOI is used, etching a trench may include: etching through the top silicon device layer, through the low-refractive-index layer, through the intermediate device layer, and into the other low-refractive-index layer. The trench may be etched through the entire height of the other low-refractive-index layer, such that the bottom of the trench is formed by the surface of the substrate. The etching of the trench may pass through the top silicon device layer and into the low-refractive-index layer. The trench may be etched through the entire height of the low-refractive-index layer, such that the bottom of the trench is formed by the surface of the intermediate device layer.

[0093] Figures 5A to 5G It shows from such Figure 5A This illustrates another manufacturing process for forming photonic chips, starting with a silicon wafer. Figure 5B In this example, a low-refractive-index layer 2 has been grown or deposited on the silicon substrate 1. In this example, the low-refractive-index layer 2 is formed of SiO2.

[0094] A mask can be provided above the low-refractive-index layer 2, and the mask can be patterned to the desired layout and width of the trenches in which the waveguide will later be formed. Trenches 11t, 12t, 13t, and 14t are etched into the low-refractive-index layer 2, as follows: Figure 5C As shown in the figure, the four trenches illustrated illustrate the concept of simultaneously creating trenches of different heights. In other examples, this technique can be used to form any number of trenches with any desired height combination.

[0095] Figure 5C The example shown illustrates four trenches. The first trench 11t has a first height extending from the bottom of the trench in the low-refractive-index layer 2 to the top surface of the low-refractive-index layer 2. The second trench 12t has a second height extending from the bottom of the trench on the silicon substrate 1 to the top surface of the low-refractive-index layer 2. The second height is greater than the first height. The third waveguide 13 has a third height less than the first height. The fourth waveguide 14 has a fourth height less than the third height.

[0096] The etching of the second trench extends through the low-refractive-index layer 2, such that the bottom of the second trench 12 is formed from the top surface of the silicon substrate 1. In other embodiments, the etching may penetrate into the substrate, such that the bottom is formed below the height of the top surface of the substrate within the silicon substrate. The bottoms of other trenches are located within the low-refractive-index layer 2, but in other embodiments, one or more other trenches may have their bottoms located within the silicon substrate.

[0097] An example of a suitable etching process is inductively coupled plasma reactive ion etching, as described above.

[0098] exist Figure 5D In this example, the trench is filled with the material that will form the waveguide. In other examples, the material is silicon. In other examples, the waveguide may be formed from silicon, germanium, or any combination of silicon nitride or oxynitride.

[0099] Silicon can be deposited or grown and can be polycrystalline, amorphous, or monocrystalline. Waveguide materials can be deposited via chemical vapor deposition (CVD), atomic layer deposition, evaporation, or sputtering.

[0100] Silicon 11s, 12s, 13s, and 14s fill the trenches, and excess silicon 7 is deposited on the trenches and on the low-refractive-index layer 2. The excess silicon 7 connects the silicon 11s, 12s, 13s, and 14s deposited in each of the trenches.

[0101] The bottom of the second trench 12t is formed by the silicon substrate 1, so the silicon 12s in the second trench is in contact with the silicon substrate 1, which is monocrystalline silicon. Therefore, this allows the silicon substrate 1 to be used as a seed for the regeneration of the silicon 12s in the second trench. Furthermore, because excess silicon 7 connects the silicon 12s in the second trench to the silicon 11s, 13s, and 14s in other trenches, the silicon substrate 1 can be used as a seed to regrow silicon in all trenches to form a monocrystalline waveguide. This means that the waveguide can be regrowed even if the bottom of the waveguide is not in the substrate or another monocrystalline silicon layer. An exemplary method for regeneration is described in TF Kuech's Handbook of Crystal Growth, published in 2015. 2 See Chapter 7.1 of the book, Volume III, Part A, ThinFilms and Epitaxy: Basic Techniques.

[0102] Then, for example, CMP is used to planarize the silicon to form the planar top surface of the photonic chip, such as... Figure 5F As shown. This produces as Figure 1 The photonic chip shown.

[0103] Optionally, waveguides 11, 13, and 14 can be etched to a desired width smaller than the width of trenches 11t, 13t, and 14t, such as... Figure 5G As shown. Silicon 12s does not form an effective waveguide because light can escape into the silicon substrate due to the bottom of the silicon 12s being in contact with the substrate.

[0104] Waveguides can be etched to form the shape desired for the application in which the photonic chip is to be used. One or more of waveguides 11, 13, and 14 can be etched to form strip, rib, or groove waveguides. Waveguides can all have the same shape or can be etched differently from each other as needed.

[0105] The process described in Figure 5 can be modified to begin with etching from the SOI wafer as described in the process described in Figure 4. Regeneration can then occur from the silicon substrate or the silicon device layer.

[0106] If a dual SOI is used, the etched trench may include: etching through the top silicon device layer, through the low-refractive-index layer, through the intermediate device layer, and into another low-refractive-index layer. The trench may be etched through the entire height of the other low-refractive-index layer, such that the bottom of the trench is formed from the surface of the substrate. The etching of the trench may penetrate through the top silicon device layer and into the low-refractive-index layer. The trench may be etched through the entire height of the low-refractive-index layer, such that the bottom of the trench is formed from the surface of the intermediate device layer.

[0107] When the bottom of one of the trenches is in the silicon substrate, regrowth can originate from the silicon substrate, or from the intermediate silicon device layer, or from the top silicon device layer.

[0108] Features disclosed in the foregoing description, in the following claims, or in the accompanying drawings, as appropriate, in their specific form or according to the means for performing the disclosed functions, or the methods or processes for obtaining the disclosed results, may be used alone or in any combination of such features to enable the invention to be implemented in different forms.

[0109] While the invention has been described in conjunction with the foregoing exemplary embodiments, those skilled in the art will recognize numerous equivalent modifications and variations upon consideration of this disclosure. Therefore, the foregoing exemplary embodiments of the invention are to be regarded as illustrative rather than restrictive. Various changes may be made to the embodiments without departing from the spirit and scope of the invention.

[0110] To avoid any doubt, any theoretical explanations provided herein are offered for the purpose of enhancing the reader's understanding. The inventor does not wish to be bound by any of these theoretical explanations.

[0111] Any chapter headings used in this document are for organizational purposes only and should not be considered as limiting the subject matter.

[0112] Throughout this specification, including the appended claims, unless the context otherwise requires, the words “comprise” and “include”, and their variations (such as “comprises / comprising” and “including”), shall be understood to imply inclusion of the specified integer or step or group of integers or steps, but not to exclude any other integer or step or group of integers or steps.

[0113] It must be noted that, unless the context explicitly states otherwise, the singular forms “a,” “an,” and “the” used in the specification and appended claims include plural indicators. A range may be expressed herein as from “about” a particular value and / or to “about” another particular value. When such a range is expressed, another embodiment includes from said one particular value and / or to said other particular value. Similarly, when a value is expressed as an approximation using the antecedent “about,” said particular value will be understood to form another embodiment. The term “about” in relation to numerical values ​​is optional and means, for example, + / - 10%.

Claims

1. A method for manufacturing a photonic chip, the method comprising: A wafer is provided, the wafer comprising a substrate and a low-refractive-index layer disposed on the substrate; A first trench with a first height and a second trench with a second height are formed by etching the low refractive index layer, the second height being greater than the first height, and the second trench having a lower surface closer to the bottom surface of the substrate than the bottom surface of the first trench; a first waveguide is formed in the first trench and a second waveguide is formed in the second trench, wherein the center height of the first waveguide and the center height of the second waveguide are coplanar.

2. The method of claim 1, wherein etching comprises reactive ion etching.

3. The method according to any of the preceding claims, wherein etching the first trench and etching the second trench occur simultaneously.

4. The method according to any one of claims 1-2, wherein the width of the second groove is greater than the width of the first groove.

5. The method according to any one of claims 1-2, wherein forming the second trench comprises: The etch extends through the height of the low-refractive-index layer, and the bottom of the trench is formed by the substrate.

6. The method of claim 1, wherein the first waveguide and / or the second waveguide is formed of silicon.

7. The method of claim 6, wherein the step of forming the first waveguide and / or the second waveguide comprises: The corresponding first trench and / or second trench are filled with polycrystalline silicon, amorphous silicon or monocrystalline silicon.

8. The method of claim 6, wherein the step of forming the first waveguide and / or the second waveguide comprises: Silicon is epitaxially grown in the corresponding first trench and / or second trench.

9. The method according to any one of claims 6 to 8, wherein the step of forming the first waveguide and the second waveguide comprises: The first trench and the second trench are overfilled with silicon, such that the silicon in the first trench is bonded to the silicon in the second trench through excess silicon above the low refractive index layer; as well as The silicon in the first trench and the second trench is regrown to form monocrystalline silicon.

10. The method according to any one of claims 1 to 2, wherein the step of forming the first waveguide and / or the second waveguide comprises: Etch the material in the corresponding first trench and / or second trench to form a ribbed waveguide.

11. The method according to any one of claims 1 to 2, wherein the formation of the first waveguide and the formation of the second waveguide occur simultaneously.

12. The method according to any one of claims 1 to 2, wherein the width of the first waveguide is greater than the width of the second waveguide.

13. The method according to any one of claims 1-2, wherein the wafer is a silicon-on-insulator wafer comprising the substrate formed of silicon, the low-refractive-index layer, and the silicon device layer, and forming the first trench and the second trench further comprises: The silicon device layer is etched.

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