Optoelectronic device and method of manufacturing the same

Abstract

A method of fabricating an optoelectronic device. The fabricated device includes a photonic assembly coupled to a waveguide. The method includes: providing a device coupon including the photonic assembly; providing a silicon platform including a cavity, a bonding surface of the device coupon being within the cavity; transfer printing the device coupon onto the cavity such that the surface of the device coupon directly abuts the bonding surface and at least one channel exists between the device coupon and a sidewall of the cavity; and filling the at least one channel with a fill material via a spin-on process to form a bridge coupling the III-V semiconductor-based photonic assembly to the silicon waveguide.

Description

Technical Field

[0001] This invention relates to an optoelectronic device and a method for manufacturing the same. Background Technology

[0002] By integrating III-V semiconductor-based electro-optic devices (e.g., modulators) with silicon-on-insulator (SOI) platforms via chip bonding, there is an advantage in combining the best parts of the two material systems.

[0003] However, traditional chip bonding processes typically use flip-chip bonding, in which a III-V semiconductor-based device is inverted and bonded to a cavity on an SOI platform. Devices fabricated using these methods often suffer from high optical coupling losses between the waveguides in the III-V semiconductor-based device and the waveguides in the SOI. Furthermore, the manufacturing process suffers from low yield and relatively low reliability due to the difficulty in accurately controlling the alignment of individual waveguides.

[0004] Therefore, microtransfer printing (MTP) is being investigated as an alternative method for integrating III-V semiconductor-based devices with SOI wafers. In these methods, the III-V semiconductor-based device can be printed into a cavity on the SOI with the same orientation as it was fabricated, and the alignment between the III-V semiconductor-based waveguide and the SOI waveguide is pre-determined in the vertical direction (Z-direction). Thus, the alignment requirement is reduced from three dimensions to two dimensions, which can be more easily achieved.

[0005] However, the problem with MTP stems from the gap between the III-V semiconductor-based waveguide and the SOI waveguide surface. Although the gap width can usually be well controlled (e.g., in the range of 0.5 μm to 1.5 μm), it can lead to the following problems: (i) higher optical coupling loss between the III-V semiconductor-based waveguide and the SOI waveguide; and (ii) it leaves a gap in which particles, debris, or dirt can penetrate, thus blocking the optical path and reducing the long-term reliability of the device.

[0006] Therefore, there is a need for a method for manufacturing an optoelectronic device and a resulting optoelectronic device that can overcome the above-mentioned drawbacks. Summary of the Invention

[0007] Therefore, an embodiment of the first aspect of the present invention provides a method for manufacturing an optoelectronic device, the device comprising a photonic component coupled to a waveguide, the method comprising:

[0008] A device sample is provided, the device sample comprising a photonic component;

[0009] A platform is provided, the platform including a cavity, and the mating surface of the device sample is located within the cavity;

[0010] The device sample is transferred and printed onto the cavity, such that the surface of the device sample is directly adjacent to the bonding surface and there is at least one channel between the device sample and the sidewall of the cavity; and

[0011] At least one channel is filled with a filler material via a spin coating process to form a bridge that couples the photonic component to the waveguide.

[0012] The method uses a simple manufacturing process and is suitable for mass production. Furthermore, the resulting device exhibits a reduced level of optical loss.

[0013] The method may have any of the following optional features or any combination of the following optional features to a degree of compatibility with the following optional features.

[0014] The photonic component can be a III-V semiconductor-based photonic component, meaning it can be made of III-V materials. The waveguide can be a silicon waveguide. The platform can be a silicon platform. The waveguide can be a silicon nitride waveguide.

[0015] The photonic component can be a group II-VI or IV based photonic component, as it can be made of group II-VI or IV materials. The photonic component may include a bulk semiconductor layer, a quantum well layer, a quantum dot layer, and a quantum dash layer, or any combination thereof, all with or without a Bragg grating. The Bragg grating may be located above or below the quantum well, quantum dot, or quantum dash layer (in a direction perpendicular to the substrate).

[0016] Quantum well layers can include regular (e.g., rectangular) quantum wells or triangular quantum wells. Regular quantum wells have flat energy bands in both the conduction and valence bands of each quantum well, while triangular quantum wells have V-shaped energy bands in the conduction band of each quantum well and inverted V-shaped energy bands in the valence band of each quantum well.

[0017] The photonic component can be any of the following: an electro-absorption modulator; a laser; a photodetector; or a semiconductor optical amplifier. A device sample may include two or more photonic components and may include any combination of the photonic components listed above. For example, a device sample may include a laser and an electro-absorption modulator; a laser, an electro-absorption modulator, and a semiconductor optical amplifier; or a laser, an electro-absorption modulator, a semiconductor optical amplifier, and a photodetector. The photonic component may be configured to function as a gain chip for a laser, as a photodetector, as an electro-absorption modulator, or as a phase modulator.

[0018] The waveguide located on the platform may include a waveguide grating. The waveguide grating may be a silicon waveguide grating or a silicon nitride waveguide grating. The grating may be a Bragg grating.

[0019] The platform may include one or more passive devices coupled to the waveguide. The passive device may be one of the following: an arrayed waveguide grating; an echelle grating; a Mach-Zehnder interferometer; a multimode interferometer; a ring resonator; and a directional coupler.

[0020] The combination of photonic components and waveguides can provide distributed feedback (DFB) lasers or distributed Bragg reflector (DBR) lasers. When combining to produce a DFB laser, the photonic component can be a gain sample with a Bragg grating and coupled to any of the following types of waveguides:

[0021] Passive silicon waveguide;

[0022] Functional silicon waveguide devices coupled to passive silicon waveguides;

[0023] Passive silicon nitride (e.g., Si3N4) waveguide;

[0024] Functional silicon nitride waveguide device coupled to a passive silicon nitride waveguide;

[0025] Passive silicon nitride coupled to a silicon waveguide; and

[0026] A functional silicon nitride waveguide device coupled to a passive silicon nitride waveguide, wherein the passive silicon nitride waveguide is coupled to a passive silicon waveguide.

[0027] When combining to generate a DBR laser, the photonic component can be a gain sample and can be coupled to any of the following:

[0028] Silicon waveguide grating coupled to a passive silicon waveguide;

[0029] A silicon waveguide grating coupled to a functional silicon waveguide device, wherein the functional silicon waveguide device is coupled to a passive silicon waveguide;

[0030] Silicon nitride waveguide grating coupled to a passive silicon nitride waveguide;

[0031] A silicon nitride waveguide grating coupled to a functional silicon nitride waveguide device, wherein the functional silicon nitride waveguide device is coupled to a passive silicon nitride waveguide;

[0032] A silicon nitride waveguide grating coupled to a passive silicon nitride waveguide, wherein the passive silicon nitride waveguide is coupled to a passive silicon waveguide;

[0033] And a silicon nitride waveguide grating coupled to a functional silicon nitride waveguide device, the functional silicon nitride waveguide device being coupled to a passive silicon nitride waveguide, and the passive silicon nitride waveguide being coupled to a passive silicon waveguide.

[0034] The photonic component can be an electroabsorption modulator and coupled to any of the following:

[0035] A functional silicon waveguide device, wherein the functional silicon waveguide device is coupled to a silicon waveguide;

[0036] Passive silicon nitride waveguide;

[0037] A passive silicon nitride waveguide coupled to a passive silicon waveguide;

[0038] Functional silicon nitride waveguide devices coupled to passive silicon nitride waveguides; and

[0039] A functional silicon nitride waveguide device coupled to a passive silicon nitride waveguide, wherein the passive silicon nitride waveguide is coupled to a passive silicon waveguide.

[0040] The photonic component can be a photodetector and can be coupled to any of the following:

[0041] Passive silicon waveguide;

[0042] Functional silicon waveguide devices coupled to passive silicon waveguides;

[0043] Passive silicon nitride waveguide;

[0044] Functional silicon nitride waveguide device coupled to a passive silicon nitride waveguide;

[0045] Passive silicon nitride waveguide coupled to a passive silicon waveguide; and

[0046] A functional silicon nitride waveguide device coupled to a passive silicon nitride waveguide, wherein the passive silicon nitride waveguide is coupled to a passive silicon waveguide.

[0047] The photonic component can be a phase modulator and can be part of a silicon or silicon nitride waveguide, thus forming an arm of a Mach-Zehnder interferometer.

[0048] Passive waveguides may include straight segments, curved segments, or a combination of straight and curved segments.

[0049] A functional waveguide device may mean that the waveguide contains an active device. In some examples, the waveguide contains one or more of the following: a gain medium for a laser; a photodetector; an electroabsorption modulator; or a phase modulator.

[0050] Photonic components may include waveguides. One or more photonic components may be integrated into a waveguide. The waveguide may be a III-V semiconductor-based waveguide.

[0051] A bridge may not be a waveguide, because it may not be able to confine the optical mode within the bridge structure.

[0052] The method may include a step of curing the filler material after spin coating. For example, the filler material may be cured by UV or thermal curing.

[0053] The device sample may include a first electrode and a second electrode. Therefore, the photonic component can be tested and characterized before being bonded to a silicon platform. Consequently, the yield of this method may be higher because faulty or poorly manufactured device samples are not used (and thus the silicon platform is preserved).

[0054] Silicon waveguides can be located in the device layer of a silicon wafer on an insulator provided in the platform, and silicon waveguides can be directly adjacent to cavities.

[0055] The silicon waveguide may include a waveguide whose height gradually tapers from a first height to a second height in the direction toward the cavity, where the first height is greater than the second height. Therefore, the height of the silicon waveguide can decrease as it approaches the cavity. The resulting tapered shape can be used as a mode converter between the optical mode within a III-V semiconductor-based photonic assembly and the output waveguide of the resulting optoelectronic device.

[0056] Silicon waveguides may include a T-shaped rod end portion positioned adjacent to a cavity.

[0057] The photonic component may include a U-shaped waveguide, and the platform may include two waveguides, each coupled to a corresponding branch of the U-shaped waveguide. Therefore, the input and output waveguides of the optoelectronic device can be located on the same side of the device.

[0058] The method may include the step of lining one or more sidewalls of the cavity with an anti-reflective liner before filling the channel.

[0059] The method may include the step of providing an anti-reflective coating around one or more lateral sides of the apparatus sample prior to transfer printing. The anti-reflective coating may be used to protect the lateral sides of the apparatus sample during the transfer printing process.

[0060] The method may include the step of covering the channels with a coating layer after filling them. This isolates the filling material from moisture, thereby making the resulting device more reliable. In some embodiments, the coating layer is silica.

[0061] The method may include, after transferring and printing a device sample into a cavity, providing electrode contact pads on a silicon platform and electrically connecting them to the component. The resulting device has reduced parasitic capacitance and can therefore operate more quickly.

[0062] The method may include the step of providing an adhesive layer that forms a bonding surface for creating cavities before transferring the printing apparatus sample.

[0063] The method may include the step of annealing the apparatus sample and the silicon wafer on the insulator after transferring and printing the apparatus sample.

[0064] The photonic component may include a waveguide comprising a T-shaped end portion that, when printed into a cavity, can be positioned near the channel. The waveguide may be a III-V semiconductor-based waveguide.

[0065] The filler material can be a polymer. For example, the filler material can be benzocyclobutene. In other embodiments, the filler material is a sol-gel.

[0066] In a second aspect, embodiments of the present invention provide an optoelectronic device comprising:

[0067] A waveguide disposed in the device layer of a wafer;

[0068] A photonic component, the photonic component being located within a cavity of a wafer; and

[0069] Bridge, which optically couples the waveguide to the photonic component;

[0070] The bridges are at least partially formed from polymers.

[0071] This optoelectronic device has been found to reduce optical loss between silicon waveguides and III-V semiconductor-based photonic components.

[0072] The optoelectronic device may have any of the following optional features, or any combination of the following optional features to a degree compatible with them.

[0073] A bridge may not be a waveguide, because it may not be able to confine the optical mode within the bridge structure.

[0074] The bridge may also include one or more anti-reflective coatings. The bridge may include one anti-reflective coating located on opposite sides of the polymer. One of the anti-reflective coatings is formed of a silicon nitride layer located between a pair of silicon dioxide layers.

[0075] The bridge can be covered by a passivation layer. This isolates the bridge from moisture, thus making the resulting device more reliable. In some embodiments, the passivation layer is silicon dioxide.

[0076] The polymer can be benzocyclobutene. The polymer can be a sol-gel.

[0077] In a third aspect, embodiments of the present invention provide a method for manufacturing an apparatus sample, the method being suitable for a transfer printing process, the method comprising the following steps:

[0078] A multilayer stack, including one or more optically active layers, is grown on a substrate;

[0079] Fabricating one or more photonic components from multiple layers of stacked materials; and

[0080] One or more lateral sides of the photonic component are coated with an anti-reflective coating.

[0081] Advantageously, the anti-reflective coating is used to: (i) reduce optical loss when printing device samples onto the platform; (ii) protect photonic elements during the printing process; and (iii) enhance the long-term reliability of the device.

[0082] The optical active layer can be an optical active layer based on a III-V semiconductor. The photonic component can be a photonic component based on a III-V semiconductor.

[0083] The method may further include the step of coating one or more lateral sides of the photonic component with an anti-reflective coating.

[0084] The method may further include the step of providing a first electrode and a second electrode, the first electrode and the second electrode being electrically connected to the respective layers of the multilayer stack. Advantageously, this allows the component to be tested and characterized before being printed onto the platform.

[0085] The method may include depositing one or more tethers onto a photonic component, and removing a sacrificial layer of the component between the photonic component and the substrate.

[0086] In a fourth aspect, embodiments of the present invention provide a sample of an apparatus for a transfer printing process, comprising:

[0087] One or more photonic components; and

[0088] An anti-reflective coating is located on one or more lateral sides of the photonic component.

[0089] Advantageously, the anti-reflective coating is used to: (i) reduce optical loss when printing device samples onto the platform; (ii) protect photonic elements during the printing process; and (iii) enhance the long-term reliability of the device.

[0090] Photonic components can be photonic components based on III-V semiconductors.

[0091] The device may further include a first electrode and a second electrode electrically connected to the photonic component. Advantageously, this allows the component to be tested and characterized before being printed onto a platform. The photonic component may include a waveguide. The waveguide may be a III-V semiconductor-based waveguide.

[0092] In a fifth aspect, embodiments of the present invention provide an optoelectronic device manufactured using the method of the first aspect and including any of the optional features described therein or any combination of the optional features to the extent compatible with the optional features.

[0093] In a sixth aspect, embodiments of the invention provide a device sample manufactured using the method of the third aspect of the invention and including any of the optional features described therein or any combination of the optional features to the extent compatible with the optional features.

[0094] Another aspect of the invention provides: a computer program including code, which, when executed on a computer, causes the computer to perform the methods of the first and third aspects; a computer-readable medium storing the computer program including code, which, when executed on a computer, causes the computer to perform the methods of the first and third aspects; and a computer system programmed to perform the methods of the first and third aspects. Attached Figure Description

[0095] Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which:

[0096] Figure 1A and Figure 1B A top view and a cross-sectional view of an optoelectronic device according to an embodiment of the present invention are shown respectively;

[0097] Figure 2A and Figure 2B Top view and cross-sectional view of a variant optoelectronic device according to an embodiment of the present invention are shown respectively;

[0098] Figures 3A to 3E Top view and cross-sectional view of the III-V waveguide and SOI waveguide interface according to an embodiment of the present invention are shown respectively;

[0099] Figure 4A and Figure 4B A schematic diagram of the variant interface is shown;

[0100] Figure 5 This shows another detail of the bridge and coupling structure;

[0101] Figure 6 It is a graph of the coupling loss (dB) versus wavelength (nm) of the simulated bridge and coupling structure;

[0102] Figures 7(i) to 7(vi) Various manufacturing stages of a prototype device according to an embodiment of the present invention are shown;

[0103] Figures 8(i) to 8(v) Various manufacturing stages of a variant device prototype according to an embodiment of the present invention are shown;

[0104] Figures 9(i) to 9(v) Various manufacturing stages of a silicon platform according to an embodiment of the present invention are illustrated;

[0105] Figures 10(i) to 10(viii)Various manufacturing stages of the optoelectronic device according to embodiments of the present invention are shown;

[0106] Figures 11(i) to 11(v) Various manufacturing stages of the optoelectronic device according to embodiments of the present invention are shown;

[0107] Figure 12 A cross-sectional view of two optoelectronic devices on a single silicon platform according to an embodiment of the present invention is shown;

[0108] Figure 13 A cross-sectional view of three optoelectronic devices on a single silicon platform according to an embodiment of the present invention is shown;

[0109] Figure 14 A cross-sectional view of a variant optoelectronic device according to an embodiment of the present invention is shown;

[0110] Figure 15 A cross-sectional view of a variant optoelectronic device according to an embodiment of the present invention is shown;

[0111] Figure 16 A cross-sectional view of a variant optoelectronic device according to an embodiment of the present invention is shown;

[0112] Figure 17 A cross-sectional view of a variant optoelectronic device according to an embodiment of the present invention is shown;

[0113] Figure 18 A cross-sectional view of a variant optoelectronic device according to an embodiment of the present invention is shown; and

[0114] Figure 19 A cross-sectional view of a variant optoelectronic device according to an embodiment of the present invention is shown. Detailed Implementation

[0115] Various aspects and embodiments of the invention will now be discussed with reference to the accompanying drawings. Other aspects and embodiments will be apparent to those skilled in the art.

[0116] Figure 1A and Figure 1B A top view and a cross-sectional view of an optoelectronic device according to an embodiment of the present invention are shown respectively. Figure 1AAs can be seen, the optoelectronic device 100 broadly includes a silicon platform 101, which contains silicon waveguides 103a and 103b. The silicon waveguides serve as the input and output waveguides of the device. Each silicon waveguide is coupled at a respective interface 104 to a III-V semiconductor-based waveguide 102, which is located within a III-V device sample 106. The sample has been bonded to the silicon platform. In this example, the III-V semiconductor-based waveguide 102 is U-shaped and therefore allows connection to the silicon waveguides 103a and 103b on the same side of the device sample 106.

[0117] The device sample 106 also includes a first electrical contact pad or electrode 105a and a second electrical contact pad or electrode 105b. The electrical contact pads are connected to different layers of the III-V semiconductor-based device 110 in the III-V semiconductor-based waveguide and, in use, are connected to a driver operating the device. This operation can be performed at RF frequencies.

[0118] Figure 1B It is along Figure 1A The diagram shows a cross-sectional view of device 100 taken by line ABC. The cross-sectional view shows device 110 based on a III-V semiconductor in more detail, and also shows, for clarity, [the view is shown from...]. Figure 1A The cladding layer 114 is omitted. In this example, the cladding layer is formed of silicon dioxide (SiO2). The cross-sectional structure of the silicon platform 101 is shown in more detail: the silicon substrate 117 is partially covered by a buried oxide layer 116, on top of which are silicon waveguides 103a and 103b.

[0119] Multiple layers forming the III-V semiconductor-based device 110 can also be seen, the details of which will be discussed in detail with reference to FIG. 7(i). The properties of interface 104 are also shown in more detail and include: anti-reflective coatings 111 and 306 and bridging filler 112. The anti-reflective coatings are disposed on the device sample 106 and the silicon platform 101. The spaces between the anti-reflective coatings are filled by bridging filler 112 formed of polymer. Further details related to interface 104 are provided in [the following sections / sections]. Figure 3B , Figure 4A , Figure 4B and Figure 5 The diagrams are shown and discussed in conjunction with these figures.

[0120] An anti-reflective coating 111 on the silicon platform 101 enhances the coupling from the III-V semiconductor-based waveguide 102 to the 1800 nm segment 113 of the silicon waveguide 103a. This 1800 nm segment tapers to a 3000 nm segment 115 for transmission with device 100. Then, in the example where silicon waveguide 103a is the input waveguide, the optical signal is received in the 3000 nm segment 115 and converted to a mode confined within the 1800 nm segment 113 before transmission to the III-V semiconductor-based waveguide 104.

[0121] like Figure 1B As can be seen, a gap exists between the silicon platform and the device sample already filled with bridging filler 112 (benzocyclobutene (BCB) in this example). The thickness of the gap varies as a function of its position along the periphery of the device sample 106. At locations far from interface 104, the gap can be as wide as 20 μm, such as... Figure 1B As shown in the diagram. However, at locations near and including interface 104, the gap can be as narrow as (or narrower than) 1 μm. In this example, the height x from the bottommost portion of the bridge filler 112 to the bottommost portion of the buried oxide layer is approximately 810 nm (the height of the buried oxide layer is approximately 400 nm). In the case where the buried oxide layer has a height of approximately 1 μm, the height x can be approximately 210 nm.

[0122] Figure 2A and Figure 2B A top view and a cross-sectional view of a variant optoelectronic device 200 according to an embodiment of the present invention are shown, respectively. Where this embodiment shares features with the device 100 described above, the same features are indicated by the same reference numerals. Figure 2A and Figure 2B The main difference between device 200 and the previous device is that contact pads 201a and 201b extend across device sample 206 to silicon platform 202. This has the advantage of lower parasitic capacitance during use and thus increases device speed.

[0123] Figures 3A to 3E Top and cross-sectional views of the III-V waveguide and SOI waveguide interfaces according to embodiments of the present invention are shown respectively. Although Figure 3A The example shown in the (top view) is device 100, but the interface shown has the same structure when implemented in device 200. Figure 3B It is a cross-sectional view taken along line A-A'. Figure 3C It is a cross-sectional view taken along line B-B'. Figure 3D It is a cross-sectional view taken along line C-C'; and Figure 3E It is a cross-sectional view taken along line D-D'.

[0124] exist Figure 3B In this embodiment, light is guided from the 1.8 μm silicon waveguide 113 into the III-V semiconductor waveguide 102 along the 'x' direction, or vice versa. As can be seen, the gap between the III-V semiconductor waveguide 102 and the 1.8 μm silicon waveguide has the following structure in the layers along the 'x' direction: a 20 nm silicon dioxide layer 302; a 180 nm anti-reflective silicon nitride (Si3N4) layer 111; a 100 nm silicon dioxide layer 304; a BCB filler 305; and a 180 nm anti-reflective silicon nitride (Si3N4) layer 306. The 20 nm silicon dioxide layer 302 has a refractive index of approximately 1.45. The silicon nitride layer 111 has a refractive index of approximately 1.995, while the 100 nm silicon dioxide layer 304 has a refractive index of approximately 1.45. The 180 nm Si3N4 layer 306 has a refractive index of approximately 2.28, and in this embodiment, its composition differs slightly from that of the Si3N4 layer 111. However, the refractive indices of Si3N4 layers 111 and 306 can be the same, either 1.995 or 2.28, with only slight adjustments to their thicknesses. The width of the entire gap is approximately 1 μm. The total thickness of the antireflective coating formed by layers 302, 111, 304, and 306 is approximately 480 nm. The refractive index of the BCB filler is approximately 1.56. All these refractive indices are referenced for light with a wavelength of approximately 1310 nm.

[0125] It has been found that combining these layers in this manner improves the coupling efficiency from the III-V semiconductor waveguide 102 to the 1.8 μm silicon waveguide 113.

[0126] This view also shows a silicon substrate portion 307, which extends upwards into the cavity containing the device sample. This portion has a height of approximately 810 nm. An optically active layer 301 of a waveguide 102 based on a III-V semiconductor, which in this example is a multiple quantum well, can also be seen.

[0127] Figure 3C It is along Figure 3A The cross-sectional view taken along line B-B' shows the structure of the III-V semiconductor-based waveguide 102 in more detail. Broadly speaking, the waveguide includes a waveguide plate or base 102b and ridges or ribs 102 extending therefrom. An optically active layer 301 is located between the plate and the ribs or forms part of the ribs. In this example, the plate height is approximately 1.74 μm, while the rib height is approximately 3.956 μm. The rib width is approximately 2.5 μm.

[0128] Figure 3D It is along Figure 3A The image shows a cross-sectional view taken along line C-C'. The structure of the 1.8 μm silicon waveguide 113 can be seen in more detail. Broadly speaking, the waveguide comprises a plate or base and ridges or ribs. The plate has a height of approximately 200 nm, while the ribs have a height of approximately 1.8 μm and a width of approximately 2.6 μm. Figure 3E It is along Figure 3A A cross-sectional view taken along line D-D' is shown. The structure of the 3μm silicon waveguide 115 can be seen in more detail. Broadly speaking, the waveguide includes a plate or base and ridges or ribs. The plate has a height of approximately 1.8μm, while the ribs have a height of approximately 3μm and a width of approximately 2.6μm. In this document, the height of the feature is typically measured from the uppermost surface of the buried oxide layer 116 to the uppermost surface of the feature. The heights of the ribs and plates in the 1.8μm waveguide 113 gradually taper to the height in the 3μm waveguide, such that the tapered region serves as a mode converter between the 1.8μm and 3μm waveguides.

[0129] Figure 4A and Figure 4B A schematic diagram and top view of the variant interface are shown. Figure 4A The example shown is, Figure 1A and Figure 2A In the interface implemented in the diagram, the interface between the III-V semiconductor-based waveguide 102 and the silicon waveguide 103a / b forms an angle α with respect to the guiding direction (AB, or vice versa). The angle α is typically a value between 1° and 10°, including both 1° and 10°. Figure 4A The diagram also shows the 'T' geometry of the interfaces. In a III-V semiconductor waveguide, the T-shaped 'strip,' extending at angle α, has a width of approximately 2 μm. In a silicon waveguide, the T-shaped 'strip,' also extending at angle α, has a width of approximately 1 μm. The gap between the individual T-interfaces is approximately 1 μm.

[0130] Figure 4B It can be replaced Figure 4A The interface shown is a top view of a variant interface. Although its geometry is still 'T' shaped, in... Figure 4B In the example shown, the T-shaped strip is not at an angle relative to the guide direction (AB). Figure 5 This shows another detail of the interface and coupling structure. Figure 5 This is a 3D perspective view of the interface between waveguide 102, which is based on III-V semiconductor, and silicon waveguides 103a / b.

[0131] Figure 6 This is a graph showing the coupling loss (dB) of the simulated bridge and coupling structure versus wavelength (nm). Notably, the graph shows that the optical coupling loss in the O-band (approximately 1260 nm to approximately 1360 nm) is between 1.22 and 1.32 dB.

[0132] Figures 7(i) to 7(vi) Various manufacturing stages of a device prototype according to an embodiment of the present invention are shown. In the step shown in FIG7(i), a stack based on III-V semiconductors is provided. In the example shown, the stack comprises the following layers (from top to bottom):

[0133] 701-P doped InGaAs layer;

[0134] 702-P doped InP layer;

[0135] 301-Multiple quantum well layers;

[0136] 703-N doped InP layer;

[0137] 704 - Undoped InP layer;

[0138] 705 - Sacrificial Layer; and

[0139] 706-InP substrate.

[0140] In another example, the stack has the following layers:

[0141]

[0142]

[0143] Table 1

[0144] Layer 4 forms the bottom surface layer of the device sample after separation from the InP substrate, and layers 3 and 2 are sacrificial layers for releasing the sample from the substrate.

[0145] These layers can be provided, for example, by molecular beam epitaxy or chemical vapor deposition. Once provided, a III-V electroabsorption modulator (EAM) structure can be fabricated using standard manufacturing processes, such as etching, deposition, and masking. This result is illustrated in Figure 7(ii). The structure includes the previously discussed III-V semiconductor-based device 110. Its upper layer is electrically connected to a first electrical contact pad 105a, and its lower layer (N-InP layer) is electrically connected to a second electrical contact pad 105b.

[0146] It is also worth noting that an anti-reflective coating (ARC) formed by SiO2 layer 303, Si3N4 layer 111, and second SiO2 layer 304 is formed as part of the device sample fabrication. The ARC is then also used as a surface protection coating for the sacrificial release layer etching process discussed below. The structure includes, for example, BCB filler 801 between the III-V semiconductor-based device 110 and peripheral components. The use of BCB utilizes its relatively low dielectric constant, which reduces parasitic capacitance and thus provides higher operating speeds.

[0147] Next, in the step shown in Figure 7(iii), a dry etching process is performed to remove the portion of the sacrificial layer 705 with its exposed upper surface. That is, as shown in Figure 7(iii), the portion of the sacrificial layer extending laterally beyond the ARC is removed. This step 'releases' the multilayer stack as it is ready for subsequent processing. The upper surface of the InP substrate is thus exposed, as are the lateral sides of the sacrificial layer 705. Subsequently, in the step shown in Figure 7(iv), photoetchant tethers (PR) 707 are applied to the exterior of the device sample, at least partially covering the sample sidewalls, the ARC, and the upper surface. Notably, the lateral sides of the sacrificial layer 705 remain exposed (as a result of partially covering the sample sidewalls and the ARC).

[0148] Subsequently, in the step shown in Figure 7(v), a wet etching process is initiated to begin removing the sacrificial layer 705. Etching is performed in the indicated direction, i.e., laterally from its periphery toward the center of the sample. Upon completion of the wet etching process, the structure shown in Figure 7(vi) is produced. The sample 106 is suspended above the InP substrate 704 by photoresist 707, with the lowermost surface of the undoped InP layer 704 facing the uppermost surface of the substrate. The device sample is then ready for transfer printing.

[0149] Figures 8(i) to 8(v) Various manufacturing stages of a variant device prototype according to an embodiment of the present invention are shown. Figures 8(i) to 8(v) The method shown begins after the steps shown in Figure 7(i); that is, providing a multilayer epitaxial stack formed from III-V semiconductor layers. In the steps whose results are shown in Figure 8(i), standard fabrication processes (e.g., etching, deposition, and masking) can be provided for a variant III-V electroabsorption modulator (EAM) structure. The structure in Figure 8(i) differs from the structure in Figure 7(ii) in that electrode traces 805a and 805b are provided, which will be electrically connected to contact pads that extend at least partially to the silicon platform (as previously discussed). Figure 2A and Figure 2B (Discussion).

[0150] Following the steps shown in Figure 8(i), a dry etching process is performed to remove the portion of the sacrificial layer 705 with its exposed upper surface. This result is shown in Figure 8(ii). The upper surface of the InP substrate 706 is thus exposed, as are the lateral sides of the sacrificial layer 705. Subsequently, in the steps shown in Figure 8(iii), photoetchant tethers 707 are applied to the exterior of the device sample, at least partially covering the ARC and the upper surface. Notably, the lateral sides of the sacrificial layer 705 remain exposed (resulting in partial coverage).

[0151] Following this step, in the step shown in Figure 8(iv), a wet etching process is initiated to begin removing the sacrificial layer 705. Etching is performed in the indicated direction, i.e., laterally from its periphery toward the center of the sample. Upon completion of the wet etching process, the structure shown in Figure 8(v) is produced. The sample 206 is suspended above the InP substrate 704 by photoresist 707, with the lowermost surface of the undoped InP layer 704 facing the uppermost surface of the substrate. The sample is then ready for transfer printing.

[0152] Figures 9(i) to 9(v) Various manufacturing stages of a silicon platform according to an embodiment of the invention are shown. In the first step shown in FIG9(i), a silicon-on-insulator wafer is provided. A silicon device layer 901, approximately 3000 nm or 3 μm high, is situated above a 400 nm buried oxide (e.g., SiO2) layer 116. The buried oxide layer is situated above a silicon substrate 117.

[0153] Next, in the step shown in Figure 9(ii), the first cavity 902 is etched into the silicon device layer. Part of this step includes the deposition of an overlay layer 114 (here formed of silicon dioxide). The first cavity is etched such that an 1800 nm portion of the silicon device layer remains above the buried oxide layer. This etching also provides the previously discussed 3 μm to 1800 μm waveguide cone, which serves as a mode converter for light passing through the cone.

[0154] After the cone has been provided, a second etching is performed to form a second cavity 903. This second cavity extends through the buried oxide layer and partially into the silicon substrate. The precise depth of the etching is chosen such that the optical mode supported by the 1800 nm silicon waveguide 113 is generally aligned with the optical mode supported by the III-V semiconductor-based waveguide 102 (when present in the cavity 903). The surface roughness (e.g., R0) of the bed of the second cavity is measured using an atomic force microscope. a R z Or R MAX Preferably at the sub-nanometer level. The measurement area is typically approximately 10 μm x 10 μm.

[0155] Next, in the step shown in Figure 9(iv), a 180 nm Si3N4 anti-reflective coating is provided on one or more sidewalls of cavity 903. The silicon platform is then ready for microtransfer printing. Figure 9(v) shows an optional additional step in which an adhesive layer 904 (e.g., BCB) is spin-coated onto the silicon platform. The thickness of the adhesive layer is between 30 nm and 100 nm.

[0156] Figures 10(i) to 10(viii)Various manufacturing stages of the optoelectronic device according to an embodiment of the present invention are illustrated. In the first step shown in FIG10(i), a mold (in some examples, an elastomeric mold) is used to pick up the device sample 106 by attaching it to a photoresist tether 707. In a first movement indicated by the left-hand arrow in FIG10(i), the mold and the device sample 106 are lifted and moved away from the InP substrate 706, thereby breaking the tether. Subsequently, the mold and the device sample are moved laterally toward the silicon platform.

[0157] Next, in the steps shown in FIG10(ii), device sample 106 is deposited into the second cavity 903 previously formed in the silicon platform. This deposition step includes aligning the III-V semiconductor-based waveguide 102 within device sample 106 with the 1800 nm silicon waveguide. Once deposited, the lowermost surface of the undoped InP layer 704 is directly adjacent to the upper surface of the silicon substrate layer 117 (except in the example using adhesive 904, in which case the adhesive would be located between the undoped InP layer and the silicon substrate).

[0158] Subsequently, in the step shown in Figure 10(iii), the mold is released and the device sample 106 remains within the cavity 903. After the mold has been released, the photoresist 707 is removed using a dry etching process. The combination of the device sample 106 and the silicon platform is then annealed at a temperature between 280°C and 300°C (inclusive) for at least 1 hour and no more than 15 hours. The results of this process are shown in Figure 10(iv). It is also noteworthy that in Figure 10(iv) is channel 906, which surrounds the periphery of the device sample 106 between the device sample and the sidewalls of the cavity 903. Channel 906 thus defines the boundary around the device sample 106.

[0159] Following the annealing step, the sample 106 was then spin-coated using a combination of polymer 907 (benzocyclobutene in this example) and a silicon platform, and thermally cured at approximately 280°C for approximately 60 minutes in a nitrogen atmosphere (N2). The results of this spin-coating step are shown in Figure 10(v). Notably, the spin-coated BCB 907 filled channel 906 and provided the previously discussed bridging filler 305.

[0160] After the thermosetting process is completed, polymer 907 is etched back in a dry etching step (using gases such as O2, CF4, or SF6), exposing the upper surfaces of contact pads 105a and 105b and the overlay layer 114. This result is shown in Figure 10(vi). Alternatively, photosensitive BCB can be used to fill channel 906. In this case, the photosensitive BCB functions similarly to a negative photoresist. The upper surfaces of contact pads 105a and 105b can be exposed after BCB spin-coating, UV exposure, and development, followed by a thermosetting process. Subsequently, an additional overlay layer 114 is added as shown in Figure 10(vii) to isolate the bridging filler 305 from moisture. In some examples, this overlay layer, formed of SiO2, has a thickness of approximately 500 nm. Finally, in the step shown in Figure 10(viii), vias are opened in the overlay layer above contact pads 105a and 105b for wire bonding.

[0161] Figures 11(i) to 11(v) Various manufacturing stages of a variant optoelectronic device according to an embodiment of the present invention are illustrated. (Using information...) Figures 8(i) to 8(v) The apparatus under discussion was repeated in sample 206. Figures 10(i) to 10(v) The steps are shown in Figure 11(i). The result is a device sample 206 bonded to a silicon substrate on a silicon platform. The spin-coated polymer 907 refills the channel 906, and the device has been thermally cured in a nitrogen atmosphere (N2) at approximately 280°C for about 60 minutes.

[0162] Next, as shown in Figure 11(ii), an etching and / or planarization process is performed to expose the upper surfaces of the wire traces 805b and 805a. Alternatively, a photosensitive BCB can be used to fill channel 906. In this case, the photosensitive BCB functions similarly to a negative photoresist. The upper surfaces of contact pads 105a and 105b can be exposed after BCB spin coating, UV exposure, and development, followed by a thermal curing process. After this, an additional cladding layer is deposited to provide a 500 nm thick SiO2 cladding layer 114, as shown in Figure 11(iii). Following this deposition, vias are opened in the cladding layer 114 above traces 805a and 805b. This result is shown in Figure 11(iv). This allows a metallization process to provide contact pads 201a and 201b, which extend at least partially above the silicon platform. The device is then ready for wire bonding and operation.

[0163] Figure 12A cross-sectional view of two optoelectronic devices on a single silicon platform according to an embodiment of the present invention is shown. In this example, three cavities are formed: a first cavity that at least partially defines an 1800 nm silicon waveguide; a second cavity in which a III-V semiconductor-based electroabsorption modulator 1201 has been printed; and a third cavity adjacent to a 3000 nm silicon waveguide 115 in which a III-V semiconductor-based laser 1202 has been deposited. The III-V semiconductor-based electroabsorption modulator 1201 is optically coupled to the first and second 1800 nm silicon waveguides 113. In use, the laser 1202 generates an optical signal coupled to the 3000 nm silicon waveguide 115, and a cone in or between the 3000 nm and 1800 nm silicon waveguides converts the optical mode into an optical mode that can be coupled to the EAM 1201. The EAM 1201 provides a modulation profile to the signal, which is then coupled to the 1800 nm silicon waveguide 113 for further transmission.

[0164] Figure 13 A cross-sectional view of three optoelectronic devices on a single silicon platform according to an embodiment of the present invention is shown. Figure 13 The layout and Figure 12 The difference in the arrangement is that it also includes a semiconductor optical amplifier SOA 1203 located in a fourth cavity. The SOA is configured to receive signals from the EAM via an 1800nm ​​silicon waveguide 113 and amplify the signals before coupling them to the output waveguide 1301.

[0165] Figure 14 A cross-sectional view of a variant optoelectronic device according to an embodiment of the invention is shown. A photonic component 1400 of the type previously discussed has been incorporated into a cavity bed formed in a silicon substrate (Si-sub) of a silicon platform. The silicon platform includes a silicon nitride (Si3N4) waveguide 1402, in which a Bragg grating 1404 is formed. The silicon nitride waveguide 1402 is coupled to the photonic component and a silicon waveguide 1408 formed in a silicon-on-insulator layer. An antireflective coating 1406 is located between the silicon nitride waveguide 1402 and the silicon waveguide 1408. Antireflective coatings 111 and 306, and a bridge filler 112 are located between the photonic component 1400 and the silicon nitride waveguide 1402.

[0166] Figure 15 A cross-sectional view of a variant optoelectronic device according to an embodiment of the present invention is shown. It is related to... Figure 14 The difference in the embodiment shown is that no silicon waveguide is formed in the silicon device layer. Instead, the photonic component is coupled only to the silicon nitride waveguide 1402. Figure 16 A cross-sectional view is shown of a variant of an embodiment according to the present invention. It is related to... Figure 14 The difference in the embodiment shown is that the silicon nitride waveguide 1402 does not contain a Bragg grating. Figure 17A variant optoelectronic device according to an embodiment of the present invention is shown. It is related to… Figure 14 The difference in the embodiment shown is that it does not include a silicon waveguide formed in the silicon device layer, and it does not include a Bragg grating in the silicon nitride waveguide 1402.

[0167] Figure 18 A cross-sectional view of a variant optoelectronic device according to an embodiment of the invention is shown. A photonic component 1400 of the type previously discussed has been incorporated into a cavity bed formed in a silicon substrate SI-sub of a silicon platform. The silicon platform includes a silicon waveguide 1408 formed in a silicon-on-insulator layer, and the silicon waveguide 1408 includes a Bragg grating 1808. The silicon waveguide is coupled to the photonic component via antireflective coatings 111 and 306 and a bridge filler 112. Figure 19 A schematic diagram of a variant optoelectronic device according to an embodiment of the present invention is shown. It is related to... Figure 18 The difference in the embodiment shown is that the silicon waveguide 1408 does not contain a Bragg grating.

[0168] While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when this disclosure is given. Therefore, the exemplary embodiments of the invention set forth above should be considered illustrative rather than restrictive. Various changes may be made to the described embodiments without departing from the spirit and scope of the invention.

[0169] Feature list

[0170] 101, 202 Silicon Platform 1201 EAM

[0171] 102 Waveguide based on III-V semiconductor 1202 Laser

[0172] 103a / b Silicon Waveguide 1203 SOA

[0173] 104 Waveguide Interface 1301 Output Waveguide

[0174] 105a / b Contact Pad 1400 Photonic Component

[0175] 106,206 III-V device sample 1402 SiN3 waveguide

[0176] 110 Photonic Components Based on III-V Semiconductors

[0177] 111 Anti-reflective coating 1404 SiN grating

[0178] 112 Bridge filler 1408 SOI waveguide

[0179] 113 1800nm ​​silicon waveguide section 1808 Si grating

[0180] 114 Coating Layer

[0181] 115 3000nm silicon waveguide section

[0182] 116 Buried oxide layer

[0183] 117 Silicon substrate

[0184] 201a / b contact pads

[0185] 301 Multiple Quantum Well (QMW) Layer

[0186] 302 First silica lining

[0187] 304 Second Silica Liner

[0188] 305 BCB bridge filler

[0189] 306 Secondary Silica Liner

[0190] 307 Silicon Substrate Section

[0191] 102a III-V waveguide ridge

[0192] 102b III-V waveguide plate

[0193] 701–706 III-V semiconductor layer

[0194] 707 Photoresist Tie

[0195] 801 BCB filler

[0196] 805a / b electrode traces

[0197] 901 Silicon-on-Insulator / Device Layer

[0198] 902 First Cavity

[0199] 903 Combined cavity

[0200] 904 adhesive

[0201] 905 Imprint (elastomer)

[0202] 907 Spin-coated BCB

Claims

1. An optoelectronic device, the optoelectronic device comprising: A wafer, the wafer including a substrate, a buried oxide (BOX) layer on the substrate and a silicon device layer on the BOX layer, the wafer having a cavity extending through the silicon device layer such that the silicon device layer surrounds the periphery of the cavity; Waveguide, the waveguide being disposed in the silicon device layer; A photonic component, the photonic component being located within the cavity of the wafer; as well as A bridge that optically couples the waveguide to the photonic component; The bridge is at least partially formed of a polymer.

2. The optoelectronic device of claim 1, wherein the bridge also includes one or more anti-reflective coatings.

3. The optoelectronic device of claim 2, wherein the bridge comprises an anti-reflective coating located on opposite sides of the polymer.

4. The optoelectronic device of claim 3, wherein one of the antireflective coatings is formed of a silicon nitride layer located between a pair of silicon dioxide layers.

5. A method of manufacturing an optoelectronic device, the device comprising a photonic component coupled to a waveguide, the method comprising: A device sample is provided, the device sample including the photonic component; A platform is provided, the platform including a wafer, the wafer including a substrate, a buried oxide (BOX) layer on the substrate and a silicon device layer on the BOX layer, the wafer having a cavity extending through the silicon device layer such that the silicon device layer surrounds the periphery of the cavity, and a bonding surface of the device sample is within the cavity; The device sample is transferred and printed onto the cavity, such that the surface of the device sample is directly adjacent to the bonding surface and there is at least one channel between the device sample and the sidewall of the cavity. as well as The at least one channel is filled with a filler material via a spin coating process to form a bridge that couples the photonic component to the waveguide.

6. The method of claim 5, further comprising the step of curing the filler material after spin-coating.

7. The method of claim 5, wherein the device sample comprises first and second electrodes.

8. The method of claim 5, wherein the wafer is a silicon-on-insulator wafer, and the silicon waveguide is in the silicon device layer, the silicon waveguide being directly adjacent to the cavity.

9. The method of claim 8, wherein the silicon waveguide comprises a waveguide that tapers in height from a first height to a second height in a direction toward the cavity, the first height being greater than the second height.

10. The method of claim 8, wherein the silicon waveguide includes a T-shaped rod end portion positioned adjacent to the cavity.

11. The method of claim 8, wherein the silicon waveguide comprises a Bragg grating.

12. The method of claim 5, wherein the platform has a silicon nitride waveguide.

13. The method of claim 12, wherein the silicon nitride waveguide comprises a Bragg grating.

14. The method of claim 5, wherein the photonic component is made of a III-V material.

15. The method of claim 5, wherein the photonic component is made of a II-VI material.

16. The method of claim 5, wherein the photonic component is made of a group IV material.

17. The method of claim 5, wherein the photonic component comprises a regular quantum well.

18. The method of claim 5, wherein the photonic component comprises a triangular quantum well.

19. The method of claim 5, wherein the photonic component is a photodetector.

20. The method of claim 5, wherein the photonic component is an electroabsorption modulator (EAM) utilizing the quantum confined Stark effect (QCSE).

21. The method of claim 5, wherein the photonic component is an electroabsorption modulator (EAM) utilizing the Franz-Keldysh (FK) effect.

22. The method of claim 5, wherein the photonic component comprises a U-shaped waveguide, and the platform comprises two waveguides, each waveguide being coupled to a corresponding branch of the U-shaped waveguide.

23. The method of claim 5, further comprising the step of lining one or more sidewalls of the cavity with an anti-reflective liner before filling the channel.

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