Semiconductor optical device and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor optical device and a manufacturing method thereof. The semiconductor optical device includes a substrate including silicon and having a platform, a waveguide, and a diffraction grating in regions each different when viewed from above; and a semiconductor element bonded on the diffraction grating and the platform, the semiconductor element being in contact with an upper surface of the substrate, formed of a group III-V compound semiconductor, and having optical gain, the waveguide being optically coupled with the diffraction grating in an extension direction of the waveguide, the platform being located on both sides of the waveguide and the diffraction grating in a direction crossing the extension direction of the waveguide, the substrate having a groove between the platform and the waveguide, and the diffraction grating being continuous with the platform in the direction crossing the extension direction of the waveguide.

Description

Technical Field

[0001] This disclosure relates to semiconductor optical elements and methods for manufacturing the same. Background Technology

[0002] Techniques are known for bonding semiconductor elements formed of compound semiconductors and having optical gain to substrates such as SOI (Silicon On Insulator) substrates (silicon photonics) that form waveguide paths (e.g., non-patent literature 1).

[0003] Existing technical documents

[0004] Non-patent literature

[0005] Non-patent literature 1: Amin Abbasi et al. "43Gb / s NRZ-OOK Direct Modulation ofaHeterogeneously Integrated InP / Si DFB Laser" JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL.35, NO.6.MARCH 15, 2017 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] By forming waveguides and diffraction gratings on a substrate, semiconductor elements with optical gain are bonded to the diffraction grating, thereby forming a distributed feedback (DFB) laser element.

[0008] If an interlayer such as resin is provided between the substrate and the semiconductor device, the thermal resistance increases. Temperature rises easily with operation, leading to performance degradation. On the other hand, if the substrate and semiconductor device are directly bonded without an interlayer, the contact area between the substrate and semiconductor device decreases due to the presence of grooves in the substrate, resulting in reduced bonding strength. Furthermore, the thermal resistance increases because the grooves in the substrate are filled with air. Therefore, the object of this disclosure is to provide a semiconductor optical device and a method for manufacturing the same that can reduce thermal resistance and improve bonding strength.

[0009] Methods for solving problems

[0010] The semiconductor optical element disclosed herein comprises: a substrate containing silicon and having a platform, a waveguide, and a diffraction grating in different regions when viewed from above; and a semiconductor element bonded to the diffraction grating and the platform, the semiconductor element being in contact with the upper surface of the substrate, formed of a III-V compound semiconductor and having optical gain, the waveguide being optically coupled to the diffraction grating in the direction of extension of the waveguide, the platform being located on both sides of the waveguide and the diffraction grating in a direction intersecting the direction of extension of the waveguide, the substrate having a groove between the platform and the waveguide, and the diffraction grating being continuous with the platform in a direction intersecting the direction of extension of the waveguide.

[0011] The method for manufacturing a semiconductor optical element disclosed herein includes: a preparation step of preparing a substrate comprising silicon and having a platform, a waveguide, and a diffraction grating formed in different regions when viewed from above; and a bonding step of bonding a semiconductor element formed of a III-V compound semiconductor and having optical gain onto the diffraction grating and the platform in the substrate, wherein in the bonding step, the semiconductor element is in contact with the upper surface of the substrate, the waveguide is optically coupled to the diffraction grating in the direction of extension of the waveguide, the platform is located on both sides of the waveguide and the diffraction grating in a direction intersecting the direction of extension of the waveguide, the substrate has a groove between the platform and the waveguide, and the diffraction grating is continuous with the platform in a direction intersecting the direction of extension of the waveguide.

[0012] Invention Effects

[0013] According to this disclosure, it is possible to reduce thermal resistance and increase bonding strength. Attached Figure Description

[0014] Figure 1A This is a top view illustrating an example of a semiconductor optical element involved in the implementation method.

[0015] Figure 1B It is along Figure 1A A sectional view of line AA.

[0016] Figure 1C It is along Figure 1A A sectional view of line BB.

[0017] Figure 1D It is along Figure 1A A sectional view of line CC.

[0018] Figure 1E It is along Figure 1A A sectional view of line DD.

[0019] Figure 2This is a top view illustrating the substrate.

[0020] Figure 3A This is a diagram illustrating the intensity of light.

[0021] Figure 3B This is a diagram illustrating the intensity of light.

[0022] Figure 4A This is a diagram illustrating the intensity of light.

[0023] Figure 4B This is a diagram illustrating the intensity of light.

[0024] Figure 5 This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0025] Figure 6A This is a top view illustrating an example of a method for manufacturing semiconductor optical elements.

[0026] Figure 6B It is along Figure 6A A sectional view of line AA.

[0027] Figure 6C It is along Figure 6A A sectional view of line BB.

[0028] Figure 6D It is along Figure 6A A sectional view of line CC.

[0029] Figure 6E It is along Figure 6A A sectional view of line DD.

[0030] Figure 7A This is a top view illustrating an example of a method for manufacturing semiconductor optical elements.

[0031] Figure 7B It is along Figure 7A A sectional view of line AA.

[0032] Figure 7C It is along Figure 7A A sectional view of line BB.

[0033] Figure 7D It is along Figure 7A A sectional view of line CC.

[0034] Figure 7E It is along Figure 7A A sectional view of line DD.

[0035] Figure 8A This is a top view illustrating an example of a method for manufacturing semiconductor optical elements.

[0036] Figure 8B It is along Figure 8A A sectional view of line AA.

[0037] Figure 8C It is along Figure 8A A sectional view of line BB.

[0038] Figure 8D It is along Figure 8A A sectional view of line CC.

[0039] Figure 8E It is along Figure 8A A sectional view of line DD.

[0040] Figure 9A This is a top view illustrating an example of a method for manufacturing semiconductor optical elements.

[0041] Figure 9B It is along Figure 9A A sectional view of line AA.

[0042] Figure 9C It is along Figure 9A A sectional view of line BB.

[0043] Figure 9D It is along Figure 9A A sectional view of line CC.

[0044] Figure 9E It is along Figure 9A A sectional view of line DD.

[0045] Figure 10A This is a top view illustrating the semiconductor optical element involved in the comparative example.

[0046] Figure 10B It is along Figure 10A A sectional view of line AA.

[0047] Figure 10C It is along Figure 10A A sectional view of line BB.

[0048] Figure 10D It is along Figure 10A A sectional view of line CC.

[0049] Figure 10E It is along Figure 10A A sectional view of line DD.

[0050] Figure 11 This is a top view illustrating the substrate.

[0051] Explanation of reference numerals in the attached figures

[0052] 10, 10R, 12, 50: Substrate; 14: SiO2 layer; 16: Si layer; 20: Waveguide; 21, 39, 43: Taper; 22: Groove; 24: Plateau; 24a: Protrusion; 26: Diffraction grating; 26a: Recess; 26b: Convex; 30: Semiconductor element; 32, 35: Cladding layer; 34: Active layer; 36: Contact layer; 37, 38: Electrode; 40, 42, 44: Mesa; 46: Insulating film; 100, 100R: Semiconductor optical element. Detailed Implementation

[0053] [Description of embodiments of this disclosure]

[0054] First, the contents of the disclosed embodiments will be listed for explanation.

[0055] One embodiment of this disclosure is as follows: (1) A semiconductor optical element comprises: a substrate containing silicon and having a platform, a waveguide, and a diffraction grating in different regions when viewed from above; and a semiconductor element bonded to the diffraction grating and the platform, the semiconductor element being in contact with the upper surface of the substrate, formed of a III-V compound semiconductor, and having optical gain, the waveguide being optically coupled to the diffraction grating in the direction of extension of the waveguide, the platform being located on both sides of the waveguide and the diffraction grating in a direction intersecting the direction of extension of the waveguide, the substrate having a groove between the platform and the waveguide, and the diffraction grating being continuous with the platform in a direction intersecting the direction of extension of the waveguide. By increasing the contact area between the semiconductor element and the substrate, the bonding strength is improved, and the thermal resistance is reduced.

[0056] (2) Alternatively, the substrate may have a silicon layer, and the platform, the waveguide, and the diffraction grating may be disposed on the silicon layer. The diffraction grating includes recesses and protrusions periodically arranged on the silicon layer along the extension direction of the waveguide. The upper surface of the platform and the upper surface of the protrusions of the diffraction grating form a plane. Because the semiconductor element contacts the platform and the protrusions, the bonding strength is improved, and the thermal resistance is reduced.

[0057] (3) The semiconductor device may have a first cladding layer, an active layer, and a second cladding layer stacked sequentially from the substrate side, and a first mesa protruding from the substrate side toward a side opposite to the substrate above the diffraction grating, the first mesa including the second cladding layer. Because the semiconductor device has the first mesa, light confinement to the semiconductor device is strengthened, light leakage to the substrate is suppressed, and light mode control is possible.

[0058] (4) Alternatively, the width of the diffraction grating in the direction intersecting the extension direction of the waveguide is greater than the width of the first mesa. Since the platform is separated from the first mesa, the light confinement to the semiconductor device is strengthened, and the leakage of light to the substrate is suppressed.

[0059] (5) Alternatively, the semiconductor element may have a second mesa protruding from the substrate side toward a side opposite to the substrate on the platform of the substrate. The second mesa includes a second cladding layer and is separated from the first mesa. The semiconductor element comprises: a first electrode electrically connected to the first cladding layer; and a second electrode electrically connected to the second cladding layer of the first mesa. Light confinement to the active layer located below the first mesa is strengthened, and light leakage to the substrate is suppressed, enabling light mode control.

[0060] (6) Alternatively, the platform may have a protrusion extending toward the diffraction grating, and the diffraction grating is connected to the protrusion. Due to the increased contact area between the semiconductor element and the substrate, the bonding strength is improved, and the thermal resistance is reduced.

[0061] (7) The waveguide may have a first tapered portion that points from the diffraction grating side toward the side opposite to the diffraction grating. This can suppress light loss.

[0062] (8) The semiconductor element may have a second tapered portion that is pointed from the diffraction grating side toward the waveguide side. The optical coupling between the semiconductor element and the substrate is strengthened, which can suppress light loss.

[0063] (9) A method for manufacturing a semiconductor optical element comprises: a preparation step of preparing a substrate containing silicon, wherein a platform, a waveguide, and a diffraction grating are formed in different regions when viewed from above; and a bonding step of bonding a semiconductor element formed of a III-V compound semiconductor and having optical gain onto the diffraction grating and the platform in the substrate, wherein in the bonding step, the semiconductor element is in contact with the upper surface of the substrate, the waveguide is optically coupled to the diffraction grating in the extending direction of the waveguide, the platform is located on both sides of the waveguide and the diffraction grating in a direction intersecting the extending direction of the waveguide, the substrate has a groove between the platform and the waveguide, and the diffraction grating is continuous with the platform in a direction intersecting the extending direction of the waveguide. By increasing the contact area between the semiconductor element and the substrate, the bonding strength is improved and the thermal resistance is reduced.

[0064] [Details of the embodiments disclosed herein]

[0065] Specific examples of semiconductor optical elements and manufacturing methods relating to embodiments of the present disclosure are described below with reference to the accompanying drawings. Furthermore, the present disclosure is not limited to these examples, but is defined by the claims in order to include all modifications of the same meaning and scope as the claims.

[0066] Figure 1A This is a top view illustrating the semiconductor optical element 100 according to the embodiment. Figure 1B It is along Figure 1A A sectional view of line AA. Figure 1C It is along Figure 1A A sectional view of line BB. Figure 1D It is along Figure 1A A sectional view of line CC. Figure 1E It is along Figure 1A A sectional view of line DD. Figure 2 This is a top view illustrating substrate 10. Figures 1A to 1E As shown, the semiconductor optical element 100 is a hybrid DFB laser element having a substrate 10 and a semiconductor element 30. The surfaces of the substrate 10 and the semiconductor element 30 are covered with an insulating film 46, but... Figure 1A The insulating film 46 is viewed through a microscope.

[0067] (substrate)

[0068] like Figures 1B to 1E As shown, substrate 10 is an SOI substrate consisting of a silicon (Si) substrate 12, a silicon oxide (SiO2) layer 14, and a Si layer 16 sequentially stacked. The end faces of substrate 10 are coated to prevent light reflection. Substrate 10 has an edge extending along the X-axis and an edge extending along the Y-axis. The stacking direction of substrate 12, SiO2 layer 14, and Si layer 16 is set as the Z-axis direction. The X-axis, Y-axis, and Z-axis directions are orthogonal to each other.

[0069] like Figure 1A as well as Figure 2 As shown, a waveguide 20, a groove 22, a platform 24, and a diffraction grating 26 are disposed on the Si layer 16 of the substrate 10. The waveguide 20, diffraction grating 26, and waveguide 20 are arranged sequentially from one end of the substrate 10 along the X-axis to the other end. The waveguide 20 extends along the X-axis, is optically coupled to the diffraction grating 26, and has a tapered portion 21 at the connection with the diffraction grating 26. The tapered portion 21 is wider on the diffraction grating 26 side and has a pointed tip along the X-axis towards the side opposite to the diffraction grating 26.

[0070] The portion of the Si layer 16 sandwiched between two cones 21 has periodic recesses and protrusions along the X-axis. The air within the recesses 26a and the protrusions 26b of the Si layer have a refractive index difference, and the multiple recesses and protrusions function as a diffraction grating 26. In other words, the diffraction grating 26 includes multiple recesses 26a and multiple protrusions 26b. A semiconductor element 30 is bonded to the diffraction grating 26.

[0071] Grooves 22 are provided on both sides of the waveguide 20 and the cone 21 in the Y-axis direction. A platform 24 is provided on the outside of the grooves 22. The upper surfaces of the waveguide 20, the cone 21, the platform 24, and the protrusion 26b are at the same height in the Z-axis direction, forming the same plane.

[0072] The groove 22 and the recess 26a extend along the Z-axis to the middle of the Si layer 16. The bottom surfaces of the groove 22 and the recess 26a are formed by the Si layer 16, and are located at the same height along the Z-axis, below the upper surfaces of the platform 24 and the protrusion 26b. Figure 1D as well as Figure 1E As shown, the inner side of the groove 22 is covered by an insulating film 46. The inner side of the recess 26a is hollow.

[0073] like Figure 1A as well as Figure 2 As shown, no groove 22 is provided between the diffraction grating 26 and the platform 24. The diffraction grating 26 reaches the platform 24 in the Y-axis direction and is continuous with the platform 24. Specifically, the platform 24 has a protrusion 24a at a position opposite the diffraction grating 26 in the Y-axis direction. The protrusion 24a protrudes in the Y-axis direction and connects with the diffraction grating 26. The convex portion 26b of the diffraction grating 26 extends to the protrusion 24a of the platform 24 and together with the protrusion 24a forms the upper surface of the substrate 10. The two ends of the concave portion 26a of the diffraction grating 26 in the Y-axis direction reach the protrusion 24a.

[0074] Figure 1C as well as Figure 2 The width W1 of the diffraction grating 26 shown in the Y-axis direction is, for example, 5 μm. The width W1 of the diffraction grating 26 refers to the width of the concave portion 26a and the convex portion 26b. Figure 2 The width W2 of the waveguide 20 shown is, for example, 0.5 μm. The width W3 of the slot 22 is, for example, 5 μm.

[0075] (Semiconductor components)

[0076] Figure 1A The semiconductor element 30 shown is a light-emitting element with a ridgemesa structure formed from a III-V compound semiconductor. Figures 1B to 1EAs shown, the semiconductor element 30 has a cladding layer 32 (first cladding layer), an active layer 34, a cladding layer 35 (second cladding layer), and a contact layer 36 stacked sequentially in the Z-axis direction from the substrate 10 side.

[0077] The cladding layer 32 is formed, for example, of n-type indium phosphide (n-InP). The cladding layer 35 is formed, for example, of p-InP. The contact layer 36 is formed, for example, of p-type indium gallium arsenide (p-InGaAs). The active layer 34 includes, for example, multiple well layers and barrier layers formed of undoped gallium indium arsenide phosphide (i-GaInAsP), and has a multi-quantum well (MQW) structure. Spacer layers may also be provided between the active layer 34 and the cladding layer 32, and between the active layer 34 and the cladding layer 35. The semiconductor element 30 may include an n-type contact layer (not shown) on the cladding layer 32, or may be formed of a semiconductor other than those described above.

[0078] Semiconductor element 30 has three mesa 40, 42, and 44. Mesa 40, 42, and 44 are arranged sequentially in the Y-axis direction and are separated from each other. Mesa 40 and mesa 44 (the second mesa) are located on platform 24. Mesa 42 (the first mesa) is located on diffraction grating 26. Figure 1B as well as Figure 1C As shown, mesa 40, 42, and 44 are formed by a cladding layer 35 and a contact layer 36, protruding in the opposite direction (upward in the Z-axis direction) to the substrate 10, with reference to the lower surface of the semiconductor element 30 (cladding layer 32). The cladding layer 32 and the active layer 34 extend from mesa 40 to mesa 44.

[0079] Figure 1C The width W4 of the stage 42 shown is smaller than the width W1 of the diffraction grating 26, for example, 2.5 μm. Figure 1A As shown, the lengths of the stages 40 and 44 in the X-axis direction are, for example, the same as the length of the diffraction grating 26. The length of the stage 42 in the X-axis direction is greater than the lengths of the diffraction grating 26, stages 40, and 44. Stage 42 has two cones 43. The cones 43 protrude beyond the diffraction grating 26 in the X-axis direction and have pointed tips facing the side opposite to the diffraction grating 26.

[0080] like Figure 1A , Figure 1D as well as Figure 1E As shown, the cladding layer 32 and the active layer 34 have two cones 39. The cones 39 are located above the cone 21 of the substrate 10, protrude beyond the diffraction grating 26 in the X-axis direction, and have pointed tips facing the opposite side to the diffraction grating 26. Figures 1D to 1E As shown, cone 43 is located above cone 39. Figure 1EAs shown, at the front end of the tip, cone 43 and cone 39 merge. The length of cones 39 and 43 in the X-axis direction is smaller than the length of cone 21 of substrate 10.

[0081] like Figures 1B to 1E As shown, the insulating film 46 covers the upper and side surfaces of mesa 40, 42, and 44, the upper surface of the active layer 34 between the mesa, and the upper surface of the substrate 10. The insulating film 46 is formed, for example, from silicon oxide (SiO2). The refractive index of the insulating film 46 is lower than that of the Si layer 16 and the refractive index of the mesa 42. Therefore, the insulating film 46 functions as a cladding layer that confines light within the mesa 42 and the waveguide 20. The electrode 37 is an n-type electrode. Figure 1B As shown, electrode 37 is disposed between mesa 42 and mesa 44, and is electrically connected to cladding layer 32 through an opening in insulating film 46. Electrode 37 has an ohmic electrode layer formed of an alloy of gold, germanium, and Ni (AuGeNi), and a wiring layer formed of Au. Electrode 38 is a p-type electrode. Electrode 38 is disposed on the upper surface of mesa 42, and is electrically connected to contact layer 36 and cladding layer 35 through an opening in insulating film 46. Electrode 38 has an ohmic electrode layer formed of a laminate of titanium, platinum, and gold (Ti / Pt / Au), and a wiring layer formed of Au.

[0082] Semiconductor element 30 has optical gain. By applying a voltage to electrodes 37 and 38, current flows through mesa 42, and charge carriers are injected into active layer 34. The active layer 34 at the bottom of mesa 42 then emits light. The active layer 34 of semiconductor element 30 is evanescently coupled to diffraction grating 26 of substrate 10. The light generated by semiconductor element 30 propagates through diffraction grating 26, cone 21, and waveguide 20, and exits from end face of substrate 10 toward the outside of semiconductor optical element 100.

[0083] Because grooves 22 are provided on both sides of the waveguide 20, the light can be strongly confined to the waveguide 20 by the refractive index difference between the waveguide 20, which is made of Si layer, and the insulating film 46 (or air) in the grooves 22. On the other hand, grooves 22 are not provided on both sides of the diffraction grating 26, and the diffraction grating 26 is connected to the protrusion 24a of the platform 24. The semiconductor device 30 has a ridge-shaped mesa structure with mesa 42 on the diffraction grating 26. With the ridge-shaped mesa structure, the light is strongly confined to the region of the active layer 34 located below the mesa 42, and it is difficult for it to leak to the Si layer 16 of the substrate 10. As a result, the desired light pattern distribution can be obtained.

[0084] Figures 3A to 4B This is a diagram illustrating the intensity of light. Figure 3A as well as Figure 3B Indicates as Figure 1BThe intensity of light in the cross section where the semiconductor element 30 and the protrusion 26b of the diffraction grating 26 are arranged. Figure 4A as well as Figure 4B Indicates as Figure 1C The intensity of light in the cross section where the semiconductor element 30 and the recess 26a of the diffraction grating 26 are arranged. Figures 3A to 4B The vertical axis represents the intensity of light.

[0085] Figure 3A as well as Figure 4A The horizontal axis represents the position along the Y-axis. That is, Figure 3A as well as Figure 4A This represents the light distribution along the Y-axis. The 5μm position along the Y-axis corresponds to the center of the width direction in the stage 42. (Example...) Figure 3A as well as Figure 4A As shown, the light distribution is in the range of 4–6 μm, with a peak intensity within this range. The light is concentrated at the center along the Y-axis, i.e., concentrated on the mesa 42. The width of the diffraction grating 26 is preferably greater than [missing value]. Figure 3A as well as Figure 4A The diagram shows the range of light distribution along the Y-axis. Specifically, the width of the diffraction grating 26 is more than twice the width of the terrace 42.

[0086] Figure 3B as well as Figure 4B The horizontal axis represents the position along the Z-axis, which includes the platform 42. That is, Figure 3B as well as Figure 4B This represents the distribution of light along the Z-axis. For example... Figure 3B As shown, in the cross-section including protrusion 26b, the light has two peaks, P1 and P2. Peak P1 appears in the Si layer 16 of substrate 10. Peak P2 is larger than peak P1 and appears in the active layer 34 of mesa 42. Figure 4B As shown, in the cross-section including the recess 26a, light only shows a peak in the active layer 34.

[0087] In the cross-section including protrusion 26b, the light confinement factor toward the active layer 34 is 3.74%. Light is primarily distributed within the active layer 34, but... Figure 3B As shown, light also leaks into the Si layer 16. In the cross-section including the recess 26a, the light confinement factor is 5.77%. Figure 4A as well as Figure 4BAs shown, compared to the cross-section containing the protrusion 26b, the light is more strongly confined by the active layer 34 in the cross-section containing the concave portion 26a. By alternately arranging multiple concave portions 26a and protrusions 26b on the diffraction grating 26 and bonding the semiconductor element 30 with the ridge-shaped mesa structure, the overall light confinement factor of the bonded portion is 4% or more. Here, the overall light confinement factor refers to the average light confinement factor calculated by considering the distribution of the lengths of the concave portions 26a and convex portions 26b in the X-axis direction (duty cycle of the diffraction grating) using the light confinement factors in the cross-section containing the concave portion 26a and the cross-section containing the protrusion 26b.

[0088] (Manufacturing method)

[0089] In the manufacture of semiconductor optical element 100, for example, two wafers are used. The two wafers refer to: a wafer (substrate 10) used to manufacture the SOI substrate and a wafer used to manufacture the III-V compound semiconductor of semiconductor element 30.

[0090] The SOI substrate in wafer form has multiple regions for forming semiconductor optical elements 100. In each of these regions of the SOI substrate, [the following is a list of regions and their formations]. Figure 2 The waveguide 20, cone 21, groove 22, plateau 24, and diffraction grating 26 are shown. A resist pattern is formed using electron beam drawing or similar methods, and the portion forming the protrusion 26b of the waveguide 20, cone 21, plateau 24, and diffraction grating 26 is covered with resist. The portion of the Si layer 16 exposed from the resist is dry-etched to form the groove 22 and the recess 26a. The waveguide 20, cone 21, plateau 24, and protrusion 26b are formed in the portion protected by the resist (see reference). Figure 2 ).

[0091] Figure 5 This is a cross-sectional view illustrating an example of a manufacturing method for semiconductor element 30. For example, a contact layer 36, a cladding layer 35, an active layer 34, and a cladding layer 32 are sequentially epitaxially grown on an InP substrate 50 using a method such as organometallic vapor phase epitaxy (OMVPE). The wafer is then diced to form multiple semiconductor elements 30. At the time of dicing, mesa 40, 42, and 44, electrodes, and tapers 43 are not yet formed on the semiconductor element 30.

[0092] Figure 6A , Figure 7A , Figure 8A as well as Figure 9A This is a top view illustrating an example of a manufacturing method for a semiconductor optical element 100, showing the process after the semiconductor element 30 is bonded to the substrate 10. Figure 6B , Figure 7B , Figure 8B as well as Figure 9B The cross sections along line AA in the corresponding top view are illustrated. Figure 6C , Figure 7C , Figure 8C as well as Figure 9C The cross-sections along line BB in the corresponding top view are shown in the diagrams. Figure 6D , Figure 7D , Figure 8D as well as Figure 9D The cross sections along line CC in the corresponding top view are illustrated. Figure 6E , Figure 7E , Figure 8E as well as Figure 9E The cross sections along line DD in the corresponding top view are illustrated.

[0093] For example, the surface of the cladding layer 32 of the semiconductor element 30 and the surface of the Si layer 16 of the substrate 10 can be activated by plasma irradiation. Figures 6A to 6E As shown, the semiconductor element 30 is brought into contact with the Si layer 16, and the semiconductor element 30 is bonded to the upper surface of the substrate 10. No adhesive or similar material is placed between the surface of the semiconductor element 30 and the upper surface of the substrate 10, allowing the surfaces to contact each other. After bonding, the substrate 50 of the semiconductor element 30 is removed by wet etching, exposing the surface of the contact layer 36. The etchant used in the wet etching flows into the trench 22 of the substrate 10, but is blocked by the protrusions 26b of the diffraction grating 26 and the platform 24. Etching of the lower surface (cladding layer 32) of the semiconductor element 30 is suppressed.

[0094] like Figures 7A to 7E As shown, mesas 40, 42, and 44 are formed on the semiconductor device 30. An insulating film for masking is formed on the surface of the semiconductor device 30, and a resist pattern is formed on the insulating film. The insulating film is dry-etched using the resist pattern to form an insulating film mask with openings (not shown). The resist pattern is removed. A portion of the contact layer 36 is exposed from the openings in the insulating film mask. The exposed portion in the semiconductor device 30 is dry-etched to form mesas 40, 42, and 44. The portion covered by the insulating film mask is not etched. The insulating film mask is removed after etching.

[0095] like Figures 8A to 8E As shown, a cone 39 is formed in the semiconductor device 30. An insulating film for a mask is formed in the semiconductor device 30, and a resist pattern is formed on the insulating film. An insulating film mask (not shown) is formed by dry etching the insulating film using the resist pattern. The resist pattern is then removed. A portion of the active layer 34 is exposed from the insulating film mask. The cone 39 is formed by dry etching the portion of the semiconductor device 30 exposed from the insulating film mask. Figure 8B as well as Figure 8CAs shown, platforms 40, 42, and 44, as well as the area between platforms, were not etched. Figure 8D as well as Figure 8E As shown, a portion of the upper surface of substrate 10 is exposed. The insulating film mask is then removed.

[0096] like Figures 9A to 9E As shown, an insulating film 46 is formed on the surface of the substrate 10 and the semiconductor device 30, for example, by chemical vapor deposition (CVD). Openings are provided on the mesa 42 and between the mesa 42 and the mesa 44, for example, by vacuum deposition. Figure 1A Electrodes 38 and 37 are shown. Through the above processes, a [structure / form] is formed. Figures 1A to 1E The semiconductor optical element 100 shown.

[0097] (Comparative Example)

[0098] Figure 10A This is a top view illustrating the semiconductor optical element 100R involved in the comparative example. Figures 10B to 10E They are along Figure 10A Cross-sectional views of lines AA, BB, CC, and DD. Figure 11 This is a top view illustrating substrate 10R. Semiconductor optical element 100R has substrate 10R instead of substrate 10.

[0099] like Figures 10A to 11 As shown, grooves 22 are provided on both sides of the diffraction grating 26 on the substrate 10R. The platform 24 does not have a protrusion 24a and is separated from the diffraction grating 26. In order to enhance the confinement of light to the active layer 34 of the semiconductor element 30, the grooves 22 are preferably enlarged. However, since there are grooves 22 between the diffraction grating 26 and the platform 24, the contact area between the semiconductor element 30 and the substrate 10R is reduced, and the bonding strength is decreased.

[0100] In the comparative example, the inner side of the trench 22 exposed from the semiconductor element 30 is covered by an insulating film 46. On the other hand, the inner side of the trench 22 located below the semiconductor element 30 is filled with air. Air has a lower thermal conductivity than the substrate 10R, thus increasing thermal resistance. Due to the temperature rise accompanying operation, the characteristics of the semiconductor optical element 100R deteriorate. During wet etching of the substrate of the semiconductor element 30, the etchant penetrates the trench 22, sometimes etching the semiconductor element 30 from below. Through etching, the semiconductor element 30 is easily peeled off.

[0101] According to this embodiment, the substrate 10 has a platform 24, a diffraction grating 26, and a waveguide 20. For example... Figure 2As shown, by having grooves 22 on both sides of the waveguide 20, light can be strongly confined within the waveguide 20. On the other hand, no grooves 22 are provided on both sides of the diffraction grating 26. The diffraction grating 26 extends to and connects to the platform 24 in the Y-axis direction. The semiconductor element 30 is bonded to the platform 24 and the diffraction grating 26, and contacts the surface of the substrate 10. Compared with the comparative example, the contact area between the semiconductor element 30 and the substrate 10 is larger, and therefore the bonding strength is higher.

[0102] like Figures 1B to 1E As shown, no adhesive or similar agent is present between the semiconductor element 30 and the substrate 10, and the lower surface of the semiconductor element 30 is in contact with the upper surface of the substrate 10. Compared to the case where adhesives such as resin are used, the thermal resistance is reduced. Furthermore, since no grooves 22 are provided on both sides of the diffraction grating 26, the amount of air between the semiconductor element 30 and the substrate 10 is reduced compared to the comparative example, and the contact area between the semiconductor element 30 and the substrate 10 is increased. The thermal resistance is reduced, and heat during operation is effectively released to the substrate 10. The temperature rise of the semiconductor element 30 is suppressed, and its characteristics are stable. Because no grooves 22 are provided on both sides of the diffraction grating 26, for example, when... Figure 5 When the substrate 50 shown is wet-etched, the etchant has difficulty penetrating under the semiconductor element 30. The etching of the semiconductor element 30 is suppressed, making it difficult to peel off.

[0103] A waveguide 20, a plateau 24, and a diffraction grating 26 are formed in the Si layer 16 of the substrate 10. For example... Figure 2 As shown, the diffraction grating 26 includes a recess 26a and a convex portion 26b. (As...) Figure 1B As shown, the protrusion 26b and platform 24 are located at the same height in the Z-axis direction, forming the upper surface of the substrate 10. The semiconductor element 30 is in contact with the protrusion 26b and platform 24. Because the contact area between the substrate 10 and the Si layer 16 is increased, the bonding strength is improved, and the heat dissipation is also enhanced. The bottom surface of the recess 26a is preferably the Si layer 16. Heat is transferred and released within the Si layer 16.

[0104] The diffraction grating 26 includes a plurality of periodically arranged recesses 26a and a plurality of convex portions 26b. The periodic arrangement of the recesses 26a and convex portions 26b allows for adjustment of the wavelength of light. Figure 2 As shown, the multiple recesses 26a and multiple convexities 26b can also be arranged in the same manner. The diffraction grating 26, for example, has multiple partial diffraction gratings and can function as an SG-DBR (Sampled Grating-Distributed Bragg Reflector).

[0105] Figure 2The protrusion 24a of the platform 24 shown protrudes toward the diffraction grating 26 in the Y-axis direction. The protrusion 24a contacts the semiconductor element 30, increasing the bonding strength and improving heat dissipation. Because the protrusion 24a blocks etchant from penetrating the trench 22, etching from the underside of the semiconductor element 30 is suppressed.

[0106] The semiconductor element 30 has a ridge-shaped mesa structure with mesa 42 on the diffraction grating 26 and mesa 40 and 44 on the platform 24. Electrode 38 is disposed on mesa 42. When a voltage is applied to electrodes 37 and 38, light is emitted from the active layer 34 below mesa 42. The shape of the light pattern can be defined by mesa 42, thus improving the controllability of the pattern. Figure 1C The light confinement factor in the cross-section including the recess 26a shown is 3.74%. Figure 1B The light confinement factor in the cross-section including the protrusion 26b shown is 5.77%. A light confinement factor of over 4% can be obtained across the entire junction portion of the semiconductor element 30. Therefore, characteristic degradation can be suppressed. To improve light confinement, the semiconductor element 30 may or may not have mesas 42 above the diffraction grating 26.

[0107] The longer the protrusion 24a of the platform 24, the larger the contact area, which improves the bonding strength. On the other hand, if the protrusion 24a is long, the width W1 of the diffraction grating 26 is small, and the confinement of light to the semiconductor element 30 weakens, causing light to leak into the substrate 10. The width W1 of the diffraction grating 26 is preferably greater than, for example, the width of the mesa 42 of the semiconductor element 30. As an example, the width W1 of the diffraction grating 26 is preferably more than twice the width of the mesa 42. The mesa 42 is separated from the platform 24, thus strengthening the confinement of light to the semiconductor element 30, suppressing light leakage into the substrate 10, and controlling the shape of the pattern. If the width W1 of the diffraction grating 26 is large enough to block the groove 22, the protrusion 24a may not be provided on the platform 24.

[0108] like Figure 1A as well as Figure 2 As shown, the Si layer 16 of the substrate 10 has a tapered portion 21. The tapered portion 21 is pointed from the diffraction grating 26 side toward the side opposite to the diffraction grating 26. The tapered portion 21 can suppress light reflection and light loss between the diffraction grating 26 and the waveguide 20.

[0109] like Figure 1A As shown, the semiconductor element 30 has a tapered portion 43 that points towards the waveguide 20 from the diffraction grating 26 side. The tapered portion 43 enhances the optical coupling between the semiconductor element 30 and the waveguide 20 and suppresses light loss.

[0110] The embodiments of this disclosure have been described in detail above, but this disclosure is not limited to specific embodiments. Various modifications and alterations can be made within the scope of the spirit of this disclosure as set forth in the claims.

Claims

1. A semiconductor optical element, characterized in that, The semiconductor optical element comprises: A substrate comprising silicon and having, when viewed from above, distinct regions having platforms, waveguides, and diffraction gratings; and A semiconductor element, bonded to the diffraction grating and the platform, is in contact with the upper surface of the substrate, is formed of a III-V compound semiconductor, and has optical gain. The waveguide path is optically coupled to the diffraction grating in the direction of its extension. The platform is located on both sides of the waveguide and the diffraction grating in a direction intersecting the extension direction of the waveguide. The substrate has a groove between the platform and the waveguide. The diffraction grating is continuous with the platform in the direction intersecting the extension direction of the waveguide path. The semiconductor device has a first cladding layer, an active layer, and a second cladding layer stacked sequentially from the substrate side, and has a first mesa protruding from the substrate side toward a side opposite to the substrate on the diffraction grating. The first countertop includes a second covering layer. The width of the diffraction grating in the direction intersecting the extension direction of the waveguide is greater than the width of the first platform.

2. The semiconductor optical element according to claim 1, characterized in that, The substrate has a silicon layer. The platform, the waveguide, and the diffraction grating are disposed on the silicon layer. The diffraction grating includes recesses and convexities periodically arranged in the silicon layer along the extension direction of the waveguide path. The upper surface of the platform and the upper surface of the convex part of the diffraction grating form a plane.

3. The semiconductor optical element according to claim 1 or 2, characterized in that, The semiconductor element has a second mesa projecting from the substrate side toward a side opposite to the substrate above the platform of the substrate. The second countertop includes a second covering layer and is separate from the first countertop. The semiconductor element includes: a first electrode electrically connected to the first cladding layer; and a second electrode electrically connected to the second cladding layer of the first mesa.

4. The semiconductor optical element according to claim 1 or 2, characterized in that, The platform has a protrusion that extends toward the diffraction grating. The diffraction grating is connected to the protrusion.

5. The semiconductor optical element according to claim 1 or 2, characterized in that, The waveguide has a first cone-shaped section that points from the diffraction grating side toward the side opposite to the diffraction grating.

6. The semiconductor optical element according to claim 1 or 2, characterized in that, The semiconductor element has a second cone that is pointed from the diffraction grating side toward the waveguide side.

7. A method for manufacturing a semiconductor optical element, characterized in that, The manufacturing method comprises: Preparation steps for a substrate containing silicon, wherein platforms, waveguides, and diffraction gratings are formed in distinct regions when viewed from above; and The bonding process of bonding a semiconductor element formed of a III-V compound semiconductor and having optical gain to the diffraction grating in the substrate and onto the platform. During the bonding process, the semiconductor element comes into contact with the upper surface of the substrate. The waveguide path is optically coupled to the diffraction grating in the direction of its extension. The platform is located on both sides of the waveguide and the diffraction grating in a direction intersecting the extension direction of the waveguide. The substrate has a groove between the platform and the waveguide. The diffraction grating is continuous with the platform in the direction intersecting the extension direction of the waveguide path. The semiconductor device has a first cladding layer, an active layer, and a second cladding layer stacked sequentially from the substrate side, and has a first mesa protruding from the substrate side toward a side opposite to the substrate on the diffraction grating. The first countertop includes a second covering layer. The width of the diffraction grating in the direction intersecting the extension direction of the waveguide is greater than the width of the first platform.

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