Display panel, manufacturing method thereof, and display device

Abstract

This disclosure provides a display panel and its manufacturing method and display device. The display panel includes: a substrate, including a display area and a peripheral area surrounding the display area; a plurality of sub-pixels located in the display area, at least one of the sub-pixels including a driving transistor, the driving transistor including multiple conductive layers; a first dam surrounding the display area located in the peripheral area; a second dam surrounding the display area located in the peripheral area and located on the side of the first dam away from the display area; an encapsulation layer located on the side of the plurality of sub-pixels, the first dam and the second dam away from the substrate, the orthographic projection of the plurality of sub-pixels, the first dam and the second dam on the substrate being located within the orthographic projection of the encapsulation layer on the substrate; at least one pressure sensor located on at least one of a first side of the second dam near the first dam and a second side away from the first dam, at least one resistor in each pressure sensor being located in the same layer as one of the multiple conductive layers.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] With the development of display technology, the application of organic light-emitting diode (OLED) display panels is becoming increasingly common. In related technologies, additional interactive buttons are needed to achieve human-computer interaction, such as volume buttons and power buttons. Summary of the Invention

[0003] According to one aspect of the present disclosure, a display panel is provided, comprising: a substrate including a display area and a peripheral area surrounding the display area; a plurality of sub-pixels located in the display area, at least one of the plurality of sub-pixels including a driving transistor, the driving transistor including a multilayer conductive layer; a first dam surrounding the display area located in the peripheral area; a second dam surrounding the display area located in the peripheral area and on a side of the first dam away from the display area; an encapsulation layer located on a side of the plurality of sub-pixels, the first dam, and the second dam away from the substrate, wherein the orthographic projections of the plurality of sub-pixels, the first dam, and the second dam on the substrate are within the orthographic projections of the encapsulation layer on the substrate; and at least one pressure sensor located on at least one side of the second dam near the first dam and a second side away from the first dam, wherein at least one resistor in each of the at least one pressure sensor is located in the same layer as one of the multilayer conductive layers.

[0004] In some embodiments, the driving transistor includes: an active layer and a gate located on one side of the substrate; a first insulating layer located between the active layer and the gate; a second insulating layer located on the side of the active layer, the gate, and the first insulating layer away from the substrate; a third insulating layer located on the side of the second insulating layer away from the substrate; and a first electrode and a second electrode located on the side of the third insulating layer away from the substrate and electrically connected to the active layer, wherein the multilayer conductive layer includes the gate, the first electrode, and the second electrode, and the at least one resistor, the first electrode, and the second electrode are located in the same layer.

[0005] In some embodiments, the at least one sub-pixel further includes a storage capacitor comprising: a first electrode plate located on the same layer as the gate; and a second electrode plate located between the second insulating layer and the third insulating layer. The at least one resistor includes a first resistor electrically connected between a first input terminal and a first output terminal, a second resistor electrically connected between the first output terminal and the second input terminal, a third resistor electrically connected between the second input terminal and the second output terminal, and a fourth resistor electrically connected between the second output terminal and the first input terminal, wherein the first resistor, the second resistor, the third resistor, and the fourth resistor have the same resistance value when not under pressure. The display panel further includes a first signal output line electrically connected to the first output terminal and a second signal output line electrically connected to the second output terminal, wherein the first signal output line and the second signal output line are located on the same layer as one of the first electrode plate and the second electrode plate.

[0006] In some embodiments, the first signal output line and the second signal output line are located on the same layer as the second electrode plate.

[0007] In some embodiments, the display panel further includes: a first signal input line electrically connected to the first input terminal; and a second signal input line electrically connected to the second input terminal, wherein the first signal input line and the second signal input line are located on the same layer as another of the first electrode plate and the second electrode plate.

[0008] In some embodiments, the first resistor and the third resistor are symmetrically arranged with respect to the first line, and the second resistor and the fourth resistor are symmetrically arranged with respect to the second line.

[0009] In some embodiments, the first line and the second line are perpendicular.

[0010] In some embodiments, the first resistor is located on one side of the first line, and the second resistor, the third resistor, and the fourth resistor are located on the other side of the first line.

[0011] In some embodiments, the display panel further includes a crack stopper located on the side of the encapsulation layer away from the display area, wherein the at least one pressure sensor is located on the side of the crack stopper closer to the display area.

[0012] In some embodiments, the at least one pressure sensor includes: a first pressure sensor located between the second dike and the first dike, wherein the orthographic projection of the first pressure sensor on the substrate is located within the orthographic projection of the encapsulation layer on the substrate.

[0013] In some embodiments, the at least one pressure sensor includes: a second pressure sensor located between the second dike and the crack arrester, wherein the orthographic projection of the second pressure sensor on the substrate is located within the orthographic projection of the encapsulation layer on the substrate.

[0014] In some embodiments, the at least one pressure sensor includes a third pressure sensor located between the encapsulation layer and the crack arrester.

[0015] In some embodiments, the display panel further includes a buffer layer located between the substrate and the first insulating layer, wherein the first insulating layer, the second insulating layer, the third insulating layer and the buffer layer extend from the display area to the peripheral area, and the crack-stopping member penetrates the third insulating layer, the second insulating layer, the first insulating layer and the buffer layer.

[0016] In some embodiments, the at least one sub-pixel further includes: a planarization layer located on the side of the first electrode, the second electrode, and the third insulating layer away from the substrate; an anode located on the side of the planarization layer away from the substrate and electrically connected to one of the first electrode and the second electrode; a pixel defining layer located on the side of the anode and the planarization layer away from the substrate and having a first opening, the orthographic projection of the first opening on the substrate at least partially overlapping the orthographic projection of the anode on the substrate; a functional layer located at least partially in the first opening and on the side of the anode away from the substrate; and a cathode located at least partially in the first opening and on the side of the functional layer away from the substrate. The display panel further includes a power bus located in the peripheral area, electrically connected to the cathode, and located on the same layer as the first electrode and the second electrode.

[0017] In some embodiments, the planarization layer has a second opening, the pixel defining layer also has a third opening, and the orthographic projections of the second opening and the third opening onto the substrate are located in the peripheral region; the display panel further includes an electrical connection portion located at least partially in the second opening, on the same layer as the anode, and in contact with the power bus; and the cathode is partially located in the third opening and in contact with the electrical connection portion.

[0018] In some embodiments, the display panel further includes: a plurality of initialization lines located in the display area, electrically connected to the plurality of sub-pixels, and configured to provide initialization signals to the plurality of sub-pixels; and an initialization bus located in the peripheral area, between the planarization layer and the substrate, electrically connected to the plurality of initialization lines, and located on the same layer as the first electrode and the second electrode.

[0019] In some embodiments, the first dike includes: a first layer located on the same layer as the planarization layer; and a second layer located on the side of the first layer away from the substrate and on the same layer as the pixel defining layer.

[0020] In some embodiments, the second dike includes: a third layer located on the same layer as the planarization layer; a fourth layer located on the side of the third layer away from the substrate and on the same layer as the pixel defining layer; and a fifth layer located on the side of the fourth layer away from the substrate and on the same layer as the support layer, wherein the support layer is located in the display area and on the side of the pixel defining layer away from the substrate.

[0021] According to another aspect of the present disclosure, a display device is provided, comprising: the display panel described in any of the above embodiments.

[0022] According to another aspect of the present disclosure, a method for manufacturing a display panel is provided, comprising: providing a substrate, the substrate including a display area and a peripheral area surrounding the display area; forming a plurality of sub-pixels, a first dam, a second dam, and at least one pressure sensor, wherein: the plurality of sub-pixels are located in the display area, at least one of the plurality of sub-pixels includes a driving transistor, the driving transistor including multiple conductive layers, the first dam and the second dam are located in the peripheral area and surrounding the display area, the second dam is located on a side of the first dam away from the display area, and the at least one pressure sensor is located on at least one side of the second dam near the first dam and a second side away from the first dam, wherein at least one resistor in each of the at least one pressure sensor is located in the same layer as one of the multiple conductive layers; and forming an encapsulation layer located on the side of the plurality of sub-pixels, the first dam, and the second dam away from the substrate, wherein the orthographic projection of the plurality of sub-pixels, the first dam, and the second dam on the substrate is located within the orthographic projection of the encapsulation layer on the substrate. Attached Figure Description

[0023] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0024] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0025] Figure 1 This is a schematic diagram illustrating the structure of a display panel according to an embodiment of the present disclosure;

[0026] Figure 2A This is a cross-sectional schematic diagram showing a sub-pixel in a display panel according to an embodiment of the present disclosure;

[0027] Figure 2B This is a cross-sectional schematic diagram showing a display panel according to an embodiment of the present disclosure;

[0028] Figure 3 This is a circuit diagram illustrating a pressure sensor according to an embodiment of the present disclosure;

[0029] Figure 4A This is a schematic cross-sectional view showing the wiring of a pressure sensor according to an embodiment of the present disclosure;

[0030] Figure 4B This is a schematic cross-sectional view showing the wiring of a pressure sensor according to another embodiment of the present disclosure;

[0031] Figure 5A and Figure 5B This is a schematic diagram showing the layout of a pressure sensor according to some embodiments of the present disclosure;

[0032] Figure 6 This is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0033] It should be understood that the dimensions of the various parts shown in the accompanying drawings are not necessarily drawn to actual scale. Furthermore, the same or similar reference numerals denote the same or similar components. Detailed Implementation

[0034] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0035] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.

[0036] In this disclosure, when a particular component is described as being located between a first component and a second component, an intermediary component may or may not be present between the particular component and the first or second component. When a particular component is described as being electrically connected to other components, the particular component may be directly electrically connected to the other components without having an intermediary component, or it may not be directly electrically connected to the other components but may have an intermediary component.

[0037] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0038] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0039] Figure 1 This is a schematic diagram illustrating the structure of a display panel according to an embodiment of the present disclosure.

[0040] like Figure 1 As shown, the display panel includes a substrate 11 and a plurality of sub-pixels 12.

[0041] The substrate 11 includes a display area 111 and a peripheral area 112 surrounding the display area. In some embodiments, the substrate 11 includes a first substrate layer, a second substrate layer, a first barrier layer, and a second barrier layer. The first barrier layer is located between the first substrate layer and the second substrate layer, and the second substrate layer is located between the first barrier layer and the second barrier layer. For example, the material of at least one of the first substrate layer and the second substrate layer may include a flexible material such as polyimide (PI). For example, the material of at least one of the first barrier layer and the second barrier layer may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxide oxynitride.

[0042] Multiple sub-pixels 12 are located in display area 111. For example, the multiple sub-pixels 12 may include red sub-pixels, green sub-pixels, or blue sub-pixels, etc. Each sub-pixel 12 includes pixel circuitry. For example, pixel circuitry may include 6 transistors and 1 capacitor (6T1C); or, for example, pixel circuitry may include 7 transistors and 1 capacitor (7T1C).

[0043] In some embodiments, see Figure 1 The display panel also includes multiple data lines DL. These data lines DL are located in the display area 111 and are electrically connected to multiple sub-pixels 12 located in the display area 111. The data lines DL are configured to provide data signals to the multiple sub-pixels 12. For example, each data line DL is electrically connected to a column of sub-pixels 12.

[0044] In some embodiments, see Figure 1 The display panel also includes multiple gate lines GL. These gate lines GL are located in the display area 111 and are electrically connected to multiple sub-pixels 12. The gate lines GL are configured to provide gate signals to the multiple sub-pixels 12. For example, each gate line GL is electrically connected to a row of sub-pixels 12.

[0045] In some embodiments, see Figure 1 The display panel also includes multiple light-emitting control lines (GCLs). These GCLs are located in the display area 111 and are electrically connected to multiple sub-pixels 12. The GCLs are configured to provide light-emitting control signals to the multiple sub-pixels 12. For example, each GCL is electrically connected to a row of sub-pixels 12.

[0046] In some embodiments, see Figure 1 The display panel also includes multiple power lines PL. These power lines PL are located in the display area 111 and are electrically connected to multiple sub-pixels 12. The power lines PL are configured to provide power signals to the multiple sub-pixels 12.

[0047] In some embodiments, see Figure 1 The display panel also includes multiple initialization lines IL. These initialization lines IL are located in the display area 111 and are electrically connected to multiple sub-pixels 12. The multiple initialization lines IL are configured to provide initialization signals to the multiple sub-pixels 12.

[0048] Figure 2A This is a cross-sectional schematic diagram showing a sub-pixel in a display panel according to an embodiment of the present disclosure. Figure 2B This is a cross-sectional schematic diagram showing a display panel according to an embodiment of the present disclosure. The following is in conjunction with... Figure 2A and Figure 2B The structure of a display panel according to some embodiments of the present disclosure will be described.

[0049] like Figure 2A As shown, sub-pixel 12 includes a driving transistor 121. Here, the driving transistor 121 includes multiple conductive layers. In some implementations, the driving transistor 121 may be a top-gate transistor; in other implementations, the driving transistor 121 may be a bottom-gate transistor. Figure 2A The diagram shows the case where the driving transistor 121 is a top-gate transistor.

[0050] like Figure 2B As shown, in addition to a substrate 11 and a plurality of sub-pixels 12, the display panel also includes a first dam 13, a second dam 14, an encapsulation layer 15, and at least one pressure sensor 16. For example, the pressure sensor 16 can serve as a volume button or a power button.

[0051] The first cofferdam 13 and the second cofferdam 14 both surround the display area 111 and are both located in the peripheral area 112. The second cofferdam 14 is located on the side of the first cofferdam 13 away from the display area 111. Here, the first cofferdam 13 and the second cofferdam 14 can prevent water and oxygen from entering the sub-pixel 12.

[0052] The encapsulation layer 15 is located on the side of the plurality of sub-pixels 12, the first dam 13, and the second dam 14 away from the substrate 11. Here, the orthographic projections of the plurality of sub-pixels 12, the first dam 13, and the second dam 14 onto the substrate 11 lie within the orthographic projection of the encapsulation layer 15 onto the substrate 11. For example, the encapsulation layer 15 may include a thin-film encapsulation layer. In some embodiments, the encapsulation layer 15 may include a first inorganic layer 151, a second inorganic layer 153, and an organic layer 152 located between the first inorganic layer 151 and the second inorganic layer 153. In some embodiments, the display panel may further include a third dam 22 located between the second dam 14 and the display area 111. The third dam 22 is used to block the flow of the organic layer 152.

[0053] At least one pressure sensor 16 is located on at least one side of the second cofferdam 14, either on a first side close to the first cofferdam 13 or on a second side away from the first cofferdam 13. For example, all of the at least one pressure sensor 16 is located on the first side of the second cofferdam 14 close to the first cofferdam 13; or, for another example, all of the at least one pressure sensor 16 is located on the second side of the second cofferdam 14 away from the first cofferdam 13; or, for yet another example, one or more of the at least one pressure sensor 16 are located on the first side of the second cofferdam 14 close to the first cofferdam 13, and one or more of the at least one pressure sensor 16 are located on the second side of the second cofferdam 14 away from the first cofferdam 13.

[0054] At least one resistor R in each pressure sensor 16 is located on the same layer as one of the multilayer conductive layers in the driving transistor 121. For example, at least one resistor R in the pressure sensor 16 includes four resistors.

[0055] It should be noted that, in the embodiments disclosed herein, multiple components located on the same layer means that multiple components are formed by patterning the same material layer. Therefore, these multiple components are made of the same material and have substantially the same thickness.

[0056] In the above embodiment, at least one pressure sensor 16 is located on at least one side of the second dike 14, either near the first dike 13 or away from the first dike 13, and at least one resistor R in each pressure sensor 16 is located on the same layer as one of the multilayer conductive layers in the driving transistor 121. With this structure, the pressure sensor 16 can be formed during the formation of the sub-pixel 12 without the need for additional interactive buttons, which helps to reduce the thickness of the display panel.

[0057] In addition, the pressure sensor 16 can make full use of the space of the peripheral area 112 without increasing the size of the peripheral area 112. Therefore, some embodiments of this disclosure can reduce the thickness of the display panel while achieving a narrow bezel.

[0058] The following is combined Figure 2A This section introduces some specific implementation methods of the driver transistor 121.

[0059] See Figure 2A The driving transistor 121 includes an active layer 1211, a gate 1212, a first insulating layer 1213, a second insulating layer 1214, a third insulating layer 1215, a first electrode 1216, and a second electrode 1217. The multilayer conductive layers in the driving transistor 121 include the gate 1212, the first electrode 1216, and the second electrode 1217.

[0060] The active layer 1211 and the gate 1212 are located on one side of the substrate 11. For example, the gate 1212 is located on the side of the active layer 1211 away from the substrate 11. For example, the material of the active layer 1211 may include polysilicon. For example, the material of the gate 1212 may include Mo.

[0061] The first insulating layer 1213 is located between the active layer 1211 and the gate layer 1212. The second insulating layer 1214 is located on the side of the active layer 1211, the gate layer 1212, and the first insulating layer 1213 away from the substrate 11. The third insulating layer 1215 is located on the side of the second insulating layer 1214 away from the substrate 11. For example, the material of at least one of the first insulating layer 1213, the second insulating layer 1214, and the third insulating layer 1215 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxide nitride.

[0062] The first electrode 1216 and the second electrode 1217 are located on the side of the third insulating layer 1215 away from the substrate 11 and are electrically connected to the active layer 1211. In some embodiments, the first electrode 1216 is the drain and the second electrode 1217 is the source. For example, the first electrode 1216 and the second electrode 1217 are electrically connected to the active layer 1211 through vias penetrating the third insulating layer 1215, the second insulating layer 1214, and the first insulating layer 1213, respectively. For example, the first electrode 1216 and the second electrode 1217 may comprise a Ti / Al / Ti stack.

[0063] In some implementations, at least one resistor R and gate 1212 of pressure sensor 16 are located on the same layer.

[0064] In some implementations, at least one resistor R, the first electrode 1216, and the second electrode 1217 of the pressure sensor 16 are located on the same layer. For example, the resistor R comprises a Ti / Al / Ti stack. In this configuration, the pressure sensor 16 is more sensitive to changes in resistance under external pressure.

[0065] In some embodiments, the pixel circuit in sub-pixel 12 includes seven transistors and one capacitor. For example, in addition to driving transistor 121, sub-pixel 12 also includes a first switching transistor, a second switching transistor, and a third switching transistor. The first electrode of the first switching transistor is electrically connected to one of the multiple data lines DL, the second electrode of the first switching transistor is electrically connected to the second electrode 1217 (e.g., the source) of driving transistor 121, and the gate of the first switching transistor is electrically connected to one of the multiple gate lines GL. The first electrode of the second switching transistor is electrically connected to one of the multiple power lines PL, the second electrode of the second switching transistor is electrically connected to the second electrode 1217 (e.g., the source) of driving transistor 121, and the gate of the second switching transistor is electrically connected to one of the multiple light emission control lines GCL. The first electrode of the third switching transistor is electrically connected to the first electrode 1216 (e.g., the drain) of driving transistor 121, the second electrode of the third switching transistor is electrically connected to the anode 124, and the gate of the third switching transistor is electrically connected to one of the multiple light emission control lines GCL.

[0066] In some embodiments, see Figure 2A The sub-pixel 12 also includes a planarization layer 123, an anode 124, a pixel definition layer 125, a functional layer 126, and a cathode 127.

[0067] The planarization layer 123 is located on the side of the first electrode 1216, the second electrode 1217, and the third insulating layer 1215 away from the substrate 11. For example, the material of the planarization layer 123 may include organic insulating materials such as PI and resin materials.

[0068] The anode 124 is located on the side of the planarization layer 123 away from the substrate 11 and is electrically connected to one of the first electrode 1216 and the second electrode 1217. For example, the anode 124 is electrically connected to the first electrode 1216 via a through-hole through the planarization layer 123. For example, the material of the anode 124 may include indium tin oxide (ITO) or the like.

[0069] The pixel defining layer 125 is located on the side of the anode 124 and planarization layer 123 away from the substrate 11. The pixel defining layer 125 has a first opening V1. Here, the orthographic projection of the first opening V1 onto the substrate 11 at least partially overlaps with the orthographic projection of the anode 124 onto the substrate 11. In other words, the first opening V1 exposes at least a portion of the anode 124. For example, the material of the pixel defining layer 125 may include organic insulating materials such as PI or resin materials.

[0070] The functional layer 126 is at least partially located in the first opening V1 and on the side of the anode 124 away from the substrate 11. Here, the functional layer 126 includes at least a light-emitting layer, such as an organic light-emitting layer. In some embodiments, the functional layer 126 may also include one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer.

[0071] The cathode 127 is at least partially located in the first opening V1 and is located on the side of the functional layer 126 away from the substrate 11. For example, the cathode 127 can extend from the display area 111 to the peripheral area 112.

[0072] In some embodiments, see Figure 2B The display panel also includes a power bus 18 electrically connected to the cathode 127. Here, the power bus 18 is located in the peripheral area 112 and is on the same layer as the first electrode 1216 and the second electrode 1217. For example, a power signal can be applied to the cathode via the power bus 18.

[0073] The following describes the electrical connection between the cathode 127 and the power bus 18 according to some implementations of this disclosure.

[0074] See Figure 2BThe planarization layer 123 has a second opening V2, and the pixel defining layer 125 also has a third opening V3. Here, the orthographic projections of the second opening V2 and the third opening V3 onto the substrate 11 are located in the peripheral region 112. For example, the second opening V2 and the third opening V3 can be holes or slots. In some embodiments, the second opening V2 and the third opening V3 can be slots disposed around the display area 111.

[0075] The display panel also includes an electrical connection portion 19. The electrical connection portion 19 is at least partially located in the second opening V2 and is in contact with the power line bus 18. The cathode 127 is partially located in the third opening V3 and is in contact with the electrical connection portion 19. In addition, the electrical connection portion 19 and the anode 124 are located on the same layer.

[0076] In this manner, the cathode 127 is electrically connected to the power bus 18 via the electrical connection portion 19 located on the same layer as the anode 124.

[0077] In some embodiments, the display panel further includes an initialization bus 21 located in the peripheral region 112 and electrically connected to multiple initialization lines IL located in the display region 111. Initialization signals can be provided to the multiple initialization lines IL via the initialization bus 21. The initialization bus 21 is located between the planarization layer 123 and the substrate 11, and is located on the same layer as the first electrode 1216 and the second electrode 1217. For example, the initialization bus 21 is located between the power bus 18 and the display region 111.

[0078] In some embodiments, the display panel further includes a driving circuit 20. The driving circuit 20 is located between the power bus 18 and the initialization bus 21, and between the planarization layer 123 and the substrate 11. In some embodiments, the driving circuit 20 may include a gate driving circuit and a light-emitting control driving circuit. The gate driving circuit includes a plurality of gate driving units electrically connected to a plurality of gate lines GL, for example, a plurality of cascaded first shift registers. The light-emitting control driving circuit includes a plurality of light-emitting control driving units electrically connected to a plurality of light-emitting control lines GCL, for example, a plurality of cascaded second shift registers.

[0079] The following describes some specific implementation methods of the first cofferdam 13 and the second cofferdam 14.

[0080] In some implementations, see Figure 2B The first dam 13 includes a first layer 131 and a second layer 132 located on the side of the first layer away from the substrate 11. The first layer 131 is located on the same layer as the planarization layer 123, and the second layer 132 is located on the same layer as the pixel defining layer 125. For example, the orthographic projection of the first dam 13 on the substrate 11 overlaps with the orthographic projection of the power bus 18 on the substrate 11.

[0081] In some implementations, see Figure 2B The second dike 14 includes a third layer 141, a fourth layer 142 located on the side of the third layer 141 away from the substrate 11, and a fifth layer 143 located on the side of the fourth layer 142 away from the substrate 11. The third layer 141 is located on the same layer as the planarization layer 123, the fourth layer 142 is located on the same layer as the pixel defining layer 125, and the fifth layer 143 is located on the same layer as the support layer 24 located in the display area 111 (see...). Figure 2A The support layer 24 is located on the side of the pixel defining layer 125 away from the substrate 11. For example, the material of the support layer 24 may include organic insulating materials such as PI and resin materials.

[0082] In some embodiments, see Figure 2B The display panel also includes a crack arrestor 17 for preventing cracks from extending into the display area 111 during the cutting process. Here, the crack arrestor 17 is located on the side of the encapsulation layer 15 away from the display area 111, and the pressure sensor 16 in the display panel is located on the side of the crack arrestor 17 closer to the display area 111.

[0083] In some embodiments, the distance between the boundary of the orthographic projection of the first dam 13 on the substrate 11 near the boundary of the second dam 14 and the boundary of the orthographic projection of the second dam 14 on the substrate 11 near the boundary of the first dam 13 is a first distance; the distance between the boundary of the orthographic projection of the second dam 14 on the substrate 11 away from the first dam 13 and the boundary of the orthographic projection of the encapsulation layer 15 on the substrate 11 is a second distance; and the distance between the boundary of the orthographic projection of the encapsulation layer 15 on the substrate 11 and the boundary of the orthographic projection of the crack arrestor 17 on the substrate 11 near the boundary of the display area 111 is a third distance. Here, the first and second distances are greater than the third distance. For example, the first and second distances are greater than 50 micrometers, such as 80 micrometers, 90 micrometers, 100 micrometers, 110 micrometers, 130 micrometers, 150 micrometers, etc. For example, the third distance is 30 to 70 micrometers, such as 40 micrometers, 50 micrometers, 60 micrometers, etc. It should be understood that those skilled in the art can adjust the first, second, and third distances according to the size of the bezel of the display panel. In addition, it should be understood that the distance between two boundaries can be understood as the minimum distance from each point on one boundary to each point on the other boundary.

[0084] In some embodiments, see Figure 2A and Figure 2BThe display panel also includes a buffer layer 23 located between the substrate 11 and the first insulating layer 1213. For example, the material of the buffer layer 23 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. Here, the first insulating layer 1213, the second insulating layer 1214, and the third insulating layer 1215 extend from the display area 111 to the peripheral area 112, and the crack arrester 17 penetrates the third insulating layer 1215, the second insulating layer 1214, the first insulating layer 1213, and the buffer layer 23.

[0085] For example, the display panel has one or more trenches penetrating the third insulating layer 1215, the second insulating layer 1214, the first insulating layer 1213, and the buffer layer 23. One or more crack arresters 17 can be formed by filling the one or more trenches with a material, such as an organic material. In some embodiments, the crack arrester 17 includes multiple material layers, which may be located in the same layer as one or more of the planarization layer 123, the pixel defining layer 125, and the support layer 24. For example, the crack arrester 17 includes two material layers, each located in the same layer as the planarization layer 123 and the pixel defining layer 125, respectively.

[0086] The following describes some implementation methods for setting the position of the pressure sensor 16 in the display panel.

[0087] In some embodiments, see Figure 2B At least one pressure sensor 16 of the display panel includes a first pressure sensor 16. Here, the first pressure sensor 16 is located between the second dike 14 and the first dike 13, and the orthographic projection of the first pressure sensor 16 on the substrate 11 lies within the orthographic projection of the encapsulation layer 15 on the substrate 11. In this manner, on the one hand, the first pressure sensor 161 is covered by the encapsulation layer 15; on the other hand, the second dike 14 can block the adverse effects of water and oxygen on the first pressure sensor 161. Thus, the reliability of the first pressure sensor 161 can be improved.

[0088] In other embodiments, see Figure 2B At least one pressure sensor 16 of the display panel includes a second pressure sensor 16. Here, the second pressure sensor 162 is located between the second containment dam 14 and the crack arrestor 17, and the orthographic projection of the second pressure sensor 162 on the substrate 11 lies within the orthographic projection of the encapsulation layer 15 on the substrate 11. In this manner, the second pressure sensor 162 is covered by the encapsulation layer 15, which can reduce the adverse effects of water and oxygen on the second pressure sensor 162.

[0089] In some other embodiments, see Figure 2B At least one pressure sensor 16 of the display panel includes a third pressure sensor 163 located between the encapsulation layer 15 and the crack arrester 17.

[0090] Figure 3 This is a circuit diagram illustrating a pressure sensor according to an embodiment of the present disclosure.

[0091] like Figure 3 As shown, at least one resistor R in the display panel includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0092] The first resistor R1 is electrically connected between the first input terminal IN1 and the first output terminal OUT1. The second resistor R2 is electrically connected between the first output terminal OUT1 and the second input terminal IN2. The third resistor R3 is electrically connected between the second input terminal IN2 and the second output terminal OUT2. The fourth resistor R4 is electrically connected between the second output terminal OUT2 and the first input terminal IN1. Here, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are the same when no pressure is applied. It should be understood that this sameness is within the range of semiconductor process tolerances.

[0093] The working principle of pressure sensor 16 is explained below using the example of the first resistor R1 being subjected to external pressure, while the other three resistors are not subjected to external pressure.

[0094] An input voltage Vin is applied between the first input terminal IN1 and the second input terminal IN2. When none of them are under external pressure, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are the same, and the output voltage Vout between the first output terminal OUT1 and the second output terminal OUT2 is 0. When the first resistor R1 is under external pressure, while the other three resistors are not, the resistance value of the first resistor R1 changes, but the resistance values ​​of the other three resistors do not change; therefore, Vout is not 0. Thus, the value of Vout can be used to identify whether external pressure is applied to the first resistor R1 of the pressure sensor 16.

[0095] Regarding the signal input and signal output of the pressure sensor 16, the present disclosure also provides the following wiring method.

[0096] Figure 4A This is a cross-sectional schematic diagram showing the wiring of a pressure sensor according to an embodiment of the present disclosure.

[0097] like Figure 4A As shown, the display panel also includes a first signal output line SG1 electrically connected to the first output terminal OUT1 and a second signal output line SG2 electrically connected to the second output terminal OUT2. It should be noted that the electrical connection method between the first output terminal OUT1 and the first signal output line SG1, and the electrical connection method between the second output terminal OUT2 and the second signal output line SG2, are similar. Figure 4AWhen the output terminal shown is the first output terminal OUT1, the signal line shown in Figure 4 is the first signal output line SG1; when the output terminal shown in Figure 4 is the second output terminal OUT2, the signal line shown in Figure 4 is the second signal output line SG2.

[0098] The first signal output line SG1 and the second signal output line SG2 can be located in the same layer as one of the layers in sub-pixels 12. The following is in conjunction with... Figure 2A and Figure 4A Please provide an explanation.

[0099] See Figure 2A The sub-pixel 12 also includes a storage capacitor 122. The storage capacitor 122 includes a first electrode plate 1221 located on the same layer as the gate 1212, and a second electrode plate 1222 located between a second insulating layer 1214 and a third insulating layer 1215. It should be understood that the storage capacitor 122 also includes a second insulating layer 1214 located between the first electrode plate 1221 and the second electrode plate 1222.

[0100] In some embodiments, the first signal output line SG1 and the second signal output line SG2 are located on the same layer as one of the first electrode plate 1221 and the second electrode plate 1222.

[0101] For example, the first signal output line SG1 and the second signal output line SG2 are located on the same layer as the first electrode plate 1221. In this case, the first output terminal OUT1 can be electrically connected to the first signal output line SG1 through one or more vias penetrating the third insulating layer 1215 and the second insulating layer 1214, and the second output terminal OUT2 can be electrically connected to the second signal output line SG2 through one or more vias penetrating the third insulating layer 1215 and the second insulating layer 1214.

[0102] For example, see Figure 4A The first signal output line SG1 and the second signal output line SG2 are located on the same layer as the second electrode plate 1222. In this case, the first output terminal OUT1 can be electrically connected to the first signal output line SG1 through one or more vias penetrating the third insulating layer 1215, and the second output terminal OUT2 can be electrically connected to the second signal output line SG2 through one or more vias penetrating the third insulating layer 1215.

[0103] Figure 4B This is a cross-sectional schematic diagram showing the wiring of a pressure sensor according to another embodiment of the present disclosure.

[0104] like Figure 4BAs shown, the display panel also includes a first signal input line SI1 electrically connected to the first input / output terminal IN1 and a second signal input line SI2 electrically connected to the second input terminal IN2. It should be noted that the electrical connection method between the first input terminal IN1 and the first signal input line SI1, as well as the electrical connection method between the second input terminal IN2 and the second signal input line SI2, are similar. Figure 4B When the input terminal shown is the first input terminal IN1, Figure 4B The signal line shown is the first signal input line SI1; in Figure 4B When the input terminal shown is the second input terminal IN2, Figure 4B The signal line shown is the second signal input line SI2.

[0105] When the first signal output line SG1 and the second signal output line SG2 are located on the same layer as one of the first electrode plate 1221 and the second electrode plate 1222, the first signal input line SI1 and the second signal input line SI2 are located on the same layer as the other of the first electrode plate 1221 and the second electrode plate 1222. In other words, the two signal output lines SG1 and SG2 are located on different layers from the two signal input lines SI1 and SI2.

[0106] For example, see Figure 4B The first signal input line SI1 and the second signal input line SI2 are located on the same layer as the first electrode plate 1221. For example, the first input terminal IN1 can be electrically connected to the first signal input line SI1 through one or more vias penetrating the third insulating layer 1215 and the second insulating layer 1214, and the second input terminal IN2 can be electrically connected to the second signal input line IG2 through one or more vias penetrating the third insulating layer 1215 and the second insulating layer 1214.

[0107] This method can reduce signal interference between the two signal output lines SG1 and SG2 and the two signal input lines SI1 and SI2.

[0108] Figure 5A and Figure 5B This is a schematic diagram showing the layout of a pressure sensor according to some embodiments of the present disclosure.

[0109] exist Figure 5A and Figure 5B In this configuration, the first resistor R1 and the third resistor R3 are symmetrically arranged with respect to the first line L1, and the second resistor R2 and the fourth resistor R4 are symmetrically arranged with respect to the second line L2. For example, the first line L1 and the second line L2 are perpendicular.

[0110] In some embodiments, see Figure 5BThe first resistor R1 is located on one side of the first line L1, and the second resistor R2, the third resistor R3, and the fourth resistor R4 are located on the other side of the first line L1. In this arrangement, it is easier to arrange the four resistors such that the first resistor R1 is subjected to external pressure, while the other three resistors are not.

[0111] in addition, Figure 5A and Figure 5B The positions of the first input terminal IN1, the second input terminal IN2, the first output terminal OUT1, and the second output terminal OUT2 are schematically shown.

[0112] Figure 6 This is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure;

[0113] In step 602, a substrate is provided, the substrate including a display area and a peripheral area surrounding the display area;

[0114] In step 604, multiple sub-pixels, a first cofferdam, a second cofferdam, and at least one pressure sensor are formed. For example, the first cofferdam, the second cofferdam, and the pressure sensor can be formed simultaneously during the formation of the sub-pixels.

[0115] Multiple sub-pixels are located in the display area, and at least one of the multiple sub-pixels includes a driving transistor, which includes multiple conductive layers.

[0116] The first and second cofferdams are located in the surrounding area and surround the display area, with the second cofferdam located on the side of the first cofferdam away from the display area.

[0117] At least one pressure sensor is located on at least one side of the second cofferdam, either on a first side close to the first cofferdam or on a second side far from the first cofferdam. At least one resistor in each of the at least one pressure sensor is located in the same layer as one of the multilayer conductive layers.

[0118] In step 606, an encapsulation layer is formed on the side of the plurality of sub-pixels, the first dam, and the second dam that is away from the substrate.

[0119] Here, the orthographic projections of multiple sub-pixels, the first dike, and the second dike onto the substrate lie within the orthographic projection of the encapsulation layer onto the substrate.

[0120] In the above embodiments, at least one pressure sensor is located on at least one side of the second cofferdam, either near the first cofferdam or away from the first cofferdam, and at least one resistor R in each pressure sensor is located on the same layer as one of the multilayer conductive layers in the driving transistor. With this structure, the pressure sensor can be formed during the formation of sub-pixels, eliminating the need for additional interactive buttons and reducing the thickness of the display panel.

[0121] This disclosure also provides a display device, which may include the display panel of any of the above embodiments. In some embodiments, the display device may be, for example, any product or component with display function such as a mobile terminal, television, monitor, laptop computer, digital photo frame, navigator, electronic paper, etc.

[0122] For example, the display device is a mobile terminal. In some embodiments, by designing the bezel on the side of the mobile terminal, the first resistor R1 in the pressure sensor 16 of the display panel can be subjected to external pressure, while the other three resistors cannot be subjected to external pressure, thus causing the output voltage Vout of the pressure sensor 16 to change.

[0123] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0124] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A display panel, comprising: a substrate, comprising a display area and a peripheral area surrounding the display area; a plurality of sub-pixels located in the display area, at least one of the plurality of sub-pixels comprising a driving transistor, the driving transistor comprising a plurality of conductive layers; a first dam located in the peripheral area surrounding the display area; a second dam located in the peripheral area surrounding the display area and located on a side of the first dam away from the display area; an encapsulation layer located on a side of the plurality of sub-pixels, the first dam and the second dam away from the substrate, wherein a footprint of the plurality of sub-pixels, the first dam and the second dam on the substrate is within a footprint of the encapsulation layer on the substrate; a crack stopper located on a side of the encapsulation layer away from the display area; and at least one pressure sensor located on at least one of a first side of the second dam close to the first dam and a second side of the second dam away from the first dam, wherein at least one resistance in each of the at least one pressure sensor is in the same layer as one of the plurality of conductive layers, the at least one pressure sensor comprising: a first pressure sensor located between the second dam and the first dam, wherein a footprint of the first pressure sensor on the substrate is within the footprint of the encapsulation layer on the substrate; a second pressure sensor located between the second dam and the crack stopper, wherein a footprint of the second pressure sensor on the substrate is within the footprint of the encapsulation layer on the substrate; and a third pressure sensor located between the encapsulation layer and the crack stopper, wherein a footprint of the third pressure sensor on the substrate does not overlap with the footprint of the encapsulation layer on the substrate.

2. The display panel of claim 1, wherein, the driving transistor comprising: an active layer and a gate located on a side of the substrate; a first insulating layer located between the active layer and the gate; a second insulating layer located on a side of the active layer, the gate and the first insulating layer away from the substrate; a third insulating layer located on a side of the second insulating layer away from the substrate; and a first electrode and a second electrode located on a side of the third insulating layer away from the substrate and electrically connected to the active layer, wherein the plurality of conductive layers comprise the gate, the first electrode and the second electrode, the at least one resistance, the first electrode and the second electrode being in the same layer. 3.The display panel of claim 2, wherein: the at least one sub-pixel further comprises a storage capacitor, the storage capacitor comprising: a first electrode plate in the same layer as the gate, and a second electrode plate located between the second insulating layer and the third insulating layer. The at least one resistor includes a first resistor electrically connected between the first input terminal and the first output terminal, a second resistor electrically connected between the first output terminal and the second input terminal, a third resistor electrically connected between the second input terminal and the second output terminal, and a fourth resistor electrically connected between the second output terminal and the first input terminal, the first resistor, the second resistor, the third resistor, and the fourth resistor having the same resistance value under no pressure; and The display panel further includes a first signal output line electrically connected to the first output terminal and a second signal output line electrically connected to the second output terminal, the first signal output line and the second signal output line being located in the same layer as one of the first electrode plate and the second electrode plate.

4. The display panel of claim 3, wherein, The first signal output line and the second signal output line are located in the same layer as the second electrode plate.

5. The display panel of claim 3, further comprising: a first signal input line electrically connected to the first input terminal; and a second signal input line electrically connected to the second input terminal, the first signal input line and the second signal input line being located in the same layer as the other one of the first electrode plate and the second electrode plate.

6. The display panel of claim 5, wherein, The first resistor and the third resistor are symmetrically arranged with respect to a first line, and the second resistor and the fourth resistor are symmetrically arranged with respect to a second line.

7. The display panel of claim 6, wherein, The first line and the second line are perpendicular.

8. The display panel of claim 7, wherein, The first resistor is located on one side of the first line, and the second resistor, the third resistor, and the fourth resistor are located on the other side of the first line.

9. The display panel of any of claims 2-8, further comprising: A buffer layer is located between the substrate and the first insulating layer, wherein: The first insulating layer, the second insulating layer, the third insulating layer, and the buffer layer extend from the display area to the peripheral area, and The crack stopper penetrates through the third insulating layer, the second insulating layer, the first insulating layer, and the buffer layer.

10. The display panel of claim 2, wherein: The at least one sub-pixel further includes: a planarization layer located on a side of the first electrode, the second electrode, and the third insulating layer away from the substrate, an anode located on a side of the planarization layer away from the substrate and electrically connected to one of the first electrode and the second electrode, a pixel defining layer located on a side of the anode and the planarization layer away from the substrate and having a first opening, a projection of the first opening on the substrate at least partially overlapping a projection of the anode on the substrate, a functional layer at least partially located in the first opening and on a side of the anode away from the substrate, and a cathode at least partially located in the first opening and on a side of the functional layer away from the substrate; and The display panel further includes a power bus located in the peripheral area, electrically connected to the cathode, and located in the same layer as the first electrode and the second electrode.

11. The display panel of claim 10, wherein: The planarization layer has a second opening, and the pixel defining layer has a third opening, a normal projection of the second opening and the third opening on the substrate is located in the peripheral area; The display panel further includes an electrical connection portion, at least partially located in the second opening, located in the same layer as the anode, and in contact with the power bus line; and The cathode is partially located in the third opening, and in contact with the electrical connection portion.

12. The display panel of claim 10, further comprising: a plurality of initialization lines located in the display area, electrically connected to the plurality of sub-pixels, and configured to provide an initialization signal to the plurality of sub-pixels; and an initialization bus located in the peripheral area, located between the planarization layer and the substrate, electrically connected to the plurality of initialization lines, and located in the same layer as the first electrode and the second electrode.

13. The display panel according to any one of claims 10-12, wherein, The first coffer includes: a first layer located in the same layer as the planarization layer; and a second layer located on a side of the first layer away from the substrate, and located in the same layer as the pixel defining layer.

14. The display panel according to any one of claims 10-12, wherein, The second coffer includes: a third layer located in the same layer as the planarization layer; a fourth layer located on a side of the third layer away from the substrate, and located in the same layer as the pixel defining layer; and a fifth layer located on a side of the fourth layer away from the substrate, and located in the same layer as a support layer, wherein the support layer is located in the display area, and on a side of the pixel defining layer away from the substrate.

15. A display device comprising: The display panel of any one of claims 1-14.

16. A method of manufacturing a display panel, comprising: providing a substrate including a display area and a peripheral area surrounding the display area; forming a plurality of sub-pixels, a first coffer, a second coffer, and at least one pressure sensor, wherein: the plurality of sub-pixels are located in the display area, at least one sub-pixel of the plurality of sub-pixels includes a driving transistor, the driving transistor includes a plurality of conductive layers, the first coffer and the second coffer are located in the peripheral area and surround the display area, the second coffer is located on a side of the first coffer away from the display area, and the at least one pressure sensor is located on at least one of a first side of the second coffer close to the first coffer and a second side of the second coffer away from the first coffer, wherein at least one resistance in each pressure sensor of the at least one pressure sensor is located in the same layer as one of the plurality of conductive layers; and ​ forming a crack stopper and a packaging layer located on a side of the plurality of sub-pixels, the first dam, and the second dam away from the substrate, wherein a projection of the plurality of sub-pixels, the first dam, and the second dam on the substrate is within a projection of the packaging layer on the substrate, the crack stopper is located on a side of the packaging layer away from the display area, and the at least one pressure sensor includes a first pressure sensor located between the second dam and the first dam, a second pressure sensor located between the second dam and the crack stopper, and a third pressure sensor located between the packaging layer and the crack stopper, wherein a projection of the first pressure sensor on the substrate and a projection of the second pressure sensor on the substrate are both within the projection of the packaging layer on the substrate, and a projection of the third pressure sensor on the substrate does not overlap with the projection of the packaging layer on the substrate.

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