Semiconductor device and etching method

Abstract

Provided is an etching method capable of improving defects caused by etching when processing contact holes in a semiconductor device. The etching method includes: bonding a first polymer film to an insulating film provided on a semiconductor layer containing silicon by using plasma of a first gas; forming a deteriorated layer by oxidizing an upper surface of the insulating film while removing the first polymer film by using plasma of a second gas; bonding a second polymer film to the deteriorated layer by using plasma of a third gas; and removing the second polymer film and the deteriorated layer by using plasma of a fourth gas.

Description

Technical Field

[0001] The technology of the present disclosure (this technology) relates to semiconductor devices and etching methods. Background Art

[0002] Conventionally, various methods have been studied as etching methods for semiconductor devices. For example, Patent Document 1 discloses an etching method in which a silicon oxide film (SiO 2 film) is used as the film to be etched, and each atomic layer is removed by repeating a plasma generation process of a fluorocarbon gas and a plasma generation process of argon (Ar) gas.

[0003] [Citation List]

[0004] [Patent Document]

[0005] [Patent Document 1]

[0006] JP 2017-183688 A Summary of the Invention

[0007] Technical Problem

[0008] In addition, when processing contact holes in a semiconductor device, a silicon nitride film (SiN film) is sometimes used as an etch stop film. However, due to over-etching of the SiN film, a recess (dent) is formed in the semiconductor layer under the SiN film, and residual defects are generated at the bottom of the recess, resulting in an increase in dark current in some cases.

[0009] An object of this technology is to provide a semiconductor device and an etching method capable of reducing defects by etching when processing contact holes of a semiconductor device.

[0010] [Solution to the Problem]

[0011] In summary, a semiconductor device according to one aspect of this technology includes a silicon-containing semiconductor layer, a first insulating film provided on the semiconductor layer and having an opening, a conductive layer filled in the opening of the first insulating film and having a lower edge in contact with the semiconductor layer, and a deteriorated layer provided between the first insulating film and the conductive layer and containing oxygen.

[0012] In summary, an etching method according to one aspect of this technology includes: attracting and adhering a first polymer film to an insulating film provided on a silicon-containing semiconductor layer by plasma of a first gas; removing the first polymer film by plasma of a second gas, and oxidizing an upper surface of the insulating film exposed by removing the first polymer film to form a deteriorated layer; attracting and adhering a second polymer film to the deteriorated layer by plasma of a third gas, and removing the second polymer film and the deteriorated layer by plasma of a fourth gas. Brief Description of the Drawings

[0013] Figure 1 Figure 1 is a cross-sectional view of a semiconductor device according to the first embodiment.

[0014] Figure 2 Figure 2 is a schematic diagram of a plasma processing apparatus according to the first embodiment.

[0015] Figure 3 Figure 3 is a flowchart of an etching method of a semiconductor device according to the first embodiment.

[0016] Figure 4 Figure 4 is a process cross-sectional view of the etching method according to the first embodiment.

[0017] Figure 5 Figure 5 is the subsequent Figure 4 process cross-sectional view of the etching method according to the first embodiment.

[0018] Figure 6A Figure 6A is the subsequent Figure 5 process cross-sectional view of the etching method according to the first embodiment.

[0019] Figure 6B Figure 6B is Figure 6A a partial enlarged view of.

[0020] Figure 7A Figure 7A is the subsequent Figure 6A process cross-sectional view of the etching method according to the first embodiment.

[0021] Figure 7B Figure 7B is Figure 7A a partial enlarged view of.

[0022] Figure 8A Figure 8A is the subsequent Figure 7A process cross-sectional view of the etching method according to the first embodiment.

[0023] Figure 8B Figure 8B is Figure 8A a partial enlarged view of.

[0024] Figure 9A Figure 9A is the subsequent Figure 8A process cross-sectional view of the etching method according to the first embodiment.

[0025] Figure 9B ​​​​​​​​​​​​​​​​​​​​​​​​​Figure 9B is Figure 9A a partially enlarged view of.

[0026] Figure 10 Figure 10 is a subsequent Figure 9A process cross-sectional view of the etching method according to the first embodiment.

[0027] Figure 11 Figure 11 is a graph showing the simulation results of Ar ion penetration.

[0028] Figure 12 Figure 12 is a process cross-sectional view of the etching method according to the first comparative example.

[0029] Figure 13 Figure 13 is a subsequent Figure 12 process cross-sectional view of the etching method according to the first comparative example.

[0030] Figure 14 Figure 14 is a subsequent Figure 13 process cross-sectional view of the etching method according to the first comparative example.

[0031] Figure 15 Figure 15 is a process cross-sectional view of the etching method according to the second comparative example.

[0032] Figure 16 Figure 16 is a subsequent Figure 15 process cross-sectional view of the etching method according to the second comparative example.

[0033] Figure 17 Figure 17 is a cross-sectional view of a semiconductor device according to the second embodiment.

[0034] Figure 18 Figure 18 is a cross-sectional view of a semiconductor device according to the third embodiment.

[0035] Figure 19 Figure 19 is a process cross-sectional view of the etching method according to the fourth to sixth embodiments.

[0036] Figure 20 Figure 20 is a cross-sectional view of a semiconductor device according to the fourth embodiment.

[0037] Figure 21 Figure 21 is a cross-sectional view of a semiconductor device according to the fifth embodiment. ​​​​​​​​​​​​​​​​​​​​​​​​​

[0038] Figure 22 Figure 22 is a cross-sectional view of a semiconductor device according to the sixth embodiment.

[0039] Figure 23 Figure 23 is a block diagram of a solid-state imaging device according to the seventh embodiment.

[0040] Figure 24 Figure 24 is an equivalent circuit diagram showing a pixel according to the seventh embodiment.

[0041] Figure 25 Figure 25 is a block diagram of an electronic device according to the seventh embodiment. DETAILED DESCRIPTION

[0042] Hereinafter, first to seventh embodiments of the present technology will be described with reference to the accompanying drawings. They will be referred to in the following description. In the illustrations of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and the relationship between the thickness and the planar dimensions, the thickness ratio of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined by considering the following description. In addition, it goes without saying that the drawings also include parts having different dimensional relationships and ratios with each other. The beneficial effects described in this specification are merely exemplary and not restrictive, and other beneficial effects may be produced.

[0043] In this specification, it should be understood that the definitions of directions such as "upward" and "downward" are provided only for simplicity and are not intended to limit the technical concept of the present technology. For example, it is obvious that when an object is observed after being rotated by 90°, "upward" and "downward" are interpreted as being converted to "left" and "right", and when an object is observed after being rotated by 180°, "upward" and "downward" are interpreted as being inverted.

[0044] (First Embodiment)

[0045] <Structure of Semiconductor Device>

[0046] As Figure 1 shown, the semiconductor device according to the first embodiment includes a semiconductor layer 11 containing silicon (Si), an insulating film (lower insulating film) 12 provided on the semiconductor layer 11, an insulating film (intermediate insulating film) 13 provided on the lower insulating film 12, and an insulating film (upper insulating film) 14 provided on the intermediate insulating film 13.

[0047] ​​​​​​​​The semiconductor layer 11 is made of, for example, silicon (Si). The semiconductor layer 11 may be formed of a Si substrate and may be formed of an epitaxial growth layer epitaxially grown on the Si substrate. The semiconductor layer 11 may be formed of a compound semiconductor such as silicon carbide (SiC) and silicon germanium (SiGe).

[0048] For example, the lower insulating film 12 is made of a natural oxide film of a silicon oxide film (SiO 2 film). For example, the thickness of the lower insulating film 12 is about 1 nm, although it is not limited thereto. Alternatively, the lower insulating film 12 may be omitted, and the semiconductor layer 11 and the intermediate insulating film 13 may be in direct contact with each other.

[0049] For example, the intermediate insulating film 13 is formed of a silicon nitride film (Si 3 N 4 film). For example, the thickness of the intermediate insulating film 13 is about 30 nm - 300 nm, although it is not limited thereto. For example, the upper insulating film 14 is made of a silicon oxide film (SiO 2 film). For example, the thickness of the upper insulating film 14 is about 30 nm to 300 nm, although it is not limited thereto. Alternatively, the upper insulating film 14 may be omitted.

[0050] The lower insulating film 12, the intermediate insulating film 13, and the upper insulating film 14 are each provided with an opening (contact hole) for exposing a part of the upper surface of the semiconductor layer 11. For example, the diameter of the openings of the lower insulating film 12, the intermediate insulating film 13, and the upper insulating film 14 is about 30 nm to 100 nm, but it is not limited thereto. The openings of the lower insulating film 12, the intermediate insulating film 13, and the upper insulating film 14 are filled with a conductive layer 18. The lower edge of the conductive layer 18 is in contact with the upper surface of the semiconductor layer 11. For example, the conductive layer 18 is made of a metal material such as copper (Cu), aluminum (Al), and tungsten (W). Although not shown, wirings are connected to the upper edge of the conductive layer 18. The conductive layer 18 serves as a contact or via for electrically connecting the semiconductor layer 11 to wirings and the like. For example, the planar pattern of the conductive layer 18 is rectangular, but it can even be circular or groove-shaped.

[0051] Between the intermediate insulating film 13 and the conductive layer 18, a deteriorated layer (changed layer) 15 is formed so as to surround the side surface of the conductive layer 18. The inner surface (inner peripheral surface) of the deteriorated layer 15 is in contact with the side surface of the conductive layer 18. The thickness T1 in the circumferential direction ( Figure 1 the horizontal direction) of the conductive layer 18 sandwiched between the intermediate insulating film 13 and the deteriorated layer 15 becomes thinner toward the semiconductor layer 11. The outer surface (outer peripheral surface) in contact with the intermediate insulating film 13 of the deteriorated layer 15 has a stepped shape. Figure 1 The case where the level difference T2 of the stepped shape is substantially equal is shown. In addition, Figure 1The case where the number of steps of the stepped shape of the deteriorated layer 15 is six is shown, but the number of steps is not particularly limited and may even be one step, or may be one to five steps, and may be seven or more steps.

[0052] The deteriorated layer 15 is made of a region where the intermediate layer insulating film 13 is oxidized to change (modify) its quality. The deteriorated layer 15 is a layer containing oxygen and is composed of, for example, silicon oxide (SiO x ), such as silicon monoxide (SiO) or silicon dioxide (SiO 2 ), or silicon oxynitride (SiON). For example, the oxygen concentration in the deteriorated layer 15 may have a gradient from the inside to the outside, such that one side of the side surface in contact with the conductive layer 18 of the deteriorated layer 15 is composed of SiO x and one side of the side surface in contact with the intermediate layer insulating film 13 of the deteriorated layer 15 is composed of SiON.

[0053] Here, the passivation property of Si 3 N 4 is higher than that of SiON, and the passivation property of SiON is higher than that of SiO x . Therefore, the passivation property of the intermediate layer insulating film 13 made of Si 3 N 4 is higher than that of the deteriorated layer 15 made of SiON or SiO x .

[0054] In addition, the dielectric constant of Si 3 N 4 (7.0) is higher than that of SiON or SiO x (4.2). Therefore, the dielectric constant of the intermediate layer insulating film 13 made of Si 3 N 4 is higher than that of the deteriorated layer 15 made of SiON or SiO x .

[0055] Furthermore, the pressure tightness of SiO x is higher than that of SiON, and the pressure tightness of SiON is higher than that of Si 3 N 4 . Therefore, the pressure tightness of the deteriorated layer 15 made of SiON or SiO x is higher than that of the intermediate layer insulating film 13 made of Si 3 N 4 .

[0056] The semiconductor device according to the first embodiment can achieve a lower dielectric constant compared to the case where the oxygen-containing deteriorated layer 15 is not provided and there is no deteriorated layer 15 between the intermediate layer insulating film 13 and the conductive layer 18. Therefore, the capacitance can be reduced, and the speed of the device can be increased. In addition, compared to the case where the deteriorated layer 15 is not provided, since the pressure tightness of the deteriorated layer 15 is higher than that of the intermediate layer insulating film 13, the pressure tightness can be enhanced, and the leakage current can be reduced.

[0057] In addition, since the shorter the distance to the semiconductor layer 11, the thinner the thickness T1 in the circumferential direction of the deteriorated layer 15, the passivation characteristics for moisture and gas near the semiconductor layer 11 can be improved, and the deterioration of the device characteristics can be prevented. In addition, oxidation of the semiconductor layer 11 in the portion exposed to the contact hole can be suppressed, and an increase in contact resistance can be suppressed.

[0058] <Etching equipment>

[0059] Next, a schematic configuration of an etching apparatus (plasma processing apparatus) according to the first embodiment of the present disclosure for implementing an etching method of a semiconductor device according to the first embodiment to be described later is described. As Figure 2 shown, the plasma processing apparatus according to the first embodiment includes a processing container 21 for storing an object to be processed 100.

[0060] In the processing container 21, there are a lower electrode 23 for placing the object to be processed 100 and an upper electrode 22 provided opposite to the lower electrode 23. High-frequency power supplies 27 and 28 are respectively connected to the lower electrode 23 and the upper electrode 22. The high-frequency power supply 27 generates a high-frequency electric current (high-frequency voltage) for introducing ions into the object to be processed 100. The high-frequency power supply 28 generates a high-frequency electric current for plasma generation.

[0061] A gas supply unit 24 and an exhaust unit 26 are connected to the processing container 21. The gas supply unit 24 selectively supplies various gases, such as a processing gas, into the processing container 21 while adjusting the flow rate. The exhaust device 26 is composed of a vacuum pump such as a turbo molecular pump, and decompresses the inside of the processing container 21.

[0062] The gas supply unit 24, the exhaust unit 26, and the high-frequency power supplies 27 and 28 are electrically connected to a control unit 25. The control unit 25 controls the gas selection and flow rate of the gas supply unit 24, the exhaust volume of the exhaust unit 26, the power supply amounts of the high-frequency power supplies 27 and 28, etc. Note that Figure 2 the plasma processing apparatus shown according to the first embodiment is schematic, and actually, the plasma processing apparatus further includes various components, and their illustrations are omitted.

[0063] <Etching method>

[0064] Next, with reference to Figure 3 the flowchart of Figures 4 to 10 and the process cross-sectional view of Figure 6A and Figure 6B show the same process, and Figure 6A the enlarged view of the portion A surrounded by the dashed line in Figure 6B is Figure 7A and Figure 7B the relationship between Figure 8A and Figure 8B the relationship between Figure 9A and Figure 9B and the relationship between Figure 6A and Figure 6B are also the same as the relationship between

[0065] In Figure 3 step S1, a to-be-processed object (semiconductor wafer) that is a processing target in the etching method of the semiconductor device according to the first embodiment is prepared. As Figure 4 shown, the semiconductor wafer includes: a semiconductor layer 11; a lower insulating film 12 provided on the semiconductor layer 11; an intermediate insulating film (film to be etched) 13 provided on the lower insulating film 12; and an upper insulating film 14 provided on the intermediate insulating film 13. Alternatively, the lower insulating film 12 may not be formed. Using photolithography technology and etching technology, a part of the upper insulating film 14 is selectively removed, and an opening 14a for exposing a part of the upper surface of the intermediate insulating film 13 is formed.

[0066] Next, as Figure 2 shown, the Figure 4 shown semiconductor wafer is placed on the lower electrode 23 of the processing container 21 that is the to-be-processed object 100. Using the upper insulating film 14 as an etching mask, a part of the upper portion of the intermediate insulating film 13 is selectively removed by normal dry etching such as reactive ion etching (RIE). Therefore, as Figure 5 shown, a recess 13a having a predetermined depth is formed in the upper portion of the intermediate insulating film 13.

[0067] In Figure 3 step S2, a first gas is supplied into the processing container 21 through the Figure 2 shown gas supply unit 24 to generate plasma of the first gas. For example, the first gas contains CH x F y gas containing carbon (C), fluorine (F), and hydrogen (H). Specific examples of the first gas include trifluoromethane (CHF 3 ), difluoromethane (CH 2 F2 ) gases and fluoromethane (CH 3 F) gas. In addition, an inert gas made of rare gases such as argon (Ar) and nitrogen (N 2 ) can also be supplied into the processing container 21, and the inert gas is appropriately diluted.

[0068] In an example of the process conditions during the plasma generation of the first gas in step S2, the pressure inside the processing container 21 is set to 20 to 30 mTorr, the power of the upper electrode 22 is set to 400 to 600 W, the high-frequency voltage is set to 0 V, the flow rate of the first gas is set to 5 to 15 sccm, the flow rate of Ar gas is 400 to 600 sccm, and the processing time is 5 to 20 seconds.

[0069] As Figure 6A and Figure 6B shown, ions (shown by straight arrows) and radicals (shown by wavy arrows) contained in the plasma of the first gas deposit the first polymer film 16 on the upper surface of the upper insulating film 14 and the side surfaces of the opening 14a, as well as on the side surfaces and bottom surface of the concave portion 13a of the intermediate insulating film 13. The first polymer film 16 is attracted and adhered to the surface of the intermediate insulating film 13 located in the concave portion 13a of the intermediate insulating film 13. The first polymer film 16 is composed of, for example, a polymer containing carbon (C), fluorine (F), and hydrogen (H). The first polymer film 16 is made of, for example, hydrofluorocarbon (HFC).

[0070] In Figure 3 step S3, the inside of the processing container 21 is purged by the exhaust device 26 shown in Figure 2 to discharge the first gas supplied in step S2. For example, the processing container 21 can be subjected to a vacuum treatment, or a purging gas such as Ar gas can be supplied into the processing container 21.

[0071] In Figure 3 step S4, a second gas is supplied into the processing container 21 through the gas supply unit 24 shown in Figure 2 to generate a plasma of the second gas. The second gas is a gas containing oxygen (O). Specific examples of the second gas include oxygen (O 2 ), carbon monoxide (CO) gas, carbon dioxide (CO 2 ), nitric oxide (NO) gas, nitrogen dioxide (NO 2 ) gas, etc. In addition to the second gas, an inert gas composed of rare gases (such as argon (Ar) and nitrogen (N 2 )) can also be supplied and appropriately diluted.

[0072] In the example of the process conditions during the generation of the plasma of the second gas in step S4, the pressure inside the processing container 21 is set to 20 to 30 mTorr, the power of the upper electrode 22 is set to 300 to 500 W, the high-frequency voltage is set to 0 V, the flow rate of the second gas is set to 400 to 600 sccm, and the processing time is set to 20 to 40 seconds.

[0073] Since the plasma of the second gas contains oxygen ions and radicals, as Figure 7A and Figure 7B shown, Figure 6A and Figure 6B shown, the first polymer film 16 is removed. At this time, as Figure 6B shown, the upper part (outer layer part) 13b of the intermediate layer insulating film 13 that attracts and adheres to the first polymer film 16 (shown by a dotted line) is separated and removed. In addition, as Figure 7A and Figure 7B shown, the surface of the intermediate layer insulating film 13 is oxidized (changed) to form an oxygen-containing deteriorated layer (deteriorated layer) 15x.

[0074] The thickness T3 of the deteriorated layer 15x is at the same level in the side surface and the bottom surface of the concave portion 13a of the intermediate layer insulating film 13. For example, the thickness T3 of the deteriorated layer 15x is about 3 nm to 10 nm, and can be appropriately set by adjusting the plasma energy (high-frequency electricity) of the second gas. The higher the plasma energy of the second gas, the thicker the thickness T3 of the deteriorated layer 15x becomes, and the higher the oxygen concentration in the deteriorated layer 15x also becomes. At the same time, the upper layer insulating film 14 does not deteriorate as much as the intermediate layer insulating film 13 because the upper layer insulating film 14 initially contains oxygen.

[0075] In Figure 3 step S5, the second gas supplied to step S4 is exhausted by purifying the inside of the processing container 21 through the Figure 2 shown exhaust device 26. For example, the processing container 21 can be subjected to a vacuum treatment, or a purifying gas such as Ar gas can be supplied into the processing container 21.

[0076] In Figure 3 step S6, a third gas is supplied into the processing container 21 through the Figure 2 shown gas supply unit 24 to generate a plasma of the third gas. For example, the third gas is made of a fluorocarbon (C x F y )-type gas containing carbon and fluorine. Specific examples of the third gas include carbon tetrafluoride (CF 4 ) gas, perfluorocyclobutane (C 4 F 8 ) gas, hexafluoro-1, 3-butadiene (C 4 F 6)Gas, octafluorocyclopentene (C 5 F 8 ) gas. In addition, an inert gas made of argon (Ar), nitrogen (N 2 ) or the like can also be supplied into the processing container 21 and appropriately diluted.

[0077] Examples of the process conditions during the generation of the plasma of the third gas in step S6 are as follows: the pressure inside the processing container 21 is set to 20 to 30 mTorr, the power of the upper electrode 22 is 400 to 600 W, the high-frequency voltage is 0 V, the flow rate of the CF-based gas, as the third gas, is set to 5 to 20 sccm, the flow rate of the Ar gas is 400 to 600 sccm, and the processing time is 5 to 15 seconds.

[0078] As Figure 8A and Figure 8B shown, the ions and radicals contained in the plasma of the third gas attract and adhere the second polymer film 17 to the surface of the modified layer 15. The second polymer film 17 is composed of a CF polymer containing carbon (C) and fluorine (F).

[0079] In Figure 3 step S7, the third gas supplied to step S6 is discharged by purifying the inside of the processing container 21 through the exhaust device 26 shown in Figure 2 . For example, the processing container 21 can be subjected to a vacuum treatment, or a purifying gas such as Ar gas can be supplied into the processing container 21.

[0080] In Figure 3 step S8, a fourth gas is supplied into the processing container 21 through the gas supply unit 24 shown in Figure 2 to generate a plasma of the fourth gas. The fourth gas is a gas containing a noble gas. Specific examples of the fourth gas include helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), etc.

[0081] Examples of the process conditions during the generation of the plasma of the fourth gas in step S8 are as follows: the pressure inside the processing container 21 is set to 20 to 30 mTorr, the power of the upper electrode 22 is set to 300 to 400 W, the high-frequency voltage is set to 70 V, the flow rate of the Ar gas as the fourth gas is set to 400 to 500 sccm, and the processing time is set to 20 to 40 seconds.

[0082] As Figure 9A and Figure 9B shown, due to the inert gas ions included in the plasma of the fourth gas, the modified layer 15x separates and is removed together with the second polymer film 17. At this time, the modified layer 15x on the bottom surface of the concave portion 13a of the intermediate layer insulating film 13 is substantially completely removed, thereby removing the intermediate layer insulating film 13. At the same time, asFigure 9A As shown, since the Ar ion penetration is shallower than the bottom surface of the recess 13a, the side surface of the recess 13a of the intermediate layer insulating film 13 is removed thinner. Accordingly, the deteriorated layer 15x in the deep portion of the side surface of the recess 13a is retained.

[0083] In Figure 3 step S9, the inside of the processing container 21 is purged by the exhaust device 26 shown in Figure 2 thereby discharging the fourth gas supplied to step S8. For example, the processing container 21 may be subjected to vacuum processing, or a purging gas such as Ar gas may be supplied into the processing container 21.

[0084] In Figure 3 step S10, it is determined whether to repeat a cycle a predetermined number of times, where each cycle includes the processes of steps S2 to S9. The predetermined number of times may be set in advance to the number of times to achieve a predetermined etching amount. The predetermined number of times is one, and the processes of steps S2 to S9 do not have to be repeated. If the predetermined number of times is not repeated, the process returns to step S2, and the cycle of steps S2 to S9 is repeated. In each cycle, the process conditions may be the same or different between the cycles.

[0085] By repeatedly performing the cycle of steps S2 to S9 including Figure 3 the depth of the recess 13a of the intermediate layer insulating film 13 is deepened. Further, the thickness of the deteriorated layer 15x on the side surface of the recess 13a of the intermediate layer insulating film 13 becomes thicker each time the plasma of the second gas in step S4 is generated in each cycle. Accordingly, each cycle forms one step in the step of forming the deteriorated layer 15x.

[0086] In Figure 3 step S10, if the cycle of steps S2 to S9 is repeatedly performed a specified number of times, the polymer, the natural oxide film, etc. are removed using dilute hydrofluoric acid (DHF), and the etching process is terminated. As a result, as Figure 10 shown, the intermediate layer insulating film 13 and the lower layer insulating film 12 are removed, and openings (contact holes) are formed in the intermediate layer insulating film 13 and the lower layer insulating film 12, and a part of the upper surface of the semiconductor layer 11 is exposed. The thickness T1 in the circumferential direction of the deteriorated layer 15 becomes thinner toward the semiconductor layer 11, and the outer peripheral surface of the deteriorated layer 15 becomes a stepped shape. The level difference T2 of the stepped shape of the outer peripheral surface of the deteriorated layer 15 can be formed substantially uniformly by making the plasma energy of the second gas in step S4 the same in each cycle of Figure 3 steps S2 to S9.

[0087] Thereafter, the semiconductor device shown is manufactured by filling the conductive layer 18 in the openings (contact holes) of the lower insulating film 12, the intermediate insulating film 13, and the upper insulating film 14 by using a chemical vapor deposition (CVD) method. After removing the upper insulating film 14, the conductive layer 18 can be filled in the openings (contact holes) of the lower insulating film 12 and the intermediate insulating film 13. Figure 1 The conductive layer 18 can be filled in the openings (contact holes) of the lower insulating film 12 and the intermediate insulating film 13 after removing the upper insulating film 14.

[0088] In the etching method of the semiconductor device according to the first embodiment, the intermediate insulating film 13 made of Si3N4 is selected as the etching target, and by repeating atomic layer etching (ALE) of plasma generation and removal at least four times in the process of steps S2 to S9, each atomic layer of the intermediate insulating film 13 can be removed. Thus, a high selectivity ratio with respect to the semiconductor layer 11 can be achieved, and low-damage processing can be realized.

[0089] Figure 11 The left side of the graph in shows the result of argon (Ar) ion penetration simulation when the power of the upper electrode 22 is set to 30 W (18 eV) and processing is performed for 60 seconds using ALE. Figure 11 The solid line curve of shows the distribution of Ar ions and shows the curve obtained by converting this distribution into a continuous value with a dashed line. Figure 11 The right side of the graph in represents the composition in the depth direction from the Si surface measured using an ellipsometer. Figure 11 It shows that the depth of Ar ions penetrating into Si is 5 nm or less, the degree of the amount of Si depression, and the thickness of the damaged layer 15 is 5 nm or less.

[0090] <First Comparative Example>

[0091] Next, the etching method according to the first comparative example is described. In the etching method according to the first comparative example, as Figure 12 shown, a semiconductor wafer is prepared, which includes a semiconductor layer 11, a lower insulating film 12 provided on the semiconductor layer 11, an intermediate insulating film 13 provided on the lower insulating film 12, and an upper insulating film 14 provided on the intermediate insulating film 13. Using photolithography technology and etching technology, a part of the upper insulating film 14 is selectively removed, and an opening is formed.

[0092] Next, as Figure 13 shown, using the upper insulating film 14 as an etching mask, the intermediate insulating film 13 and the lower insulating film 12 are removed by reactive ion etching (RIE). At this time, the upper part of the semiconductor layer 11 is oxidized, and an oxide layer 11a is formed by over-etching.

[0093] Next, by performing DHF treatment, as Figure 14As shown, the oxide layer 11a on the upper part of the semiconductor layer 11 is removed to form a recess 11b, and residual defects 11c of Si are generated at the bottom of the recess 11b. Due to the formation of the recess 11b and the appearance of the residual defects 11c, the dark current increases. In addition, since slits 12a appear in the lateral direction in the lower insulating film 12, there are concerns about yield degradation and metal filling failure.

[0094] In contrast, as Figure 10 shown, according to the etching method of the semiconductor device of the first embodiment, it is possible to suppress the formation of a recess in the semiconductor layer 11 due to over-etching, or even if a recess is formed, the depth of the recess in the semiconductor layer 11 can be made shallower than the recess 11b of the first comparative example (for example, 5 nm or less). In addition, it is possible to suppress or reduce the residual defects at the bottom of the recess in the semiconductor layer 11, and thus the dark current can be reduced. Furthermore, as Figure 10 shown, it is possible to suppress the formation of slits in the lateral direction of the lower insulating film 12, and thus the yield can be increased and metal filling failure can be suppressed.

[0095] <Second Comparative Example>

[0096] Next, the etching method according to the second comparative example is described. In the etching method of the second comparative example, as Figure 12 shown, similar to the first comparative example, a semiconductor wafer is prepared, which includes a semiconductor layer 11, a lower insulating film 12 provided on the semiconductor layer 11, an intermediate insulating film 13 provided on the lower insulating film 12, and an upper insulating film 14 provided on the intermediate insulating film 13. Using photolithography and etching techniques, a part of the upper insulating film 14 is selectively removed to form an opening.

[0097] Next, a recess 13a with a predetermined depth is formed in the intermediate insulating film 13. Then, a cycle including the step of generating a plasma of a CH Figure 15 as x F y -like gas to attract and adhere the first polymer film 16 and the step of generating a plasma of an Ar gas as Figure 16 shown to remove the intermediate insulating film 13 is repeated. At this time, as Figure 16 shown, sometimes a part of the first polymer film 16 remains when the plasma of the Ar gas is generated. Therefore, the film thickness of the first polymer film 16 may be relatively thick, and if the processes shown in Figure 15 and Figure 16 are repeated, in some cases, the removal of the intermediate insulating film 13 may become difficult.

[0098] On the contrary, the etching method of the semiconductor device according to the first embodiment can be achieved by repeating Figure 3The process of steps S2 to S9 shown in [reference] easily removes the intermediate layer insulating film 13 without leaving the first polymer film 16.

[0099] (Second Embodiment)

[0100] The semiconductor device according to the second embodiment is different from Figure 1 the semiconductor device according to the first embodiment shown in [reference] in that the outer peripheral surface of the deteriorated layer 15 is a substantially curved surface (conical shape) as Figure 17 shown in [reference]. Since the step difference of the stepped shape of the outer peripheral surface of the deteriorated layer 15 is shallower and more finely formed compared to the semiconductor device according to the Figure 1 first embodiment shown in [reference], the steps are continuously connected and can be regarded as a substantially curved surface. The thickness T1 in the circumferential direction of the deteriorated layer 15 becomes thinner toward the semiconductor layer 11. Overlapping descriptions of other structures of the semiconductor device according to the second embodiment are omitted because such other structures are similar to the semiconductor device according to the Figure 1 first embodiment shown in [reference].

[0101] The etching method of the semiconductor device according to the second embodiment is similar to the etching method of the semiconductor device according to the first embodiment, and when generating Figure 3 the plasma of the second gas in step S4 shown in [reference], the plasma energy of the second gas should be reduced.

[0102] (Third Embodiment)

[0103] As Figure 18 shown in [reference], the semiconductor device according to the third embodiment is different from the semiconductor device according to the Figure 1 first embodiment shown in [reference] in the shape of the deteriorated layer 15. The outer peripheral surface of the upper portion 15a of the deteriorated layer 15 is substantially vertical, and the thickness T1 in the circumferential direction of the upper portion 15a of the deteriorated layer 15 is substantially constant. The outer peripheral surface of the lower portion 15b of the deteriorated layer 15 is stepped, and the thickness T1 in the circumferential direction of the lower portion 15b of the deteriorated layer 15 becomes thinner toward the semiconductor layer 11. Overlapping descriptions of other configurations of the semiconductor device according to the third embodiment are omitted because such other configurations are similar to the semiconductor device according to the Figure 1 first embodiment shown in [reference].

[0104] In the etching method of the semiconductor device according to the third embodiment, as Figure 5 shown in [reference], after forming the recess 13a on the intermediate layer insulating film 13, and in the etching method of the semiconductor device according to the first embodiment Figure 3Before the plasma generation of the second gas in step S2 shown, the intermediate layer insulating film 13 at the bottom of the recess 13a is removed to a predetermined depth by dry etching such as RIE. After that, the procedures of steps S2 to S9 shown in Figure 3 are repeated. As a result, the outer peripheral surface of the upper portion 15a of the deteriorated layer 15 (corresponding to the position where the intermediate layer insulating film 13 is removed by dry etching such as RIE) becomes substantially vertical, as shown in Figure 18 . At the same time, the outer peripheral surface of the lower portion 15b of the deteriorated layer 15 corresponding to the position where the intermediate layer insulating film 13 is removed by repeating the process of steps S2 to S9 shown in Figure 3 becomes a stepped shape.

[0105] According to the etching method of the semiconductor device of the third embodiment, by using normal dry etching in the first half of the etching process of the intermediate layer insulating film 13, the number of repetitions of the process of steps S2 to S9 can be reduced. At the same time, by repeating the process of steps S2 to S9 in the second half of the etching process of the intermediate layer insulating film 13, the formation of the recess in the semiconductor layer 11 can be suppressed or the depth of the depression can be reduced.

[0106] (Fourth Embodiment)

[0107] In the following fourth to sixth embodiments, an example is shown in which the plasma energy of the second gas is increased when generating the plasma of the second gas in step S4 shown compared with the etching method of the semiconductor device of the first embodiment. For example, when Figure 3 the plasma energy of the second gas in step S4 shown is increased, compared with the thickness T3 in the circumferential direction of the deteriorated layer 15x shown in Figure 3 , as shown in Figure 7A , the thickness T4 in the circumferential direction of the deteriorated layer 15x becomes thicker. Figure 19 The semiconductor device according to the fourth embodiment has the same characteristics as the semiconductor device according to the first embodiment shown in

[0108] because, as shown in Figure 1 , the outer peripheral surface of the deteriorated layer 15 has a stepped shape and the thickness T1 in the circumferential direction of the deteriorated layer 15 becomes thinner toward the semiconductor layer 11. However, the step difference T5 of the stepped shape of the outer peripheral surface of the deteriorated layer 15 of the semiconductor device according to the fourth embodiment is larger than the step difference T2 of the semiconductor device according to the first embodiment shown in Figure 20 Figure 1 . The overlapping description of other structures of the semiconductor device according to the fourth embodiment is omitted because such other structures are similar to the semiconductor device according to the first embodiment shown in Figure 1 .

[0109] ​When repeating the process of steps S2 to S9 shown in Figure 3 in the etching method of the semiconductor device according to the first embodiment, the etching method of the semiconductor device according to the fourth embodiment should be performed so that the plasma energy of the second gas is increased in step S4, as shown in Figure 19 .

[0110] In the etching method of the semiconductor device according to the fourth embodiment, the etching amount in one cycle of steps S2 to S9 shown in Figure 3 can be increased, and the number of repetitions of the process of steps S2 to S9 shown in Figure 3 can be reduced.

[0111] (Fifth Embodiment)

[0112] As shown in Figure 21 , the semiconductor device according to the fifth embodiment is different from the semiconductor device according to the first embodiment shown in Figure 1 in the shape of the upper portion 15a of the deteriorated layer 15. The outer peripheral surface of the upper portion 15a of the deteriorated layer 15 is a stepped shape, and the thickness T5 of the step of the stepped shape is substantially constant. At the same time, the outer peripheral surface of the lower portion 15b of the deteriorated layer 15 is also a stepped shape, but the thickness T2 of the step of the stepped shape is thinner than the thickness T5 of the step of the upper portion 15a of the deteriorated layer 15. The overlapping description of other structures of the semiconductor device according to the fifth embodiment is omitted because such other structures are similar to the semiconductor device according to the first embodiment shown in Figure 1 .

[0113] The etching method of the semiconductor device according to the fifth embodiment should be performed such that in the etching method of the semiconductor device according to the first embodiment, in the first half of a plurality of cycles in the process of steps S2 to S9 shown in Figure 3 in the etching method of the semiconductor device according to the first embodiment, the plasma energy of the second gas in step S4 is made relatively large. After that, in the cycles in the second half of a plurality of cycles in the process of steps S2 to S9 shown in Figure 3 , the plasma energy of the second gas in step S4 is made relatively small.

[0114] In the etching method of the semiconductor device according to the fifth embodiment, the etching amount in one cycle can be increased in the first half of a plurality of cycles, and the number of repetitions of the cycle can be reduced. On the other hand, by reducing the etching amount in one cycle, the etching accuracy in the second half of a plurality of cycles is improved, and the formation of recesses in the semiconductor layer 11 can be suppressed, or the depth of the recesses can be reduced.

[0115] (Sixth Embodiment)

[0116] The semiconductor device according to the sixth embodiment is the same asFigure 1 The semiconductor device according to the first embodiment shown differs in the shapes of the upper portion 15a and the lower portion 15b of the deteriorated layer 15, as Figure 22 shown. The outer peripheral surface of the upper portion 15a of the deteriorated layer 15 is substantially vertical, and the thickness T1 in the circumferential direction of the upper portion 15a of the deteriorated layer 15 is substantially constant. The outer peripheral surface of the lower portion 15b of the deteriorated layer 15 is in a stepped shape. Note that although the number of steps of the stepped shape of the lower portion 15b of the deteriorated layer 15 is one in Figure 22 , the number can be plural. A repeated description of other configurations of the semiconductor device according to the sixth embodiment is omitted because such other configurations are similar to those of the semiconductor device according to the Figure 1 first embodiment shown.

[0117] In the etching method of the semiconductor device according to the sixth embodiment, as Figure 5 shown, a recess 13a is formed on the intermediate layer insulating film 13. Thereafter, in the etching method of the semiconductor device according to the first embodiment, the intermediate layer insulating film 13 at the bottom of the recess 13a is removed to a predetermined depth by dry etching such as RIE. Thereafter, the processes of steps S2 to S9 shown in Figure 3 are repeated as long as the plasma energy of the second gas in step S4 is relatively greater than the plasma energy in the etching method of the semiconductor device according to the first embodiment. As a result, the outer peripheral surface (corresponding to the position where the intermediate layer insulating film 13 is removed by dry etching such as RIE) of the upper portion 15a of the deteriorated layer 15 becomes substantially vertical, as Figure 22 shown. At the same time, the outer peripheral surface of the lower portion 15b of the deteriorated layer 15 corresponding to the position where the intermediate layer insulating film 13 is removed by repeating the processes of steps S2 to S9 shown in Figure 3 becomes a stepped shape.

[0118] In the etching method of the semiconductor device according to the sixth embodiment, by using normal dry etching in the first half etching process of the intermediate layer insulating film 13, the number of repetitions of the processes of steps S2 to S9 can be reduced. At the same time, by repeating the processes of steps S2 to S9 in the latter half of the etching process of the intermediate layer insulating film 13, the formation of recesses in the semiconductor layer 11 can be suppressed or the depth of the recesses can be reduced.

[0119] (Seventh Embodiment)

[0120] In the seventh embodiment, a solid-state imaging device and an electronic device to which the semiconductor devices of the first to sixth embodiments can be applied are listed as examples.

[0121] <Electronic Device>

[0122] As an example of a solid-state imaging device according to the seventh embodiment, a CMOS (Complementary Metal Oxide Semiconductor) image sensor is described. The solid-state imaging device according to the seventh embodiment includes a pixel region (imaging region) 3 and peripheral circuits (4, 5, 6, 7, and 8), where pixels 2 are arranged in a matrix, and the peripheral circuits process pixel signals output from the pixel region 3, as Figure 23 shown.

[0123] Pixels 2 generally have a photoelectric conversion region made of a photodiode that electrically converts incident light and a plurality of pixel transistors to read signal charges generated by photoelectric conversion in the photoelectric conversion region. For example, the plurality of pixel transistors can be made of three transistors: a transfer transistor, a reset transistor, and an amplifier transistor. Alternatively, the plurality of pixel transistors can be made of four transistors that also include a selection transistor.

[0124] The peripheral circuits (4, 5, 6, 7, and 8) include a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The control circuit 8 receives an input clock and data indicating a movement mode or the like, and outputs data such as internal information of the solid-state imaging device. For example, the control circuit 8 generates a clock signal or a control signal based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock as a reference for operating the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc. The control circuit 8 outputs the generated clock signal or control signal to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0125] For example, the vertical drive circuit 4 is composed of a shift register. The vertical drive circuit 4 selects pixel drive wirings, supplies pulses for driving pixels 2 to the selected pixel drive wirings, and drives pixels 2 in units of rows. For example, the vertical drive circuit 4 sequentially performs selection scanning on pixels 2 in the pixel region 3 in units of rows in the vertical direction, and supplies pixel signals based on signal charges generated according to the amount of light received by the photodiodes that serve as the photoelectric conversion regions of each pixel 2 to the column signal processing circuit 5 through the vertical signal lines 9.

[0126] The column signal processing circuit 5 is located, for example, in each row of pixels 2. The column signal processing circuit 5 performs signal processing on the signals output from pixels 2 for each row of each pixel column, such as noise reduction. For example, the column signal processing circuit 5 performs signal processing such as CDS, signal amplification, AD conversion, etc. to remove fixed pattern noise peculiar to pixels 2. A horizontal selection switch (not shown) is connected and provided between the output terminal of the column signal processing circuit 5 and the horizontal signal line 10.

[0127] For example, the horizontal drive circuit 6 is composed of a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scan pulses, thereby sequentially selecting each of the column signal processing circuits 5 and outputting pixel signals from each of the column signal processing circuits 5 to the horizontal signal lines 10.

[0128] The output circuit 7 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal lines 10 and outputs pixel signals. For example, the output circuit 7 may only perform buffering, or may perform black level adjustment, column change correction, various types of digital signal processing, etc. The input / output terminal 31 exchanges signals with the outside.

[0129] In Figure 23 , the pixel region 3 and the peripheral circuits (4, 5, 6, 7, and 8) of the solid-state imaging device according to the seventh embodiment are formed on one substrate 1, but may be formed as a laminated structure in which a plurality of substrates are laminated. For example, the solid-state imaging device according to the seventh embodiment may be made of a first substrate and a second substrate, and the photoelectric conversion region and pixel transistors may be provided on the first substrate, and the peripheral circuits (3, 4, 5, 6, and 7), etc. may be provided on the second substrate. Alternatively, a configuration may be adopted in which a part of the photoelectric conversion region and pixel transistors is provided on the first substrate, and a part of the remaining pixel transistors and peripheral circuits (3, 4, 5, 6, and 7), etc. is provided on the second substrate.

[0130] Figure 24 An example of an equivalent circuit of the pixel 2 of the solid-state imaging device according to the seventh embodiment is shown. The anode of the photodiode PD is grounded. The photodiode PD is the photoelectric conversion region of the pixel 2. The source of the transfer transistor T1 is connected to the cathode of the photodiode PD. The transfer transistor T1 is an active element. The floating diffusion region FD is connected to the drain of the transfer transistor T1. The floating diffusion region FD is connected to the source of the reset transistor T2, which is an active element, and the gate of the amplification transistor T3, which is an active element. The source of the amplification transistor T3 is connected to the drain of the selection transistor T4, which is an active element, and the drain of the amplification transistor T3 is connected to the power supply Vdd. The source of the selection transistor T4 is connected to the vertical signal line VSL. The drain of the reset transistor T2 is connected to the power supply Vdd.

[0131] During the operation of the solid-state imaging device according to the seventh embodiment, a control potential TRG is applied to the transfer transistor T1, and the signal charge generated in the photodiode PD is transferred to the floating diffusion region FD. The signal charge transferred to the floating diffusion region FD is read out and applied to the gate of the amplifying transistor T3. A selection signal SEL of a horizontal line is given from the vertical shift register to the gate of the selection transistor T4. The selection transistor T4 is turned on by making the selection signal SEL at a high (H) level, and a current corresponding to the potential of the floating diffusion region FD amplified in the amplifying transistor T3 flows into the vertical signal line VSL. Further, the reset transistor T2 is turned on by making the reset signal RST applied to the gate of the reset transistor T2 at a high (H) level and resetting the signal charge accumulated in the floating diffusion region FD.

[0132] For example, the semiconductor device according to the first to sixth embodiments may be a semiconductor device including a semiconductor layer (diffusion layer) connected to a conductive layer (contact) filled in a contact hole, such as the Figure 24 photodiode PD, transfer transistor T1, reset transistor T2, amplifying transistor T3, and selection transistor T4 shown in

[0133] <Electronic device>

[0134] Figure 25 is a block diagram showing a configuration example of an imaging device as an electronic device to which the present disclosure is applied. Figure 25 The imaging device 1000 of

[0135] is a camera or a digital still camera or the like. The imaging device 1000 includes a lens unit 1001, a solid-state imaging device 1002, a DSP circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to each other via a bus 1009.

[0136] The DSP circuit 1003 performs predetermined image processing on the pixel signals provided from the solid-state image pickup device 1002, supplies the pixel signals after the image processing to the frame memory 1004 in the frame unit, and the pixel signals are temporarily stored in the frame memory 1004.

[0137] For example, the display unit 1005 is made of a panel-type display device such as a liquid crystal panel or an organic EL (electroluminescence) panel, and displays an image based on the pixel signals in the frame unit (temporarily stored in the frame memory 1004).

[0138] The recording unit 1006 is made of a DVD (Digital Versatile Disc), a flash memory, etc., and reads out the pixel signals and stores them in the frame unit temporarily stored in the frame memory 1004.

[0139] The operation unit 1007 issues operation commands for various functions of the image pickup device 1000 based on the user's operation. The power supply unit 1008 appropriately supplies power to the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007.

[0140] In addition to the image pickup device 1000, the electronic device to which this technology is applied can be any device that uses a CMOS image sensor in the image pickup unit (photoelectric conversion unit), and can be a mobile terminal device having an image pickup function, a copying machine that uses a CMOS image sensor in an image reader, etc.

[0141] (Other embodiments)

[0142] Although the present technology has been described above in the form of the first embodiment to the seventh embodiment, it should be understood that the description and drawings that form part of this disclosure limit the present technology. When understanding the purpose of the technical content disclosed by the above embodiments, it is obvious to those skilled in the art that various alternative embodiments, examples, and operable technologies are included in the present technology. In addition, the respective structures disclosed in the first to seventh embodiments can be appropriately combined within a non-contradictory range.

[0143] Examples of applications of this disclosure include an infrared light receiving element, and an image pickup device and an electronic device using the infrared light receiving element. Possible uses include a conventional camera, a smart phone, and various applications for imaging and sensing, including a surveillance camera, a camera for industrial instruments (such as for factory inspection), a vehicle-mounted camera, a distance measurement sensor (ToF sensor), an infrared sensor, etc. Examples thereof are described below.

[0144] This technology can also adopt the following configuration.

[0145] (1) A semiconductor device, comprising:

[0146] A semiconductor layer containing silicon;

[0147] A first insulating film disposed on the semiconductor layer and having an opening for exposing a part of the semiconductor layer;

[0148] A conductive layer filled in the opening of the first insulating film and having a lower edge in contact with the semiconductor layer; and

[0149] A deteriorated layer disposed between the first insulating film and the conductive layer and containing oxygen.

[0150] (2) The semiconductor device according to (1), wherein

[0151] The deteriorated layer has a thickness between the first insulating film and the conductive layer, and the thickness becomes thinner toward the semiconductor layer.

[0152] (3) The semiconductor device according to (2), wherein

[0153] The side surface of the deteriorated layer in contact with the first insulating film has a stepped shape.

[0154] (4) The semiconductor device according to (3), wherein

[0155] The level difference of the stepped shape at the lower part of the deteriorated layer is smaller than the level difference of the stepped shape at the upper part of the semiconductor layer.

[0156] (5) The semiconductor device according to any one of (1) to (4), wherein

[0157] The relative permittivity of the deteriorated layer is lower than the relative permittivity of the first insulating film.

[0158] (6) The semiconductor device according to any one of (1) to (5), wherein

[0159] The first insulating film is made of silicon nitride.

[0160] (7) The semiconductor device according to any one of (1) to (6), wherein

[0161] The deteriorated layer contains silicon oxide or silicon oxynitride.

[0162] (8) The semiconductor device according to any one of (1) to (7), further comprising:

[0163] A second insulating film disposed between the semiconductor layer and the first insulating film.

[0164] (9) The semiconductor device according to (8), wherein

[0165] The second insulating film is made of silicon oxide.

[0166] The semiconductor device according to any one of (1) to (9) further includes:

[0167] A third insulating film provided on the first insulating film.

[0168] The semiconductor device according to (10), wherein

[0169] The third insulating film is made of a silicon oxide film.

[0170] An etching method, comprising:

[0171] Attracting and adhering a first polymer film to an insulating film on a semiconductor layer containing silicon by plasma of a first gas;

[0172] Removing the first polymer film by plasma of a second gas, and oxidizing an upper surface of the insulating film exposed by removing the first polymer film to form a deteriorated layer;

[0173] Attracting and adhering a second polymer film to the deteriorated layer by plasma of a third gas; and

[0174] Removing the second polymer film and the deteriorated layer by plasma of a fourth gas.

[0175] The etching method according to (12), wherein

[0176] The first gas contains carbon, hydrogen, and fluorine.

[0177] The etching method according to (12) or (13), wherein

[0178] The second gas contains oxygen.

[0179] The etching method according to any one of (12) to (14), wherein

[0180] The third gas contains carbon and fluorine.

[0181] The etching method according to any one of (12) to (15), wherein

[0182] The fourth gas contains a noble gas.

[0183] The etching method according to any one of (12) to (16) further includes:

[0184] Before attracting and adhering the first polymer film;

[0185] Removing an upper portion of the insulating film by dry etching.

[0186] (18) The etching method according to any one of (12) to (17), wherein,

[0187] Repeat multiple cycles, each cycle including attracting and adhering a first polymer film, forming a deteriorated layer, attracting and adhering a second polymer film, and removing the deteriorated layer.

[0188] (19) The etching method according to (18), wherein,

[0189] The plasma energy of the second gas is made the same in each of the multiple repeated cycles.

[0190] (20) The etching method according to (18), wherein,

[0191] The plasma energy of the second gas in the latter half of the multiple cycles is made less than the plasma energy of the second gas in the first half of the multiple cycles.

[0192] [Reference numeral list]

[0193] 1 Substrate

[0194] 2 Pixel

[0195] 3 Pixel region (imaging region)

[0196] 4 Vertical drive circuit

[0197] 5 Column signal processing circuit

[0198] 6 Horizontal drive circuit

[0199] 7 Output circuit

[0200] 8 Control circuit

[0201] 9 Vertical signal line

[0202] 10 Horizontal signal line

[0203] 11 Semiconductor layer

[0204] 11a Oxide layer

[0205] 11b Recess (depression)

[0206] 11c Residual defect

[0207] 12 Insulating film (lower insulating film)

[0208] 12a Slit

[0209] 13 Insulating film (intermediate insulating film)

[0210] 13a Recess

[0211] Upper part of 13b

[0212] 14 Insulating film (upper insulating film)

[0213] 14a Opening

[0214] 15 Metamorphic layer (modified layer)

[0215] Upper part of 15a

[0216] Lower part of 15b

[0217] 18 Conductive layer

[0218] 21 Processing container

[0219] 22 Upper electrode

[0220] 22 Electrode

[0221] 23 Lower electrode

[0222] 24 Gas supply unit

[0223] 25 Control unit

[0224] 26 Exhaust unit

[0225] 27, 28 High-frequency power supply

[0226] 31 Input and output terminals

[0227] 100 Object to be processed

[0228] 1000 Image pickup device

[0229] 1001 Lens group

[0230] 1002 Solid-state image pickup device

[0231] 1003 DSP circuit

[0232] 1004 Frame memory

[0233] 1005 Display unit

[0234] 1006 Recording unit

[0235] 1007 Operation unit

[0236] 1008 Power supply unit

[0237] 1009 Bus

Claims

1. A semiconductor device, comprising: a semiconductor layer containing silicon; a first insulating film provided on the semiconductor layer and having an opening for exposing a part of the semiconductor layer; a conductive layer filled in the opening of the first insulating film and having a lower edge in contact with the semiconductor layer; and a modified layer provided between the first insulating film and the conductive layer and containing oxygen, wherein, the opening of the first insulating film is formed by an etching method, the etching method comprising: attracting and adhering a first polymer film to the insulating film by plasma of a first gas, the insulating film being provided on a semiconductor layer containing silicon; removing the first polymer film by plasma of a second gas, and oxidizing an upper surface of the insulating film exposed by removing the first polymer film to form a modified layer; attracting and adhering a second polymer film to the modified layer by plasma of a third gas; and removing the second polymer film and the modified layer by plasma of a fourth gas, wherein, before attracting and adhering the first polymer film; removing an upper portion of the insulating film by dry etching; and repeating a plurality of cycles, each cycle including attracting and adhering the first polymer film, forming the modified layer, attracting and adhering the second polymer film, and removing the modified layer.

2. The semiconductor device according to claim 1, wherein, the modified layer has a thickness between the first insulating film and the conductive layer, and the thickness becomes thinner toward the semiconductor layer.

3. The semiconductor device according to claim 2, wherein, a side surface of the modified layer in contact with the first insulating film has a stepped shape.

4. The semiconductor device according to claim 3, wherein, a level difference of the stepped shape at a lower portion of the modified layer is smaller than a level difference of the stepped shape at an upper portion of the semiconductor layer.

5. The semiconductor device according to claim 1, wherein, a relative dielectric constant of the modified layer is lower than a relative dielectric constant of the first insulating film.

6. The semiconductor device according to claim 1, wherein, the first insulating film is made of silicon nitride.

7. The semiconductor device according to claim 1, wherein, the modified layer contains silicon oxide or silicon oxynitride.

8. The semiconductor device according to claim 1, further comprising: a second insulating film provided between the semiconductor layer and the first insulating film.

9. The semiconductor device according to claim 8, wherein, the second insulating film is made of silicon oxide.

10. The semiconductor device according to claim 1, further comprising: a third insulating film provided on the first insulating film.

11. The semiconductor device according to claim 10, wherein, the third insulating film is made of a silicon oxide film.

12. An etching method, comprising: attracting and adhering a first polymer film to the insulating film by plasma of a first gas, the insulating film being provided on a semiconductor layer containing silicon; removing the first polymer film by plasma of a second gas, and oxidizing an upper surface of the insulating film exposed by removing the first polymer film to form a modified layer; Attract and adhere the second polymer film to the deteriorated layer by plasma of a third gas; and Remove the second polymer film and the deteriorated layer by plasma of a fourth gas, wherein, before attracting and adhering the first polymer film; Remove the upper portion of the insulating film by an etching method and form an opening.

13. The etching method according to claim 12, wherein, The first gas contains carbon, hydrogen and fluorine.

14. The etching method according to claim 12, wherein, The second gas contains oxygen.

15. The etching method according to claim 12, wherein, The third gas contains carbon and fluorine.

16. The etching method according to claim 12, wherein, The fourth gas contains a noble gas.

17. The etching method according to claim 12, wherein, Repeat multiple cycles, each cycle including attracting and adhering the first polymer film, forming the deteriorated layer, attracting and adhering the second polymer film, and removing the deteriorated layer.

18. The etching method according to claim 17, wherein, Make the plasma energy of the second gas the same in each of the multiple repeated cycles.

19. The etching method according to claim 17, wherein, Make the plasma energy of the second gas in the latter half of the multiple cycles less than the plasma energy of the second gas in the former half of the multiple cycles.

Images