All-around gate transistor with high charge mobility channel material

Abstract

A semiconductor device (200) is disclosed, which includes an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor (206) having a high charge mobility channel material and a P-type metal oxide semiconductor (PMOS) GAA transistor (222). The semiconductor device may include a substrate (202). The semiconductor device may further include an NMOS GAA transistor on the substrate, where the NMOS GAA transistor includes a first channel material (210, 214). The semiconductor device may further include a PMOS GAA transistor on the substrate, where the PMOS GAA transistor includes a second channel material (230, 234). The first channel material may have an electron mobility greater than the electron mobility of silicon (Si), and the second channel material may have a hole mobility greater than the hole mobility of Si.

Description

[0001] Priority Claim

[0002] This patent application claims the priority of the non - provisional application No. 16 / 749,897, titled "GATE ALL AROUND TRANSISTORS WITH HIGH CHARGE MOBILITY CHANNEL MATERIALS", filed on January 22, 2020, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] Certain aspects of the present disclosure generally relate to transistors, and more particularly, to gate - all - around transistors with high - charge - mobility channel materials. BACKGROUND ART

[0004] Transistors are essential components in modern electronic devices. As modern electronic devices become increasingly complex in function, an increasing number of transistors are integrated in such devices. This increase in the number of transistors is achieved in part by continuous efforts to reduce the size of transistors. As transistors become smaller, the gate length of the transistors decreases accordingly, resulting in reduced gate control and degraded transistor performance. To overcome these problems, gate - all - around transistors have been developed. Gate - all - around transistors such as fin - field - effect transistors and gate - all - around (GAA) transistors include gate material that wraps around at least a portion of the channel structure to provide better gate control over the channel region. Taking the GAA transistor as an example, it includes gate material surrounding the channel region.

[0005] Silicon (Si) is a semiconductor material widely used in transistors. In GAA transistors, Si is typically used as the channel material. However, compared with some other semiconductor materials, Si has a lower charge mobility, which limits the performance of GAA transistors. To further improve the performance of GAA transistors, a channel material with a higher charge mobility is desired. SUMMARY OF THE INVENTION

[0006] Certain aspects of the present disclosure provide a semiconductor device. The semiconductor device may include a substrate. The semiconductor device may further include an N - type metal - oxide - semiconductor (NMOS) gate - all - around (GAA) transistor on the substrate, where the NMOS GAA transistor includes a first channel material. The semiconductor device may further include a P - type metal - oxide - semiconductor (PMOS) GAA transistor on the substrate, where the PMOS GAA transistor includes a second channel material. The first channel material may have an electron mobility greater than the electron mobility of silicon (Si), and the second channel material may have a hole mobility greater than the hole mobility of Si.

[0007] Certain aspects of the present disclosure provide a method for manufacturing a semiconductor device. The method may include forming an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor on a substrate, wherein the NMOS GAA transistor includes a first channel material. The method may further include forming a P-type metal oxide semiconductor (PMOS) GAA transistor on the substrate, wherein the PMOS GAA transistor includes a second channel material. The first channel material may have an electron mobility greater than the electron mobility of silicon (Si), and the second channel material may have a hole mobility greater than the hole mobility of Si.

[0008] This summary outlines features and embodiments of the present disclosure so that the detailed description below may be better understood. Additional features and embodiments of the present disclosure will be described below. Those skilled in the art should understand that the present disclosure can be readily used as a basis for modifying or designing other equivalent structures for carrying out the same purposes of the present disclosure. Those skilled in the art should also recognize that such equivalent configurations do not depart from the teachings of the present disclosure as set forth in the appended claims. When considered in conjunction with the accompanying drawings, the features that are considered to be characteristics of the present disclosure (both in terms of its organization and method of operation) will be better understood from the following description. However, it should be clearly understood that each figure in the drawings is provided for purposes of illustration and description only and is not intended as a definition of the limitations of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Illustrates an exemplary semiconductor device that includes an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor and a P-type metal oxide semiconductor (PMOS) GAA transistor;

[0010] Figure 2 Illustrates an exemplary semiconductor device according to certain aspects of the present disclosure that includes an NMOS GAA transistor and a PMOS GAA transistor having high charge mobility channel materials;

[0011] Figures 3A - 3F Illustrates, according to certain aspects of the present disclosure Figure 2 an exemplary manufacturing process of the semiconductor device in; and

[0012] Figure 4 is a block diagram showing an exemplary wireless communication system in which an aspect of the present disclosure can be employed. DETAILED DESCRIPTION

[0013] With reference to the accompanying drawings, several exemplary aspects of the present disclosure are described. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0014] In conjunction with the accompanying drawings, the specific embodiments described below are intended as descriptions of various aspects and are not intended to represent the only aspects in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the specific embodiments include specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0015] Figure 1 An exemplary semiconductor device is illustrated, which includes an N-type metal-oxide semiconductor (NMOS) gate-all-around (GAA) transistor and a P-type metal-oxide semiconductor (PMOS) GAA transistor. Figure 1 Semiconductor device 100 is shown in. Semiconductor device 100 includes a substrate 102. As an example, substrate 102 may include silicon (Si). Semiconductor device 100 further includes an NMOS GAA transistor 104 on substrate 102. NMOS GAA transistor 104 includes a plurality of alternating gate layers and channel layers, such as a first gate layer 106 on substrate 102, a first channel layer 108 on the first gate layer 106, a second gate layer 110 on the first channel layer 108, and a second channel layer 112 on the second gate layer 110. As an example, the first gate layer 106 and the second gate layer 110 may include hafnium oxide (HfO2) and titanium aluminum nitride (TiAlN). The first channel layer 108 and the second channel layer 112 may include Si. NMOS GAA transistor 104 further includes a first oxide layer 114 that wraps around the plurality of alternating gate layers and channel layers. As an example, the first oxide layer 114 may include silicon dioxide (SiO2). NMOS GAA transistor 104 further includes a first metal gate layer 116 that wraps around the first oxide layer 114. As an example, the first metal gate layer 116 may include tungsten (W). NMOS GAA transistor 104 further includes a first gate contact 118 on the first metal gate layer 116. As an example, the first gate contact 118 may include tungsten.

[0016] The semiconductor device 100 further includes a PMOS GAA transistor 120 on a substrate 102. The semiconductor device 100 further includes an isolation structure 122 between the NMOS GAA transistor 104 and the PMOS GAA transistor 120 to isolate the NMOS GAA transistor 104 from the PMOS GAA transistor 120. As an example, the isolation structure 122 may include a shallow trench isolation (STI) region. As an example, the STI region may include SiO2. The PMOS GAA transistor 120 includes a plurality of alternating gate layers and channel layers, such as a third gate layer 124 on the substrate 102, a third channel layer 126 on the third gate layer 124, a fourth gate layer 128 on the third channel layer 126, and a fourth channel layer 130 on the fourth gate layer 128. As an example, the third gate layer 124 and the fourth gate layer 128 may include HfO2 and titanium nitride (TiN). The third channel layer 126 and the fourth channel layer 130 may include Si. The PMOS GAA transistor 120 further includes a second oxide layer 132 surrounding the plurality of alternating gate layers and channel layers. As an example, the second oxide layer 132 may include SiO2. The PMOS GAA transistor 120 further includes a second metal gate layer 134 surrounding the second oxide layer 132. As an example, the second metal gate layer 134 may include tungsten. The PMOS GAA transistor 120 further includes a second gate contact 136 on the second metal gate layer 134. As an example, the second gate contact 136 may include tungsten. The semiconductor device 100 further includes a dielectric layer 138 covering the NMOS GAA transistor 104 and the PMOS GAA transistor 120. As an example, the dielectric layer 138 may include at least one of SiO2, silicon oxynitride, and silicon carbon oxynitride.

[0017] The charge mobility of the channel material can affect the performance of the GAA transistor. The charge mobility includes the electron mobility for NMOS and the hole mobility for PMOS. Silicon has an electron mobility of 1400 cm 2 / vs and a hole mobility of 450 cm 2 / vs, which is relatively low compared to some other semiconductor materials. To improve the performance of the GAA transistor, a channel material with a higher charge mobility is desired.

[0018] Figure 2 An exemplary semiconductor device in accordance with certain aspects of the present disclosure is illustrated that includes an NMOS GAA transistor and a PMOS GAA transistor having a high charge mobility channel material. Figure 2A semiconductor device 200 is shown. The semiconductor device 200 includes a substrate 202. As an example, the substrate 202 may include at least one of germanium (Ge), gallium arsenide (GaAs), Ge / Si (a germanium layer on a silicon substrate), and GaAs / Si (a gallium arsenide layer on a silicon substrate). The semiconductor device 200 further includes an etch stop layer 204 on the substrate 202. As an example, the etch stop layer 204 may include at least one of GaAs and aluminum arsenide (AlAs). The semiconductor device 200 further includes an NMOS GAA transistor 206 on the etch stop layer 204. The NMOS GAA transistor 206 includes a plurality of alternating gate layers and channel layers, such as a first gate layer 208 on the etch stop layer 204, a first channel layer 210 on the first gate layer 208, a second gate layer 212 on the first channel layer 210, and a second channel layer 214 on the second gate layer 212. As an example, the first gate layer 208 and the second gate layer 212 may include HfO2 and TiAlN. The first channel layer 210 and the second channel layer 214 may include a semiconductor material having an electron mobility higher than that of silicon, such as GaAs, which has an electron mobility of 8500 cm 2 2 / V·s. The NMOS GAA transistor 206 further includes a first oxide layer 216 wrapped around the plurality of alternating gate layers and channel layers. As an example, the first oxide layer 216 may include SiO2. The NMOS GAA transistor 206 further includes a first metal gate layer 218 wrapped around the first oxide layer 216. As an example, the first metal gate layer 218 may include tungsten. The NMOS GAA transistor 206 further includes a first gate contact 220 on the first metal gate layer 218. As an example, the first gate contact 220 may include tungsten.

[0019] The semiconductor device 200 further includes a PMOS GAA transistor 222 on the isolation layer 224. The isolation layer 224 is between the PMOS GAA transistor 222 and the etch stop layer 204. As an example, the isolation layer 224 may include N-type doped Ge. The semiconductor device 200 further includes an isolation structure 226 between the NMOS GAA transistor 206 and the PMOS GAA transistor 222 to isolate the NMOS GAA transistor 206 from the PMOS GAA transistor 222. As an example, the isolation structure 226 may include a STI region. As an example, the STI region may include SiO2. The PMOS GAA transistor 222 includes a plurality of alternating gate layers and channel layers, such as a third gate layer 228 on the isolation layer 224, a third channel layer 230 on the third gate layer 228, a fourth gate layer 232 on the third channel layer 230, and a fourth channel layer 234 on the fourth gate layer 232. As an example, the third gate layer 228 and the fourth gate layer 232 may include HfO2 and TiN. The third channel layer 230 and the fourth channel layer 234 may include a semiconductor material having a hole mobility higher than that of silicon, such as Ge, which has a hole mobility of 1900 cm 2 / vs. The PMOS GAA transistor 222 further includes a second oxide layer 236 wrapped around the plurality of alternating gate layers and channel layers. As an example, the second oxide layer 236 may include SiO2. The PMOS GAA transistor 222 further includes a second metal gate layer 238 wrapped around the second oxide layer 236. As an example, the second metal gate layer 238 may include W. The PMOS GAA transistor 222 further includes a second gate contact 240 on the second metal gate layer 238. As an example, the second gate contact 240 may include tungsten. The semiconductor device 200 further includes a dielectric layer 242 covering the NMOS GAA transistor 206 and the PMOS GAA transistor 222. As an example, the dielectric layer 242 may include at least one of SiO2, silicon oxynitride, and silicon oxycarbide.

[0020] As described above, the charge mobility of the channel material can affect the performance of the GAA transistor. Therefore, by replacing silicon in the channel layer with a high charge mobility material (such as gallium arsenide for the NMOS GAA transistor and germanium for the PMOS GAA transistor as shown in the semiconductor device 200), the performance of the GAA transistor can be improved.

[0021] Figures 3A - 3F An exemplary manufacturing process of the semiconductor device 200 in Figure 2 is illustrated according to certain aspects of the present disclosure. In Figure 3AIn stage 300(1), an etch stop layer 304 is formed on a substrate 302. As an example, the substrate 302 may include at least one of Ge, GaAs, Ge / Si, and GaAs / Si. The etch stop layer 304 may include at least one of GaAs and AlAs. The etch stop layer 304 may be lattice matched to the substrate 302. Stage 300(1) further includes forming an isolation layer 306 on the etch stop layer 304. As an example, the isolation layer 306 may include N-type doped Ge. The isolation layer 306 may be formed by epitaxial growth. Stage 300(1) further includes forming a plurality of alternating first material layers and second material layers on the isolation layer 306. The plurality of alternating first material layers and second material layers may be formed by epitaxial growth. As an example, the plurality of alternating first material layers and second material layers may include a first GaAs layer 308 on the isolation layer 306, a first Ge layer 310 on the first GaAs layer 308, a second GaAs layer 312 on the first Ge layer 310, and a second Ge layer 314 on the second GaAs layer 312. The last layer 316 of the plurality of alternating first material layers and second material layers may include a GaAs layer. Since the lattice constants of GaAs and Ge are close, epitaxial layers of GaAs and Ge can be formed on each other with almost no defects.

[0022] In Figure 3A In stage 300(2), forming a STI region 318 is included. As an example, the STI region 318 may include SiO2. The STI region 318 divides the plurality of alternating first material layers and second material layers and the isolation layer 306 into a first multi-layer structure 320 and a second multi-layer structure 322. The first multi-layer structure 320 may be used to form an NMOS GAA transistor. The second multi-layer structure 322 may be used to form a PMOS GAA transistor. The STI region 318 extends through the plurality of alternating first material layers and second material layers, the isolation layer 306, and the etch stop layer 304 into the substrate 302.

[0023] In Figure 3B In stage 300(3), removing the last layer 316 of the plurality of alternating first material layers and second material layers from the first multi-layer structure 320 is included. The last layer 316 may be removed by wet etching or dry etching.

[0024] In Figure 3B In stage 300(4), forming a first hard mask layer 324 on the first multi-layer structure 320, the second multi-layer structure 322, and the STI region 318 is included. As an example, the first hard mask layer 324 may include silicon nitride (SiN).

[0025] In Figure 3C In stage 300(5), patterning the first hard mask layer 324 is included.

[0026] In Figure 3C it, stage 300(6) includes a patterned first hard mask layer 324, patterning a plurality of alternating first material layers and second material layers in the first multi-layer structure 320, and an isolation layer 306. The plurality of alternating first material layers and second material layers in the first multi-layer structure 320 and the isolation layer 306 can be patterned by wet etching or dry etching. Stage 300(6) also includes patterning a plurality of alternating first material layers and second material layers in the second multi-layer structure 322 based on the patterned first hard mask layer 324. The plurality of alternating first material layers and second material layers in the second multi-layer structure 322 can be patterned by wet etching or dry etching. Stage 300(6) also includes patterning the STI region 318. The STI region 318 can be patterned by wet etching or dry etching.

[0027] In Figure 3D it, stage 300(7) includes removing the first hard mask layer 324. Stage 300(7) also includes forming an oxide layer 326 that covers the first multi-layer structure 320, the second multi-layer structure 322, the STI region 318, the exposed etch stop layer 304, and the exposed isolation layer 306. As an example, the oxide layer 326 can include SiO2.

[0028] In Figure 3D it, stage 300(8) includes forming a dummy layer 328 on the oxide layer 326. As an example, the dummy layer 328 can include polysilicon. Stage 300(8) also includes planarizing the dummy layer 328 using chemical mechanical polishing (CMP). Stage 300(8) also includes forming a second hard mask layer 330 on the dummy layer 328. As an example, the second hard mask layer 330 can include SiN.

[0029] In Figure 3E it, stage 300(9) includes patterning the second hard mask 330 and the dummy layer 328 to separate the first multi-layer structure 320 from the second multi-layer structure 322. The second hard mask layer 330 and the dummy layer 328 between the first multi-layer structure 320 and the second multi-layer structure 322 can be removed by etching the second hard mask layer 330 and the dummy layer 328 between the first multi-layer structure 320 and the second multi-layer structure 322 using the oxide layer 326 as an etch stop.

[0030] In Figure 3EIn stage 300(10), the second hard mask layer 330 is removed. Stage 300(10) also includes replacing the dummy layer 328 with a metal gate layer 332. As an example, the metal gate layer 332 may include tungsten. Stage 300(10) also includes removing a first material layer from among a plurality of alternating first material layers and second material layers in the first multi-layer structure 320. As an example, the first material layer may include Ge. Stage 300(10) also includes removing the isolation layer 306 in the first multi-layer structure 320. The first material layer and the isolation layer 306 may be removed by wet etching. Stage 300(10) also includes forming a plurality of first gate layers 334 to replace the first material layer and the isolation layer 306 in the first multi-layer structure 320. As an example, the plurality of first gate layers 334 may include HfO2 and TiAlN. The plurality of first gate layers 334 may be formed by atomic layer conformal filling. After this process, the first multi-layer structure 320 includes second material layers from among the plurality of alternating first material layers and second material layers and the plurality of first gate layers 334. As an example, the second material layer may include GaAs, which may be used as a channel material for an NMOS GAA transistor. Thus, the first multi-layer structure 320 may be used to form an NMOS GAA transistor. Stage 300(10) also includes removing a second material layer from among a plurality of alternating first material layers and second material layers in the second multi-layer structure 322. As an example, the second material layer may include GaAs. The second material layer may be removed by wet etching. Stage 300(10) also includes forming a second plurality of gate layers 336 to replace the second material layer in the second multi-layer structure 322. As an example, the plurality of second gate layers 336 may include HfO2 and TiN. The plurality of second gate layers 336 may be formed by atomic layer conformal filling. After this process, the second multi-layer structure 322 includes first material layers from among the plurality of alternating first material layers and second material layers and the plurality of second gate layers 336. As an example, the first material layer may include Ge, which may be used as a channel material for a PMOS GAA transistor. Thus, the second multi-layer structure 322 may be used to form a PMOS GAA transistor. Compared with the charge mobility of Si, both the first multi-layer structure 320 and the second multi-layer structure 322 may include channel materials with higher charge mobility. Thus, using the first multi-layer structure 320 and the second multi-layer structure 322 may improve the performance of the GAA transistor.

[0031] In Figure 3FIn stage 300(11), a dielectric layer 338 is formed to cover the metal gate layer 332. As an example, the dielectric layer 338 may include at least one of SiO2, silicon oxynitride, and silicon carbon oxynitride. Stage 300(11) also includes planarizing the dielectric layer 338 using CMP. Stage 300(11) also includes forming a first gate contact 340 for the first multi-layer structure 320 and forming a second gate contact 342 for the second multi-layer structure 322. As an example, the first gate contact 340 and the second gate contact 342 may include W.

[0032] Semiconductor devices including NMOS GAA transistors and PMOS GAA transistors having high charge mobility channel materials in accordance with certain aspects disclosed herein can be provided in or integrated into any electronic device. Examples include, but are not limited to: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, and drones.

[0033] Figure 4 is a block diagram illustrating an exemplary wireless communication system 400 in which aspects of the present disclosure may be employed. For illustrative purposes, Figure 4 three remote units 420, 430, and 450 and two base stations 440 are shown. It will be recognized that a wireless communication system may have more remote units and base stations. The remote units 420, 430, and 450 include integrated circuit (IC) devices 425A, 425C, and 425B, which may include the disclosed semiconductor devices. It will be recognized that other devices such as base stations, switching equipment, and network equipment may also include the disclosed semiconductor devices. Figure 4 Forward link signals 480 from the base station 440 to the remote units 420, 430, and 450 and reverse link signals 490 from the remote units 420, 430, and 450 to the base station 440 are shown.

[0034] In Figure 4In the figure, remote unit 420 is shown as a mobile phone, remote unit 430 is shown as a portable computer, and remote unit 450 is shown as a fixed-location remote unit in a wireless local loop system. For example, the remote unit can be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit such as a PDA, a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed-location data unit (such as meter reading equipment), or other communication devices that store or retrieve data or computer instructions, or a combination thereof. Although Figure 4 the figure illustrates remote units in accordance with certain aspects of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Certain aspects of the present disclosure can be suitably employed in many devices including the disclosed semiconductor devices.

[0035] Those skilled in the art will also understand that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with certain aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory or other computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the devices described herein can be used in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be any type and size of memory and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described generally in terms of their functionality above. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each particular application, but such implementations should not be construed as causing a departure from the scope of the present disclosure.

[0036] It should also be noted that the operation steps described in any of the exemplary aspects described herein are provided for purposes of example and discussion. The described operations can be performed in a large number of different orders other than the order illustrated. In addition, the operations described in a single operation step can actually be performed in many different steps. Additionally, one or more of the operation steps discussed in the exemplary aspects can be combined. It should be understood that the operation steps illustrated in any flowchart can be subject to many different modifications that will be apparent to those skilled in the art. Those skilled in the art will also understand that any of a variety of different techniques and technologies can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0037] The foregoing description of the disclosure is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims

1. A semiconductor device, comprising: A substrate; An etch stop layer on the substrate; An isolation layer on the etch stop layer; An N-type metal-oxide-semiconductor (NMOS) gate-all-around (GAA) transistor on the etch stop layer, the NMOS GAA transistor comprising a first channel material; and A P-type metal-oxide-semiconductor (PMOS) GAA transistor on the isolation layer, the PMOS GAA transistor comprising a second channel material, Wherein the first channel material has an electron mobility greater than that of silicon (Si), and the second channel material has a hole mobility greater than that of Si.

2. The semiconductor device according to claim 1, wherein the substrate comprises at least one of germanium (Ge), gallium arsenide (GaAs), Ge / Si, and GaAs / Si.

3. The semiconductor device according to claim 1, wherein the NMOS GAA transistor comprises a plurality of gate layers and a plurality of channel layers, the plurality of gate layers and the plurality of channel layers being alternately arranged, and wherein the plurality of channel layers comprise the first channel material.

4. The semiconductor device according to claim 3, wherein the plurality of gate layers comprise hafnium oxide (HfO2) and titanium aluminum nitride (TiAlN).

5. The semiconductor device according to claim 3, wherein the first channel material comprises GaAs.

6. The semiconductor device according to claim 1, wherein the PMOS GAA transistor comprises a plurality of gate layers and a plurality of channel layers, the plurality of gate layers and the plurality of channel layers being alternately arranged, and wherein the plurality of channel layers comprise the second channel material.

7. The semiconductor device according to claim 6, wherein the plurality of gate layers comprise HfO2 and titanium nitride (TiN).

8. The semiconductor device according to claim 6, wherein the second channel material comprises Ge.

9. The semiconductor device according to claim 1, wherein the etch stop layer comprises at least one of GaAs and aluminum arsenide (AlAs).

10. The semiconductor device according to claim 1, wherein the isolation layer comprises N-type doped Ge.

11. The semiconductor device according to claim 1, further comprising an isolation structure between the NMOS GAA transistor and the PMOS GAA transistor.

12. The semiconductor device according to claim 11, wherein the isolation structure comprises a shallow trench isolation (STI) region.

13. A method for manufacturing a semiconductor device, comprising: Forming an etch stop layer on a substrate; Forming an isolation layer on the etch stop layer; Forming an N-type metal-oxide-semiconductor (NMOS) gate-all-around (GAA) transistor on the etch stop layer, the NMOS GAA transistor comprising a first channel material; and Forming a P-type metal-oxide-semiconductor (PMOS) GAA transistor on the isolation layer, the PMOS GAA transistor comprising a second channel material, Wherein the first channel material has an electron mobility greater than that of silicon (Si), and the second channel material has a hole mobility greater than that of Si.

14. The method according to claim 13, wherein the NMOS GAA transistor includes a plurality of gate layers and a plurality of channel layers, the plurality of gate layers and the plurality of channel layers are alternately arranged with each other, and wherein the plurality of channel layers include the first channel material.

15. The method according to claim 14, wherein the first channel material includes gallium arsenide (GaAs).

16. The method according to claim 13, wherein the PMOS GAA transistor includes a plurality of gate layers and a plurality of channel layers, the plurality of gate layers and the plurality of channel layers are alternately arranged with each other, and wherein the plurality of channel layers include the second channel material.

17. The method according to claim 16, wherein the second channel material includes germanium (Ge).

18. The method according to claim 13, wherein the substrate includes at least one of Ge, GaAs, Ge / Si, and GaAs / Si.

Images