Techniques for forming integrated inductor-capacitor oscillators and related methods, oscillators, semiconductor devices, systems-on-a-chip, and other systems

Abstract

A system on chip can include an inductor-capacitor oscillator monolithically integrated into the system on chip. The inductor-capacitor oscillator can be configured to improve frequency stability and reduce noise compared to a resistor-capacitor oscillator. A method of fabricating an integrated oscillator can involve forming an inductor at least partially concurrently with forming a BEOL structure on a substrate. A capacitor can be formed prior to or concurrently with forming the BEOL structure, the capacitor supported on and / or embedded within the semiconductor material of the substrate. The inductor can be connected in parallel to the capacitor at least partially utilizing the BEOL structure to form an integrated inductor-capacitor oscillator.

Description

[0001] Priority Statement

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 62 / 961,635, filed on January 15, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates overall to techniques and related methods for forming integrated and / or internal inductor-capacitor oscillators, inductor-capacitor oscillators, semiconductor devices, systems-on-chip (SoCs), and systems. More specifically, the disclosed embodiments relate to techniques for forming integrated and / or internal inductor-capacitor oscillators that can improve the accuracy and reliability of inductor-capacitor oscillators, reduce the number of additional processing steps in manufacturing inductor-capacitor oscillators, and enhance the ability to employ SoC approaches for modules that rely on accurate timing. Background Technology

[0004] In conventional integrated circuits (ICs) known to the inventors, a fully functional device with multiple interconnecting transistors is formed using transistors monolithically built onto a silicon substrate and metal (typically aluminum or copper) wires connecting the transistors. In addition to transistors, other components traditionally mounted on printed circuit boards (PCBs) can also be monolithically built onto the same silicon substrate. This configuration is sometimes referred to in the art as a "system-on-a-chip" (SoC). Forming electronic components using techniques known to the inventors to produce an SoC configuration typically involves additional dedicated process steps, thereby increasing manufacturing process costs and introducing delays. Attached Figure Description

[0005] Although this disclosure concludes with claims that specifically point out and clearly claim protection for particular embodiments, the various features and advantages of the embodiments within the scope of this disclosure can be more readily identified by the following description when read in conjunction with the accompanying drawings, in which:

[0006] Figure 1 This is a schematic diagram of a substrate including a monolithic integrated inductor-capacitor oscillator according to one embodiment of the present disclosure;

[0007] Figure 2 It is manufacturing Figure 1 A flowchart of a method for using an inductor-capacitor oscillator;

[0008] Figure 3 It can be used to form Figure 1 A cross-sectional view of an exemplary capacitor in an inductive-capacitive oscillator;

[0009] Figure 4 It is manufacturing Figure 3 A cross-sectional view of the first intermediate product in the capacitor manufacturing process;

[0010] Figure 5 It is manufacturing Figure 3 A cross-sectional view of the second intermediate product in the capacitor manufacturing process;

[0011] Figure 6 It is manufacturing Figure 3 A cross-sectional view of the third intermediate product in the capacitor manufacturing process;

[0012] Figure 7 It is manufacturing Figure 3 A cross-sectional view of the fourth intermediate product in the capacitor method;

[0013] Figure 8 It can be used to form Figure 1 A plan view of an exemplary inductor in an inductive-capacitive oscillator;

[0014] Figure 9 yes Figure 8 A cross-sectional view of another part of the integrated inductor;

[0015] Figure 10 yes Figure 8 A cross-sectional view of the first part of the inductor; and

[0016] Figure 11 It includes Figure 1 A schematic diagram of the electronic system on the substrate. Detailed Implementation

[0017] The illustrations presented in this disclosure are not intended to be actual views of any particular microcontroller, system-on-a-chip, substrate, integrated inductor-capacitor oscillator, or components thereof, but are merely idealized representations for describing exemplary embodiments. Therefore, the figures are not necessarily drawn to scale. Throughout this specification, the same reference numerals refer to the same or similar elements, whether or not these elements are explicitly highlighted or discussed in conjunction with the given figures.

[0018] The disclosed embodiments generally relate to techniques for forming integrated and / or internal inductor-capacitor oscillators that, compared to oscillators known to the inventors of this disclosure, can improve the accuracy and reliability of inductor-capacitor oscillators, reduce the number of additional processing steps in manufacturing inductor-capacitor oscillators, and enhance the ability to employ a system-on-chip approach for modules that rely on accurate timing. More specifically, the present invention discloses embodiments for integrated and / or internal oscillators for semiconductor devices, which may include inductors and capacitors. The inductor is at least partially formed during the formation of a back-to-end (BEOL) structure on or over a substrate comprising semiconductor material, and the capacitor is supported on and / or embedded within the semiconductor material of the substrate before or simultaneously with the formation of the BEOL structure. BEOL is part of IC manufacturing, in which individual devices are interconnected with wiring on a substrate using one or more metallization layers. For example, the formation of the BEOL structure typically begins when a first metal layer is deposited on the substrate or during fabrication to facilitate the deposition of such a first metal layer. Common metals used as metallization layers are copper and aluminum. A typical BEOL structure includes contacts (e.g., pads) for chip-to-package connections, an insulating layer (dielectric layer), a metal layer (e.g., wires), and bonding locations (e.g., solder bumps, ball grid arrays).

[0019] For example, integrated and / or internal inductors for inductive-capacitive oscillators can be formed, at least in part, using processes for forming BEOL structures on or over a substrate comprising a semiconductor material. Specific techniques for manufacturing such integrated inductors are disclosed in U.S. Patent Application Serial No. 16 / 549,635, filed August 23, 2019, and U.S. Provisional Patent Application Serial No. 62 / 875,917, filed July 18, 2019, both currently unpublished, the entire disclosure of which is incorporated herein by reference. The resulting inductors can be low-resistance and insensitive to temperature fluctuations, thereby enabling the production of high-quality inductors at low cost (e.g., no cost from a process perspective).

[0020] Integrated and / or internal capacitors for inductive-capacitive oscillators can be formed, at least in part, using unconventional processes for forming BEOL structures on or over a substrate including semiconductor materials disclosed herein, or using state-of-the-art processes known to the inventors. For example, the integrated capacitor can be formed using a quantity of conductive material as one of the capacitor's plates, the conductive material being partially surrounded and / or embedded within a dielectric material. More specifically, the plates can be formed from one of the topmost wires produced on the substrate by an inlay process. Passivation material can be located above the dielectric and conductive materials, which can be placed in place as part of the process for forming the BEOL structure. Holes extending through the passivation material to the plates can be formed using masking and etching processes, which can also occur as part of the process for forming the BEOL structure, and the specific location and number of holes can differ when compared to state-of-the-art techniques known to the inventors for forming BEOL structures. A dielectric material (e.g., silicon nitride, silicon oxide, but not limited thereto) may be positioned over a passivation material, over the sidewalls of a hole extending through the passivation material, and over an electrode within the hole. Positioning the dielectric material in place is an additional process action compared to state-of-the-art techniques known to the inventors for forming BEOL structures. A protective material may be positioned within a portion of one of the holes, which is another additional process action compared to state-of-the-art techniques known to the inventors for forming BEOL structures. For example, the protective material may be a photoresist material initially deposited uniformly on the exposed surface of the dielectric material, less than the depth of the hole, and partially removed (e.g., by covering the photoresist material with a mask and exposing portions of the photoresist material accessible through the mask to light). Amounts of dielectric material not covered by the protective material or laterally adjacent to the protective material may be removed, and portions of dielectric material laterally adjacent to the protective material in the hole may be incidentally removed; this can still be an additional process action compared to state-of-the-art techniques known to the inventors for forming BEOL structures. The remaining protective material can be removed, leaving dielectric material covering the electrode plate within one of the holes extending into the electrode plate, and dielectric material extending longitudinally along the sidewall portion of the passivation material defining the associated hole. Patterning, etching, and physical vapor deposition of the conductive material can form bonding pads in the hole and extend over the passivation material to form another electrode plate of the capacitor covering the hole, which includes dielectric material. This other electrode plate is electrically connected to an electrode plate below the hole using one of the bonding pads, which in turn uses another bonding pad. This type of process allows for the production of high-quality, low-resistance integrated metal-insulator-metal (MIM) capacitors at low cost.

[0021] As an alternative embodiment, a polysilicon-oxide-polysilicon (POP) capacitor can be formed to manufacture the integrated inductive-capacitive oscillator according to the present disclosure. As yet another alternative embodiment, a metal-oxide-semiconductor (MOS) varactor diode (e.g., a MOS capacitor) can be formed to manufacture the inductive-capacitive oscillator according to the present disclosure. For example, the POP capacitor and / or the MOS varactor diode can be formed prior to the formation of the BEOL.

[0022] A capacitor or capacitor bank formed according to any of the foregoing techniques can be operatively connected to an inductor formed according to the foregoing techniques to generate an inductive-capacitive oscillator according to the present disclosure. For example, the capacitor or capacitor bank can be connected in parallel to the inductor. The capacitance of the inductive-capacitive oscillator can be adjusted to generate the desired resonant frequency of the inductive-capacitive oscillator, such as by connecting and / or disconnecting certain capacitors in the bank and / or utilizing onboard non-volatile memory in the substrate.

[0023] Compared to semiconductor devices relying on in-package resistor-capacitor oscillators, semiconductor devices (e.g., microcontrollers) according to this disclosure, including integrated inductor-capacitor oscillators, may be able to operate and communicate at a target frequency with greater accuracy and reliability without needing to be connected to another external or in-package oscillator (e.g., a crystal-based oscillator). For example, the inductor-capacitor oscillators disclosed herein are more accurate and less temperature-sensitive than resistor-capacitor oscillators configured to operate at the same resonant frequency. Therefore, a wider variety of modules can be integrated into chip-level semiconductor devices, enabling greater flexibility in the system-on-chip approach. Integrated inductor-capacitor oscillators can also be manufactured at low cost with minimal additional processing. Finally, integrated inductor-capacitor oscillators can exhibit higher quality (e.g., low resistance, low to zero temperature variation, more stable frequency response, and low noise sensitivity) compared to conventional oscillators.

[0024] As used herein, the terms “substantially” and “about” with respect to a given parameter, property, or condition mean and include the degree to which a given parameter, property, or condition satisfies the degree of variance (such as, within acceptable manufacturing tolerances) as would be understood by one of ordinary skill in the art. For example, a parameter substantially or about a specified value could be at least about 90%, at least about 95%, at least about 99%, or even at least about 99.9% of the specified value.

[0025] Figure 1This is a schematic diagram of a substrate 100 including a monolithically integrated inductor-capacitor oscillator 102 according to one embodiment of the present disclosure. When it is said that the inductor-capacitor oscillator 102 is "monolithically integrated," it means that the inductor-capacitor oscillator 102 is on the substrate 100 of the semiconductor device, rather than a discrete component disposed and connected to a support structure (such as, for example, a printed circuit board) to which the substrate 100 can be connected. For example, the monolithically integrated inductor-capacitor oscillator 102 may be a component for a system-on-a-chip configuration of the semiconductor device. The substrate 100 may include, for example, a semiconductor material 104, such as, for example, silicon. In some embodiments, the substrate 100 may be configured as a microcontroller, or include a microcontroller as a functional module within the substrate 100. The inductor-capacitor oscillator 102 may be configured as, for example, a component of a clock or clock module, such as for timing according to various communication protocols.

[0026] The inductor-capacitor oscillator 102 may include one or more inductors 800 electrically connected to one or more capacitors 300. For simplicity, only a single inductor 800 and capacitor 300 are described, but the inductor-capacitor oscillator 102 according to this disclosure may include a plurality of inductors 800, a plurality of capacitors 300, or a plurality of inductors 800 and a plurality of capacitors 300 (e.g., in corresponding groups or arrays) supported on a substrate 100 and monolithically integrated into the substrate. Each inductor 800 may include, for example, a coil 106 including a conductive material and an upper / lower region 108 that allows adjacent coils 106 to be layered above and below each other, respectively, without being electrically connected to each other or otherwise operatively connected to each other within the upper / lower region 108. In some embodiments, each capacitor 300 may include, for example, a first plate 112, a second plate 110, and a dielectric material 315 inserted between the first plate 112 and the second plate 110 (see [link to relevant documentation]). Figure 3 Both the first and second plates comprise conductive material. The inductor 800 and capacitor 300 can be interconnected, for example, in parallel, to form an inductive-capacitive oscillator 102. More specifically, the inductor 800 and capacitor 300 can be interconnected via one or more connectors 116, which can take the form of wires, lines, traces, and / or other structures for routing current, which may be part of a BEOL structure. The inductive-capacitive oscillator 102, including the inductor 800 and capacitor 300, can form at least a portion of the timing signal generator 118 (e.g., a clock generator, but not limited thereto) of the substrate 100.

[0027] Figure 2 Is to manufacture an inductor-capacitor oscillator (such as) according to this disclosure Figure 1A flowchart of method 200 for an inductor-capacitor oscillator 102. Method 200 may involve, for example, forming an inductor (e.g., while forming a BEOL structure on a substrate comprising semiconductor material) at least partially forming an inductor. Figure 1 An inductor 800 (but not limited to) is formed, as shown in action 202. More specifically, while forming the BEOL structure, the inductor can be formed by forming a portion of the coil of a first thickness and a portion of the interconnecting coil of a second, smaller thickness upper and lower region, as further shown in action 202. As a specific, non-limiting example, a portion of the inductor connected to the final layer formed using a damascene process can be formed using a conductive material (e.g., copper, copper mixture, or copper alloy) positioned on or above a substrate to form a portion of the coil and the lower region of the upper / lower region. Continuing with this specific, non-limiting example, another portion (e.g., the remaining portion) of the inductor can be formed by combining another amount of conductive material (e.g., aluminum, aluminum mixture, or aluminum alloy) positioned on the substrate to form the BEOL structure to form the remaining portion of the coil and the upper region of the upper / lower region.

[0028] Method 200 may also involve forming a capacitor supported on and / or embedded in a semiconductor material of a substrate (e.g., Figure 1 The capacitor 300 (but is not limited to this), as shown in action 204. More specifically, the capacitor can be formed before or simultaneously with the formation of the BEOL structure, as further shown in action 204. In some embodiments where the capacitor is formed simultaneously with the formation of the BEOL structure, a portion of the capacitor connected to the final layer formed using a damascene process can be formed using a conductive material (e.g., copper, copper mixture, or copper alloy) positioned on or above the substrate to form a first plate. In those same embodiments, another amount of conductive material (e.g., aluminum, aluminum mixture, or aluminum alloy) positioned above the substrate can be used to form the BEOL structure to form a second plate and an electrical connection to the first plate, and a dielectric region of the capacitor can be formed using a dielectric material positioned above the substrate to form the BEOL structure to form another portion (e.g., the remaining portion) of the capacitor. In other embodiments where the capacitor is formed before the formation of the BEOL structure, the capacitor can be a POP capacitor or a MOS varactor diode formed at least partially using a doped region of the substrate.

[0029] Finally, method 200 may involve connecting the inductor in parallel with the capacitor (e.g., using...). Figure 1 Connector 116 (but not limited thereto) is used to form an integrated inductor-capacitor oscillator, as shown in action 206. More specifically, the inductor may be electrically connected to the capacitor, at least in part, using a BEOL structure, to form an inductor-capacitor oscillator. As a specific, non-limiting example, connector 116 (see...) Figure 1 It can take the form of a wire, line, trace and / or other structure for guiding current within the BEOL structure, and can be formed simultaneously with the rest of the BEOL structure (including inductors and / or capacitors).

[0030] Figure 3 It can be used to form Figure 1 A cross-sectional view of an exemplary capacitor 300 for an inductive-capacitive oscillator 102. The capacitor 300 may include, for example, a first electrode 112, which may also be represented as a "base plate" supported on or above the substrate 100. The first electrode 112 may include, for example, a quantity of conductive material positioned on or above the substrate 100 and connected to the final layer of an interconnect 302 formed using a damascene process. More specifically, the first electrode 112 may include, for example, a large quantity of copper, a copper mixture, or a copper alloy forming the first electrode 112, and the first electrode may also be located within the uppermost layer of the interconnect 302 formed on the substrate 100 using a damascene process. The interconnect 302 may be used in the capacitor 300 to be electrically and operatively connected to one or more transistor regions 304, which may also be represented as "other integrated circuits," including doped regions within the semiconductor material 104 of the substrate 100. In some embodiments, the transistor region 304 itself may include one or more capacitors 342 in the form of, for example, a POP capacitor and / or a MOS varactor diode.

[0031] The first electrode 112 may be supported within other dielectric materials 306 of the interconnect 302. The interconnect 302 may include regions of, for example, conductive material and regions of other dielectric materials 306, the latter being selectively positioned such that the regions of conductive material (e.g., regions of the first electrode 112 and any other conductive structures of the interconnect 302) can electrically interconnect selected electronic components without forming unwanted connections (e.g., short circuits). For example, the first electrode 112 may be partially surrounded and supported by a barrier material 308 (e.g., Ta, TaN) inserted between the first electrode 112 and other dielectric materials 306. The barrier material 308 may be positioned and configured to reduce the likelihood of the material of the first electrode 112 contacting and contaminating the semiconductor material of the substrate 100. For simplicity, in Figure 3 Only the uppermost layer of interconnect 302 is shown; however, interconnects according to this disclosure may include additional layers, such as layers interposed between the first electrode 112 and the substrate 100, but are not limited thereto. Other dielectric materials 306 may include, for example, oxide materials (e.g., silicon oxide, silicon dioxide, but not limited thereto).

[0032] Passivation material 310 may cover at least a portion of the first electrode 112, any exposed portions of the barrier material 308, and the main surface of another dielectric material 306 on the side of the other dielectric material 306 opposite to the substrate 100. For example, passivation material 310 may cover a portion of the first electrode 112 and the entire other dielectric material 306. Passivation material 310 may be positioned and configured to laterally surround at least a portion of the second electrode 110 and partially cover the first electrode 112 of the capacitor 300. Passivation material 310 may include, for example, oxides, nitrides, glasses, polymers, or combinations or sub-combinations thereof (e.g., silicon oxynitride, silicon oxide, silicon nitride, silicon-rich nitride, phosphosilicate glass, but not limited thereto).

[0033] The first hole 312 can extend from the side of the passivation material 310 opposite to the first electrode 112 toward the first electrode 112 at a first position covering the first electrode 112, and the second hole 314 can extend through the passivation material 310 in the same direction and at a second offset position covering the first electrode 112. For greater clarity, please refer to... Figure 5 The diagram shows the first hole 312 and the second hole 314 in an unoccupied state. For clarity, the leads associated with reference numerals 312 and 314 terminate at the sidewalls of the passivation material 310 defining the first hole 312 and the second hole 314, rather than at the occupied areas. Figure 3 The capacitor 300 occupies a conductive material within a first aperture 312 and a second aperture 314. The first aperture 312 can be positioned and configured, for example, to support and define, at least partially, a dielectric region 316 and a second electrode 110 of the capacitor 300 within the first aperture 312, such that the dielectric region 316 is placed adjacent to the first electrode 112 and the second electrode 110 is placed adjacent to the dielectric region 316 on the side of the dielectric region 316 opposite to the first electrode 112. For example, the dielectric region 316 of the capacitor 300, comprising a dielectric material 315 (which may also be referred to as an "insulator"), can be positioned within the first aperture 312 adjacent to the first electrode 112. The dielectric region 316 can be positioned and configured to physically and electrically separate the first electrode 112 and the second electrode 110 of the capacitor 300 from each other, and the characteristics of the dielectric material 315 (e.g., resistance, mass, thickness) can at least partially determine the characteristics of the capacitor 300 (e.g., capacitance, breakdown voltage). The second hole 314 can be positioned and configured, for example, to support and define an electrical connection 330 for electrical connection via a passivation material 310 to a first electrode 112 of a capacitor 300. The second electrode 110 of the capacitor 300 can, for example, occupy the remainder of the first hole 312 and extend at least from a direct conformal contact with the dielectric region 316 to an opening in the first hole 312 positioned opposite the substrate 100, and optionally extend laterally and longitudinally beyond that opening.

[0034] For example, the dielectric region 316 may extend laterally along and cover the surface 318 of the first electrode 112, which would otherwise be exposed within the first hole 312. More specifically, a first portion 320 of the dielectric material 315 of the dielectric region 316 may, for example, be in direct contact with the surface 318 of the first electrode 112, and when projected onto the surface 318 of the first electrode 112, extend laterally through the entire surface area of ​​the first hole 312, thereby blocking the first hole 312. The dielectric material 315 of the dielectric region 316 may further extend along and cover, for example, a portion of the sidewall 322 of the passivation material 310 defining the first hole 312. More specifically, the second portion 334 of the dielectric material 315 of the dielectric region 316 may, for example, be in direct contact with a portion of the sidewall 322 of the passivation material 310 defining the first hole 312, which extends from a position near the first electrode 112 away from the first electrode 112 along the sidewall 322 into the first hole 312. The transition from the first portion 320 to the second portion 334 of the dielectric material 315 may, for example, be gradual. More specifically, at the transition from the first portion 320 to the second portion 334, at least the interior angle 324 of the dielectric material 315 may be rounded. As a specific, non-limiting example, the dielectric material 315 of the dielectric region 316 may be formed in a cup shape (e.g., a hollow, at least substantially straight cylinder with a closed end), which is supported on the first electrode 112 within the first hole 312. The dielectric material 315 of the dielectric region 316 may include, for example, an oxide or nitride material (e.g., SiO, SiN).

[0035] The second electrode 110 of the capacitor 300 (which may also be referred to as the "top plate") may be at least partially located within the first hole 312. For example, the second electrode 110 may include another quantity of conductive material positioned on the dielectric region 316 in relation to the formation of the BEOL structure 340, which may include and form, for example, at least a portion of the second electrode 110, at least a portion of the electrical connection 330, and a passivation material 310. More specifically, the second electrode 110 may include, for example, a large amount of aluminum, an aluminum mixture, or an aluminum alloy located within the lowest layer of the passivation material 310, which is supported on the substrate 100 during the formation of the BEOL structure 340. For simplicity, Figure 3Only the lowest layer of the BEOL structure 340 is shown; however, the BEOL structure according to the invention may include additional layers, such as a layer located on the side of the second electrode 110 opposite to the substrate 100, but is not limited thereto. As a specific, non-limiting example, the second electrode 110 may include a large amount of conductive material occupying the remainder of the first hole 312 and extending at least from a direct conformal contact with the dielectric material 315 of the dielectric region 316 to an opening of the first hole 312 opposite to the substrate 100, and the conductive material optionally extending laterally and longitudinally beyond the opening in the form of a first bonding pad. The dielectric material 315 of the dielectric region 316 may be longitudinally located between the first electrode 112 and the second electrode 110, may extend longitudinally along a portion of the periphery of the second electrode 110, and may extend laterally through the surface of the second electrode 110 defined by the sidewall 322 defining the first hole 312.

[0036] The transition from the surface 326 of the second electrode 110 adjacent to the dielectric region 316 to the lateral side surface 328 of the second electrode 110 adjacent to the second portion 334 of the dielectric region 316 and the sidewall 322 of the first hole 312 can be, for example, gradual. More specifically, by conforming the shape of the conductive material of the second electrode 110 to the dielectric material 315 within the first hole 312, at least the outer corner 332 of the second electrode 110 at the transition from the surface 326 adjacent to the first electrode 112 to the lateral side surface 328 can be rounded (e.g., made arc-shaped). As a non-limiting example, rounding the corner 324 of the dielectric region 316 and the corner 332 of the adjacent second electrode 110 can increase the breakdown voltage of the capacitor 300 because the rounded corners 324, 332 can reduce the concentration of the electric field, which would otherwise occur if the corners 324, 332 were sharp (i.e., not rounded).

[0037] An electrical connection 330 to the first electrode 112 of capacitor 300 may be located within a second aperture 314 defined by a passivation material 310. For example, the electrical connection 330 may include a quantity of conductive material that directly contacts a portion of the surface 318 of the first electrode 112 within the second aperture 314 and occupies at least substantially the entire second aperture 314. More specifically, the electrical connection 330 may include, for example, a large quantity of aluminum, an aluminum mixture, or an aluminum alloy located within the lowest layer of the passivation material 310, which is supported on the substrate 100 while forming the BEOL structure 340. As a specific, non-limiting example, the electrical connection 330 may include a large quantity of conductive material that occupies at least substantially the entire second aperture 314 from a location intersecting (e.g., directly contacting, but not limited to) the surface 318 of the first electrode 112 to a location adjacent to the opening of the second aperture 314 and opposite the substrate 100. Optionally, this large quantity of conductive material may extend laterally and longitudinally beyond the opening of the second aperture 314 in the form of a second bonding pad. The electrical connection to capacitor 300 can be achieved by directly connecting it to the second plate 110 and indirectly connecting it to the first plate 112 via electrical connection 330.

[0038] Figure 4 It is manufacturing Figure 3 A cross-sectional view of the first intermediate product 400 in the method of manufacturing capacitor 300. When manufacturing the first intermediate product 400, and in conjunction with reference to... Figure 3 and Figure 4 The passivation material 310 can be placed on the last layer of the interconnect 302, on the side of the layer opposite to the substrate 100. For example, the passivation material 310 can directly contact and cover any exposed portion of the first electrode 112, the barrier material 308 partially surrounding the first electrode 112, and another dielectric material 306 in which the barrier material 308 and the first electrode 112 can be embedded. The passivation material 310 can be placed in place using, for example, plasma-enhanced chemical vapor deposition (PEVCD).

[0039] Figure 5 It is manufacturing Figure 3 A cross-sectional view of the second intermediate product 500 in the method of manufacturing capacitor 300. When manufacturing the second intermediate product 500, and in conjunction with reference to... Figure 3 and Figure 5The protective material 502 can be placed on the surface of the passivation material 310 opposite to the substrate 100. The protective material 502 may include, for example, a photoresist material. A mask can be placed on those portions of the protective material 502 that will retain and protect the lower portion of the passivation material 310, and the remaining portion of the protective material 502 can be removed (e.g., by exposing it to light). The exposed portions of the passivation material 310 not directly beneath the protective material 502 can be removed, thereby forming the first hole 312 and the second hole 314, and exposing the surface 318 of the first electrode 112 within the first hole 312 and the second hole 314. The removal of the exposed portions of the passivation material 310 can be achieved, for example, by an etching process.

[0040] Figure 6 It is manufacturing Figure 3 A cross-sectional view of the third intermediate product 600 in the method of manufacturing capacitor 300. Before manufacturing the third intermediate product 600, and in conjunction with reference to... Figure 3 and Figure 6 The protective material 502 can be removed (see...) Figure 5 (For example, by mechanically peeling off the protective material 502, exposing the protective material 502 to light, dissolving the protective material 502 in a solvent, and / or any combination thereof.) The dielectric material 315 may be placed on the exposed surfaces of the passivation material 310 and the first electrode 112. For example, the dielectric material 315 may directly contact and cover the surface of the passivation material 310 on the side of the passivation material 310 opposite to the substrate 100, the portion of the surface 318 of the first electrode 112 in the first hole 312 and the second hole 314, and the sidewalls 322 of the passivation material 310 defining the first hole 312 and the second hole 314. The dielectric material 315 may be placed in place using, for example, plasma-enhanced chemical vapor deposition (PEVCD).

[0041] Figure 7 It is manufacturing Figure 3 A cross-sectional view of the fourth intermediate product 700 in the method of manufacturing capacitor 300. When manufacturing the fourth intermediate product 700, and in conjunction with reference to... Figure 3 and Figure 7 Another amount of protective material 502 can be placed on the dielectric material 315 on the side of the dielectric material 315 opposite to the substrate 100. A mask can be placed on those portions of the protective material 502 that will retain and protect the lower portion of the dielectric material 315, and the remaining portion of the protective material 502 can be removed (e.g., by exposing it to light). Exposed portions of the dielectric material 315 not directly beneath the protective material 502 can be removed, leaving the dielectric region 316 of the capacitor 300 (see...). Figure 3This exposes the remaining portion of the first hole 312, the entire second hole 314, the surface 318 of the first plate 112 within the second hole 314, and the surface of the passivation material 310 positioned opposite the substrate 100. Removal of the exposed portion of the dielectric material 315 can be achieved, for example, by an etching process.

[0042] Then we can use the combination mentioned above. Figure 6 Any combination or sub-combination of the discussed processes removes the protective material 502. Conductive material can then be placed in the remainder of the first hole 312 and the second hole 314 to form the second electrode 110 and the electrical connection 330. The conductive material can be placed using, for example, physical vapor deposition (PVD). The capacitor 300 can then be at least substantially completed, forming... Figure 3 The structure shown.

[0043] Figure 8 It can be used to form Figure 1 A plan view of an exemplary inductor 800 for an inductive-capacitive oscillator. Inductor 800 may be located previously coupled with capacitor 300 (see...). Figure 3 In some embodiments of the BEOL structure, a capacitor 300 is formed at least partially on the same layer on the substrate 100. The inductor 800 may include a coil 106 extending from an input location 802 to an output location 804, the coil 106 forming a winding path from the outermost radial coil to the innermost radial coil and back (or vice versa). The coil 106 may be formed of, for example, wires, lines, traces, and / or other structures for guiding current through the inductor 800. A certain amount of electrically insulating material, such as, for example, passivation material 310 (see...), is also included. Figure 3 The coils 106 can be located, for example, radially at the radial center of the inductor 800 (e.g., radially within coil 106) and radially between each adjacent coil 106. When viewed in a plane parallel to the main surface of the substrate 100, the coils 106 can have a generally rectangular (e.g., square), polygonal (e.g., hexagonal, octagonal), or circular shape (see...). Figure 1 The shape, size, and spacing of coil 106 may depend on, for example, the magnetic flux, length, and resistance specifications of inductor 800. In some embodiments, coil 106 may be symmetrical (e.g., having substantially the same mirror shape around a line of symmetry, but with multiple upper / lower regions 108). In other embodiments, coil 106 may be asymmetrical (e.g., the mirror image around a line of symmetry has at least one difference, such as having an upper / lower region 108 on one lateral side, while not having a corresponding upper / lower region 108 on the opposite lateral side).

[0044] The electrical isolation portion of coil 106 within the upper / lower layer region 108 Figure 8The portion of coil 106 is shown oriented at an angle relative to the rest of coil 106. However, the electrically isolated portions of coil 106 within the upper / lower region 108 can take any path guided between coils 106 within the plane of the respective isolated portions, such as, for example, a stepped pattern: the stepped portions extend alternately parallel, then perpendicular, then parallel, etc., relative to the remainder of coil 106. Furthermore, the inductor 800 according to this disclosure may include any number of coils 106 (e.g., number of turns). Available from... Figure 9 and Figure 10 Additional details about the aforementioned varying thickness of coil 106 at different locations around coil 106 are obtained through comparison. These two figures show coil 106 outside the upper / lower layer region 108. Figure 9 ) and interior ( Figure 10 The cross-section of ).

[0045] Figure 9 It was taken from section 806. Figure 8 A cross-sectional view of the first part of the integrated inductor 800. Figure 9 The portions shown may correspond to those portions of coil 106 where the upper / lower layer region 108 is not formed. In these portions, coil 106 may include a first number of conductive materials 902 embedded within the dielectric material of interconnect 302, and a second number of conductive materials 904 embedded within the passivation material 310 of the BEOL structure, in direct contact with the first number of conductive materials 902. More specifically, the first number of conductive materials 902 may, for example, be partially surrounded by barrier material 308, embedded within other dielectric materials 306, and formed as a first electrode 112 similar to that of capacitor 300 (see...). Figure 3 The second number of conductive materials 904 is part of the final layer of the interconnect 302. At least a portion of the second number of conductive materials 904 may be laterally surrounded, for example, by a passivation material 310, and the second number of conductive materials 904 may be formed as a second electrode 110 similar to that of a capacitor 300 (see...). Figure 3 This is part of the first layer of the BEOL structure. These parts of the coil 106 can utilize the previously described formation of the capacitor 300. Figures 4 to 7 The processes described are formed, particularly those related to the first electrode plate 112 and the electrical connection 330.

[0046] Figure 10 It was taken from section 808. Figure 8 A cross-sectional view of another part of the inductor 800. Figure 3The portions shown may correspond to those portions of coil 106 forming the upper / lower layer region 108. In these portions, one of the coils 106 passing underneath may include a first number of conductive materials 902 embedded within another dielectric material 306 of the interconnect 302, thereby forming a first layer 1002. The other coil 106 passing underneath may include a second number of conductive materials 904 supported on a passivation material 310 of the BEOL structure, thereby forming a second layer 1000. The passivation material 310 may physically, electrically, and operatively isolate the first number of conductive materials 902 from the second number of conductive materials 904. These portions of coil 106 may utilize the previously described formation of capacitor 300. Figures 4 to 7 The process described is used to form the passivation material 310, but no openings can be formed in the upper / lower layer region 108, thereby separating the first number of conductive materials 902 from the second number of conductive materials 904 through the passivation material 310.

[0047] Figure 11 It includes Figure 1 A schematic diagram of an electronic system 1100 on a substrate. For example, electronic system 1100 may include a control unit 1102 and a probe unit 1104. Probe unit 1104 may include a sensor device 1106 configured to generate an electrical signal representing and responding to a detected physical phenomenon. Probe unit 1104 may be a portable device, such as, for example, a handheld device. In some embodiments, probe unit 1104 may include a semiconductor device including a substrate 100 located within probe unit 1104 according to the present disclosure, the substrate 100 of which is configured to at least partially process electrical signals within probe unit 1104. Probe unit 1104 may be operatively connected to control unit 1102 (e.g., via a wired or wireless connection) and may transmit raw, partially processed, or fully processed electrical signals to control unit 1102. In some embodiments, control unit 1102 may include another semiconductor device or microprocessor 1108 having a substrate 100 according to the present disclosure, which may process or further process electrical signals. Control unit 1102 may include storage device 1110 (i.e., a physical hardware storage device that is not a transient signal) configured to store the result of a fully processed electrical signal. Control unit 1102 may optionally include output device 1112 (e.g., an electronic display, an audio speaker, a printer, but not limited thereto) configured to output the result of a fully processed electrical signal.

[0048] Compared to conventional configurations and techniques for forming integrated inductor-capacitor oscillators, the configuration of the integrated inductor-capacitor oscillator according to this disclosure and the techniques for forming it can involve performing fewer process actions, have greater synergy with process actions for forming other structures (e.g., bonding pads, interconnects, BEOL structures), reduce reliance on dedicated process actions and interconnect structures (e.g., vias and those actions for forming vias), and produce a higher quality integrated inductor-capacitor oscillator. For example, the techniques for forming the integrated inductor-capacitor oscillator according to this disclosure allow one or more components of the integrated inductor-capacitor oscillator to be formed simultaneously with bonding pads of the same semiconductor device, and formed using the same materials as the bonding pads. Furthermore, an integrated inductor-capacitor oscillator having the configuration according to this disclosure can have higher inductance, lower resistance, lower capacitance, and higher breakdown voltage capacitor, thereby producing a higher quality integrated inductor-capacitor oscillator.

[0049] While certain exemplary embodiments have been described in conjunction with the accompanying drawings, those skilled in the art will recognize and understand that the scope of this disclosure is not limited to those embodiments expressly shown and described herein. Rather, numerous additions, deletions, and modifications can be made to the embodiments described herein to produce embodiments within the scope of this disclosure, such as those specifically claimed, including legal equivalents. Furthermore, features from one disclosed embodiment may be combined with features from another disclosed embodiment while still being included within the scope of this disclosure as contemplated by the inventors.

Claims

1. A system-on-a-chip, comprising: An inductor-capacitor oscillator, which is monolithically integrated into the system-on-a-chip. The inductor includes portions of a coil as well as an upper region and a lower region. The portions of the coil are located in two adjacent layers, which are supported on the semiconductor substrate of the system-on-a-chip. The upper region and the lower region interconnect the portions of the coil. The upper region is located in one of the two adjacent layers, and the lower region is located in the other of the two adjacent layers. The coil of the inductor located outside the upper and lower regions comprises at least substantially all of a first quantity of conductive material in the first layer of the two adjacent layers and a second quantity of conductive material in the second layer of the two adjacent layers, the second quantity of conductive material being in direct contact with the first quantity of conductive material, and the second quantity of conductive material located outside the upper and lower regions comprising a monolithic continuous block of conductive material partially embedded within a passivation material in the second layer of the two adjacent layers; as well as The upper and lower regions that interconnect the portions of the coil include a passivation material between a first number of conductive materials and a second number of conductive materials, wherein the second number of conductive materials is not embedded in the passivation material within the upper and lower regions.

2. The system-on-a-chip according to claim 1, wherein at least a portion of the capacitor of the inductor-capacitor oscillator is part of the BEOL structure of the back-end process of the system-on-a-chip.

3. The system-on-a-chip according to claim 2, wherein the second plate of the capacitor is located within a second layer supported on the semiconductor substrate of the system-on-a-chip, the first plate of the capacitor is located within a first bottom layer supported on the semiconductor substrate, and the dielectric material of the capacitor is located between the first plate and the second plate.

4. The system-on-a-chip according to claim 3, wherein the transition from the surface of the second electrode plate facing the first electrode plate to the lateral side surface of the second electrode plate is circular.

5. The system-on-a-chip of claim 3, wherein the dielectric material extends laterally between the second electrode and the first electrode, and extends longitudinally along a portion of the periphery of the second electrode, such that the dielectric material is at least substantially cup-shaped.

6. The system-on-a-chip according to claim 3, wherein the second electrode plate includes a first bonding pad formed in the BEOL structure.

7. The system-on-a-chip of claim 6, wherein the electrical connection to the first electrode plate includes a second bonding pad formed in the BEOL structure.

8. The system-on-a-chip according to claim 3, wherein the second electrode plate comprises copper or a copper alloy, and the first electrode plate comprises aluminum or an aluminum alloy.

9. The system-on-a-chip according to claim 1, wherein the capacitor of the inductor-capacitor oscillator is a polysilicon-oxide-polysilicon (POP) capacitor.

10. The system-on-a-chip according to any one of claims 1 to 9, wherein the inductor-capacitor oscillator forms at least a portion of the timing signal generator of the system-on-a-chip.

11. The system-on-a-chip according to any one of claims 1 to 9, wherein the inductor-capacitor oscillator is monolithically integrated with other integrated circuits of the system-on-a-chip.

12. A method for manufacturing an integrated oscillator on a system-on-a-chip, the method comprising: An inductor is formed on a substrate comprising a semiconductor material by forming portions of a coil of a first thickness and forming an upper region and a lower region having a second thickness less than the first thickness, wherein the upper region and the lower region interconnect the portions of the coil, wherein forming the inductor includes: The inductor's coil portions are supported in two adjacent layers on the semiconductor substrate and interconnected by the upper and lower layer regions, the upper layer region being located within one of the two adjacent layers and the lower layer region being located within the other of the two adjacent layers; The coil of the inductor, which forms the inductor located outside the upper and lower regions, comprises at least substantially all of a first amount of conductive material in the first layer of the two adjacent layers and a second amount of conductive material in the second layer of the two adjacent layers, the second amount of conductive material being in direct contact with the first amount of conductive material, the second amount of conductive material located outside the upper and lower regions comprising a monolithic continuous block of conductive material partially embedded within a passivation material in the second layer of the two adjacent layers; The upper and lower regions that interconnect the portions of the coil are formed to include the passivation material between the first number of conductive materials and the second number of conductive materials, wherein the second number of conductive materials is not embedded in the passivation material within the upper and lower regions; Before or simultaneously with the formation of the inductor, a capacitor is formed, the capacitor being supported on and / or embedded within the semiconductor material of the substrate; and The inductor is connected in parallel to the capacitor to form a monolithic integrated inductor-capacitor oscillator.

13. The method of claim 12, wherein forming the capacitor comprises: The first plate of the capacitor is formed in the uppermost layer of the interconnects on the substrate using a mosaic process; The passivation material is placed on the first electrode plate; A first hole and a second hole are formed through the passivation material to expose a corresponding portion of the first electrode plate within each of the first hole and the second hole; The dielectric region of the capacitor is formed by placing a dielectric material within a portion of the first hole, the dielectric material covering the corresponding portion of the first plate adjacent to the first hole; While forming the BEOL structure, the second plate of the capacitor and its electrical connection to the first plate are formed by placing another first number of conductive materials in the remaining portion of the first hole to contact the dielectric material.

14. The method of claim 13, wherein forming the dielectric region comprises: The dielectric material is deposited at a uniform thickness on the surface of the passivation material opposite to the first electrode, on the side surface of the passivation material defining the first hole and the second hole, and on the corresponding portions of the first electrode within the first hole and the second hole. A protective material is placed on a portion of the dielectric material adjacent to the first electrode plate and within a portion of the first hole; Remove the remaining portion of the dielectric material that is not in contact with the protective material, exposing the passivation material and the corresponding portions of the first electrode plate within the second hole; as well as Remove the protective material.

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