Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes a gate line, a data line, a voltage supply line, and a pixel driving circuit. The pixel driving circuit includes a plurality of transistors and a storage capacitor. The storage capacitor includes a first capacitor electrode, a second capacitor electrode, and an insulating layer between the first capacitor electrode and the second capacitor electrode. The second capacitor electrode is electrically connected to the voltage supply line. The second capacitor electrode includes a first portion and a second portion as part of a first integral structure in each sub-pixel. The voltage supply line crosses the first portion by a first crossing distance. The data line crosses the second portion by a second crossing distance. The first crossing distance is greater than the second crossing distance.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control illuminance. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the row where the pixel unit is selected is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. This drives the OLED device to emit light of a corresponding brightness. Relevant parameters of an OLED display panel include energy consumption, brightness, color coordinates, and color shift. Summary of the Invention

[0003] In one aspect, this disclosure provides an array substrate comprising: a gate line; a data line; a voltage supply line; and a pixel driving circuit; wherein the pixel driving circuit includes a plurality of transistors and a storage capacitor; the storage capacitor includes a first capacitor electrode, a second capacitor electrode, and an insulating layer between the first capacitor electrode and the second capacitor electrode; the second capacitor electrode is electrically connected to the voltage supply line; the second capacitor electrode includes a first portion and a second portion as part of a first integral structure in each sub-pixel; the voltage supply line intersects the first portion by a first intersection distance; the data line intersects the second portion by a second intersection distance; and the first intersection distance is greater than the second intersection distance.

[0004] Optionally, the voltage supply line and the data line are substantially parallel to each other; and the sections of the voltage supply line that intersect with the first portion and the sections of the data line that intersect with the second portion are substantially parallel to each other.

[0005] Optionally, the array substrate further includes an interlayer dielectric layer between the voltage supply line and the second capacitor electrode; and a connection via extending through the interlayer dielectric layer; wherein the voltage supply line is connected to the first portion of the second capacitor electrode through the connection via.

[0006] Optionally, the array substrate includes a semiconductor material layer that intersects with at least one of the first portion and the second portion, the intersection reaching a third intersection distance; and the third intersection distance is less than or equal to the first intersection distance and greater than or equal to the second intersection distance.

[0007] Optionally, the crossing portion, the voltage supply line, and the data line are substantially parallel to each other; and the crossing portion, the section where the voltage supply line intersects with the first portion, and the section where the data line intersects with the second portion are substantially parallel to each other.

[0008] Optionally, the intersecting portion intersects both the first portion and the second portion.

[0009] Optionally, the plurality of transistors includes: a driving transistor; a first transistor; a second transistor; a third transistor; a fourth transistor; and a fifth transistor; wherein the drain of the second transistor, the active layer of the second transistor, the drain of the fourth transistor, the active layer of the fourth transistor, the source of the driving transistor, and the active layer of the driving transistor are part of a second overall structure in each sub-pixel; and at least a portion of the intersection directly connects the drain of the second transistor, the drain of the fourth transistor, and the source of the driving transistor to each other.

[0010] Optionally, the orthographic projections of the cross portion on the substrate, the orthographic projections of the voltage supply line on the substrate, and the orthographic projections of the data line on the substrate do not substantially overlap with each other.

[0011] Optionally, except for the hole region in which a portion of the second capacitor electrode is not present, the orthographic projection of the first portion on the substrate completely covers the orthographic projection of the first capacitor electrode on the substrate, with a margin.

[0012] Optionally, the array substrate further includes: an interlayer dielectric layer between the voltage supply line and the second capacitor electrode; a first connection line located on the side of the interlayer dielectric layer away from the second capacitor electrode and in the same layer as the voltage supply line and the data line; and a first via located in the via region and extending through the interlayer dielectric layer and the insulating layer; wherein the first connection line is connected to the first capacitor electrode through the first via.

[0013] Optionally, the array substrate further includes: a substrate; a semiconductor material layer on the substrate; and a gate insulating layer located on the side of the semiconductor material layer away from the substrate; wherein the first capacitor electrode is located on the side of the gate insulating layer away from the substrate; the array substrate further includes a second via extending through the interlayer dielectric layer, the insulating layer and the gate insulating layer; and the first connection line is connected to the semiconductor material layer through the second via.

[0014] Optionally, the plurality of transistors includes: a driving transistor; a first transistor; a second transistor; a third transistor; a fourth transistor; and a fifth transistor; wherein the source of the third transistor, the active layer of the third transistor, the drain of the third transistor, the source of the first transistor, the active layer of the first transistor, and the drain of the first transistor are part of a second overall structure in each sub-pixel; and the first connection line is connected to the source of the third transistor and the drain of the first transistor through the second via.

[0015] Optionally, the first part includes a main part, a first side part, and a second side part; the main part has a first side surface, a second side surface opposite to the first side surface, a third side surface connecting the first side surface and the second side surface, and a fourth side surface opposite to the third side surface; the first side surface is adjacent to the first side part; the second side surface is adjacent to the second side part; and the third side surface is adjacent to the second part.

[0016] Optionally, the first side portion has a substantially trapezoidal shape; and the second side portion has a substantially inverted trapezoidal shape.

[0017] Optionally, the third side is a side of the second portion; and the length of the third side is substantially the same as the second intersection distance.

[0018] Optionally, the array substrate further includes: an interlayer dielectric layer between the voltage supply line and the second capacitor electrode; a second connection line located on the side of the interlayer dielectric layer away from the second capacitor electrode and in the same layer as the voltage supply line and the data line; a reset signal line located on the side of the insulating layer away from the first capacitor electrode and in the same layer as the second capacitor electrode; and a third via extending through the interlayer dielectric layer; wherein the second connection line is connected to the reset signal line through the third via.

[0019] Optionally, the array substrate further includes: a substrate; a semiconductor material layer on the substrate; and a gate insulating layer located on the side of the semiconductor material layer away from the substrate; wherein the first capacitor electrode is located on the side of the gate insulating layer away from the substrate; the array substrate further includes a fourth via extending through the interlayer dielectric layer, the insulating layer and the gate insulating layer; and the second connection line is connected to the semiconductor material layer through the fourth via.

[0020] Optionally, the plurality of transistors includes: a driving transistor; a first transistor; a second transistor; a third transistor; a fourth transistor; and a fifth transistor; wherein the source of the first transistor and the active layer of the first transistor are part of a second overall structure in each sub-pixel; and the second connection line is connected to the source of the first transistor through the fourth via.

[0021] Optionally, the section where the data line intersects with the second portion has a linewidth in the range of 2.5 μm to 3.5 μm; and the section of the data line intersects with the second portion at a width of up to 60 μm. 2 up to 80μm 2 The area of ​​intersection within the range.

[0022] In another aspect, this disclosure provides a display device including an array substrate manufactured as described herein or by the methods described herein, and an integrated circuit connected to the array substrate. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0026] Figure 3 This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0027] Figure 4 This is a diagram illustrating the structure of semiconductor material layers in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0028] Figure 5 This is a diagram illustrating the structure of a first conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0029] Figure 6 This is a diagram illustrating the structure of a second conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0030] Figure 7 This is a diagram illustrating the structure of the signal line layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0031] Figure 8 It is along Figure 3 A cross-sectional view of line A-A' in the diagram.

[0032] Figure 9 This is a diagram illustrating the structure of a region in an array substrate according to some embodiments of the present disclosure, in which a signal line intersects with a second capacitor electrode.

[0033] Figure 10 This is a further enlarged view of the region in the array substrate where the signal line intersects with the second capacitor electrode, according to some embodiments of the present disclosure.

[0034] Figure 11 This is a diagram illustrating the structure of a region in an array substrate according to some embodiments of the present disclosure, in which a portion of a semiconductor layer intersects with a second capacitor electrode.

[0035] Figure 12 The structure of the first and second portions of the second capacitor electrode in an array substrate according to some embodiments of the present disclosure is shown.

[0036] Figure 13 This is a diagram illustrating the structure of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0037] Figure 14 It is along Figure 13 A cross-sectional view of line B-B' in the diagram.

[0038] Figure 15 It is along Figure 13 A cross-sectional view of line C-C' in the diagram.

[0039] Figure 16 This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0040] Figure 17 This is a diagram illustrating the structure of semiconductor material layers in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0041] Figure 18 This is a diagram illustrating the structure of a first conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0042] Figure 19 This is a diagram illustrating the structure of a second conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0043] Figure 20 This is a diagram illustrating the structure of the signal line layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0044] Figure 21 It is along Figure 16 A cross-sectional view of the D-D' line in the diagram.

[0045] Figure 22A This is a diagram illustrating the structure of the planarization layer of the array substrate and the anode of the light-emitting element according to some embodiments of the present disclosure.

[0046] Figure 22B It is along Figure 22A A cross-sectional view of the E-E' line in the diagram.

[0047] Figure 23A This is a diagram illustrating the structure of the pixel defining layer of the array substrate and the anode of the light-emitting element according to some embodiments of the present disclosure.

[0048] Figure 23B It is along Figure 23A A cross-sectional view of line F-F' in the diagram.

[0049] Figure 24 This is a diagram illustrating the structure of the pixel defining layer, the anode of the light-emitting element, and the light-emitting layer of the array substrate according to some embodiments of the present disclosure.

[0050] Figure 25 This is a diagram illustrating the structure of the cathode layer, anode layer, and light-emitting layer of the light-emitting element of an array substrate according to some embodiments of the present disclosure.

[0051] Figure 26A This is a diagram illustrating the structure of the signal line layer and the anode of the light-emitting element of an array substrate according to some embodiments of the present disclosure.

[0052] Figure 26B yes Figure 26A A magnified view of the area between the first and second virtual lines.

[0053] Figure 26C It is along Figure 26B A cross-sectional view of the G-G' line in the diagram.

[0054] Figure 27 The structure of a voltage supply line portion in an array substrate according to some embodiments of the present disclosure is shown.

[0055] Figure 28This is a diagram illustrating the structure of a first pixel driving circuit of an array substrate according to some embodiments of the present disclosure.

[0056] Figure 29 It is along Figure 28 A cross-sectional view of the H-H' line in the diagram.

[0057] Figure 30 It is along Figure 28 A cross-sectional view of line I-I' in the diagram.

[0058] Figure 31 This is a diagram illustrating the connection between the anode and the anode contact pad in an array substrate according to some embodiments of the present disclosure.

[0059] Figure 32 This is a diagram illustrating the structure of the anode of the light-emitting element of an array substrate according to some embodiments of the present disclosure.

[0060] Figure 33 The arrangement of light-emitting elements in an array substrate according to some embodiments of the present disclosure is shown.

[0061] Figure 34 This is a cross-sectional image of the array substrate.

[0062] Figure 35 This is a schematic diagram showing a cross-sectional image of the array substrate.

[0063] Figure 36 This is a schematic diagram showing a cross-sectional image of the array substrate.

[0064] Figure 37 This is a cross-sectional image of the array substrate. Detailed Implementation

[0065] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0066] This disclosure provides, in particular, an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes gate lines; data lines; voltage supply lines; and pixel driving circuitry. Optionally, the pixel driving circuitry includes a plurality of transistors and a storage capacitor. Optionally, the storage capacitor includes a first capacitor electrode, a second capacitor electrode, and an insulating layer between the first capacitor electrode and the second capacitor electrode. Optionally, the second capacitor electrode is electrically connected to the voltage supply line. Optionally, the second capacitor electrode includes a first portion and a second portion as part of an overall structure in each sub-pixel. Optionally, the voltage supply line intersects the first portion by a first intersection distance. Optionally, the data line intersects the second portion by a second intersection distance. Optionally, the first intersection distance is greater than the second intersection distance.

[0067] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 The array substrate comprises an array of subpixels Sp. Each subpixel includes an electronic component, such as a light-emitting element. In one example, the light-emitting element is driven by a pixel driving circuit PDC. The array substrate includes a gate line GL, a data line DL, a voltage supply line (e.g., a high voltage supply line Vdd), and a second voltage supply line (e.g., a low voltage supply line Vss), each of which is electrically connected to the pixel driving circuit PDC. The emission of light from each subpixel in the subpixel Sp is driven by the pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal in the range of 3V to 5V) is input to the pixel driving circuit PDC connected to the anode of the light-emitting element via the high voltage supply line Vdd; a low voltage signal (e.g., a VSS signal in the range of 0V to -5V) is input to the cathode of the light-emitting element via the low voltage supply line Vss. The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0068] Various suitable pixel driving circuits can be used in this array substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, and 8T2C. In some embodiments, each pixel driving circuit in the plurality of pixel driving circuits is a 5T1C driving circuit. Various suitable light-emitting elements can be used in this array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro OLEDs. Optionally, the light-emitting element is a micro OLED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0069] Figure 2 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2 In some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a respective reset control signal line rstN of the current stage, a source connected to a respective reset signal line VintN of the current stage of a plurality of reset signal lines, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding one of a plurality of gate lines GL, a source connected to a corresponding one of a plurality of data lines DL, and a drain connected to the source of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding gate line and a source connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the driving transistor. The gate and drain of transistor Td are connected to the drain of driving transistor Td; the gate of transistor T4 is connected to the corresponding light-emitting control signal line among a plurality of light-emitting control signal lines em, the source is connected to the corresponding voltage supply line among a plurality of voltage supply lines Vdd, and the drain is connected to the source of driving transistor Td and the drain of second transistor T2; the fifth transistor T5 has a gate connected to the corresponding light-emitting control signal line, a source connected to the drain of driving transistor Td and the drain of third transistor T3, and a drain connected to the anode of light-emitting element LE; and the sixth transistor T6 has a gate connected to the reset control signal line rst(N+1) of the next stage, a source connected to the reset signal line Vint(N+1) of the next stage, and a drain connected to the drain of fifth transistor and the anode of light-emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the source of fourth transistor T4.

[0070] Figure 3 This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 3 In some embodiments, the multiple sub-pixels Sp include red sub-pixels, green sub-pixels, and blue sub-pixels.

[0071] Figure 4 This is a diagram illustrating the structure of semiconductor material layers in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 5 This is a diagram illustrating the structure of a first conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 6 This is a diagram illustrating the structure of a second conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 7This is a diagram illustrating the structure of the signal line layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 8 It is along Figure 3 The cross-sectional view of line A-A' in the diagram. (Refer to...) Figures 3 to 8 In some embodiments, the array substrate includes a substrate BS, a semiconductor material layer SML on the substrate BS, a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS, a first conductive layer located on the side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on the side of the first conductive layer away from the gate insulating layer GI, a second conductive layer located on the side of the insulating layer IN away from the first conductive layer, an interlayer dielectric layer ILD located on the side of the second conductive layer away from the insulating layer IN, and a signal line layer located on the side of the interlayer dielectric layer ILD away from the second conductive layer.

[0072] Reference Figure 2 , Figure 3 and Figure 5 In some embodiments, the first conductive layer includes a gate line GL, a reset control signal line rst, a light emission control signal line em, and a first capacitor electrode Ce1 of a storage capacitor Cst. Figure 5 In the diagram, the sub-pixel Sp on the left is marked, indicating the region corresponding to multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and driving transistor Td) in the pixel driving circuit. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the gate line GL, reset control signal line rst, light emission control signal line em, and the first capacitor electrode Ce1 are in the same layer.

[0073] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the gate line GL and the first capacitor electrode Ce1 are formed by one or more steps of the same patterning process performed on the same material layer, the gate line GL and the first capacitor electrode Ce1 are located in the same layer. In another example, the gate line GL and the first capacitor electrode Ce1 can be formed in the same layer by simultaneously performing the steps of forming the gate line GL and forming the first capacitor electrode Ce1. The term "same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view.

[0074] Reference Figure 2 , Figure 3 and Figure 6 In some embodiments, the second conductive layer includes a reset signal line Vint and a second capacitor electrode Ce2 for a storage capacitor Cst. Figure 6 In the diagram, the sub-pixel Sp on the left is marked, indicating the region corresponding to multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and driving transistor Td) in the pixel driving circuit. Various suitable electrode materials and manufacturing methods can be used to fabricate the second conductive layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the reset signal line Vint and the second capacitor electrode Ce2 are located in the same layer.

[0075] Reference Figure 2 , Figure 3 and Figure 7 In some embodiments, the signal line layer includes a voltage supply line Vdd, a data line DL, a first connection line Cl1, and a second connection line Cl2. Figure 7 In the diagram, the sub-pixel Sp on the left is marked, indicating the region corresponding to multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and driving transistor Td) in the pixel driving circuit. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the signal line layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the voltage supply line Vdd, data line DL, first connection line Cl1, and second connection line Cl2 are located in the same layer. Figure 7 As shown, the data line DL is not completely straight, but has a detour to avoid overlapping with the semiconductor material layer.

[0076] refer to Figure 2 , Figure 3 , Figure 5 , Figure 6 and Figure 8 In some embodiments, the storage capacitor Cst includes a first capacitor electrode Ce1, a second capacitor electrode Ce2, and an insulating layer IN between the first capacitor electrode Ce1 and the second capacitor electrode Ce2. For example... Figure 2 As shown, the second capacitor electrode Ce2 is electrically connected to the voltage supply line Vdd. For example, the second capacitor electrode Ce2 and the voltage supply line Vdd are configured to always be supplied with the same voltage.

[0077] Reference Figure 2 , Figure 3 and Figure 4 In some embodiments, the semiconductor material layer has an integral structure in each sub-pixel. Figure 4 In the image, the sub-pixel Sp on the left is marked, indicating the area corresponding to multiple transistors in the pixel driving circuit (including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the driving transistor Td). Figure 4 In the diagram, the right-hand sub-pixel Sp is marked with labels indicating components of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a source S1, and a drain D1. The second transistor T2 includes an active layer ACT2, a source S2, and a drain D2. The third transistor T3 includes an active layer ACT3, a source S3, and a drain D3. The fourth transistor T4 includes an active layer ACT4, a source S4, and a drain D4. The fifth transistor T5 includes an active layer ACT5, a source S5, and a drain D5. The driving transistor Td includes an active layer ACTd, a source Sd, and a drain Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, and ACTd), sources (S1, S2, S3, S4, S5, and Sd), and drains (D1, D2, D3, D4, D5, and Dd) of the transistors (T1, T2, T3, T4, T5, and Td) in each sub-pixel are part of the overall structure in that sub-pixel. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, and ACTd), sources (S1, S2, S3, S4, S5, and Sd), and drains (D1, D2, D3, D4, D5, and Dd) of the transistors (T1, T2, T3, T4, T5, and Td) are in the same layer.

[0078] Figure 9 This is a diagram illustrating the structure of a region in an array substrate according to some embodiments of the present disclosure, in which a signal line intersects with a second capacitor electrode. Figure 10 This is a further enlarged view of a region in an array substrate according to some embodiments of the present disclosure, in which a signal line intersects with a second capacitor electrode. Reference Figure 9 and Figure 10In some embodiments, the second capacitor electrode Ce2 includes a first portion Ce2-1 and a second portion Ce-2, which are part of the overall structure in each sub-pixel. Optionally, the first portion Ce2-1 and the second portion Ce-2 are adjacent to each other. Optionally, the voltage supply line Vdd intersects the first portion Ce2-1 by a first intersection distance L1. Optionally, the data line DL intersects the second portion Ce2-2 by a second intersection distance L2. Optionally, the area of ​​the first portion Ce2-1 is larger than the area of ​​the second portion Ce-2.

[0079] In some embodiments, the first crossing distance L1 is greater than the second crossing distance L2. Optionally, the first crossing distance L1 is no more than 30% greater than the second crossing distance L2, for example, no more than 25%, no more than 20%, no more than 15%, no more than 10%, or no more than 5%.

[0080] In some embodiments, refer to Figure 3 and Figure 9 The voltage supply line Vdd and the data line DL are substantially / essentially parallel to each other. As used herein, the term "substantially / essentially parallel" means that the angle between the two signal lines is in the range of 0 degrees to approximately 25 degrees, for example, 0 degrees to approximately 5 degrees, 0 degrees to approximately 10 degrees, 0 degrees to approximately 15 degrees, or 0 degrees to approximately 20 degrees. (See reference...) Figure 10 The section where the voltage supply line Vdd intersects with the first part Ce2-1 and the section where the data line DL intersects with the second part Ce2-2 are substantially parallel to each other.

[0081] In some embodiments, reference Figure 10 The voltage supply line Vdd crosses the first portion Ce2-1 to a first cross area; and the data line DL crosses the second portion Ce2-2 to a second cross area. Optionally, the first cross area is larger than the second cross area by, for example, no more than 30%, no more than 25%, no more than 20%, no more than 15%, no more than 10%, or no more than 5%.

[0082] By making the second capacitor electrode Ce have a first portion Ce2-1 and a second portion Ce2-2, and the first crossover distance L1 is greater than the second crossover distance L2, the inventors of this disclosure have discovered that unexpected advantages can be achieved compared to capacitor electrodes where the first crossover distance L1 is equal to the second crossover distance L2. In this array substrate, the data line DL crosses the second portion Ce2-2, forming a parasitic capacitance. The data line DL is loaded before the transistor (e.g., the second transistor T2) of the pixel driving circuit is turned on. When the transistor is turned on (e.g., via the gate scan signal provided by the gate line), the presence of the parasitic capacitance can effectively prevent the degradation of the data signal in the data line DL. On the other hand, the overlap between the data line DL and the second capacitor electrode Ce2 also causes source load. A large source load can lead to signal delay and higher power consumption. By making the second crossover distance L2 smaller than the first crossover distance L1, an unexpected balance can be achieved between the parasitic capacitance required to maintain the data signal when the transistor is turned on and a relatively small source load. Furthermore, since this array substrate can alleviate source load problems, the total number of capacitor compensation circuits in the peripheral area of ​​the array substrate can be significantly reduced, thereby allowing more space to be used for image display.

[0083] In some embodiments, reference Figure 9 The section where the data line DL intersects with the second part Ce2-2 has a line width w, optionally in the range of 2.0 μm to 4.0 μm, for example, 2.0 μm to 2.5 μm, 2.5 μm to 3.0 μm, 3.0 μm to 3.5 μm, or 3.5 μm to 4.0 μm. Optionally, the line width w is approximately 3.0 μm.

[0084] In some embodiments, reference Figure 9 The data line DL segment intersects with the second part Ce2-2 to reach an intersection area of ​​50μm. 2 Up to 90μm 2 Within a range, for example, 50μm 2 Up to 60μm 2 60μm 2 Up to 70μm 2 70μm 2 up to 80μm 2 or 80μm 2 Up to 90μm 2 Optionally, the cross area is greater than or equal to 70 μm. 2 .

[0085] refer to Figure 2 , Figure 3 , Figure 5 , Figure 6 and Figure 8In some embodiments, except for the hole region H, the orthographic projection of the first portion Ce2-1 on the substrate BS completely covers the orthographic projection of the first capacitor electrode Ce1 on the substrate BS, with a margin. Within the hole region H, there is no portion of the first portion Ce2-1 of the second capacitor electrode Ce2. The hole region H is located in the middle of the first portion Ce2-1.

[0086] Reference Figure 2 , Figure 3 and Figure 8 In some embodiments, the signal line layer includes a first connection line Cl1 located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The first connection line Cl1 is located in the same layer as the voltage supply line Vdd and the data line DL. Optionally, the array substrate also includes a first via v1 located in the via region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the first connection line Cl1 is connected to the first capacitor electrode Ce1 through the first via v1.

[0087] In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer IN away from the substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, a first connection line Cl1 is connected to the first capacitor electrode Ce1 through the first via v1 and to the semiconductor material layer SML through the second via v2.

[0088] Reference Figure 2 , Figure 3 and Figure 4 In some embodiments, the source S3, active layer ACT3, and drain D3 of the third transistor T3, the source S1, active layer ACT1, and drain D1 of the first transistor T1 are part of the overall structure in each sub-pixel, and optionally, are located in the same layer. Optionally, the first connection line Cl1 is connected to the source S3 of the third transistor T3 and the drain D1 of the first transistor T1 through the second via v2.

[0089] Figure 11 This is a diagram illustrating the structure of a region in an array substrate according to some embodiments of the present disclosure, where a portion of a semiconductor layer intersects with a second capacitor electrode. Reference Figure 9 , Figure 10 and Figure 11In some embodiments, the semiconductor material layer SML includes a cross portion COP that intersects at least one of the first portion Ce2-1 and the second portion Ce2-2, reaching a third cross distance L3. Optionally, the cross portion COP intersects with the first portion Ce2-1. Optionally, the cross portion COP intersects with the second portion Ce2-2. Optionally, the cross portion COP intersects with both the first portion Ce2-1 and the second portion Ce2-2. Figure 10 and Figure 11 As shown, in one example, the left side of the intersecting part COP intersects with the first part Ce2-1, and the right side of the intersecting part COP intersects with the second part Ce2-2, with the left and right sides being parallel to each other.

[0090] In one example, such as Figure 11 As shown, the cross section COP, the voltage supply line Vdd, and the data line DL are substantially parallel to each other. In another example, the cross section COP, the voltage supply line Vdd, the section where they cross the first section Ce2-1, and the section where the data line DL crosses the second section Ce2-2 are substantially parallel to each other.

[0091] Reference Figure 8 , Figure 9 , Figure 10 and Figure 11 In some embodiments, the orthographic projections of the crossover portion COP onto the substrate BS, the orthographic projection of the voltage supply line Vdd onto the substrate BS, and the orthographic projection of the data line DL onto the substrate BS substantially do not overlap with each other. As used herein, the term "substantially non-overlapping" means that the two orthographic projections do not overlap by at least 90% (e.g., at least 92%, at least 94%, at least 96%, at least 98%, at least 99%, or 100%). By substantially overlapping the data line DL with the crossover portion COP, the source load on the data line DL can be further reduced.

[0092] In some embodiments, the orthographic projections of the semiconductor layer on the substrate BS, the voltage supply line Vdd on the substrate BS, and the data line DL on the substrate BS do not substantially overlap. This can further reduce the source load on the data line DL.

[0093] In some embodiments, the third intersection distance L3 is less than or equal to the first intersection distance L1, and greater than or equal to the second intersection distance L2. (See reference) Figure 9 , Figure 10 and Figure 11 In one example, the third cross distance L3 is less than the first cross distance L1 and greater than the second cross distance L2.

[0094] Reference Figure 11 and Figure 4In some embodiments, the drain D2 of the second transistor T2, the active layer ACT2 of the second transistor T2, the drain D4 of the fourth transistor T4, the active layer ACT4 of the fourth transistor T4, the source Sd of the driving transistor Td, and the active layer ACTd of the driving transistor Td are part of the overall structure in each sub-pixel. Optionally, at least a portion of the cross portion COP directly connects the drain D2 of the second transistor T2, the drain D4 of the fourth transistor T4, and the source Sd of the driving transistor Td to each other.

[0095] Figure 12 The structure of a first portion and a second portion of a second capacitor electrode in an array substrate according to some embodiments of the present disclosure is shown. Reference Figure 12 In some embodiments, the first portion Ce1 includes a main sub-portion Msp, a first side sub-portion Ssp1, and a second side sub-portion Ssp2. In one example, the main sub-portion Msp has a first side surface Ls1, a second side surface Ls2 opposite to the first side surface Ls1, a third side surface Ls3 connecting the first side surface Ls1 and the second side surface Ls2, and a fourth side surface Ls4 opposite to the third side surface Ls3. Optionally, the fourth side surface Ls4 connects the first side surface Ls1 and the second side surface Ls2. (See reference...) Figure 12 The first side Ls1 is adjacent to the first side sub-part Ssp1; the second side Ls2 is adjacent to the second side sub-part Ssp2; and the third side Ls3 is adjacent to the second part Ce2-2. The main sub-part Msp, the first side sub-part Ssp1, the second side sub-part Ssp2, and the second part Ce2-2 are part of the overall structure in each sub-pixel. In one example, the first side Ls1 is the side where the main sub-part Msp is directly connected to the first side sub-part Ssp1; the second side Ls2 is the side where the main sub-part Msp is directly connected to the second side sub-part Ssp2; and the third side Ls3 is the side where the main sub-part Msp is directly connected to the second part Ce2-2. Therefore, in some examples, the third side Ls3 is also a side of the second part Ce2-2. Optionally, the length of the third side Ls3 is substantially the same as the second intersection distance L2. As used herein, the term “substantially identical” means that the difference between two values ​​does not exceed 10% of a base value (e.g., one of the two values), such as not exceeding 8%, 6%, 4%, 2%, 1%, 0.5%, 0.1%, 0.05%, and 0.01% of the base value.

[0096] In some embodiments, such as Figure 11As shown, the first side sub-part Ssp1 has a substantially trapezoidal shape, and the second side sub-part Ssp2 has a substantially inverted trapezoidal shape. As used herein, "substantially trapezoidal shape" or "substantially inverted trapezoidal shape" can include a shape or geometry having at least one pair of substantially parallel sides (regardless of whether the other two sides include straight lines, curves, or others). As used herein, the term "substantially parallel sides" means two sides forming an angle ranging from 0 degrees to about 15 degrees, for example, 0 degrees to about 1 degree, about 1 degree to about 2 degrees, about 2 degrees to about 5 degrees, about 5 degrees to about 10 degrees, or about 10 degrees to about 15 degrees. Optionally, the at least one pair of substantially parallel sides of the substantially trapezoidal shape includes a shorter side and a longer side, wherein the longer side is closer to the first side Ls1 of the main sub-part Msp. Optionally, the at least one pair of substantially parallel sides of the substantially inverted trapezoidal shape includes a shorter side and a longer side, wherein the longer side is closer to the second side Ls2 of the main sub-part Msp.

[0097] Figure 13 This is a diagram illustrating the structure of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 14 It is along Figure 13 A cross-sectional view of line B-B' in the diagram. Figure 15 It is along Figure 13 A cross-sectional view of line C-C' in the diagram. (Refer to...) Figure 3 , Figure 9 , Figure 13 and Figure 15 In some embodiments, the array substrate further includes connection vias (e.g., a first connection via cv1 or a second connection via cv2) extending through the interlayer dielectric layer (ILD). Optionally, a voltage supply line Vdd is connected to a first portion Ce2-1 of the second capacitor electrode Ce2 via the connection vias (e.g., via the first connection via cv1 and the second connection via cv2). In some embodiments, the second capacitor electrode Ce2 is configured to provide a high voltage signal through the voltage supply line Vdd, such as... Figure 2 The circuit diagram is shown.

[0098] Reference Figure 3 , Figure 7 , Figure 9 , Figure 13 , Figure 14 and Figure 15 In some embodiments, the signal line layer includes a voltage supply line Vdd, a data line DL, a first connection line Cl1, and a second connection line Cl2. Optionally, the second connection line Cl2 is located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. Optionally, the second connection line Cl2 is in the same layer as the voltage supply line Vdd and the data line DL. (See reference...) Figure 3 , Figure 6 , Figure 9 , Figure 13 , Figure 14 and Figure 15 In some embodiments, the second conductive layer includes a second capacitor electrode Ce2 and a reset signal line Vint. (See also...) Figure 13 , Figure 14 and Figure 15 In some embodiments, the array substrate includes a third via v3. The third via v3 extends through the interlayer dielectric layer ILD. A second connection line Cl2 is connected to a reset signal line Vint through the third via v3. Optionally, the array substrate also includes a fourth via v4 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The second connection line Cl2 is connected to the semiconductor material layer SML through the fourth via v4.

[0099] Reference Figure 3 , Figure 4 and Figure 14 In some embodiments, the source S1 of the first transistor T1 and the active layer ACT1 of the first transistor T1 are part of the overall structure in each sub-pixel. The second connection line Cl2 is connected to the source S1 of the first transistor T1 through a fourth via v4. (Refer to...) Figure 2 and Figure 14 The reset signal can be provided from the reset signal line Vint to the source S1 of the first transistor T1 through the second connection line Cl2.

[0100] Reference Figure 3 , Figure 7 , Figure 9 , Figure 13 and Figure 14 In some embodiments, the array substrate includes a fifth via v5 that extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Data lines DL are connected to the semiconductor material layer SML through the fifth via v5. (See reference...) Figure 3 , Figure 4 and Figure 14 In some embodiments, the source S2, active layer ACT2, and drain D2 of the second transistor T2 are part of the overall structure in each sub-pixel. The data line DL is connected to the source S2 of the second transistor T2 through a fifth via v5. (Refer to...) Figure 2 and Figure 14 The data signal can be provided from the data line DL through the fifth via v5 to the source S2 of the second transistor T2.

[0101] Reference Figure 3 , Figure 7 , Figure 9 , Figure 13 and Figure 15In some embodiments, the array substrate includes a sixth via 6 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. A voltage supply line Vdd is connected to the semiconductor material layer SML through the sixth via 6. (See reference...) Figure 3 , Figure 4 and Figure 15 In some embodiments, the source S4, active layer ACT4, and drain D4 of the fourth transistor T4 are part of the overall structure in each sub-pixel. The voltage supply line Vdd is connected to the source S4 of the fourth transistor T4 through a sixth via v6. (Refer to...) Figure 2 and Figure 14 A high-voltage signal can be supplied from the voltage supply line Vdd through the sixth via v6 to the source S4 of the fourth transistor T4.

[0102] Reference Figure 3 , Figure 7 , Figure 9 , Figure 13 and Figure 15 In some embodiments, the array substrate includes a seventh via 7 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The anode contact pad ACP is connected to the semiconductor material layer SML through the seventh via 7. (See reference...) Figure 3 , Figure 4 and Figure 15 In some embodiments, the source S5, active layer ACT5, and drain D5 of the fifth transistor T5 are part of the overall structure in each sub-pixel. The anode contact pad ACP is connected to the drain D5 of the fifth transistor T5 through the seventh via v7. (Refer to...) Figure 2 and Figure 14 The voltage signal is provided from the drain D5 of the fifth transistor T5 through the anode contact pad ACP to the anode of the light-emitting element LE, so as to drive the light-emitting element LE to emit light.

[0103] In some embodiments, refer to Figures 3 to 7 Multiple sub-pixels Sp include the first sub-pixel (e.g., Figure 3 The left sub-pixel), the second sub-pixel (e.g., Figure 3 The middle sub-pixel) and the third sub-pixel (e.g., Figure 3The right sub-pixel in the image. In the first sub-pixel (e.g., the red sub-pixel), the voltage signal line Vdd intersects the semiconductor material layer SML to reach a first overlap area. In the second sub-pixel (e.g., the green sub-pixel), the voltage signal line Vdd intersects the semiconductor material layer SML to reach a second overlap area. In the third sub-pixel (e.g., the blue sub-pixel), the voltage signal line Vdd intersects the semiconductor material layer SML to reach a third overlap area. Optionally, the third overlap area is larger than the first overlap area and larger than the second overlap area.

[0104] In some embodiments, in a first sub-pixel (e.g., a red sub-pixel), the voltage signal line Vdd intersects with the second capacitor electrode Ce2 to a fourth overlapping area. In a second sub-pixel (e.g., a green sub-pixel), the voltage signal line Vdd intersects with the second capacitor electrode Ce2 to a fifth overlapping area. In a third sub-pixel (e.g., a blue sub-pixel), the voltage signal line Vdd intersects with the second capacitor electrode Ce2 to a sixth overlapping area. Optionally, the sixth overlapping area is larger than the fourth overlapping area and larger than the fifth overlapping area.

[0105] Figure 16 This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 16 In some embodiments, the array substrate includes a first data line DL1, a second data line DL2, and a third data line DL3, configured to provide data signals to a first pixel driving circuit pdc1, a second pixel driving circuit pdc2, and a third pixel driving circuit pdc3, respectively; and a first voltage supply line Vdd1, a second voltage supply line Vdd2, and a third voltage supply line Vdd3, configured to provide high voltage signals to the first pixel driving circuit pdc1, the second pixel driving circuit pdc2, and the third pixel driving circuit pdc3, respectively. In one example, the first pixel driving circuit pdc1, the second pixel driving circuit pdc2, and the third pixel driving circuit pdc3 are configured to drive image display in a first sub-pixel, a second sub-pixel, and a third sub-pixel, respectively. In one example, the first sub-pixel, the second sub-pixel, and the third sub-pixel are a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.

[0106] Figure 17 This is a diagram illustrating the structure of semiconductor material layers in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 18 This is a diagram illustrating the structure of a first conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 19 This is a diagram illustrating the structure of a second conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 20This is a diagram illustrating the structure of the signal line layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 21 It is along Figure 16 A cross-sectional view of line D-D' in the diagram. (Refer to...) Figures 16 to 21 In some embodiments, the array substrate includes a substrate BS, a semiconductor material layer SML on the substrate BS, a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS, a first conductive layer located on the side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on the side of the first conductive layer away from the gate insulating layer GI, a second conductive layer located on the side of the insulating layer IN away from the first conductive layer, an interlayer dielectric layer ILD located on the side of the second conductive layer away from the insulating layer IN, a signal line layer located on the side of the interlayer dielectric layer ILD away from the second conductive layer, and a planarization layer PLN located on the side of the signal line layer away from the interlayer dielectric layer ILD.

[0107] Reference Figure 16 Each of the first pixel driving circuit pdc1, the second pixel driving circuit pdc2, and the third pixel driving circuit pdc3 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td.

[0108] Reference Figure 2 , Figure 16 and Figure 18 In some embodiments, the first conductive layer includes a gate line GL, a reset control signal line rst, a light emission control signal line em, and a first capacitor electrode Ce1 for a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the gate line GL, the reset control signal line rst, the light emission control signal line em, and the first capacitor electrode Ce1 are located in the same layer.

[0109] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the gate line GL and the first capacitor electrode Ce1 are formed by one or more steps of the same patterning process performed on the same material layer, the gate line GL and the first capacitor electrode Ce1 are located in the same layer. In another example, the gate line GL and the first capacitor electrode Ce1 can be formed in the same layer by simultaneously performing the steps of forming the gate line GL and forming the first capacitor electrode Ce1. The term "same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view.

[0110] Reference Figure 2 , Figure 16 and Figure 19 In some embodiments, the second conductive layer includes a reset signal line Vint and a second capacitor electrode Ce2 for a storage capacitor Cst. Various suitable conductive materials and manufacturing methods can be used to fabricate the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the reset signal line Vint and the second capacitor electrode Ce2 are located in the same layer.

[0111] refer to Figure 2 , Figure 16 and Figure 20 In some embodiments, the signal line layer includes a first voltage supply line Vdd1, a second voltage supply line Vdd2, a third voltage supply line Vdd3, a first data line DL1, a second data line DL2, and a third data line DL3, a first anode contact pad ACP1, a second anode contact pad ACP2, a third anode contact pad ACP3, a first connection line Cl1, and a second connection line Cl2. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the first voltage supply line Vdd1, the second voltage supply line Vdd2, the third voltage supply line Vdd3, the first data line DL1, the second data line DL2, the third data line DL3, the first anode contact pad ACP1, the second anode contact pad ACP2, the third anode contact pad ACP3, the first connecting line Cl1, and the second connecting line Cl2 are on the same layer. Figure 20As shown, the data lines (e.g., the first data line DL1, the second data line DL2, and the third data line DL3) are basically straight lines.

[0112] refer to Figure 2 , Figure 16 , Figure 18 , Figure 19 and Figure 21 In some embodiments, the storage capacitor Cst includes a first capacitor electrode Ce1, a second capacitor electrode Ce2, and an insulating layer IN between the first capacitor electrode Ce1 and the second capacitor electrode Ce2. For example... Figure 2 As shown, the second capacitor electrode Ce2 is electrically connected to the corresponding voltage supply line. For example, the second capacitor electrode Ce2 and the corresponding voltage supply line are configured to always be supplied with the same voltage.

[0113] Reference Figure 2 , Figure 16 and Figure 17 In some embodiments, the semiconductor material layer has an integral structure in each pixel driving circuit. Figure 17 In the diagram, the pixel driving circuit (first pixel driving circuit pdc1) on the left is marked, indicating the area corresponding to multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in the pixel driving circuit. Figure 17In the diagram, the pixel driving circuit on the left (the third pixel driving circuit pdc3) is labeled, indicating the components of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a source S1, and a drain D1. The second transistor T2 includes an active layer ACT2, a source S2, and a drain D2. The third transistor T3 includes an active layer ACT3, a source S3, and a drain D3. The fourth transistor T4 includes an active layer ACT4, a source S4, and a drain D4. The fifth transistor T5 includes an active layer ACT5, a source S5, and a drain D5. The sixth transistor T6 includes an active layer ACT6, a source S6, and a drain D6. The driving transistor Td includes an active layer ACTd, a source Sd, and a drain Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), sources (S1, S2, S3, S4, S5, S6, and Sd), and drains (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each sub-pixel are part of the overall structure in that sub-pixel. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), sources (S1, S2, S3, S4, S5, and Sd), and drains (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are on the same layer.

[0114] Reference Figure 2 , Figure 16 and Figure 21 In some embodiments, the signal line layer includes a first connection line Cl1 located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The first connection line Cl1 is in the same layer as voltage supply lines (e.g., the second voltage supply line Vdd2) and data lines (e.g., the second data line DL2). Optionally, the array substrate also includes a first via v1 located in the via region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the first connection line Cl1 is connected to the first capacitor electrode Ce1 through the first via v1.

[0115] In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer IN away from the substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, a first connection line Cl1 is connected to the first capacitor electrode Ce1 through the first via v1 and to the semiconductor material layer SML through the second via v2.

[0116] Figure 22A This is a diagram illustrating the structure of the planarization layer of the array substrate and the anode of the light-emitting element according to some embodiments of the present disclosure. Figure 22B It is along Figure 22A A cross-sectional view of line E-E' in the diagram. (Refer to...) Figure 2 , Figure 16 , Figure 20 , Figure 22A and Figure 22B In some embodiments, the signal line layer includes a first anode contact pad ACP1, a second anode contact pad ACP2, and a third anode contact pad ACP3, respectively, located on the interlayer dielectric layer ILD. The array substrate includes a planarization layer PLN located on the side of the signal line layer away from the interlayer dielectric layer ILD; first anode contact holes AH1, AH2, and AH3 extending through the planarization layer PLN; and first anodes AD1, AD2, and AD3, respectively, connected to the first anode contact pads ACP1, ACP2, and ACP3 through the first anode contact holes AH1, AH2, and AH3. The first anodes AD1, AD2, and AD3 are respectively the anodes of a first light-emitting element, a second light-emitting element, and a third light-emitting element connected to a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit.

[0117] Figure 23A This is a diagram illustrating the structure of the pixel defining layer of the array substrate and the anode of the light-emitting element according to some embodiments of the present disclosure. Figure 23B It is along Figure 23A The cross-sectional view of line F-F' in the diagram. (Refer to...) Figure 2 , Figure 16 , Figure 23A and Figure 23B In some embodiments, the array substrate further includes a pixel defining layer (PDL) located on the side of the first anode AD1, the second anode AD2, and the third anode AD3 away from the planarization layer PLN. The array substrate also includes a first sub-pixel opening SA1, a second sub-pixel opening SA2, and a third sub-pixel opening SA3 extending through the pixel defining layer (PDL), respectively.

[0118] Figure 24 This is a diagram illustrating the structure of the pixel defining layer, the anode of the light-emitting element, and the light-emitting layer of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 2 , Figure 16 and Figure 24In some embodiments, the array substrate further includes a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3 located in the first sub-pixel opening SA1, the second sub-pixel opening SA2, and the third sub-pixel opening SA3, respectively. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 are respectively connected to the first anode AD1, the second anode AD2, and the third anode AD3 through the first sub-pixel opening SA1, the second sub-pixel opening SA2, and the third sub-pixel opening SA3. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 are the light-emitting layers of the first light-emitting element, the second light-emitting element, and the third light-emitting element, respectively. The first light-emitting element, the second light-emitting element, and the third light-emitting element are respectively connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit.

[0119] Figure 25 This is a diagram illustrating the structure of the cathode layer, anode, and light-emitting layer of a light-emitting element in an array substrate according to some embodiments of the present disclosure. (See reference...) Figure 2 , Figure 16 and Figure 25 In some embodiments, the array substrate further includes a cathode layer CD, which is located on the side of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 away from the first anode AD1, the second anode AD2, and the third anode AD3. Optionally, the cathode layer CD is an integral layer for all light-emitting elements in the array substrate.

[0120] Figure 26A This is a diagram illustrating the structure of the signal line layer and the anode of the light-emitting element of an array substrate according to some embodiments of the present disclosure. (See reference...) Figure 26A In some embodiments, the first virtual line Vl1 and the second virtual line Vl2 pass through the first voltage supply line Vdd1, the second voltage supply line Vdd2 and the third voltage supply line Vdd3, respectively, as well as the first data line DL1, the second data line DL2 and the third data line DL3. Figure 26B yes Figure 26A A magnified view of the area between the first and second virtual lines. (Reference) Figure 26A and Figure 26B In some embodiments, the first voltage supply line Vdd1, the second voltage supply line Vdd2, and the third voltage supply line Vdd3 each include a first voltage supply line portion vp1, a second voltage supply line portion vp2, and a third voltage supply line portion vp3, which are located between the first virtual line Vl1 and the second virtual line Vl2, respectively.

[0121] Figure 26C It is along Figure 26B A cross-sectional view of the G-G' line. (Refer to...) Figure 26A , Figure 26B and Figure 26C In some embodiments, the orthographic projection of the third anode AD3 of the third light-emitting element onto the substrate (e.g., the interlayer dielectric layer ILD) completely covers the orthographic projection of the third voltage supply line portion vp3 onto the substrate. The third voltage supply line portion vp3 has a third linewidth w3 that is greater than the first linewidth w1 of the first voltage supply line portion vp1 and greater than the second linewidth w2 of the second voltage supply line portion vp2.

[0122] Optionally, w1 is in the range of 3 μm to 9 μm, for example, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, or 8 μm to 9 μm. Optionally, w1 is about 5.6 μm. Optionally, w2 is in the range of 3 μm to 9 μm, for example, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, or 8 μm to 9 μm. Optionally, w2 is about 5.6 μm. Optionally, w3 is in the range of 6 μm to 12 μm, for example, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, 9 μm to 10 μm, 10 μm to 11 μm, or 11 μm to 12 μm. Optionally, w3 is approximately 9 micrometers.

[0123] refer to Figure 26A , Figure 26B and Figure 26C In some embodiments, the first data line DL1, the second data line DL2, and the third data line DL3 each include a first data line portion dp1, a second data line portion dp2, and a third data line portion dp3, respectively, between the first virtual line Vl1 and the second virtual line Vl2. Optionally, the first data line portion dp1, the second data line portion dp2, and the third data line portion dp3 have substantially the same linewidth w4. As used herein, the term "substantially the same" means that the difference between two values ​​does not exceed 10% of a base value (e.g., one of the two values), such as not exceeding 8%, 6%, 4%, 2%, 1%, 0.5%, 0.1%, 0.05%, and 0.01% of the base value.

[0124] Optionally, w4 is in the range of 1 μm to 5 μm, for example, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, or 4 μm to 5 μm. Optionally, w4 is about 3 μm.

[0125] Optionally, the third line width w3 refers to the maximum line width of the third voltage supply line portion vp3, the first line width w1 refers to the maximum line width of the first voltage supply line portion vp1, the second line width w2 refers to the maximum line width of the second voltage supply line portion vp2, and the line width w4 refers to the maximum line width of each of the first data line portion dp1, the second data line portion dp2, and the third data line portion dp3.

[0126] Optionally, the third line width w3 refers to the average line width of the third voltage supply line portion vp3, the first line width w1 refers to the average line width of the first voltage supply line portion vp1, the second line width w2 refers to the average line width of the second voltage supply line portion vp2, and the line width w4 refers to the average line width of the first data line portion dp1, the second data line portion dp2, and the third data line portion dp3, respectively.

[0127] Optionally, the third line width w3 refers to the minimum line width of the third voltage supply line portion vp3, the first line width w1 refers to the minimum line width of the first voltage supply line portion vp1, the second line width w2 refers to the minimum line width of the second voltage supply line portion vp2, and the line width w4 refers to the minimum line width of each of the first data line portion dp1, the second data line portion dp2, and the third data line portion dp3.

[0128] Optionally, when measuring the line widths w1, w2, and w3 along lines parallel to the first virtual line Vl1 and the second virtual line Vl2 and passing through the first voltage supply line portion vp1, the second voltage supply line portion vp2, and the third voltage supply line portion vp3, the third voltage supply line portion vp3 has a third line width w3 that is greater than the first line width w1 of the first voltage supply line portion vp1 and greater than the second line width w2 of the second voltage supply line portion vp2.

[0129] Reference Figure 26A , Figure 26B and Figure 26C In some embodiments, the orthographic projection of the third anode AD3 onto the substrate (e.g., the interlayer dielectric layer ILD) at least partially overlaps with the orthographic projection of the third data line portion dp3 onto the substrate. Optionally, the orthographic projection of the third anode AD3 onto the substrate (e.g., the interlayer dielectric layer ILD) completely covers the orthographic projection of the third data line portion dp3 onto the substrate.

[0130] refer to Figure 26A In some embodiments, the first data line DL1, the second data line DL2, the third data line DL3, the first voltage supply line Vdd1, the second voltage supply line Vdd2, and the third voltage supply line Vdd3 are substantially parallel to each other (see also...). Figure 1 , Figure 16 and Figure 20Optionally, data lines (e.g., first data line DL1, second data line DL2, and third data line DL3) and voltage supply lines (e.g., first voltage supply line Vdd1, second voltage supply line Vdd2, and third voltage supply line Vdd3) are arranged alternately. Optionally, the first data line portion dp1, the second data line portion dp2, the third data line portion dp3, the first voltage supply line portion vp1, the second voltage supply line portion vp2, and the third voltage supply line portion vp3 are substantially parallel to each other. Optionally, the data line portions (e.g., first data line portion dp1, second data line portion dp2, and third data line portion dp3) and voltage supply line portions (e.g., first voltage supply line portion vp1, second voltage supply line portion vp2, and third voltage supply line portion vp3) are arranged alternately. As used herein, the term “substantially parallel” means that the angle between the two signal lines is in the range of 0 to about 25 degrees, such as 0 to about 5 degrees, 0 to about 10 degrees, 0 to about 15 degrees, or 0 to about 20 degrees.

[0131] Figure 27 The structure of a voltage supply line portion in an array substrate according to some embodiments of the present disclosure is shown. Reference Figure 27 In some embodiments, the third voltage supply line portion VP3 includes a main sub-portion MSP and a widened sub-portion WSP. The main sub-portion MSP is located between the widened sub-portion WSP and the third data line portion DP3, therefore the main sub-portion MSP is located between the widened sub-portion WSP and the third data line. Figure 27 As shown, in one example, the main sub-section msp, the first voltage supply line section VP1, and the second voltage supply line section VP2 have the same shape and substantially the same dimensions. The difference between the third voltage supply line section VP3 and either the first voltage supply line section VP1 or the second voltage supply line section VP2 is the widened sub-section wsp, which makes the linewidth of the third voltage supply line section VP3 greater than that of the first voltage supply line section VP1 and the second voltage supply line section VP2. The main sub-section msp, the first voltage supply line section VP1, and the second voltage supply line section VP2 have the same linewidth. Reference Figure 27 The main part msp has a line width w3m equal to w1 or w2.

[0132] Optionally, when measuring the line width along a line parallel to the first virtual line Vl1 and the second virtual line Vl2 and passing through the first voltage supply line portion vp1, the second voltage supply line portion vp2 and the main sub-portion msp, the main sub-portion msp, the first voltage supply line portion vp1, and the second voltage supply line portion vp2 have the same line width.

[0133] refer to Figure 26AIn some embodiments, the first anode AD1 of the first light-emitting element is located between the first voltage supply line Vdd1 and the second data line DL2; and the second anode AD2 of the second light-emitting element is located between the first voltage supply line Vdd1 and the second data line DL2. (See reference...) Figure 26C The orthographic projection of the first anode AD1 onto the substrate (e.g., the interlayer dielectric layer ILD) at least partially overlaps with the orthographic projection of the first data line DL1 (e.g., the portion of the first data line dp1) onto the substrate, and at least partially overlaps with the orthographic projection of the second voltage supply line Vdd2 (e.g., the portion of the second voltage supply line vp2) onto the substrate. Similarly, the orthographic projection of the second anode AD2 onto the substrate at least partially overlaps with the orthographic projection of the first data line DL1 (e.g., the portion of the first data line dp1) onto the substrate, and at least partially overlaps with the orthographic projection of the second voltage supply line Vdd2 (e.g., the portion of the second voltage supply line vp2) onto the substrate.

[0134] Optionally, the orthographic projection of the first anode AD1 onto the substrate (e.g., the interlayer dielectric layer ILD) covers the orthographic projection of the first portion (e.g., the first data line portion dp1) of the first data line DL1 onto the substrate, and covers the orthographic projection of the second portion (e.g., the second voltage supply line portion vp2) of the second voltage supply line Vdd2 onto the substrate. Optionally, the orthographic projection of the second anode AD2 onto the substrate covers the orthographic projection of the third portion (e.g., the first data line portion dp1) of the first data line DL1 onto the substrate, and covers the orthographic projection of the fourth portion (e.g., the second voltage supply line portion vp2) of the second voltage supply line Vdd2 onto the substrate.

[0135] In some embodiments, the orthographic projection of the first anode AD1 on the substrate also at least partially overlaps with the orthographic projection of the first voltage supply line Vdd1 (e.g., the portion of the first voltage supply line vp1) on the substrate; and the orthographic projection of the second anode AD2 on the substrate at least partially overlaps with the orthographic projection of the first voltage supply line Vdd1 (e.g., the portion of the first voltage supply line vp1) on the substrate.

[0136] Optionally, the orthographic projection of the first anode AD1 onto the substrate also covers the orthographic projection of the fifth portion (e.g., the first voltage supply line portion vp1) of the first voltage supply line Vdd1 onto the substrate; the orthographic projection of the second anode AD2 onto the substrate covers the orthographic projection of the sixth portion (e.g., the first voltage supply line portion vp1) of the first voltage supply line Vdd1 onto the substrate.

[0137] See Figure 16 , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24 and Figure 25 In some embodiments, the array substrate includes a first anode contact pad ACP1, a second anode contact pad ACP2, and a third anode contact pad ACP3; a planarization layer PLN located on the side of the first anode contact pad ACP1, the second anode contact pad ACP2, and the third anode contact pad ACP3 away from the substrate (interlayer dielectric layer ILD); a first anode contact hole AH1, a second anode contact hole AH2, and a third anode contact hole AH3 extending through the planarization layer PLN; a pixel defining layer PDL located on the side of the first anode AD1, the second anode AD2, and the third anode AD3 away from the planarization layer PLN; a first sub-pixel opening SA1, a second sub-pixel opening SA2, and a third sub-pixel opening SA3 extending through the pixel defining layer PDL; and a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3 located on the side of the pixel defining layer PDL away from the substrate. The first anode AD1, the second anode AD2, and the third anode AD3 are connected to the first anode contact pad ACP1, the second anode contact pad ACP2, and the third anode contact pad ACP3 respectively through the first anode contact hole AH1, the second anode contact hole AH2, and the third anode contact hole AH3. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 are connected to the first anode AD1, the second anode AD2, and the third anode AD3 respectively through the first sub-pixel opening SA1, the second sub-pixel opening SA2, and the third sub-pixel opening SA3.

[0138] Reference Figure 24 In some embodiments, the first anode contact hole AH1 is outside the region having the first sub-pixel opening SA1; the second anode contact hole AH2 is outside the region having the second sub-pixel opening SA2; and the third anode contact hole AH3 is outside the region having the third sub-pixel opening SA3.

[0139] Figure 28 This is a diagram illustrating the structure of a first pixel driving circuit of an array substrate according to some embodiments of the present disclosure. Figure 29 It is along Figure 28 A cross-sectional view of the H-H' line in the diagram. Figure 30 for Figure 28 Cross-sectional view of line I-I'. (Refer to...) Figure 16 , Figure 20 , Figure 28 , Figure 29 and Figure 30In some embodiments, the array substrate further includes connection vias (e.g., a first connection via cv1 or a second connection via cv2) extending through the interlayer dielectric layer (ILD). Optionally, a voltage supply line (e.g., a first voltage supply line Vdd1) is connected to a first portion Ce2-1 of the second capacitor electrode Ce2 via connection vias (e.g., via the first connection via cv1 and the second connection via cv2). In some embodiments, the second capacitor electrode Ce2 is configured to be supplied with a high voltage signal via the voltage supply line (e.g., the first voltage supply line Vdd1), such as... Figure 2 The circuit diagram is shown.

[0140] Reference Figure 16 , Figure 20 , Figure 28 , Figure 29 and Figure 30 In some embodiments, the signal line layer further includes a first connection line Cl1 and a second connection line Cl2. Optionally, the second connection line Cl2 is located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. Optionally, the second connection line Cl2 is in the same layer as the voltage supply line (e.g., the first voltage supply line Vdd1) and the data line (e.g., the first data line DL1). In some embodiments, the second conductive layer includes the second capacitor electrode Ce2 and the reset signal line Vint. (See also...) Figure 28 , Figure 29 and Figure 30 In some embodiments, the array substrate includes a third via 3. The third via 3 extends through the interlayer dielectric layer ILD. A second connection line Cl2 is connected to a reset signal line Vint through the third via 3. Optionally, the array substrate also includes a fourth via 4 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The second connection line Cl2 is connected to the semiconductor material layer SML through the fourth via 4.

[0141] Reference Figure 16 , Figure 17 and Figure 29 In some embodiments, the source S1 of the first transistor T1 and the active layer ACT1 of the first transistor T1 are part of the overall structure in each sub-pixel. The second connection line Cl2 is connected to the source S1 of the first transistor T1 through a fourth via v4. (Refer to...) Figure 2 and Figure 29 The reset signal can be provided from the reset signal line Vint to the source S1 of the first transistor T1 through the second connection line Cl2.

[0142] Reference Figure 16 , Figure 20 Figure 22 Figure 28 and Figure 29In some embodiments, the array substrate includes a fifth via v5 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Data lines (e.g., the first data line DL1) are connected to the semiconductor material layer SML through the fifth via v5. (See reference...) Figure 16 , Figure 17 and Figure 29 In some embodiments, the source S2 of the second transistor T2, the active layer ACT2 of the second transistor T2, and the drain D2 of the second transistor T2 are part of the overall structure in each sub-pixel. Data lines (e.g., first data line DL1) are connected to the source S2 of the second transistor T2 through a fifth via v5. Reference Figure 2 and Figure 29 The data signal can be supplied from the data line (e.g., the first data line DL1) through the fifth via v5 to the source S2 of the second transistor T2.

[0143] Reference Figure 16 , Figure 20 , Figure 28 and Figure 30 In some embodiments, the array substrate includes a sixth via V6 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Voltage supply lines (e.g., a first voltage supply line Vdd1) are connected to the semiconductor material layer SML through the sixth via V6. (See reference...) Figure 16 , Figure 17 and Figure 30 In some embodiments, the source S4, active layer ACT4, and drain D4 of the fourth transistor T4 are part of the overall structure in each sub-pixel. A voltage supply line (e.g., a first voltage supply line Vdd1) is connected to the source S4 of the fourth transistor T4 via a sixth via v6. Reference Figure 2 and Figure 29 A high voltage signal can be supplied from the voltage supply line (e.g., the first voltage supply line Vdd1) through the sixth via v6 to the source S4 of the fourth transistor T4.

[0144] Reference Figure 16 , Figure 20 , Figure 28 and Figure 30 In some embodiments, the array substrate includes pad contact vias (e.g., first pad contact via CNT1) extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Anode contact pads (e.g., first anode contact pad ACP1) are connected to the semiconductor material layer SML via the pad contact vias (e.g., first pad contact via CNT1). See reference... Figure 16 , Figure 17 and Figure 30In some embodiments, the source S5, active layer ACT5, and drain D5 of the fifth transistor T5 are part of the overall structure in each sub-pixel. An anode contact pad (e.g., a first anode contact pad ACP1) is connected to the drain D5 of the fifth transistor T5 via a pad contact via (e.g., a first pad contact via CNT1). Reference Figure 2 and Figure 29 A voltage signal is provided from the drain D5 of the fifth transistor T5 through the anode contact pad (e.g., the first anode AD1) to the anode of the light-emitting element, for driving the light-emitting element to emit light.

[0145] In some embodiments, the array substrate further includes at least one insulating layer between the base substrate and the first anode contact pad, the second anode contact pad, and the third anode contact pad. (Reference) Figure 16 , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24 , Figure 25 and Figure 30 In some embodiments, the array substrate includes a gate insulating layer GI, an insulating layer IN, and an interlayer dielectric layer ILD between the base substrate BS and the first anode contact pad ACP1, the second anode contact pad ACP2, and the third anode contact pad ACP3.

[0146] Figure 31 This is a diagram illustrating the connection between the anode and anode contact pads in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 31 and Figure 30 The array substrate includes a first pad contact via CNT1, a second pad contact via CNT2, and a third pad contact via CNT3 extending through the gate insulating layer GI, the insulating layer IN, and the interlayer dielectric layer ILD, respectively. The first anode contact pad ACP1, the second anode contact pad ACP2, and the third anode contact pad ACP3 are connected to the first pixel driving circuit pdc1, the second pixel driving circuit pdc2, and the third pixel driving circuit pdc3, respectively, through the first pad contact via CNT1, the second pad contact via CNT2, and the third pad contact via CNT3.

[0147] refer to Figure 31Along the direction of either the first virtual line Vl1 or the second virtual line Vl2, the first anode contact hole AH1 is located between the first pad contact via CNT1 and the first voltage supply line Vdd1. Along the direction of either the first virtual line Vl1 or the second virtual line Vl2, the second anode contact hole AH2 is located between the second pad contact via CNT2 and the second voltage supply line Vdd2. In one example, the third pad contact via CNT3 and the third anode contact hole AH3 are arranged in a direction substantially parallel to the third data line DL3 and the third voltage supply line Vdd3.

[0148] Figure 32 This is a diagram illustrating the structure of the anode of the light-emitting element of an array substrate according to some embodiments of the present disclosure. See also Figure 32 In some embodiments, the first anode AD1 includes a first body portion MP1 and a first bridge portion P1; the second anode AD2 includes a second body portion MP2 and a second bridge portion P2; and the third anode AD3 includes a third body portion MP3 and a third bridge portion P3. In one example, the first body portion MP1, the second body portion MP2, and the third body portion MP3 have a substantially rectangular shape. As used herein, the term "substantially rectangular" refers to a polygonal shape (e.g., a parallelogram) in which opposite sides are substantially parallel and the vertex angle is substantially 90 degrees. As used herein, the term "opposite sides are substantially parallel" means that two opposite sides form an angle ranging from 0 degrees to about 15 degrees, such as 0 degrees to about 1 degree, about 1 degree to about 2 degrees, about 2 degrees to about 5 degrees, about 5 degrees to about 10 degrees, and about 10 degrees to about 15 degrees. Alternatively, the apex angle of the essentially rectangular shape is in the range of about 75 degrees to about 105 degrees, for example, about 89 degrees to about 91 degrees, about 88 degrees to about 92 degrees, about 85 degrees to about 95 degrees, and about 80 degrees to about 100 degrees.

[0149] In some embodiments, the first bridge portion P1, the second bridge portion P2, and the third bridge portion P3 protrude outward from the first main body portion MP1, the second main body portion MP2, and the third main body portion MP3, respectively. See also... Figure 30 , Figure 31 and Figure 23B The first bridge portion P1, the second bridge portion P2, and the third bridge portion P3 are respectively connected to the first anode contact pad ACP1, the second anode contact pad ACP2, and the third anode contact pad ACP3 through the first anode contact hole AH1, the second anode contact hole AH2, and the third anode contact hole AH3. In such a case... Figure 31 and Figure 32In one example shown, the third bridge portion P3 protrudes outward from the third body portion MP3 in a direction substantially parallel to the first virtual line Vl1 or the second virtual line Vl2. The second bridge portion P2 protrudes outward from the second body portion MP2 in a direction substantially parallel to the second data line DL2 or the second voltage supply line Vdd2. The first bridge portion P1 protrudes outward from the first body portion MP1 in a direction inclined at an angle to the first virtual line Vl1 and the first data line DL1.

[0150] In some embodiments, each data line is configured to provide a data signal to a column of pixel driving circuits (or a column of sub-pixels), and each voltage supply line is configured to provide a high voltage signal to a column of pixel driving circuits (or a column of sub-pixels). Figure 33 The arrangement of light-emitting elements in an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 33 In some embodiments, the array substrate includes a first pixel driving circuit pdc1, a second pixel driving circuit pdc2, a third pixel driving circuit pdc3, a fourth pixel driving circuit pdc4, a fifth pixel driving circuit pdc5, and a sixth pixel driving circuit pdc6. (Refer to...) Figure 31 and Figure 33 In some embodiments, the first data line DL1, the second data line DL2, and the third data line DL3 are configured to provide data signals to the first pixel driving circuit pdc1, the second pixel driving circuit pdc2, the third pixel driving circuit pdc3, the fourth pixel driving circuit pdc4, the fifth pixel driving circuit pdc5, and the sixth pixel driving circuit pdc6, respectively. The first pixel driving circuit pdc1, the second pixel driving circuit pdc2, and the third pixel driving circuit pdc3 are arranged sequentially along a direction substantially parallel to the first virtual line Vl1 or the second virtual line Vl2. The fourth pixel driving circuit pdc4, the fifth pixel driving circuit pdc5, and the sixth pixel driving circuit pdc6 are arranged sequentially along a direction substantially parallel to the first virtual line Vl1 or the second virtual line Vl2. The first pixel driving circuit pdc1 and the fourth pixel driving circuit pdc4 are arranged along a direction substantially parallel to the first data line DL1 or the first voltage supply line Vdd1. The second pixel driving circuit PDC2 and the fifth pixel driving circuit PDC5 are arranged in a direction substantially parallel to the second data line DL2 or the second voltage supply line Vdd2. The third pixel driving circuit PDC3 and the sixth pixel driving circuit PDC6 are arranged in a direction substantially parallel to the third data line DL3 or the third voltage supply line Vdd3.

[0151] Reference Figure 33In some embodiments, the first light-emitting element LE1 is driven by the first pixel driving circuit pdc1 and is at least partially located in the region having the fifth pixel driving circuit pdc5. The second light-emitting element LE2 is driven by the second pixel driving circuit pdc2 and is partially located in the region having the first pixel driving circuit pdc1 and also partially located in the region having the second pixel driving circuit pdc2. The third light-emitting element LE3 is driven by the third pixel driving circuit pdc3 and is partially located in the region having the third pixel driving circuit pdc3 and also partially located in the region having the sixth pixel driving circuit pdc6.

[0152] This disclosure reveals that the uniformity of the anode in a display panel can adversely affect image display. For example, color shift can be caused by anode tilt. This disclosure also finds that the signal lines beneath the anode can significantly influence the degree of anode tilt. In one example, signal lines are positioned on one side beneath the anode, while no signal lines are present on the other side. This results in surface inhomogeneity of the planarization layer on top of the signal lines. This surface inhomogeneity of the planarization layer, in turn, causes anode tilt on top of the planarization layer. Figure 34 This is a cross-sectional view of the array substrate. (For example...) Figure 34 As shown, the presence of signal line 1 beneath the left portion of planarization layer 2 causes unevenness in the planarized surface, which in turn causes the anode 3 on top of planarization layer 2 to tilt to the right. The tilted anode reflects more light towards the right side of the display panel. In the display panel, the anodes associated with sub-pixels of different colors have different tilt angles, so the light reflected by the anodes in sub-pixels of different colors is reflected at different angles to reflect different colors of light. The cumulative effect of this problem leads to color shift at wide viewing angles.

[0153] Figure 35 This is a schematic diagram showing a cross-sectional view of the array substrate. (Example) Figure 35 As shown, there is no signal line 1 below the untilted third anode 3-3. Signal line 1 is located below anodes 3-1 and 3-2. However, the signal line is only located below the right side of anode 3-1 and only below the left side of anode 3-2, which causes these two anodes to be tilted. Anodes 3-1, 3-2, and 3-3 are the anodes of the red, green, and blue subpixels, respectively. Because the tilt angles of the anodes in the three subpixels of different colors are different from each other, color shift occurs at large viewing angles.

[0154] Figure 36 This is a schematic diagram showing a cross-sectional view of the array substrate. (Example) Figure 36 As shown, the signal lines are located below the left and right portions of anode 3-1, and below the left and right portions of anode 3-2. All anodes are essentially flat, thus mitigating the color shift problem.

[0155] In this array substrate, the third voltage supply line portion vp3 (below the third anode AD3) has an increased linewidth. For example... Figure 26A and Figure 27 As shown, the main sub-section MSP and the third data line DL3 are mostly located below the right side of the third anode AD3. Without compensation, this can lead to anode tilt and color shift in the display panel. By widening the sub-section WSP to increase the line width of the third voltage supply section VP3 below the third anode AD3, the signal lines (third voltage supply section VP3 and data line DL3) are more evenly distributed below the left and right sides of the third anode AD3, preventing anode tilt. Therefore, the color shift problem can be mitigated.

[0156] The presence of anode contact holes in the array substrate can also affect the tilt angle of the relevant anodes. Furthermore, residual planarization layer material in the anode contact holes may cover part of the anode. As discovered in this disclosure, these issues also affect the performance of the display panel. Figure 37 This is a cross-sectional image of the array substrate. (Reference) Figure 37 An anode contact hole AH extends through the planarization layer PLN to expose the surface of the anode contact pad ACP. A portion of the anode AD is connected to the anode contact pad ACP through the anode contact hole AH. A pixel defining layer PDL is formed to define the sub-pixel opening SA. Figure 37 As shown, the anode AD includes a bridge portion BP that connects the main body of the anode in the sub-pixel opening SA to the anode contact pad ACP. By separating the anode contact hole AH from the sub-pixel opening SA by the bridge portion BP, for example, by placing the anode contact hole AH outside the area containing the sub-pixel opening SA, the adverse effects caused by the presence of the anode contact hole can be minimized or eliminated.

[0157] In another aspect, this disclosure provides a display panel comprising an array substrate manufactured as described herein or by the methods described herein, and a counter substrate facing the array substrate. Optionally, the display panel is an organic light-emitting diode (OLED) display panel. Optionally, the display panel is a micro-LED display panel.

[0158] In another aspect, the present invention provides a display device comprising an array substrate manufactured as described herein or by the methods described herein, and one or more integrated circuits connected to the array substrate.

[0159] In another aspect, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes forming gate lines; forming data lines; forming voltage supply lines; and forming pixel driving circuitry. Optionally, forming the pixel driving circuitry includes forming a plurality of transistors and forming a storage capacitor. Optionally, forming the storage capacitor includes forming a first capacitor electrode, forming a second capacitor electrode, and forming an insulating layer between the first capacitor electrode and the second capacitor electrode. Optionally, the second capacitor electrode is formed to be electrically connected to the voltage supply line. Optionally, forming the second capacitor electrode includes forming a first portion and a second portion as part of a first integral structure in each sub-pixel. Optionally, the voltage supply line intersects the first portion by a first intersection distance. Optionally, the data line intersects the second portion by a second intersection distance. Optionally, the first intersection distance is greater than the second intersection distance.

[0160] In some embodiments, the voltage supply line and the data line are substantially parallel to each other; and the sections of the voltage supply line that intersect the first portion and the sections of the data line that intersect the second portion are substantially parallel to each other.

[0161] In some embodiments, the method further includes forming an interlayer dielectric layer between a voltage supply line and a second capacitor electrode; and forming a connection via extending through the interlayer dielectric layer. Optionally, the voltage supply line is formed to be connected to the first portion of the second capacitor electrode through the connection via.

[0162] In some embodiments, the method further includes forming a semiconductor material layer that intersects with at least one of the first portion and the second portion, the intersection reaching a third intersection distance. Optionally, the third intersection distance is less than or equal to the first intersection distance and greater than or equal to the second intersection distance. Optionally, the intersection portion intersects with both the first portion and the second portion.

[0163] In some embodiments, the crossing portion, the voltage supply line, and the data line are substantially parallel to each other; and the crossing portion, the section where the voltage supply line intersects with the first portion, and the section where the data line intersects with the second portion are substantially parallel to each other.

[0164] In some embodiments, forming a plurality of transistors includes forming a driving transistor; forming a first transistor; forming a second transistor; forming a third transistor; forming a fourth transistor; and forming a fifth transistor. Optionally, the drain of the second transistor, the active layer of the second transistor, the drain of the fourth transistor, the active layer of the fourth transistor, the source of the driving transistor, and the active layer of the driving transistor are formed as part of a second integral structure in each sub-pixel. Optionally, at least a portion of the intersection portion is formed to directly connect the drain of the second transistor, the drain of the fourth transistor, and the source of the driving transistor to each other.

[0165] In some embodiments, the orthographic projections of the cross portion on the substrate, the orthographic projections of the voltage supply line on the substrate, and the orthographic projections of the data line on the substrate do not substantially overlap with each other.

[0166] In some embodiments, except for the hole region in which a portion of the second capacitor electrode is not present, the orthographic projection of the first portion on the substrate completely covers the orthographic projection of the first capacitor electrode on the substrate, with a margin.

[0167] In some embodiments, the method further includes forming an interlayer dielectric layer between a voltage supply line and a second capacitor electrode; forming a first connection line located on the side of the interlayer dielectric layer away from the second capacitor electrode and in the same layer as the voltage supply line and the data line; and forming a first via located in the via region and extending through the interlayer dielectric layer and the insulating layer. Optionally, the first connection line is connected to the first capacitor electrode through the first via.

[0168] In some embodiments, the method further includes forming a semiconductor material layer on a substrate; and forming a gate insulating layer on the side of the semiconductor material layer away from the substrate. Optionally, the first capacitor electrode is formed on the side of the gate insulating layer away from the substrate. Optionally, the method further includes forming a second via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer. Optionally, the first connection line is connected to the semiconductor material layer through the second via.

[0169] In some embodiments, forming a plurality of transistors includes forming a driving transistor; forming a first transistor; forming a second transistor; forming a third transistor; forming a fourth transistor; and forming a fifth transistor. Optionally, the source, active layer, and drain of the third transistor, the source, active layer, and drain of the first transistor are part of a second overall structure in each sub-pixel. Optionally, the first connection line is connected to the source of the third transistor and the drain of the first transistor through the second via.

[0170] In some embodiments, forming the first portion includes forming a main portion, a first side portion, and a second side portion. Optionally, the main portion is formed having a first side surface, a second side surface opposite to the first side surface, a third side surface connecting the first side surface and the second side surface, and a fourth side surface opposite to the third side surface. Optionally, the first side surface is adjacent to the first side portion. Optionally, the second side surface is adjacent to the second side portion. Optionally, the third side surface is adjacent to the second portion. Optionally, the first side portion has a substantially trapezoidal shape; while the second side portion has a substantially inverted trapezoidal shape. Optionally, the third side surface is a side surface of the second portion; and the length of the third side surface is substantially the same as the second intersection distance.

[0171] In some embodiments, the method further includes forming an interlayer dielectric layer between a voltage supply line and a second capacitor electrode; forming a second connection line located on the side of the interlayer dielectric layer away from the second capacitor electrode and in the same layer as the voltage supply line and the data line; forming a reset signal line located on the side of the insulating layer away from the first capacitor electrode and in the same layer as the second capacitor electrode; and forming a third via extending through the interlayer dielectric layer. Optionally, the second connection line is connected to the reset signal line through the third via.

[0172] In some embodiments, the method further includes forming a semiconductor material layer on a substrate; and forming a gate insulating layer located on the side of the semiconductor material layer away from the substrate. Optionally, a first capacitor electrode is formed located on the side of the gate insulating layer away from the substrate. Optionally, the method further includes forming a fourth via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer. Optionally, a second connection line is formed to connect to the semiconductor material layer through the fourth via.

[0173] In some embodiments, forming a plurality of transistors includes forming a driving transistor; forming a first transistor; forming a second transistor; forming a third transistor; forming a fourth transistor; and forming a fifth transistor. Optionally, the source of the first transistor and the active layer of the first transistor are part of a second integral structure in each sub-pixel. Optionally, the second connection line is connected to the source of the first transistor through the fourth via.

[0174] In another aspect, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit; forming a first data line, a second data line, and a third data line configured to provide data signals to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively; forming a first voltage supply line, a second voltage supply line, and a third voltage supply line configured to provide high voltage signals to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively; and forming a first light-emitting element, a second light-emitting element, and a third light-emitting element, respectively connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit. Optionally, a first virtual line and a second virtual line pass through the first voltage supply line, the second voltage supply line, and the third voltage supply line, respectively. Optionally, the first voltage supply line, the second voltage supply line, and the third voltage supply line each include a first voltage supply line portion, a second voltage supply line portion, and a third voltage supply line portion, respectively, located between the first virtual line and the second virtual line. Optionally, the orthographic projection of the third anode of the third light-emitting element onto the substrate completely covers the orthographic projection of the third voltage supply line portion onto the substrate. Optionally, the third voltage supply line portion has a third linewidth, which is greater than the first linewidth of the first voltage supply line portion and greater than the second linewidth of the second voltage supply line portion.

[0175] In some embodiments, the first virtual line and the second virtual line are formed to also pass through the first data line, the second data line, and the third data line, respectively. Optionally, forming the first data line, the second data line, and the third data line respectively includes forming a first data line portion, forming a second data line portion, and forming a third data line portion, wherein the first data line portion, the second data line portion, and the third data line portion are respectively located between the first virtual line and the second virtual line. Optionally, the first data line portion, the second data line portion, and the third data line portion are formed to have substantially the same linewidth. Optionally, the orthographic projection of the third anode on the substrate at least partially overlaps with the orthographic projection of the third data line portion on the substrate.

[0176] Optionally, the first data line, the second data line, the third data line, the first voltage supply line, the second voltage supply line, and the third voltage supply line are formed to be substantially parallel to each other. Optionally, the data lines and voltage supply lines are arranged alternately.

[0177] In some embodiments, forming the third voltage supply line portion includes forming a main sub-portion and forming a widened sub-portion. Optionally, the main sub-portion is located between the widened sub-portion and the third data line. Optionally, the main sub-portion, the first voltage supply line portion, and the second voltage supply line portion have the same shape. Optionally, the main sub-portion, the first voltage supply line portion, and the second voltage supply line portion have the same shape and the same width.

[0178] In some embodiments, a first anode of a first light-emitting element is formed between a first voltage supply line and a second data line; and a second anode of a second light-emitting element is formed between the first voltage supply line and the second data line. Optionally, the orthographic projection of the first anode on the substrate at least partially overlaps with the orthographic projection of the first data line on the substrate, and at least partially overlaps with the orthographic projection of the second voltage supply line on the substrate. Optionally, the orthographic projection of the second anode on the substrate at least partially overlaps with the orthographic projection of the first data line on the substrate, and at least partially overlaps with the orthographic projection of the second voltage supply line on the substrate. Optionally, the orthographic projection of the first anode on the substrate also at least partially overlaps with the orthographic projection of the first voltage supply line on the substrate. Optionally, the orthographic projection of the second anode on the substrate at least partially overlaps with the orthographic projection of the first voltage supply line on the substrate.

[0179] In some embodiments, the method further includes forming a first anode contact pad, a second anode contact pad, and a third anode contact pad; forming a planarization layer located on the side of the first anode contact pad, the second anode contact pad, and the third anode contact pad away from the substrate; forming a first anode contact hole, a second anode contact hole, and a third anode contact hole, which respectively extend through the planarization layer; forming a pixel defining layer located on the side of the first anode, the second anode, and the third anode away from the planarization layer; forming a first sub-pixel opening, a second sub-pixel opening, and a third sub-pixel opening, which respectively extend through the pixel defining layer; and forming a first light-emitting layer, a second light-emitting layer, and a third light-emitting layer, which are located on the side of the pixel defining layer away from the substrate. Optionally, the first anode, the second anode, and the third anode are formed to be connected to the first anode contact pad, the second anode contact pad, and the third anode contact pad respectively through the first anode contact hole, the second anode contact hole, and the third anode contact hole. Optionally, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer are formed to be connected to the first anode, the second anode, and the third anode respectively through the first sub-pixel opening, the second sub-pixel opening, and the third sub-pixel opening.

[0180] In some embodiments, a first anode contact hole is formed outside the region having a first sub-pixel opening; a second anode contact hole is formed outside the region having a second sub-pixel opening; and a third anode contact hole is formed outside the region having a third sub-pixel opening.

[0181] In some embodiments, the method further includes forming at least one insulating layer between the substrate and the first anode contact pad, the second anode contact pad, and the third anode contact pad. Optionally, the method further includes forming a first pad contact via, a second pad contact via, and a third pad contact via, the first pad contact via, the second pad contact via, and the third pad contact via extending through the at least one insulating layer. Optionally, the first anode contact pad, the second anode contact pad, and the third anode contact pad are formed to be connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively, through the first pad contact via, the second pad contact via, and the third pad contact via. Optionally, along the direction of the first virtual line or the second virtual line, the first anode contact via is formed between the first pad contact via and the first voltage supply line. Optionally, along the direction of the first virtual line or the second virtual line, the second anode contact via is formed between the second pad contact via and the second voltage supply line. Optionally, the third pad contact via and the third anode contact via are arranged in a direction substantially parallel to the third data line and the third voltage supply line.

[0182] In some embodiments, forming a first anode includes forming a first body portion and forming a first bridge portion; forming a second anode includes forming a second body portion and forming a second bridge portion; forming a third anode includes forming a third body portion and forming a third bridge portion. Optionally, the first body portion, the second body portion, and the third body portion have a substantially rectangular shape. Optionally, the first bridge portion, the second bridge portion, and the third bridge portion protrude outward from the first body portion, the second body portion, and the third body portion, respectively.

[0183] In some embodiments, the method further includes forming a first anode contact pad, a second anode contact pad, and a third anode contact pad; forming a planarization layer located on the side of the first anode contact pad, the second anode contact pad, and the third anode contact pad away from the substrate; and forming a first anode contact hole, a second anode contact hole, and a third anode contact hole, the first anode contact hole, the second anode contact hole, and the third anode contact hole respectively extending through the planarization layer. Optionally, the first bridge portion, the second bridge portion, and the third bridge portion are formed to be connected to the first anode contact pad, the second anode contact pad, and the third anode contact pad respectively through the first anode contact hole, the second anode contact hole, and the third anode contact hole.

[0184] Optionally, the third bridge portion protrudes outward from the third body portion in a direction substantially parallel to the first or second virtual line. Optionally, the second bridge portion protrudes outward from the second body portion in a direction substantially parallel to the second data line or the second voltage supply line. Optionally, the first bridge portion protrudes outward from the first body portion in a direction at an angle to the first virtual line and the first data line.

[0185] In some embodiments, the first data line, the second data line, and the third data line are further configured to provide the data signal to the fourth pixel driving circuit, the fifth pixel driving circuit, and the sixth pixel driving circuit, respectively; the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit are arranged sequentially along a direction substantially parallel to the first virtual line or the second virtual line; the fourth pixel driving circuit, the fifth pixel driving circuit, and the sixth pixel driving circuit are arranged sequentially along the direction substantially parallel to the first virtual line or the second virtual line; the first pixel driving circuit and the fourth pixel driving circuit are arranged along a direction substantially parallel to the first data line or the first voltage supply line; the second pixel driving circuit and the fifth pixel driving circuit are arranged along a direction substantially parallel to the second data line or the second voltage supply line; and the third pixel driving circuit and the sixth pixel driving circuit are arranged along a direction substantially parallel to the third data line or the third voltage supply line.

[0186] In some embodiments, a first light-emitting element is formed to be driven by a first pixel driving circuit and is formed to be at least partially located in the region having the fifth pixel driving circuit; a second light-emitting element is formed to be driven by a second pixel driving circuit and is formed to be partially located in the region having the first pixel driving circuit and partially located in the region having the second pixel driving circuit; and a third light-emitting element is formed to be driven by a third pixel driving circuit and is formed to be partially located in the region having the third pixel driving circuit and partially located in the region having the sixth pixel driving circuit.

[0187] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising: grid lines; Data cable; Voltage supply line; as well as Multiple pixel driving circuits are arranged into multiple pixel driving circuit rows, and the second capacitor electrodes in adjacent pixel driving circuits in the same pixel driving circuit row are electrically connected to each other through a connecting part. The pixel driving circuit includes multiple transistors and a storage capacitor; The storage capacitor includes a first capacitor electrode, a second capacitor electrode, and an insulating layer between the first capacitor electrode and the second capacitor electrode. The second capacitor electrode is electrically connected to the voltage supply line; The second capacitor electrode includes a first portion and a second portion that are part of a first overall structure in each sub-pixel; The voltage supply line intersects with the first part at a first intersection distance; The data line intersects the second portion at a second intersection distance; and The first intersection distance is greater than the second intersection distance; In the arrangement direction of the multiple pixel driving circuit rows, the size of the first part is larger than the size of the second part, and the size of the second part is larger than the size of the connecting part; The array substrate includes a semiconductor material layer, the semiconductor material layer having an intersection portion with at least one of the first portion and the second portion, the intersection portion reaching a third intersection distance; and The third intersection distance is less than or equal to the first intersection distance and greater than or equal to the second intersection distance; The plurality of transistors includes: Drive transistors; First transistor; Second transistor; Third transistor; The fourth transistor; and The fifth transistor; Wherein, the drain of the second transistor, the active layer of the second transistor, the drain of the fourth transistor, the active layer of the fourth transistor, the source of the driving transistor, and the active layer of the driving transistor are part of the second overall structure in each sub-pixel; and At least a portion of the cross section directly connects the drain of the second transistor, the drain of the fourth transistor, and the source of the driving transistor to each other. The orthographic projections of the intersection portion, the voltage supply line, and the data line onto the substrate do not overlap.

2. The array substrate according to claim 1, wherein, The voltage supply line and the data line are substantially parallel to each other; and The sections where the voltage supply line intersects with the first portion and the sections where the data line intersects with the second portion are substantially parallel to each other.

3. The array substrate according to claim 1, further comprising an interlayer dielectric layer between the voltage supply line and the second capacitor electrode; and A connecting via extends through the interlayer dielectric layer; in, The voltage supply line is connected to the first portion of the second capacitor electrode through the connection via.

4. The array substrate according to claim 1, wherein, The crossing portion, the voltage supply line, and the data line are substantially parallel to each other; and The crossing section, the section where the voltage supply line intersects with the first section, and the section where the data line intersects with the second section are substantially parallel to each other.

5. The array substrate according to claim 1 or 4, wherein, The intersecting portion intersects with both the first portion and the second portion.

6. The array substrate according to any one of claims 1 to 4, wherein, The orthographic projections of the intersection portion, the voltage supply line, and the data line onto the substrate do not substantially overlap with each other.

7. The array substrate according to any one of claims 1 to 4, wherein, Except for the hole region, the orthographic projection of the first portion on the substrate completely covers the orthographic projection of the first capacitor electrode on the substrate, with a margin, and there is no part of the second capacitor electrode in the hole region.

8. The array substrate according to claim 7, further comprising: An interlayer dielectric layer is located between the voltage supply line and the second capacitor electrode; The first connection line is located on the side of the interlayer dielectric layer away from the second capacitor electrode and is in the same layer as the voltage supply line and the data line; as well as A first through-hole is located in the hole region and extends through the interlayer dielectric layer and the insulating layer; The first connecting line is connected to the first capacitor electrode through the first through hole.

9. The array substrate according to claim 8, further comprising: Substrate; A semiconductor material layer on the substrate; as well as A gate insulating layer is located on the side of the semiconductor material layer away from the substrate. Wherein, the first capacitor electrode is located on the side of the gate insulating layer away from the substrate; The array substrate further includes a second via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer; and The first connection line is connected to the semiconductor material layer through the second through-hole.

10. The array substrate according to claim 9, wherein, The source of the third transistor, the active layer of the third transistor, the drain of the third transistor, the source of the first transistor, the active layer of the first transistor, and the drain of the first transistor are part of the second overall structure in each sub-pixel. as well as The first connection line is connected to the source of the third transistor and the drain of the first transistor through the second via.

11. The array substrate according to any one of claims 1 to 4, wherein, The first part includes a main part, a first side part, and a second side part; The main part has a first side, a second side opposite to the first side, a third side connecting the first side and the second side, and a fourth side opposite to the third side; The first side is adjacent to the first side sub-part; The second side is adjacent to the second side sub-part; as well as The third side is adjacent to the second part.

12. The array substrate according to claim 11, wherein, The first side portion has a substantially trapezoidal shape; and The second side portion has a substantially inverted trapezoidal shape.

13. The array substrate according to claim 11, wherein, The third side is a side of the second part; and The length of the third side is substantially the same as the second intersection distance.

14. The array substrate according to any one of claims 1 to 4, further comprising: An interlayer dielectric layer between the voltage supply line and the second capacitor electrode; The second connection line is located on the side of the interlayer dielectric layer away from the second capacitor electrode, and is in the same layer as the voltage supply line and the data line; The reset signal line is located on the side of the insulating layer away from the first capacitor electrode and is in the same layer as the second capacitor electrode; as well as A third through-hole extends through the interlayer dielectric layer; The second connecting line is connected to the reset signal line through the third through hole.

15. The array substrate according to claim 14, further comprising: Substrate; A semiconductor material layer on the substrate; as well as A gate insulating layer is located on the side of the semiconductor material layer away from the substrate. Wherein, the first capacitor electrode is located on the side of the gate insulating layer away from the substrate; The array substrate further includes a fourth via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer; and The second connection line is connected to the semiconductor material layer through the fourth through-hole.

16. The array substrate according to claim 15, wherein, The source of the first transistor and the active layer of the first transistor are part of a second overall structure in each sub-pixel; and The second connection line is connected to the source of the first transistor through the fourth through hole.

17. The array substrate according to any one of claims 1 to 4, wherein, The section where the data line intersects with the second portion has a linewidth in the range of 2.5μm to 3.5μm; and The section of the data cable intersects with the second part by approximately 60 μm. 2 up to 80μm 2 The area of ​​intersection within the range.

18. A display device comprising an array substrate according to any one of claims 1 to 17 and an integrated circuit connected to the array substrate.

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