A time-division multiplexing full adder-based serial adder and an operation method thereof

Abstract

The application provides a time-sharing multiplexing full adder structure and a serial adder based on the full adder. At present, the full adder is generally designed based on XOR logic. The application is based on the similarity of the sum signal condition and the carry signal condition, and realizes the time-sharing multiplexing of the same circuit structure by controlling the MOS circuit structure and the two sets of transmission gate circuit structures through clock control, so as to complete the time-sharing output of the sum signal and the carry signal. In addition, the total output signal cooperates with the clock signal to output the sum signal and the carry signal in different time periods. The carry signal output by the full adder is optimized and prolonged to be used as the carry input signal of the next adder calculation unit, so that the complete carry signal can be obtained at the total output end in the next calculation unit. With the continuous input of the carry signal, the total output end can output the total sum signal after optimization.

Description

Technical Field

[0001] This invention relates to serial adder technology, belonging to the field of digital integrated circuit design technology, and specifically to a serial adder based on a time-division multiplexed full adder and its operation method. Background Technology

[0002] Data processing has been indispensable in the development of large-scale integrated circuits. Among them, addition is the most basic data processing method. In some digital systems, such as CPU, ALU, and ADC architectures, adders are the most fundamental components.

[0003] As portable devices become smaller, the requirements for integrated circuit size are increasing. While current mainstream parallel adders are fast, their numerous full adders consume significant resources. The parallel input characteristics also require a matching number of pins, making them unsuitable for implementing very high-bit adders. In many applications, such high processing speeds are not necessary; the focus is on minimizing resource consumption.

[0004] Compared to traditional adders, digital serial adders have advantages such as lower resource consumption and greater design flexibility. In domestic and international literature, most parallel adder designs are implemented using integrated chips or XOR logic, while serial adder designs mostly use integrated chips such as shift registers to achieve their functions, and serial adders also require significantly less memory.

[0005] Current serial adders operate by feeding data bit by bit sequentially into the adder for computation. A shift register provides the operands bit by bit, from least significant bit to most significant bit, for addition. If the operand is n bits long, the addition is performed n times, generating one bit of sum each time, which is then serially sent back to the register. A carry flip-flop stores the carry signal for use in the next operation. Most serial adders still use the classic 28T full adder circuit for their half-adder section, where the clock signal only controls the register.

[0006] To address the aforementioned shortcomings, this invention designs a circuit structure specifically for implementing N-bit addition from the ground up. While avoiding the drawbacks of parallel adders, such as a large number of full adder units, large area occupied by acceleration channels, and complex circuit structure, it utilizes time-division multiplexing to reuse the full adder circuit structure, thereby improving circuit utilization and overcoming the large area requirement of existing adders. This solves the problem of adder applications in scenarios where high speed and small area resource requirements are not necessary. Summary of the Invention

[0007] Technical issues:

[0008] To address the aforementioned shortcomings, the technical problem this invention aims to solve is how to design an adder with fewer full adder units, thereby reducing the number of transistors, simplifying the adder's circuit structure, and reducing the area and other resource consumption of multi-bit adders, while simultaneously designing a full adder with clock control, while maintaining the good driving capability and robustness of traditional CMOS.

[0009] Technical solution:

[0010] To solve the above problems, the present invention provides a serial adder based on a full adder, the serial adder comprising: the full adder comprising: a circuit switching structure (1), a selection output structure (2), and an output integration structure (3);

[0011] The circuit switching structure (1) is based on the clock signal CLK (4) switching circuit structure. When CLK is at different levels, the circuit switches to a circuit structure for calculating carry signals or a circuit structure for calculating summation signals.

[0012] The selected output structure (2) is based on two sets of transmission gate circuits. When the transmission gate receives a specific signal, it will transmit the carry signal or summation signal under the specific signal state.

[0013] The output integration structure (3) is based on gate circuits. The gate circuits are used to combine the carry signal or summation signal output by the selected output structure (2) with the clock signal CLK (4) into a port. The port outputs the carry signal or summation signal when the clock signal CLK (4) is at different levels.

[0014] The serial adder includes: based on the full adder, it consists of a delay calibration structure (6) and a feedback input structure (5);

[0015] The time delay calibration structure (6) is based on a tri-state gate. By combining the carry signal or summation signal of the selected output structure (2) with the clock-controlled tri-state gate, the time delay is extended and postponed by an appropriate period to obtain the delayed carry signal or summation signal.

[0016] The feedback input structure (5) is connected to the carry signal input terminal of the adder with the delayed carry signal in the delay calibration structure (6);

[0017] To address the aforementioned technical problems, the present invention also provides a calculation method for the serial adder involved in the present invention, the method comprising:

[0018] S1. After inputting a string of information at the addend input terminal and the augend input terminal, the i-1 level carry signal C can be obtained in the i-1 level calculation unit through the circuit switching structure (1), the selection output structure (2), and the output integration structure (3). i-1 ;

[0019] S2, Carry Signal C i-1 The carry signal C is delayed and optimized by the delay calibration structure (6). i-1 ;

[0020] S3, Optimized carry signal C i-1 The signal is transmitted to the carry signal input terminal through the feedback input structure (5) and serves as the carry signal of the i-th stage.

[0021] Furthermore, the i-th level carry signal, the i-th level addend signal, and the i-th level augend signal in step S3 are calculated together to generate the i-th level summation signal. The i-th level summation signal is delayed and optimized, so that the i-th level summation signal with a clock cycle difference of the clock signal CLK(4) can be output at the summation signal output port.

[0022] Beneficial effects: This invention provides a serial adder based on a full adder and its operation method, which improves upon the traditional CMOS adder and has the following advantages:

[0023] First, a clock-controlled full adder was designed, which utilizes the full adder structure twice within one clock cycle, thereby improving the utilization rate of the full adder circuit.

[0024] Secondly, the adder proposed in this invention uses only one full adder unit and has no acceleration channel, which reduces the number of pins of the multi-bit adder and effectively reduces the area occupied by the multi-bit adder.

[0025] Third, the operation speed of the adder proposed in this invention depends on the clock frequency, thus shifting the speedup problem from how to design the acceleration channel to how to increase the clock frequency.

[0026] Fourth, when one of the addend inputs B is kept grounded, the output signal S can be used as a delay for one clock cycle of the addend input A. Attached Figure Description

[0027] Figure 1 This is the circuit schematic of a time-division multiplexed full adder;

[0028] Figure 2 The circuit schematic for calculating the carry signal C for a full adder;

[0029] Figure 3 The circuit schematic for calculating the summation signal S using a full adder;

[0030] Figure 4 Multisim simulation circuit diagram for a time-division multiplexed full adder;

[0031] Figure 5 Waveform diagram of the Multisim simulation circuit for the time-division multiplexed full adder;

[0032] Figure 6 The delay relationship diagram is for the delay calibration circuit;

[0033] Figure 7 Carry signal C i Delay calibration circuit;

[0034] Figure 8 The total summation signal S i Delay calibration circuit;

[0035] Figure 9 This is a schematic diagram of a serial adder.

[0036] Figure 10 This is the Multisim simulation circuit diagram for a serial adder.

[0037] Figure 11 The waveform diagram is shown in the Multisim simulation of the serial adder circuit. Detailed Implementation

[0038] To address the issues of excessive resource consumption by numerous full adders and a large number of pins due to parallel input in existing multi-bit adders, this invention provides a serial input adder. This adder is based on a time-division multiplexed full adder, requiring only a small structure to implement the functionality of a multi-bit adder.

[0039] The embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the invention. Furthermore, the embodiments and features described herein can be combined with each other without conflict.

[0040] Example 1:

[0041] In Embodiment 1 of the present invention, a full adder based on time-division multiplexing is first provided. The full adder specifically includes: a circuit switching structure 1, a selection output structure 2, and an output integration structure 3.

[0042] The circuit switching structure 1 is as follows: Figure 1As shown, the clock signal CLK controls MOSFETs M7, M8, M9, M10, M11, and M12. When the clock signal CLK is high, MOSFETs M7, M8, M10, and M12 are turned off, while MOSFETs M9 and M11 are turned on, forming the circuit for calculating the carry signal C1. Figure 2 As shown; when the clock signal CLK is low, MOSFETs M7, M8, M10, and M12 can be turned on, thus shielding MOSFETs M2 and M5, while MOSFETs M9 and M10 are turned off, forming the circuit for calculating the summation signal S as shown. Figure 3 As shown.

[0043] Choose output structure 2 as follows Figure 1 As shown, the output selection structure consists of transmission gates T1 and T2, MOSFETs M9, M10, M11, and M12, and an inverter INV2. When the signal at the input of INV1 is high, transmission gate T1 opens, transmission gate T2 closes, and the carry signal is output. Or summation signal When the signal at the INV1 input terminal is high, the T1 transmission gate is closed, the T2 transmission gate is open, and the carry signal C1 = C0 or the summation signal S = B is output.

[0044] Output integration structure 3, such as Figure 1 As shown, it consists of an inverter INV1, AND gates AND1 and AND2, and an OR gate. The output of AND1 is the C1 / S output of the full adder circuit when the pull-up network is on, and the output of AND2 is the C1 / S output of the full adder circuit when the pull-down network is on. OR integrates the outputs of AND1 and AND2 together, so that the output port of OR outputs the value of the carry signal C1 when it is high and the value of the summation signal S when it is low.

[0045] This embodiment, supported by Multisim software, is based on the following... Figure 1 The circuit diagram of the full adder shown is used to build the circuit, and the simulation circuit is as follows. Figure 4 As shown; resistors R2, R3, R4, R1, R5, and R6 are used to discharge the charge stored in the previous calculation unit, thereby improving circuit accuracy; inverters U7A and U6B are used to improve the driving capability of the signal at the input terminal of the inverter INV1, thereby improving circuit stability; similarly, U8A and U3B, U9A and U4B, U19A and U5B, and U10A and U7B are also used to improve the driving capability of the signal and improve circuit stability.

[0046] This embodiment, supported by Multisim software, includes... Figure 4In the simulation circuit shown, the addend signal A is set to a 64Hz square wave with a 50% duty cycle, the augend signal B is set to a 32Hz square wave with a 50% duty cycle, and the carry signal C is set to... i_1 The control signal CLK1 is a 128Hz square wave with a 50% duty cycle, and the frequency of the control signal CLK1 is twice that of the addend signal A. The frequency of the addend signal A is twice that of the augend signal B. The frequency of the augend signal B is the carry signal C from the previous level. i_1 The value is twice that of the waveform, and this setting is made to facilitate the observation of waveform information.

[0047] The waveform of the full adder simulation circuit is as follows: Figure 5 As shown, from top to bottom, the waveforms are: addend signal A, augend signal B, and carry signal C. i_1 Waveform, output signal C i Due to the aforementioned relationship, the waveform of / S outputs a carry signal C1 in the first half of a signal A period starting from the initial position, and a summation signal S in the second half of the period.

[0048] Logical verification: When the signal input information is A: 10101010…, B: 11001100…, C… i_1 :11110000……:ABC i_1 A full adder C = 111 i S outputs 11, ABC i_1 A full adder C with a value of 011 i S output is 10, ABC i_1 A full adder C = 101 i S output is 10, ABC i_1 =001 full adder C i S outputs 01, ABC i_1 =110 full adder C i S output is 10, ABC i_1 =010 full adder C i S outputs 01, ABC i_1 A full adder C = 100 i S outputs 01, ABC i_1 =000 full adder C i S outputs 00; C i The output waveform of S should be 1110100110010100……, which conforms to the logic output of the full adder itself.

[0049] Example 2:

[0050] Embodiment 2 of the present invention provides an adder based on the full adder described in Embodiment 1, wherein the circuit deconstruction of the adder is as follows: Figure 9 As shown, it specifically includes: the full adder described in Example 1, the time delay calibration structure 4, and the feedback input structure 5.

[0051] The time delay calibration structure 4 is based on, as follows: Figure 6 The timing diagram shown uses a combination of three-state gates and capacitors to construct the carry signal C. i The delay calibration circuit 6 and the summation signal S i The delay calibration circuit 7.

[0052] Among them, the carry signal C i Delay calibration circuit 6 Figure 7 As shown, C is received by the AND3 gate. i The / S signal and clock signal, and the purified carry signal C output from the AND3 gate. i However, this purified signal is like Figure 6 As shown in the second row of the waveform, each effective period contains a low level without information. This is used to refine the carry signal C. i By using a three-state gate group consisting of TRI1, TRI2, TRI3, TRI4, TRI5, and TRI6, and capacitors C1, C2, and C3, the following can be obtained: Figure 6 The third row of waveforms shown is the carry signal C. i The delay calibration circuit 6 extends by half a clock cycle and delays by one clock cycle, and the aforementioned clock cycle is the clock cycle of CLK.

[0053] Wherein, the summation signal S i Delay calibration circuit 7, such as Figure 8 As shown, C is received by the AND4 gate. i The / S signal and the inverted clock signal are output by the AND4 gate, resulting in a purified summation signal S. However, this purified signal is as follows: Figure 6 As shown in the fourth row of the waveform, each effective period contains a low level with no information. Passing the purified summation signal S through a tri-state gate group consisting of TRI7, TRI8, TRI9, TRI10, TRI11, and TRI12, and capacitors C4, C5, and C6, yields the following result: Figure 6 The waveform in the fifth row shown is the summation signal S. i The delay calibration circuit 7 extends by half a clock cycle and delays by half a clock cycle, and the aforementioned clock cycle is the clock cycle of CLK.

[0054] The feedback input structure 5 is as follows: Figure 7 The output signal of TRI6 shown is connected to the carry input of the adder, allowing the carry signal chain to participate in the operation at the corresponding number of stages through time difference, thereby realizing the function of serial addition. Since C... iThe information is low during the first clock cycle, so no additional operation is needed to make C... -1 =0.

[0055] like Figure 6 The second row of waveforms shown above, after the above transformation, can output as follows: Figure 6 The third row of waveforms shown represents the carry signal, which is the carry signal required for the addend A and augend B signals to be processed together. Under the corresponding input information, the output of the TRI12 tri-state gate is as follows: Figure 6 The summation signal in the third row of the waveform shown above is an invalid low-level signal in the first clock cycle, and the correct summation signal is obtained from the second clock cycle onwards.

[0056] This embodiment, supported by Multisim software, is based on the following... Figure 9 The circuit diagram of the adder shown is used to build the circuit. The simulation circuit built is as follows: Figure 10 As shown; resistors R2, R3, R4, R1, R5, and R6 are used to discharge the charge stored in the previous calculation unit, thereby improving circuit accuracy; inverters U7A and U6B are used to improve the driving capability of the signal at the input terminal of the inverter INV1, thereby improving circuit stability; similarly, U8A and U3B, U9A and U4B, U19A and U5B, and U10A and U7B are also used to improve the driving capability of the signal and improve circuit stability.

[0057] This embodiment, supported by Multisim software, includes... Figure 10 In the simulation circuit shown, the addend signal A is set to a 64Hz square wave with a duty cycle of 50%, the augend signal B is set to a 32Hz square wave with a duty cycle of 50%, and the control signal CLK is set to a 128Hz square wave with a duty cycle of 50%. Since the frequency of the control signal CLK is twice that of the addend signal A, and the frequency of the addend signal A is twice that of the augend signal B, this setting is made to facilitate the observation of waveform information.

[0058] The waveform of the full adder simulation circuit is as follows: Figure 11 As shown, from top to bottom, the waveforms are: addend signal A, augend signal B, control signal CLK, and total summation signal S. i The waveform, due to the above relationship, in the second total summation signal S calculated from the initial point... i Only within the specified period is a valid total summation signal output;

[0059] Logic verification: When the signal input information is A: 10101010…, B: 11001100…:

[0060] 1+1 with carry-over 1, sum to 0;

[0061] 0 + 1 + 1 (carry 1) sums to 0;

[0062] 1 + 0 + 1 (carry 1, sum 0);

[0063] 0+0+1 (carry 0, sum 1);

[0064] 1 + 1 + 0 (carry 1, sum 0);

[0065] 0 + 1 + 1 (carry 1) sums to 0;

[0066] 1 + 0 + 1 (carry 1, sum 0);

[0067] 0+0+1 (carry 0, sum 1);

[0068] ...

[0069] like Figure 11 The total summation signal S shown i The output waveform is (0)00010001……, where the 0 in parentheses represents the invalid low-level information mentioned above. This conforms to the logic output of the adder itself.

Claims

1. A serial adder based on a time-division multiplexed full adder, the serial adder having a carry signal input terminal, an addend input terminal, an augend input terminal, a summation signal output terminal, and a clock signal terminal, characterized in that: The serial adder includes a time-division multiplexed full adder, which comprises a circuit switching structure, a selection output structure, and an output integration structure. The circuit switching structure is configured to be controlled by a clock signal CLK to switch between circuits calculating the carry signal or the sum signal. The selection output structure is configured based on two sets of transmission gates to select the output carry signal or the sum signal. The output integration structure is configured based on gates to integrate the selected signal with the clock signal CLK into a time-division output on the same port. The serial adder also includes a delay calibration structure and a feedback input structure. The delay calibration structure is connected to the output of the full adder and is used to delay the carry signal or the sum signal. The feedback input structure is used to feed back the delayed carry signal to the carry signal input terminal of the full adder.

2. The serial adder as described in claim 1, characterized in that: The circuit switching structure includes multiple MOS transistors controlled by the clock signal CLK.

3. The serial adder as described in claim 1, characterized in that: The transmission gates in the selected output structure are controlled by inverters to maintain their conduction state.

4. The serial adder as described in claim 1, characterized in that: The output integration structure includes AND gates and OR gates.

5. The serial adder as described in claim 1, characterized in that: The delay calibration structure is configured to extend the carry signal by half a clock cycle and delay it by one clock cycle, the clock cycle being the period of the clock signal CLK.

6. The serial adder as described in claim 1, characterized in that: The delay calibration structure is configured to extend and delay the summation signal by half a clock cycle, wherein the clock cycle is the period of the clock signal CLK.

7. The serial adder as described in claim 5, characterized in that: The feedback input structure is specifically used to connect the carry signal delayed by one clock cycle to the carry signal input terminal.

8. The serial adder as described in claim 1, characterized in that: The serial adder is configured to output a total summation signal at the summation signal output terminal when the addend and augend are input bit by bit, and the first clock cycle of the total summation signal is low.

9. The operational method of the serial adder according to any one of claims 1-8, characterized in that, Includes the following steps: S1. After inputting a string of information at the addend input terminal and the augend input terminal, the i-1 level carry signal is obtained in the i-1 level calculation unit through the circuit switching structure, the selection output structure and the output integration structure. S2. The carry signal is delayed and optimized by the time delay calibration structure; S3. The optimized carry signal is transmitted to the carry signal input terminal through the feedback input structure and serves as the carry signal of the i-th stage. The i-th stage carry signal, together with the i-th stage addend signal and the i-th stage augend signal, are calculated to generate the i-th stage summation signal. The i-th stage summation signal is delayed and optimized, and then the i-th stage summation signal with a clock cycle difference of the clock signal CLK can be output at the summation signal output port.

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