Code translation method, device, equipment, storage medium and program product

Abstract

The present application relates to a code translation method, apparatus, device, storage medium, and program product. The method includes: obtaining source machine code, where the source machine code includes a plurality of source basic blocks; according to the execution order of the plurality of source basic blocks when the source machine code runs, performing a plurality of target operations on the plurality of source basic blocks until the target operation on the last source basic block in the execution order is completed; wherein, the i-th target operation among the plurality of target operations includes: detecting whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; if so, obtaining the target basic block obtained after the translation processing of the candidate source basic block, and running the target basic block; if not, performing translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block, and running the target basic block. Using this method can improve the efficiency of machine code translation.

Description

Technical Field

[0001] This application relates to the technical field of binary software porting, and particularly to a code translation method, apparatus, device, storage medium, and program product. Background Art

[0002] In order to directly run a program compiled for a processor of architecture B (such as the x86 architecture) on a processor of architecture A (such as the ARMv8 architecture), the support of dynamic binary translation technology is required.

[0003] In related technologies, the open-source software QEMU (Quick Emulator) can implement dynamic binary translation technology, which can support multiple different architectures. Specifically, QEMU parses the source machine code through the built-in TCG (Tiny Code Generator) compiler front-end and translates it into the required target machine code. However, the TCG compiler can only provide translation technology and cannot directly run the translated target machine code, and can only provide a very limited optimization mechanism during the translation process, and its efficiency of generating target machine code is low. Summary of the Invention

[0004] Based on this, it is necessary to provide a code translation method, apparatus, device, storage medium, and program product that can improve the efficiency of machine code translation for the above technical problems.

[0005] In a first aspect, this application provides a code translation method. The method includes:

[0006] Obtain source machine code, where the source machine code includes multiple source basic blocks; according to the execution order of the multiple source basic blocks when the source machine code runs, perform multiple target operations on the multiple source basic blocks until the target operation on the last source basic block in the execution order is completed; where the i-th target operation in the multiple target operations includes: detecting whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; if so, obtain the target basic block obtained after the translation processing of the candidate source basic block, and run the target basic block; if not, perform translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block, and run the target basic block.

[0007] In one embodiment, the candidate source basic block is translated based on the LLVM compiler to obtain the target basic block, including: creating an LLVM function corresponding to the candidate source basic block; obtaining the entry address of the candidate source basic block, sequentially obtaining source instructions from the source basic block according to the entry address, and after each source instruction is obtained, obtaining the intermediate instruction corresponding to the source instruction, and after each intermediate instruction is obtained, adding the intermediate instruction to the LLVM function; after all the intermediate instructions corresponding to the source instructions in the candidate source basic block are added to the LLVM function, running the LLVM function to perform translation processing on the candidate source basic block to obtain the target basic block.

[0008] In one embodiment, obtaining the entry address of the candidate source basic block includes: if i = 1, using the entry address of the source machine code as the entry address of the candidate source basic block; if i > 1, determining the entry address of the candidate source basic block according to the last source instruction in the source basic block corresponding to the (i - 1)-th target operation.

[0009] In one embodiment, sequentially obtaining source instructions from the source basic block according to the entry address includes: sequentially performing multiple instruction acquisition operations according to the entry address until the obtained source instruction is a control flow instruction; wherein, the i-th instruction acquisition operation in the instruction acquisition operation includes: determining the byte identifier of the candidate source instruction corresponding to the i-th instruction acquisition operation according to the entry address; obtaining the candidate source instruction according to the byte identifier.

[0010] In one embodiment, obtaining the intermediate instruction corresponding to the source instruction includes: querying a preset instruction database according to the source instruction to obtain the intermediate instruction corresponding to the source instruction, wherein multiple groups of corresponding relationships between preset source instructions and preset intermediate instructions are stored in the instruction database.

[0011] In one embodiment, the construction process of the instruction database includes: obtaining the instruction set specification corresponding to the source machine code, where multiple preset source instructions are included in the instruction set specification; after simulating and implementing each preset source instruction using a preset programming language, performing translation processing on each preset source instruction to obtain the preset intermediate instruction corresponding to each preset source instruction; constructing the instruction database according to each preset source instruction and each preset intermediate instruction.

[0012] In one embodiment, after obtaining the target basic block, the method further includes: using the entry address of the candidate source basic block as the identifier of the target basic block, and storing the target basic block in a preset cache space.

[0013] In one embodiment, detecting whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing includes: according to the entry address of the candidate source basic block, detecting whether the preset cache space contains a target identifier corresponding to the entry address of the candidate source basic block. If so, the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; correspondingly, obtaining the target basic block obtained after translating the candidate source basic block includes: searching in the preset buffer space for the target basic block corresponding to the target identifier as the target basic block obtained after translating the candidate source basic block.

[0014] In one embodiment, performing multiple target operations on the multiple source basic blocks until the target operation on the last source basic block in the execution order is completed includes: performing multiple target operations on the multiple source basic blocks until the exit instruction in the source machine code is detected.

[0015] In a second aspect, the present application also provides a code translation device. The device includes:

[0016] An acquisition module, configured to acquire source machine code, where the source machine code includes multiple source basic blocks;

[0017] An execution module, configured to perform multiple target operations on the multiple source basic blocks according to the execution order of the multiple source basic blocks when the source machine code runs, until the target operation on the last source basic block in the execution order is completed; where the i-th target operation in the multiple target operations includes: detecting whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; if so, obtaining the target basic block obtained after translating the candidate source basic block and running the target basic block; if not, performing translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block and running the target basic block.

[0018] In one embodiment, the execution module is specifically configured to: create an LLVM function corresponding to the candidate source basic block; obtain the entry address of the candidate source basic block, sequentially obtain source instructions from the source basic block according to the entry address, and after each acquisition of a source instruction, obtain an intermediate instruction corresponding to the source instruction, and after each acquisition of the intermediate instruction, add the intermediate instruction to the LLVM function; after all the intermediate instructions corresponding to the source instructions in the candidate source basic block are added to the LLVM function, run the LLVM function to perform translation processing on the candidate source basic block to obtain the target basic block.

[0019] In one embodiment, the execution module is specifically configured to: if i = 1, use the entry address of the source machine code as the entry address of the candidate source basic block; if i > 1, determine the entry address of the candidate source basic block according to the last source instruction in the source basic block corresponding to the (i - 1)-th target operation.

[0020] In one embodiment, the execution module is specifically configured to: according to the entry address, sequentially perform multiple instruction acquisition operations until the obtained source instruction is a control flow instruction; wherein, the i-th instruction acquisition operation in the instruction acquisition operations includes: determining the byte identifier of the candidate source instruction corresponding to the i-th instruction acquisition operation according to the entry address; and obtaining the candidate source instruction according to the byte identifier.

[0021] In one embodiment, the execution module is specifically configured to: query a preset instruction database according to the source instruction to obtain the intermediate instruction corresponding to the source instruction, where multiple groups of corresponding relationships between preset source instructions and preset intermediate instructions are stored in the instruction database.

[0022] In one embodiment, the process of constructing the instruction database includes: obtaining the instruction set specification corresponding to the source machine code, where multiple preset source instructions are included in the instruction set specification; after simulating and implementing each preset source instruction using a preset programming language, performing a translation process on each preset source instruction to obtain the preset intermediate instruction corresponding to each preset source instruction; and constructing the instruction database according to each preset source instruction and each preset intermediate instruction.

[0023] In one embodiment, the apparatus further includes:

[0024] A storage module, configured to use the entry address of the candidate source basic block as the identifier of the target basic block, and store the target basic block in a preset cache space.

[0025] In one embodiment, the execution module is specifically configured to: according to the entry address of the candidate source basic block, detect whether the preset cache space contains a target identifier corresponding to the entry address of the candidate source basic block. If so, the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; correspondingly, the execution module is specifically configured to: find, from the preset buffer space, the target basic block corresponding to the target identifier as the target basic block obtained after the translation processing of the candidate source basic block.

[0026] In one embodiment, the execution module is specifically configured to: perform multiple target operations on the multiple source basic blocks until an exit instruction in the source machine code is detected.

[0027] In a third aspect, the present application further provides a computer device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the method described in any one of the above first aspects are implemented.

[0028] In a fourth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in any one of the above first aspects are implemented.

[0029] In a fifth aspect, the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the method described in any one of the above first aspects are implemented.

[0030] The above code translation method, device, equipment, storage medium and program product obtain source machine code including multiple source basic blocks, and according to the execution order of the multiple source basic blocks when the source machine code runs, perform a plurality of target operations on the multiple source basic blocks until the target operation is completed for the last source basic block in the execution order. Specifically, the i-th target operation in the multiple target operations includes: detecting whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; if so, obtaining the target basic block obtained after the translation processing of the candidate source basic block, and running the target basic block; if not, performing translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block, and running the target basic block. Among them, when the candidate source basic block corresponding to the target operation has not been translated, the LLVM compiler can be called to perform translation processing on the candidate source basic block, so that the optimization mechanism in the LLVM compiler can be fully utilized to perform optimization processing such as redundancy removal or merging on the instructions in the candidate source basic block, improving the efficiency of machine code translation, and making the target basic block generated after optimization by the processor run more efficiently. And, when the candidate source basic block has been translated, the basic block is directly run. Therefore, the source machine code can be directly translated and executed without repeatedly translating the candidate source basic block, realizing that the machine code compiled in a processor of one architecture can be directly run in a processor of another architecture, while effectively improving the efficiency of translation processing and execution of the source machine code. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic flowchart of code translation in an embodiment;

[0032] Figure 2 It is a schematic flowchart of obtaining a target basic block in an embodiment;

[0033] Figure 3It is a flowchart of the instruction database construction process in an embodiment;

[0034] Figure 4 It is a schematic architecture diagram of a dynamic binary translation method in an embodiment;

[0035] Figure 5 It is a structural block diagram of a code translation device in an embodiment;

[0036] Figure 6 It is a structural block diagram of a code translation device in another embodiment;

[0037] Figure 7 It is an internal structure diagram of a computer device in an embodiment. Detailed implementation manners

[0038] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0039] In order to directly run a program compiled for a B architecture (such as the x86 architecture) processor on an A architecture (such as the ARMv8 architecture) processor, the support of dynamic binary translation technology is required. Currently, the mainstream dynamic binary translation software is the open-source project QEMU, which can support the translation process of machine codes between many different architectures. QEMU parses the source machine code through the built-in TCG compiler and translates it into the required target machine code. However, the translation method of QEMU has the problem of low translation efficiency, and there is a large decline compared with the native performance of the program. This is mainly due to two major deficiencies of the TCG compiler: (1) For complex instructions such as vector instructions, they can only be implemented through simulation and cannot make full use of the vector instruction acceleration mechanism of the processor hardware itself. (2) The TCG compiler can only provide very limited optimization mechanisms, and the generated target machine code is not efficient enough. Moreover, the TCG compiler can only provide translation technology and cannot directly run the translated target machine code.

[0040] In view of this, the embodiments of the present application provide a code translation method, which can improve the translation efficiency of machine codes.

[0041] In one embodiment, as Figure 1As shown, a code translation method is provided. In the embodiments of the present application, this method is exemplified by being applied to a terminal. The terminal includes a processor with architecture A, which can perform translation processing and execution on a program compiled for a processor with architecture B. It can be understood that this method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. Among them, the terminal can be, but is not limited to, various personal computers, laptop computers, smart phones, tablet computers, etc., and the server can be implemented by an independent server or a server cluster composed of multiple servers.

[0042] In the embodiments of the present application, the code translation method includes the following steps:

[0043] Step 101, obtain the source machine code, which includes multiple source basic blocks.

[0044] Among them, the architecture of the processor can be IA-32, IA-64, x86-32, x86-64, or ARMv8, etc. Programs compiled for processors with different architectures cannot be directly run on processors with other architectures, and need to be rewritten or translated.

[0045] For the process of directly running a program compiled for a processor with architecture B on a processor with architecture A, the source code refers to the program compiled for the processor with architecture B. In order to use the functions implemented by the source code without re-compiling the program, therefore, the source code is translated so that it can be directly run on the processor with architecture A.

[0046] Among them, a basic block refers to a sequence of instructions executed in order, including multiple instructions. A basic block has only one entry and one exit. The entry is the first instruction among them, and the exit is the last instruction among them; for a basic block, it only enters from its entry and exits from its exit during execution. The source code can include multiple basic blocks, and the basic blocks included in the source code are the source basic blocks. The translation processing of the source code can be achieved by translating each instruction in the multiple source basic blocks included in the source code.

[0047] Step 102, according to the execution order of the multiple source basic blocks when the source machine code runs, perform multiple target operations on the multiple source basic blocks until the target operation on the last source basic block in the execution order is completed. Among them, the i-th target operation in the multiple target operations includes: detecting whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; if so, obtain the target basic block obtained after translating the candidate source basic block, and run the target basic block; if not, perform translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block, and run the target basic block.

[0048] Among them, the source machine code includes multiple source basic blocks, and when the source machine code is run, it is run in sequence according to the execution order of each source basic block. Among them, different functions can be realized after each source basic block is run, and the source machine code can include multiple same source basic blocks with different execution orders.

[0049] During the translation process, according to the execution order of each source basic block when the source machine code is run, target operations can be respectively executed for each of the multiple source basic blocks until the target operation is completed for the last source basic block in the execution order, thus completing the process of translating and executing the source machine code.

[0050] Specifically, for each target operation, the source basic block it processes is its corresponding candidate source basic block. For each source basic block, during the process of executing the target operation on it, after obtaining the source basic block, it is used as a candidate source basic block, and first it is detected whether the candidate source basic block has been completed with translation processing. Among them, if it is detected that the candidate source basic block has not been completed with translation processing, the target operation is to perform translation processing on the candidate source basic block based on the LLVM (Low Level Virtual Machine) compiler to obtain a target basic block, and the target basic block is the program corresponding to the candidate source basic block that can run on the processor of architecture A. Therefore, the target basic block can be directly run after translation processing to realize the function of the candidate source basic block. If it is detected that the candidate source basic block has been completed with translation processing, it means that the candidate source basic block does not appear for the first time during the translation processing of the source machine code and has already been translated. Therefore, the target operation is to directly obtain the corresponding target basic block that has been translated for the candidate source basic block before and directly execute the target basic block, without performing repeated translation processing on the candidate basic block, thus improving the translation processing efficiency of the source machine code. Among them, LLVM is an open-source compiler framework, which can provide a powerful optimization mechanism, be able to vectorize some parts of the instructions, merge redundant instructions, perform redundancy removal processing or inlining optimization on the instructions, etc. Therefore, by calling LLVM to perform translation processing on the source basic block, efficient machine code can be generated and the translation processing efficiency can be improved.

[0051] The above code translation method obtains the source machine code containing multiple source basic blocks, and according to the execution order of the multiple source basic blocks during the runtime of the source machine code, performs multiple target operations on the multiple source basic blocks until the target operation on the last source basic block in the execution order is completed; specifically, the i-th target operation in the multiple target operations includes: detecting whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; if so, obtaining the target basic block obtained after the translation processing of the candidate source basic block, and running the target basic block; if not, performing translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block, and running the target basic block. Among them, when the candidate source basic block corresponding to the target operation has not been translated, the LLVM compiler can be called to perform translation processing on the candidate source basic block, so that the optimization mechanism in the LLVM compiler can be fully utilized to perform optimization processing such as redundancy removal or merging on the instructions in the candidate source basic block, improving the efficiency of machine code translation, and making the target basic block generated after optimization by the processor run more efficiently. And, when the candidate source basic block has been translated, the basic block is directly run. Therefore, the source machine code can be directly translated and executed without repeatedly translating the candidate source basic block, realizing that the machine code compiled on a processor of one architecture can be directly run on a processor of another architecture, while effectively improving the efficiency of translation processing and execution of the source machine code.

[0052] In one embodiment, as Figure 2 shown, it shows a schematic flowchart of a process for obtaining a target basic block provided by an embodiment of the present application. Performing translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block includes:

[0053] Step 201, create an LLVM function corresponding to the candidate source basic block.

[0054] During the process of performing translation processing on each candidate source basic block, first establish an LLVM function corresponding to the candidate source basic block, so that each instruction included in the candidate source basic block corresponding to the LLVM function can be translated and executed based on the LLVM compiler.

[0055] Step 202, obtain the entry address of the candidate source basic block, sequentially obtain source instructions from the source basic block according to the entry address, and after each source instruction is obtained, obtain the intermediate instruction corresponding to the source instruction.

[0056] Among them, as mentioned above, a basic block has only one entry and one exit. The entry is the first instruction therein, and the exit is the last instruction therein. For a basic block, during execution, it only enters from its entry and exits from its exit. Moreover, each instruction in the basic block corresponds to a memory address. The various instructions included in the candidate source basic block are source instructions. Translating and executing the candidate source basic block means performing translation processing and execution on the various source instructions in the candidate source basic block.

[0057] Among them, intermediate instructions refer to instructions that can be directly recognized and translated by LLVM. Therefore, it is necessary to obtain the intermediate instructions corresponding to each source instruction and perform translation processing on the intermediate instruction. Since the intermediate instruction corresponds to the source instruction respectively, the translation processing of the source instruction is realized.

[0058] Specifically, the entry address of the candidate source basic block is the memory address corresponding to the source instruction at the entry in the candidate source basic block. By obtaining the entry address of the candidate source basic block, the various source instructions included in the basic block are determined, and further, the intermediate instructions corresponding to the various source instructions are obtained for further translation processing.

[0059] In one embodiment, obtaining source instructions sequentially from the source basic block according to the entry address includes: according to the entry address, performing multiple instruction obtaining operations sequentially until the obtained source instruction is a control flow instruction; wherein, the i-th instruction obtaining operation in the instruction obtaining operation includes: determining the byte identifier of the candidate source instruction corresponding to the i-th instruction obtaining operation according to the entry address; obtaining the candidate source instruction according to the byte identifier.

[0060] Among them, based on the entry address, the various source instructions in the candidate source basic block can be obtained sequentially. The candidate source instruction is the source instruction to be obtained by each instruction obtaining operation. Specifically, each candidate source instruction corresponds to a byte identifier, and moreover, the byte identifier can be determined according to the memory address corresponding to each source instruction, and further, the source instruction is determined based on the byte identifier. Therefore, the process of obtaining the various source instructions sequentially can be as follows:

[0061] For example, the entry address is the memory address corresponding to the first candidate source instruction in the source basic block. According to the entry address, determine the byte identifier corresponding to the first candidate source instruction for the first instruction fetch operation, and obtain the first candidate source instruction according to the byte identifier. Further, according to the byte identifier corresponding to the first candidate source instruction, add the byte identifier to the entry address to obtain an updated entry address, that is, the memory address corresponding to the second candidate source instruction. Therefore, according to the memory address corresponding to the second candidate source instruction, determine the memory identifier corresponding to the second candidate source instruction for the second instruction fetch operation, and further obtain the second candidate source instruction according to the memory identifier. Further, add the byte identifier corresponding to the (i - 1)-th candidate source instruction to the updated entry address to obtain the memory address corresponding to the i-th candidate source instruction, and obtain the byte identifier corresponding to the i-th candidate source instruction according to the memory address, so as to further obtain the i-th candidate source instruction for the i-th instruction fetch operation based on the byte identifier. Until the obtained candidate source instruction is a control flow instruction, all source instructions included in the candidate source basic block are obtained. Among them, the control flow instruction refers to an instruction that affects the program execution flow, such as a jump instruction, a loop instruction, or a judgment instruction.

[0062] In one embodiment, obtaining the entry address of the candidate source basic block includes: if i = 1, then use the entry address of the source machine code as the entry address of the candidate source basic block; if i > 1, then determine the entry address of the candidate source basic block according to the last source instruction in the source basic block corresponding to the (i - 1)-th target operation.

[0063] Among them, i is the number of times of executing the target operation. When i is equal to 1, that is, the first time of executing the target operation, directly use the entry address of the source machine code as the entry address of the candidate source basic block. Among them, the entry address of the source machine code is the entry address of the basic block with the first execution order in the source machine code, so that the respective source instructions of the candidate source basic block can be further obtained.

[0064] When i > 1, then determine the entry address of the candidate source basic block according to the last source instruction in the source basic block corresponding to the (i - 1)-th target operation. For example, the memory address obtained by adding the byte identifier and the memory address of the last source instruction in the source basic block corresponding to the (i - 1)-th target operation is the entry address of the source basic block corresponding to the current execution of the i-th target operation.

[0065] The above is the process of obtaining source instructions. After obtaining the source instructions, obtain the intermediate instructions corresponding to the source instructions, so that the intermediate instructions can be directly translated based on the LLVM compiler. The following is the description of obtaining the intermediate instructions corresponding to the source instructions.

[0066] In one embodiment, obtaining the intermediate instruction corresponding to the source instruction includes: querying a preset instruction database according to the source instruction to obtain the intermediate instruction corresponding to the source instruction, where the instruction database stores multiple groups of corresponding relationships between preset source instructions and preset intermediate instructions.

[0067] Among them, an instruction database is preset in the terminal, and the instruction database includes multiple groups of corresponding relationships between preset source instructions and preset intermediate instructions. Among them, each preset source instruction can correspond to each source instruction in the source machine code respectively. Therefore, after obtaining the source instruction, determine the preset source instruction corresponding to the source instruction in the instruction database, and the preset intermediate instruction corresponding to the preset source instruction is the intermediate instruction corresponding to the source instruction. Thus, the intermediate instruction corresponding to the source instruction can be obtained.

[0068] Step 203, after obtaining the intermediate instruction each time, add the intermediate instruction to the LLVM function.

[0069] Among them, for each source instruction, after obtaining the intermediate instruction corresponding to the source instruction, add the obtained intermediate instruction to the LLVM function. Therefore, for the intermediate instructions corresponding to all source instructions in the candidate source basic block, they can be added to the LLVM function in the execution order, so that the LLVM compiler can be called based on the LLVM function to perform translation processing and execution on the added intermediate instructions.

[0070] Step 204, after adding all the intermediate instructions corresponding to the source instructions in the candidate source basic block to the LLVM function, run the LLVM function to perform translation processing on the candidate source basic block to obtain the target basic block.

[0071] As mentioned above, until the obtained source instruction is a control flow instruction, that is, all the intermediate instructions corresponding to the source instructions in the candidate source basic block are added to the LLVM function. Therefore, the LLVM function contains all the intermediate instructions corresponding to the source instructions in the candidate source basic block. Therefore, by running the LLVM function based on the LLVM compiler, the intermediate instructions in the LLVM function can be translated into the target basic block composed of the instructions of the target machine code as required.

[0072] In one embodiment, after obtaining the target basic block, the method further includes: using the entry address of the candidate source basic block as the identifier of the target basic block, and storing the target basic block in a preset cache space.

[0073] Among them, after running the LLVM function to perform translation processing on the candidate source basic block to obtain the target basic block, the target basic block is identified with the entry address of the candidate source basic block, and the identified target basic block is stored in a preset cache space, that is, the identified target basic block is stored in the terminal. Therefore, after the target basic blocks obtained by performing translation processing based on the LLVM function corresponding to each candidate source basic block are all identified, they are stored in the terminal. When a candidate source basic block that has been translated and processed is detected again during the translation processing of the source machine code, the corresponding target basic block can be directly obtained from the preset cache space according to the identifier and run, without repeated translation, saving computer resources and improving the translation and execution efficiency of the source machine code.

[0074] In one embodiment, detecting whether the candidate source basic block corresponding to the i-th target operation has been completely translated and processed includes: according to the entry address of the candidate source basic block, detecting whether the preset cache space contains a target identifier corresponding to the entry address of the candidate source basic block. If so, the candidate source basic block corresponding to the i-th target operation has been completely translated and processed; correspondingly, obtaining the target basic block obtained after translating and processing the candidate source basic block includes: searching for the target basic block corresponding to the target identifier in the preset buffer space as the target basic block obtained after translating and processing the candidate source basic block.

[0075] Among them, as mentioned above, the target basic block obtained after the translation processing is stored in the preset cache space after being identified based on the entry address of the corresponding candidate source basic block. Therefore, for the candidate source basic block corresponding to the i-th target operation, according to the entry address of the candidate source basic block corresponding to the i-th target operation, it is detected whether there is a target basic block identified by the entry address in the preset cache space, that is, whether there is a target identifier corresponding to the entry address of the candidate source basic block corresponding to the i-th target operation. If so, it means that the candidate source basic block corresponding to the i-th target operation has been previously completely translated and processed. Then, directly based on the entry address of the candidate source basic block corresponding to the i-th target operation, the target basic block identified by the corresponding target identifier is obtained and used as the target basic block obtained after translating and processing the candidate source basic block corresponding to the i-th target operation, and it is directly run.

[0076] In the embodiment of the present application, according to the entry address of the candidate source basic block, it is detected whether the preset cache space contains a target identifier corresponding to the entry address of the candidate source basic block. Thus, in the case where it is detected that the preset cache space contains a target identifier corresponding to the entry address of the candidate source basic block, the target basic block corresponding to the candidate source basic block can be directly obtained and directly executed without performing translation processing, greatly improving the translation processing efficiency of the source machine code and saving hardware resources.

[0077] In one embodiment, Figure 3 As shown, it shows a flow chart of a command database construction process provided by an embodiment of the present application. The command database construction process includes:

[0078] Step 301, obtaining an instruction set specification corresponding to the source machine code, wherein the instruction set specification includes a plurality of preset source instructions.

[0079] The source machine code corresponds to an instruction set specification, which contains a plurality of different preset source instructions. Each instruction contained in the source machine code can be found from the preset source instructions in the instruction set specification; and the instruction set specification contains a description of the semantics and functions of each preset source instruction. Therefore, the instruction database is constructed based on each preset source instruction in the instruction set specification.

[0080] Step 302, after simulating and implementing each preset source instruction using a preset programming language, each preset source instruction is translated and processed to obtain the preset intermediate instruction corresponding to each preset source instruction.

[0081] In order to obtain the intermediate instructions corresponding to each source instruction during the translation process of the source machine code, it is necessary to determine the corresponding preset intermediate instructions based on each preset source instruction in advance. Specifically, for each preset source instruction in the instruction set specification, a preset programming language is used to simulate and implement each preset source instruction, and the simulated instructions are translated to obtain the preset intermediate instructions corresponding to each preset source instruction.

[0082] Optionally, the preset programming language may be a high-level language, for example, a programming language such as C, C++ or Java.

[0083] Optionally, after simulating and implementing each preset source instruction using a preset programming language, the simulated instruction can be translated and processed using software that matches the LLVM compiler to obtain corresponding preset intermediate instructions.

[0084] Step 303: construct the instruction database according to each preset source instruction and each preset intermediate instruction.

[0085] The constructed instruction database includes multiple preset source instructions and preset intermediate instructions, and each preset source instruction corresponds to a preset intermediate instruction, so that in the process of translating the candidate source basic block, the intermediate instruction corresponding to the candidate source instruction can be obtained based on the instruction database, thereby improving the efficiency of obtaining the intermediate instruction and ensuring the reliability of obtaining the intermediate instruction.

[0086] In one embodiment, the target operation is performed multiple times on the multiple source basic blocks until the target operation is completed for the last source basic block in the execution order, including: performing the target operation multiple times on the multiple source basic blocks until an exit instruction in the source machine code is detected.

[0087] Among them, the source machine code contains an exit instruction. Optionally, the exit instruction may be included in the last source basic block in the execution order. Therefore, according to the execution order of the multiple source basic blocks when the source machine code runs, the target operation is performed multiple times on the multiple source basic blocks until the exit instruction is detected, indicating that the translation and execution of the source machine code have ended, and all source basic blocks in the source machine code have been subjected to the target operation. Thus, the source machine code corresponding to the program compiled for the B-architecture processor has been executed completely on the terminal including the A-architecture processor.

[0088] In one embodiment, as Figure 4 shown, it shows a schematic architecture diagram of a dynamic binary translation method provided by an embodiment of the present application. Based on this dynamic binary translation method, a program written for a B-architecture processor can be directly run on an A-architecture processor. The process specifically includes:

[0089] S1. Read the binary file and extract the source machine code, obtain the entry address x of the source machine code, and set the program counter PC to x;

[0090] S2. Create an LLVM intermediate function func and identify the intermediate function func with the value of PC;

[0091] S3. Determine whether the corresponding source basic block has been cached in the preset cache space according to the value of PC. If so, execute step S7; otherwise, execute step S2, and then execute step S4;

[0092] S4. According to the value of PC, obtain the source instruction pointed to by PC, and update PC according to the byte identifier of the source instruction. And, find the intermediate instruction corresponding to the source instruction from file f, and add the found intermediate instruction to the intermediate function func. Among them, if the source instruction pointed to by PC is a control flow instruction, execute step S5; otherwise, continue to execute step S4;

[0093] Among them, the construction process of file f is: according to the instruction set architecture manual corresponding to the source machine code, use a preset programming language to simulate and implement each source instruction in the instruction set architecture manual, and compile each source instruction into an intermediate instruction recognizable and translatable by LLVM, and save them to file f.

[0094] S5. Optimize each intermediate instruction in the intermediate function func using the LLVM compiler, and perform translation processing on each intermediate instruction to obtain the target machine code, then execute step S6;

[0095] S6. Cache the target machine code corresponding to the intermediate function func based on basic blocks, identify it using the value of the PC corresponding to the first instruction in the intermediate function func, and then execute step S8;

[0096] S7. Find the cached target machine code corresponding to the intermediate function func according to the value of the PC, and execute step S8;

[0097] S8. Execute the target machine code corresponding to the intermediate function func. If no exit instruction is detected, execute step S3; otherwise, end the translation processing of the source machine code.

[0098] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the arrows, these steps do not necessarily need to be executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages do not necessarily need to be executed at the same moment, but can be executed at different moments. The execution order of these steps or stages does not necessarily need to be sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0099] Based on the same inventive concept, the embodiments of the present application also provide a code translation device for implementing the above-mentioned code translation method. The implementation solutions provided by this device to solve problems are similar to the implementation solutions described in the above method. Therefore, the specific limitations in one or more embodiments of the following code translation devices can refer to the limitations on the code translation method in the above text, and will not be repeated here.

[0100] In one embodiment, as Figure 5 shown, a code translation device is provided. The code translation device 500 includes: an acquisition module 501 and an execution module 502, where:

[0101] The acquisition module 501 is used to acquire the source machine code, and the source machine code includes multiple source basic blocks;

[0102] An execution module 502, configured to perform a target operation multiple times on the multiple source basic blocks according to the execution order of the multiple source basic blocks when the source machine code runs, until the target operation on the last source basic block in the execution order is completed; wherein, the i-th target operation among the multiple target operations includes: detecting whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; if so, obtaining the target basic block obtained after the translation processing of the candidate source basic block, and running the target basic block; if not, performing translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block, and running the target basic block.

[0103] In one embodiment, the execution module 502 is specifically configured to: create an LLVM function corresponding to the candidate source basic block; obtain the entry address of the candidate source basic block, sequentially obtain source instructions from the source basic block according to the entry address, and after each source instruction is obtained, obtain the intermediate instruction corresponding to the source instruction, and after each intermediate instruction is obtained, add the intermediate instruction to the LLVM function; after all the intermediate instructions corresponding to the source instructions in the candidate source basic block are added to the LLVM function, run the LLVM function to perform translation processing on the candidate source basic block to obtain the target basic block.

[0104] In one embodiment, the execution module 502 is specifically configured to: if i = 1, use the entry address of the source machine code as the entry address of the candidate source basic block; if i > 1, determine the entry address of the candidate source basic block according to the last source instruction in the source basic block corresponding to the (i - 1)-th target operation.

[0105] In one embodiment, the execution module 502 is specifically configured to: according to the entry address, sequentially perform multiple instruction acquisition operations until the obtained source instruction is a control flow instruction; wherein, the i-th instruction acquisition operation in the instruction acquisition operation includes: determining the byte identifier of the candidate source instruction corresponding to the i-th instruction acquisition operation according to the entry address; obtaining the candidate source instruction according to the byte identifier.

[0106] In one embodiment, the execution module 502 is specifically configured to: query a preset instruction database according to the source instruction to obtain the intermediate instruction corresponding to the source instruction, where multiple groups of corresponding relationships between preset source instructions and preset intermediate instructions are stored in the instruction database.

[0107] In one embodiment, the process of constructing the instruction database includes: obtaining the instruction set specification corresponding to the source machine code, where the instruction set specification contains multiple preset source instructions; after simulating and implementing each preset source instruction using a preset programming language, performing translation processing on each preset source instruction to obtain the corresponding preset intermediate instruction for each preset source instruction; and constructing the instruction database based on each preset source instruction and each preset intermediate instruction.

[0108] In one embodiment, as Figure 6 shown, the code translation device 500 further includes:

[0109] A storage module 503, configured to use the entry address of the candidate source basic block as the identifier of the target basic block, and store the target basic block in a preset cache space.

[0110] In one embodiment, the execution module 502 is specifically configured to: according to the entry address of the candidate source basic block, detect whether the preset cache space contains a target identifier corresponding to the entry address of the candidate source basic block. If so, the candidate source basic block corresponding to the i-th target operation has completed translation processing; correspondingly, the execution module 502 is specifically configured to: find, from the preset buffer space, the target basic block corresponding to the target identifier as the target basic block obtained after the translation processing of the candidate source basic block.

[0111] In one embodiment, the execution module 502 is specifically configured to: perform multiple target operations on the multiple source basic blocks until an exit instruction in the source machine code is detected.

[0112] Each module in the above code translation device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above respective modules.

[0113] In one embodiment, a computer device is provided. The computer device can be a server, and its internal structure diagram can be as Figure 7 shown. The computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store XX data. The network interface of the computer device is used to communicate with an external terminal through a network connection. The computer program, when executed by the processor, implements a code translation method.

[0114] Those skilled in the art can understand that Figure 7 the structure shown in Figure 7 is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0115] In one embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0116] Obtain source machine code, where the source machine code includes multiple source basic blocks; according to the execution order of the multiple source basic blocks when the source machine code runs, perform multiple target operations on the multiple source basic blocks until the target operation on the last source basic block in the execution order is completed; where, the i-th target operation in the multiple target operations includes: detecting whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; if so, obtain the target basic block obtained after the translation processing of the candidate source basic block, and run the target basic block; if not, perform translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block, and run the target basic block.

[0117] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0118] Create an LLVM function corresponding to the candidate source basic block; obtain the entry address of the candidate source basic block, sequentially obtain source instructions from the source basic block according to the entry address, and after each acquisition of a source instruction, obtain the intermediate instruction corresponding to the source instruction, and after each acquisition of the intermediate instruction, add the intermediate instruction to the LLVM function; after all the intermediate instructions corresponding to the source instructions in the candidate source basic block are added to the LLVM function, run the LLVM function to perform translation processing on the candidate source basic block to obtain the target basic block.

[0119] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0120] If i = 1, use the entry address of the source machine code as the entry address of the candidate source basic block; if i > 1, determine the entry address of the candidate source basic block according to the last source instruction in the source basic block corresponding to the (i - 1)-th target operation.

[0121] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0122] According to the entry address, execute the instruction acquisition operation multiple times in sequence until the obtained source instruction is a control flow instruction; wherein, the i-th instruction acquisition operation in the instruction acquisition operation includes: determining the byte identifier of the candidate source instruction corresponding to the i-th instruction acquisition operation according to the entry address; obtaining the candidate source instruction according to the byte identifier.

[0123] In one embodiment, when the processor executes a computer program, the following steps are further implemented:

[0124] Query a preset instruction database according to the source instruction to obtain the intermediate instruction corresponding to the source instruction, wherein multiple groups of corresponding relationships between the preset source instructions and the preset intermediate instructions are stored in the instruction database.

[0125] In one embodiment, when the processor executes a computer program, the following steps are further implemented:

[0126] Obtain the instruction set specification corresponding to the source machine code, which contains multiple preset source instructions; after simulating and implementing each preset source instruction in a preset programming language, perform translation processing on each preset source instruction to obtain the preset intermediate instruction corresponding to each preset source instruction; construct the instruction database according to each preset source instruction and each preset intermediate instruction.

[0127] In one embodiment, when the processor executes a computer program, the following steps are further implemented:

[0128] Use the entry address of the candidate source basic block as the identifier of the target basic block, and store the target basic block in a preset cache space.

[0129] In one embodiment, when the processor executes a computer program, the following steps are further implemented:

[0130] According to the entry address of the candidate source basic block, detect whether the preset cache space contains a target identifier corresponding to the entry address of the candidate source basic block. If so, the candidate source basic block corresponding to the i-th target operation has completed the translation process; correspondingly, obtaining the target basic block obtained after translating the candidate source basic block includes: searching for the target basic block corresponding to the target identifier in the preset buffer space as the target basic block obtained after translating the candidate source basic block.

[0131] In one embodiment, when the processor executes a computer program, the following steps are further implemented:

[0132] Execute multiple target operations for the multiple source basic blocks until the exit instruction in the source machine code is detected.

[0133] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0134] Obtain source machine code, which includes multiple source basic blocks; according to the execution order of the multiple source basic blocks during the runtime of the source machine code, perform the target operation multiple times on the multiple source basic blocks until the target operation on the last source basic block in the execution order is completed; wherein, the i-th target operation in the multiple target operations includes: detecting whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; if so, obtain the target basic block obtained after the translation processing of the candidate source basic block, and run the target basic block; if not, perform translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block, and run the target basic block.

[0135] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0136] Create an LLVM function corresponding to the candidate source basic block; obtain the entry address of the candidate source basic block, sequentially obtain source instructions from the source basic block according to the entry address, and after each acquisition of a source instruction, obtain the intermediate instruction corresponding to the source instruction, and after each acquisition of the intermediate instruction, add the intermediate instruction to the LLVM function; after all the intermediate instructions corresponding to the source instructions in the candidate source basic block are added to the LLVM function, run the LLVM function to perform translation processing on the candidate source basic block to obtain the target basic block.

[0137] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0138] If i = 1, use the entry address of the source machine code as the entry address of the candidate source basic block; if i > 1, determine the entry address of the candidate source basic block according to the last source instruction in the source basic block corresponding to the (i - 1)-th target operation.

[0139] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0140] According to the entry address, perform multiple instruction acquisition operations sequentially until the acquired source instruction is a control flow instruction; wherein, the i-th instruction acquisition operation in the instruction acquisition operations includes: determining the byte identifier of the candidate source instruction corresponding to the i-th instruction acquisition operation according to the entry address; obtaining the candidate source instruction according to the byte identifier.

[0141] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0142] Query a preset instruction database according to the source instruction to obtain the intermediate instruction corresponding to the source instruction, where multiple sets of corresponding relationships between preset source instructions and preset intermediate instructions are stored in the instruction database.

[0143] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0144] Obtain the instruction set description corresponding to the source machine code, where multiple preset source instructions are included in the instruction set description; after simulating and implementing each preset source instruction using a preset programming language, perform translation processing on each preset source instruction to obtain the preset intermediate instruction corresponding to each preset source instruction; construct the instruction database according to each preset source instruction and each preset intermediate instruction.

[0145] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0146] Use the entry address of the candidate source basic block as the identifier of the target basic block, and store the target basic block in a preset cache space.

[0147] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0148] According to the entry address of the candidate source basic block, detect whether the preset cache space contains a target identifier corresponding to the entry address of the candidate source basic block. If so, the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; correspondingly, obtaining the target basic block obtained after translation processing of the candidate source basic block includes: searching for the target basic block corresponding to the target identifier in the preset buffer space as the target basic block obtained after translation processing of the candidate source basic block.

[0149] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0150] Execute multiple target operations for the multiple source basic blocks until the exit instruction in the source machine code is detected.

[0151] In one embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0152] Obtain the source machine code, which includes multiple source basic blocks; according to the execution order of the multiple source basic blocks when the source machine code runs, perform the target operation multiple times on the multiple source basic blocks until the target operation on the last source basic block in the execution order is completed; wherein, the i-th target operation among the multiple target operations includes: detecting whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; if so, obtain the target basic block obtained after the translation processing of the candidate source basic block, and run the target basic block; if not, perform translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block, and run the target basic block.

[0153] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0154] Create an LLVM function corresponding to the candidate source basic block; obtain the entry address of the candidate source basic block, sequentially obtain source instructions from the source basic block according to the entry address, and after each acquisition of a source instruction, obtain the intermediate instruction corresponding to the source instruction, and after each acquisition of the intermediate instruction, add the intermediate instruction to the LLVM function; after all the intermediate instructions corresponding to the source instructions in the candidate source basic block are added to the LLVM function, run the LLVM function to perform translation processing on the candidate source basic block to obtain the target basic block.

[0155] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0156] If i = 1, use the entry address of the source machine code as the entry address of the candidate source basic block; if i > 1, determine the entry address of the candidate source basic block according to the last source instruction in the source basic block corresponding to the (i - 1)-th target operation.

[0157] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0158] According to the entry address, perform multiple instruction acquisition operations in sequence until the obtained source instruction is a control flow instruction; wherein, the i-th instruction acquisition operation in the instruction acquisition operation includes: determining the byte identifier of the candidate source instruction corresponding to the i-th instruction acquisition operation according to the entry address; obtaining the candidate source instruction according to the byte identifier.

[0159] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0160] Query a preset instruction database according to the source instruction to obtain the intermediate instruction corresponding to the source instruction, wherein multiple groups of corresponding relationships between preset source instructions and preset intermediate instructions are stored in the instruction database.

[0161] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0162] Obtain the instruction set specification corresponding to the source machine code, where the instruction set specification contains multiple preset source instructions; after simulating and implementing each preset source instruction using a preset programming language, perform translation processing on each preset source instruction to obtain the corresponding preset intermediate instruction for each preset source instruction; construct the instruction database based on each preset source instruction and each preset intermediate instruction.

[0163] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0164] Use the entry address of the candidate source basic block as the identifier of the target basic block, and store the target basic block in a preset cache space.

[0165] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0166] According to the entry address of the candidate source basic block, detect whether the preset cache space contains a target identifier corresponding to the entry address of the candidate source basic block. If so, the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; correspondingly, obtaining the target basic block obtained after translation processing of the candidate source basic block includes: searching in the preset buffer space for the target basic block corresponding to the target identifier as the target basic block obtained after translation processing of the candidate source basic block.

[0167] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0168] Execute multiple target operations for the multiple source basic blocks until the exit instruction in the source machine code is detected.

[0169] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include Read-Only Memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0170] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0171] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A code translation method, characterized in that, The method includes: Obtain source machine code, where the source machine code includes multiple source basic blocks; According to the execution order of the multiple source basic blocks when the source machine code runs, perform a target operation multiple times on the multiple source basic blocks until the target operation is completed for the last source basic block in the execution order; Wherein, the i-th target operation among the multiple target operations includes: Detect whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; If so, obtain the target basic block obtained after the translation processing of the candidate source basic block, and run the target basic block; If not, perform translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block, and run the target basic block; Wherein, the performing translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block includes: Create an LLVM function corresponding to the candidate source basic block; Obtain the entry address of the candidate source basic block, sequentially obtain source instructions from the source basic block according to the entry address, and after each source instruction is obtained, obtain the intermediate instruction corresponding to the source instruction, and after each intermediate instruction is obtained, add the intermediate instruction to the LLVM function; After all the intermediate instructions corresponding to the source instructions in the candidate source basic block are added to the LLVM function, run the LLVM function to perform translation processing on the candidate source basic block to obtain the target basic block.

2. The method according to claim 1, wherein The obtaining the entry address of the candidate source basic block includes: If i = 1, use the entry address of the source machine code as the entry address of the candidate source basic block; If i > 1, determine the entry address of the candidate source basic block according to the last source instruction in the source basic block corresponding to the (i - 1)-th target operation.

3. The method according to claim 1 or 2, characterized in that, The sequentially obtaining source instructions from the source basic block according to the entry address includes: According to the entry address, perform multiple instruction obtaining operations sequentially until the obtained source instruction is a control flow instruction; Wherein, the j-th instruction obtaining operation in the instruction obtaining operations includes: Determine the byte identifier of the candidate source instruction corresponding to the j-th instruction obtaining operation according to the entry address; Obtain the candidate source instruction according to the byte identifier.

4. The method according to claim 1, wherein The obtaining the intermediate instruction corresponding to the source instruction includes: Query a preset instruction database according to the source instruction to obtain the intermediate instruction corresponding to the source instruction, where multiple groups of corresponding relationships between preset source instructions and preset intermediate instructions are stored in the instruction database.

5. The method according to claim 4, wherein The construction process of the instruction database includes: Obtain the instruction set specification corresponding to the source machine code, where the instruction set specification includes multiple of the preset source instructions; After simulating and implementing each of the preset source instructions using a preset programming language, perform translation processing on each of the preset source instructions to obtain the preset intermediate instructions respectively corresponding to each of the preset source instructions; Construct the instruction database according to each of the preset source instructions and each of the preset intermediate instructions.

6. The method according to claim 1, wherein After obtaining the target basic block, the method further includes: Use the entry address of the candidate source basic block as the identifier of the target basic block, and store the target basic block in a preset cache space.

7. The method according to claim 6, wherein The detection of whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing includes: According to the entry address of the candidate source basic block, detect whether the preset cache space contains a target identifier corresponding to the entry address of the candidate source basic block. If so, the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; Correspondingly, the obtaining of the target basic block obtained after the translation processing of the candidate source basic block includes: Search in the preset cache space for the target basic block corresponding to the target identifier as the target basic block obtained after the translation processing of the candidate source basic block.

8. The method according to claim 1, wherein The execution of multiple target operations on the multiple source basic blocks until the target operation on the last source basic block in the execution order is completed includes: Execute multiple target operations on the multiple source basic blocks until the exit instruction in the source machine code is detected.

9. A code translation device, characterized in that, The device includes: An acquisition module, configured to acquire source machine code, where the source machine code includes multiple source basic blocks; An execution module, configured to execute multiple target operations on the multiple source basic blocks according to the execution order of the multiple source basic blocks when the source machine code runs, until the target operation on the last source basic block in the execution order is completed; Wherein, the i-th target operation among the multiple target operations includes: Detect whether the candidate source basic block corresponding to the i-th target operation has been completed with translation processing; If so, obtain the target basic block obtained after the translation processing of the candidate source basic block, and run the target basic block; If not, perform translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block, and run the target basic block; Wherein, the performing translation processing on the candidate source basic block based on the LLVM compiler to obtain the target basic block includes: Create an LLVM function corresponding to the candidate source basic block; Obtain the entry address of the candidate source basic block, sequentially obtain source instructions from the source basic block according to the entry address, and after each acquisition of a source instruction, obtain the intermediate instruction corresponding to the source instruction, and after each acquisition of the intermediate instruction, add the intermediate instruction to the LLVM function; After all the intermediate instructions corresponding to the source instructions in the candidate source basic block are added to the LLVM function, run the LLVM function to perform translation processing on the candidate source basic block to obtain the target basic block.

10. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method according to any one of claims 1 to 8.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the method according to any one of claims 1 to 8.

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