Operating methods, apparatus and devices for in-memory computing architectures applied to neural networks

Abstract

This disclosure provides an operation method, apparatus, and device for an in-memory computing architecture applied to a neural network. The operation method includes: generating a single-pulse input signal based on discrete-time encoding; inputting the single-pulse input signal into a memory array of the in-memory computing architecture to generate a bit-line current signal corresponding to the memory array; and controlling the neuron circuit of the in-memory computing architecture to output a single-pulse output signal based on discrete-time encoding according to the bit-line current signal, wherein the single-pulse output signal serves as the single-pulse input signal for the memory array of the next layer of the neural network in the next in-memory computing cycle. Therefore, single-pulse input in the in-memory computing architecture can be achieved through a single-pulse input signal based on discrete-time encoding, thereby greatly reducing the number of input pulses and significantly reducing the dynamic power consumption of the memory array and the neuron circuit.

Description

Technical Field

[0001] This disclosure relates to the fields of semiconductor device technology and integrated circuit technology, and in particular to an operating method, apparatus and device for an in-memory computing architecture applied to neural networks. Background Technology

[0002] Data-intensive deep learning models and the rapidly growing volume of unstructured data place higher demands on processor energy efficiency and area overhead. However, due to data transfer bottlenecks between the arithmetic unit and memory, traditional von Neumann architecture-based processors are difficult to reduce in terms of energy consumption and hardware resource overhead, making them unsuitable for deployment on power-constrained terminal devices. In-memory computing architectures utilize cross-arrays to perform efficient in-situ parallel computation within memory, thereby significantly accelerating matrix-vector multiplication calculations and avoiding the energy consumption associated with data transfer.

[0003] However, in existing mixed-signal coding-based in-memory computing architectures, the enormous power consumption of the analog-to-digital converter (ADC) limits improvements in energy efficiency. Although pulse-frequency coding-based in-memory computing architectures avoid high-power ADCs by utilizing integrator-emitter circuits, the energy consumption from numerous pulse emitters remains substantial. Summary of the Invention

[0004] (1) Technical issues to be resolved

[0005] To address the technical problem that existing in-memory computing architectures cannot effectively improve energy efficiency, this disclosure provides an operating method, apparatus, and device for an in-memory computing architecture applied to neural networks.

[0006] (2) Technical solution

[0007] The first aspect of this disclosure provides an operational method for an in-memory computing architecture applied to a neural network, comprising: generating a single-pulse input signal based on discrete-time encoding; inputting the single-pulse input signal into a memory array of the in-memory computing architecture to generate a bit-line current signal corresponding to the memory array; and controlling a neuron circuit of the in-memory computing architecture to output a single-pulse output signal based on discrete-time encoding according to the bit-line current signal, wherein the single-pulse output signal serves as a single-pulse input signal for the memory array of the next layer of the neural network in the next in-memory computing cycle.

[0008] According to an embodiment of this disclosure, the generation of a discrete-time encoded single-pulse signal includes: quantizing an extracted neural network input vector signal to generate a corresponding quantized input signal; and encoding the quantized input signal according to a preset discrete delay time encoding rule to generate a single-pulse input signal based on discrete-time encoding. The preset discrete delay time encoding rule is a rule that encodes the single pulse as the single-pulse input signal based on the delay time between the start time of an enable signal corresponding to the in-memory computation cycle and the arrival time of the single pulse of the single-pulse input signal responding to the enable signal, wherein the length of the delay time is the magnitude of the quantized input signal.

[0009] According to an embodiment of this disclosure, before inputting the single-pulse input signal into the memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array, the method further includes: mapping a weight matrix corresponding to the extracted neural network input vector signal to each memory cell of the memory array, including: mapping the weight matrix to the conductance values ​​of two adjacent columns of the memory array, representing positive and negative values ​​respectively, according to the weight sign; and mapping the weight difference between two adjacent columns to the conductance values ​​of two adjacent columns of the memory array, representing positive and negative values ​​respectively, according to the weight difference sign, wherein the weight difference is the difference between the sum of the weights of adjacent negative columns and the sum of the weights of positive columns.

[0010] According to an embodiment of this disclosure, the step of inputting the single-pulse input signal into the memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array includes: inputting the single-pulse input signal into the memory array of the in-memory computing architecture; controlling the memory array that has completed the weight matrix mapping to perform a multiply-accumulate operation based on the input single-pulse input signal to generate a bit line current signal.

[0011] According to an embodiment of this disclosure, before the neural circuit controlling the in-memory computing architecture outputs a single-pulse output signal based on discrete-time encoding according to the bit line current signal, the method further includes: performing selection processing on the bit line current signal through a multiplexer of the in-memory computing architecture corresponding to the memory array.

[0012] According to an embodiment of the present disclosure, in the process of the neuron circuit controlling the in-memory computing architecture to output a single pulse output signal based on discrete-time encoding according to the bit line current signal, the method includes: controlling the on / off state of the first switching transistor and the second switching transistor of the neuron circuit in response to the bit line current signal, so that the neuron circuit outputs the single pulse output signal in response to the on / off state.

[0013] According to an embodiment of this disclosure, before controlling the on / off state of the first and second switching transistors of the neuron circuit in response to the bit line current signal, such that the neuron circuit outputs the single pulse output signal in response to the on / off state, the method further includes: controlling the on / off state to satisfy the first switching transistor being on and the second switching transistor being off, and realizing the pre-charge capacitor voltage of the neuron circuit in response to the on / off state.

[0014] According to an embodiment of this disclosure, controlling the on / off states of the first and second switching transistors of the neuron circuit in response to the bit line current signal, such that the neuron circuit outputs the single-pulse output signal in response to the on / off state, includes: controlling the on / off state to satisfy that both the first and second switching transistors are off; and, in response to the on / off state and the bit line current signal, causing the neuron circuit to generate a first capacitor voltage based on the bit line current signal and the pre-charge capacitor voltage; and controlling the on / off state to satisfy that the first switching transistor is off and the second switching transistor is on, encoding and outputting the first capacitor voltage as the single-pulse output signal with a discrete delay time.

[0015] A second aspect of this disclosure provides an operating apparatus for an in-memory computing architecture applied to a neural network, comprising an input signal generation module, a bitline signal generation module, and a control output module. The input signal generation module generates a single-pulse input signal based on discrete-time encoding; the bitline signal generation module inputs the single-pulse input signal into the memory array of the in-memory computing architecture to generate a bitline current signal corresponding to the memory array; and the control output module controls the neuron circuits of the in-memory computing architecture to output a single-pulse output signal based on discrete-time encoding according to the bitline current signal, wherein the single-pulse output signal serves as the single-pulse input signal for the memory array of the next layer of the neural network in the next in-memory computing cycle.

[0016] A third aspect of this disclosure provides an electronic device comprising: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors perform the above-described method of operation applied to an in-memory computing architecture for a neural network.

[0017] A fourth aspect of this disclosure also provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the above-described operation method for an in-memory computing architecture applied to a neural network.

[0018] The fifth aspect of this disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method of operation applied to an in-memory computing architecture for neural networks.

[0019] (3) Beneficial effects

[0020] This disclosure provides an operation method, apparatus, and device for an in-memory computing architecture applied to a neural network. The operation method includes: generating a single-pulse input signal based on discrete-time encoding; inputting the single-pulse input signal into a memory array of the in-memory computing architecture to generate a bit-line current signal corresponding to the memory array; and controlling the neuron circuit of the in-memory computing architecture to output a single-pulse output signal based on discrete-time encoding according to the bit-line current signal, wherein the single-pulse output signal serves as the single-pulse input signal for the memory array of the next layer of the neural network in the next in-memory computing cycle. Therefore, single-pulse input in the in-memory computing architecture can be achieved through a single-pulse input signal based on discrete-time encoding, thereby greatly reducing the number of input pulses and significantly reducing the dynamic power consumption of the memory array and the neuron circuit. Attached Figure Description

[0021] Figure 1 The illustration schematically depicts an application scenario diagram of an operating method, apparatus, device, medium, and program product applied to an in-memory computing architecture for a neural network according to embodiments of the present disclosure;

[0022] Figure 2 A flowchart illustrating an operation method of an in-memory computing architecture applied to a neural network according to an embodiment of the present disclosure is shown schematically.

[0023] Figure 3A The diagram illustrates a corresponding matrix-vector multiplication computation diagram of an in-memory computing architecture applied to a neural network according to an embodiment of the present disclosure.

[0024] Figure 3B This illustration schematically shows the corresponding embodiments of the present disclosure. Figure 3A The structural composition and technical principle diagram of the in-memory computing architecture applied to neural networks;

[0025] Figure 3C This schematically illustrates a circuit structure diagram of a neuron circuit applied to an in-memory computing architecture of a neural network according to an embodiment of the present disclosure;

[0026] Figure 4A The diagram schematically illustrates a node waveform of a neuron circuit applied to an in-memory computing architecture of a neural network according to an embodiment of the present disclosure;

[0027] Figure 4BThe discrete delay time T of a single-pulse output signal according to an embodiment of the present disclosure is illustrated schematically. out The result of multiplying with the target vector matrix ∑G·X·T code Simulation diagram of the relationship between them;

[0028] Figure 5 This schematically illustrates a structural block diagram of an operating device for an in-memory computing architecture applied to a neural network according to embodiments of the present disclosure; and

[0029] Figure 6 A block diagram schematically illustrates an electronic device suitable for implementing an in-memory computing architecture applied to a neural network, according to an embodiment of the present disclosure. Detailed Implementation

[0030] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0031] It should be noted that implementations not illustrated or described in the accompanying drawings or the main text of the specification are all forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.

[0032] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure.

[0033] Furthermore, the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are merely illustrative of embodiments of this disclosure. Additionally, any reference numerals placed between parentheses in the claims should not be construed as limiting the scope of the claims.

[0034] Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0035] The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify the corresponding elements does not in itself imply that the element has any ordinal number, nor does it represent the order of one element with another element or the order of manufacturing methods. The use of these ordinal numbers is only to enable a named element to be clearly distinguished from another element with the same name.

[0036] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose. Furthermore, in the unit claims enumerating several means, several of these means may be embodied by the same hardware item.

[0037] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the disclosure, in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof. However, this approach to disclosure should not be construed as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, the aspects of the disclosure consist of fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the disclosure.

[0038] To address the technical problem that existing in-memory computing architectures cannot effectively improve energy efficiency, this disclosure provides an operating method, apparatus, and device for an in-memory computing architecture applied to neural networks.

[0039] Figure 1 The diagram illustrates an application scenario of an operational method for an in-memory computing architecture applied to a neural network according to an embodiment of the present disclosure.

[0040] like Figure 1 As shown, application scenario 100 according to this embodiment may include terminal devices 101, 102, and 103, network 104, and server 105. Network 104 is used as a medium to provide a communication link between terminal devices 101, 102, and 103 and server 105. Network 104 may include various connection types, such as wired or wireless communication links or fiber optic cables, etc.

[0041] Users can use terminal devices 101, 102, and 103 to interact with server 105 via network 104 to receive or send messages, etc. Various communication client applications can be installed on terminal devices 101, 102, and 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social media platform software, etc. (for example only).

[0042] Terminal devices 101, 102, and 103 can be various electronic devices with displays and web browsing capabilities, including but not limited to smartphones, tablets, laptops, and desktop computers.

[0043] Server 105 can be a server that provides various services, such as a backend management server that supports websites browsed by users using terminal devices 101, 102, and 103 (for example only). The backend management server can analyze and process data such as received user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0044] It should be noted that the operation method of the in-memory computing architecture for neural networks provided in this disclosure embodiment can generally be executed by server 105. Correspondingly, the operation device of the in-memory computing architecture for neural networks provided in this disclosure embodiment can generally be located in server 105. The operation method of the in-memory computing architecture for neural networks provided in this disclosure embodiment can also be executed by a server or server cluster that is different from server 105 and capable of communicating with terminal devices 101, 102, 103 and / or server 105. Correspondingly, the operation device of the in-memory computing architecture for neural networks provided in this disclosure embodiment can also be located in a server or server cluster that is different from server 105 and capable of communicating with terminal devices 101, 102, 103 and / or server 105.

[0045] It should be understood that Figure 1 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0046] The following will be based on Figure 1 The described scene, through Figures 2-6 The operation method of the in-memory computing architecture applied to neural networks according to the disclosed embodiments is described in detail.

[0047] Figure 2 A flowchart illustrating an operational method of an in-memory computing architecture applied to a neural network according to an embodiment of the present disclosure is shown.

[0048] like Figure 2As shown, the operation method of the in-memory computing architecture applied to the neural network in this embodiment includes operations S201 to S203.

[0049] In operation S201, a single-pulse input signal based on discrete-time encoding is generated;

[0050] In operation S202, the single-pulse input signal is input to the memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array; and

[0051] In operation S203, the neuron circuit controlling the in-memory computing architecture outputs a single-pulse output signal based on discrete-time encoding according to the bit line current signal. The single-pulse output signal serves as the single-pulse input signal of the memory array of the next layer of the neural network in the next in-memory computing cycle.

[0052] A single-pulse input signal based on discrete-time coding is a signal input to the memory array of an in-memory computing architecture that is encoded in discrete time using a discrete-time coding scheme. This allows the single-pulse signal, with its discrete delay time characteristic, to represent the magnitude of the input signal. The discrete delay time characteristic can be understood as encoding the pulse signal by utilizing the delay time between the pulse arrival time and the start time of the pulse response enable signal. This allows larger input values ​​to be encoded as pulse signals with longer delay times, and smaller input values ​​as pulse signals with shorter delay times. Specifically, the input intensity can be represented by the leakage time of charge in neurons; a longer delay time results in a shorter leakage time, more charge retained by the neuron, and a larger corresponding input value to the memory array. This enables operations on the memory array, generating corresponding memory array bit line current signals.

[0053] The in-memory computing architecture includes a memory array and its corresponding operating circuit modules. The memory array includes a non-volatile memory (NVM) array structure, which can be used to perform matrix-vector multiplication calculations on the input signal, generating a corresponding bit line current signal. The bit line current signal is a current signal generated by the memory array in response to the single-pulse input signal corresponding to the input value, and is output through the bit lines of the memory array. This bit line current signal can be used to generate the output signal corresponding to the input value, i.e., a single-pulse output signal.

[0054] Furthermore, the in-memory computing architecture may also include neural circuits adapted to the memory array. These neural circuits can convert and process bitline current signals to generate corresponding single-pulse output signals. The discrete-time characteristics of this single-pulse output signal can be consistent with those of the input single-pulse signal, thus achieving discrete-time encoding of the pulse signal as a whole while ensuring the discrete-time characteristics of the output signal, thereby reducing the number of input pulses.

[0055] For in-memory computing architectures based on neural networks, the implementation of corresponding in-memory computation involves multiple in-memory computation cycles. Each in-memory computation cycle corresponds to the data processing of one layer of the neural network. Each single-pulse output signal can serve as the input signal for the memory array of the next layer of the neural network in the next in-memory computation cycle. Due to its discrete-time signal characteristics, the memory array of the next layer of the neural network corresponding to the single-pulse output signal can output the next single-pulse output signal in the next in-memory computation cycle. This process is repeated until the in-memory computation process is completed and the result is output.

[0056] Therefore, compared to the existing technology that encodes array input values ​​using multiple pulse signals, this disclosure encodes the input signal into a single pulse signal with discrete delay time characteristics. This allows for the operation of the memory array and the generation of the corresponding memory array bit line current signal with only a single pulse signal. This significantly reduces the number of input pulses, thereby greatly reducing the dynamic power consumption of the memory array and corresponding neural network circuits and other in-memory computing architectures. Furthermore, by quantizing the delay time into discrete delay time instead of analog delay time, this disclosure achieves excellent compatibility with digital circuits.

[0057] The in-memory computing structure described in this embodiment can directly train time-coded spiking neural networks, such as the TTFS (time-to-first spike) encoding scheme, ensuring that each neuron fires at most one spike during the corresponding in-memory computing process; alternatively, it can be converted from a deep neural network to a time-coded spiking neural network. Therefore, the method described in this embodiment provides a time-coded neural network in-memory computing implementation scheme, which can achieve single-pulse input in the in-memory computing architecture using discrete-time encoded single-pulse input signals, thereby significantly reducing the number of input pulses and greatly reducing the dynamic power consumption of the memory array and neuron circuits.

[0058] like Figures 2-3C As shown, according to an embodiment of this disclosure, the generation of a discrete-time encoded single-pulse signal in operation S201 includes:

[0059] The extracted neural network input vector signal is quantized to generate the corresponding quantized input signal;

[0060] The quantized input signal is encoded according to a preset discrete delay time encoding rule to generate a single pulse input signal based on discrete time encoding;

[0061] The preset discrete delay time encoding rule is a rule that encodes the single pulse as the single pulse input signal based on the delay time between the start time of the enable signal corresponding to the in-memory calculation cycle and the arrival time of the single pulse of the single pulse input signal in response to the enable signal, wherein the length of the delay time is the magnitude of the quantized input signal.

[0062] like Figures 3A-3B The schematic diagram of vector matrix multiplication based on discrete-time encoding shown can well reflect the technical principle of discrete-time encoding of pulse signals described above in the embodiments of this disclosure. The extracted neural network input vector signal can be a vector signal of image pixel features extracted based on image recognition technology. The corresponding input vectors x[1:i,1] (where i is a positive integer greater than 0) of these neural network input vector signals are quantized to generate corresponding quantized input signals. Specifically, the quantized input signal can be embodied as follows: Figure 3A The input vector X[1:i, 1] shown satisfies:

[0063]

[0064] Among them, X i The elements in the discrete N-bit input vector X[1:i,1] are obtained by quantizing the corresponding input vector x[1:i,1]. i is a positive integer greater than 0, N is a positive integer greater than 0, and N represents the precision of the input quantization.

[0065] Therefore, discrete-time coding can specifically involve quantizing the input vector x[1:i,1] into an N-bit input vector X[1:i,1], and then encoding it into a delay time of X·T. code A single-pulse signal. Among them, such as... Figure 3B The vector-matrix multiplication operation shown is based on discrete-time coding. The total coding time of this discrete-time coding scheme is (2 N -1)·T code +T sense Where N is the quantization input precision, T code T is the unit delay time. sense It is a fixed pulse width for pulse signals.

[0066] Within the initial in-memory computation cycle of this in-memory computation process, the generated enable signal can be used to enable the single-pulse input signal. The start time of this enable signal can be understood as its generation time, and the arrival time of the single pulse can be understood as the time when the single pulse signal arrives at the memory array in response to the enable signal. The time difference between the two is the aforementioned delay time. Encoding the single pulse using this delay time generates the corresponding single-pulse input signal. The length of the delay time can be understood as the magnitude of the quantized input signal, which can be used to provide feedback on the magnitude of the input value corresponding to the quantized input signal. A longer delay time results in a larger input value.

[0067] like Figures 2-3C As shown, according to an embodiment of this disclosure, before operation S202, which involves inputting the single-pulse input signal into the memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array, the method further includes:

[0068] Mapping the weight matrix corresponding to the extracted neural network input vector signal to each memory cell of the memory array includes: mapping the weight matrix to the conductance values ​​of two adjacent columns representing positive and negative values ​​of the memory array according to the weight sign; and mapping the weight difference between two adjacent columns to the conductance values ​​of two adjacent columns representing positive and negative values ​​of the memory array according to the weight difference sign, wherein the weight difference is the difference between the sum of the weights of adjacent negative columns and the sum of the weights of positive columns.

[0069] like Figure 3A and Figure 3B As shown, the weight matrix corresponding to the input vector signal x[1:i,1] of the above neural network can be W[1:i,1:j], where the weight values ​​in this weight matrix are mapped to the conductance values ​​(G) of two adjacent columns of memory cells in the memory array according to the weight sign. + and G - In the above, the weight sign can be the sign of the weight value; if the value is positive, the sign is positive, and vice versa. The memory array can be a non-volatile memory array, specifically having (i+c)◇2j memory cells, divided into H1-H... i+c Total i+c rows and L1-L 2j There are 2j columns in total. Specifically, the weight matrix W[1:i, 1:j] is mapped to the conductance values ​​(G) of two adjacent columns of memory cells in the memory array according to the weight sign. + and G - If the weight value W ij If it is a positive value, it is mapped to positive conductance (G). + ) column, if the weight value W ij If it is negative, it is mapped to negative conductance (G). -(Column). For example, if we take W in the weight matrix... 11 、W 21 ..., W i1 The weight values ​​are mapped one-to-one to H1-H in column L1 or L2 according to their weight symbols. i The memory cell of the row, if W i1 If it is a positive value, it is mapped to column L1. If W i1 If the value is negative, it is mapped to column L2. This corresponds to W. 12 、W 22 ..., W i2 The weight values ​​are mapped one-to-one to H1-H in column L3 or L4 according to their weight symbols. i The memory cells are rows. Adjacent columns are L1 and L2, and the next adjacent columns are L3 and L4. The conductance of the weight mapping in the original neural network algorithm is represented by G. weight express.

[0070] In addition, the difference G between the sum of the weights of two adjacent columns diff =k leak (∑G - -∑G + It also needs to be mapped to the adjacent columns of the memory array according to the sign of its weight difference, where k leak The leakage coefficients are those of a known neuron model. The difference between the sums of the weights of two adjacent columns corresponds to the H-th column of the memory array. i+1 -H i+c The corresponding adjacent columns of the row are mapped, as shown above, by applying the mapping to W in the weight matrix. 11 W 21 ..., W i1 The weight values ​​are mapped one-to-one to H1-H in column L1 or L2 according to their weight symbols. i The memory cell of the row corresponds to W 12 、W 22 ..., W i2 The weight values ​​are mapped one-to-one to H1-H in column L3 or L4 according to their weight symbols. i After the memory cell of the row, the difference between the weights is mapped to the Hth column corresponding to the L1 or L2 column. i+1 -H i+c The memory cell of the row and the Hth column of the L3 or L4 column i+1 -H i+c A row of memory cells.

[0071] Among them, the difference G between the weights is called the difference between the weights. i diff The difference conductance of the weighted sum of two adjacent positive and negative columns satisfies:

[0072]

[0073] Where, k leak denoted as the leakage coefficient of a known neuron model. This neuron model corresponds to the neural network in the aforementioned in-memory computing architecture.

[0074] like Figures 2-3C As shown, according to an embodiment of this disclosure, in operation S202, inputting the single-pulse input signal into the memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array includes:

[0075] The single-pulse input signal is input into the memory array of the in-memory computing architecture;

[0076] The memory array that completes the weight matrix mapping performs a multiply-accumulate operation based on the input single-pulse input signal to generate a bit line current signal.

[0077] After mapping the aforementioned weight differences, the discrete-time encoded single-pulse input signal can be applied to the corresponding operation lines, such as word lines, of the memory array in the in-memory computing architecture to complete the response to the input values ​​of the memory array. Based on the above... Figure 3A The diagram shown illustrates the principle of matrix multiplication calculation. The memory array is controlled to complete the multiplication and accumulation process for the single-pulse input signal, and outputs the response current on the bit line of the array as the bit line current signal.

[0078] like Figures 2-3C As shown, according to an embodiment of this disclosure, before the neuron circuit controlling the in-memory computing architecture in operation S203 outputs a single-pulse output signal based on discrete-time encoding according to the bit line current signal, the method further includes:

[0079] The bit line current signal is selected by a multiplexer of the in-memory computing architecture corresponding to the memory array.

[0080] like Figure 3A As shown, before inputting the bitline current signal into the neuron circuit, for some special cases, such as multiple neuron circuits, a multiplexer set between the neuron circuit and the memory array can be used to select the neuron circuit into which the bitline current signal is ultimately input. This multiplexer can serve as an alternative technique to accommodate different correspondences between memory arrays and neuron circuits.

[0081] like Figures 2-3CAs shown, according to an embodiment of this disclosure, in the operation S203, the neuron circuit controlling the in-memory computing architecture outputs a single-pulse output signal based on discrete-time encoding according to the bit line current signal, including:

[0082] In response to the bit line current signal, the opening and closing states of the first and second switching transistors of the neuron circuit are controlled, so that the neuron circuit outputs the single pulse output signal in response to the opening and closing state.

[0083] Based on the aforementioned discrete-time encoding principle, the control of the neuron circuit requires a leakage integral trigger to integrate the bitline current signal and convert it into a single-pulse output signal with a discrete delay time. By controlling this neuron circuit, the charging current corresponding to the positive weights and the discharging current corresponding to the negative weights in the memory array can be integrated simultaneously to obtain the capacitor voltage. Then, based on this capacitor voltage, the neuron circuit is further controlled to convert the voltage difference between the capacitor voltage and the threshold voltage into a single-pulse output signal with a discrete delay time. In addition, the neuron circuit also needs to maintain a constant array read voltage over a large range of capacitor voltage variations.

[0084] Therefore, as Figure 3C The neuron circuit 300 shown in the diagram mainly includes a charging terminal 301, a discharging terminal 302, an operational amplifier 303, a comparator 304, a positive current mirror 305, a negative current mirror 306, an operational amplifier 307, and an output pulse memory 308. It also includes a first switching transistor S1, a second switching transistor S2, a capacitor C, a resistor R, a constant current source CS, and a pre-charge resistor R. pre The charging terminal 301 and the discharging terminal 302 are used to connect to the aforementioned memory array, for introducing the bit line current signal of the weight array into the neuron circuit.

[0085] Therefore, the neuron circuit of this embodiment has the following functions: it integrates the bit line current and leaks the capacitor voltage through capacitor C and resistor R. Operational amplifiers 303 and 307 control the positive and negative bit line voltages of the memory array of the in-memory computing architecture to be unaffected by the voltage value of capacitor C in the neuron circuit. Furthermore, the bit line current signals corresponding to the positive and negative weights are input to the neuron circuit through charging terminal 301 and discharging terminal 302 to simultaneously charge and discharge capacitor C. The bit line current signal corresponding to the positive weight charges capacitor C through positive current mirror 305, while the bit line current signal corresponding to the negative weight discharges the capacitor through negative current mirror 306 composed of two current mirror circuits. Next, the pre-charge resistor R... preThis is used to precharge the capacitor C, ensuring it reaches the precharge voltage. Specifically, before the bit line current signal is input to the neuron circuit, capacitor C is precharged to retain enough initial electrons for the column current corresponding to the negative weight to discharge it. Furthermore, after the input pulse ends, the constant current source CS discharges capacitor C via the second switching transistor S2. Controlling the magnitude of the constant current source CS controls the accuracy of the single-pulse output signal based on discrete delay time encoding. Additionally, the capacitor voltage of C leaks to the threshold voltage V of the voltage comparator 304. th Then, a trigger output pulse is generated as the aforementioned single-pulse output signal. Capacitor C is connected to comparator 304; when the capacitor voltage is less than the threshold voltage V... th When the rising edge of the clock arrives, the neuron circuit 300 will trigger an output pulse as the aforementioned single-pulse output signal. This output pulse can be temporarily stored in register 308.

[0086] Therefore, as Figure 3C As shown, the capacitor C and resistor R of the neuron circuit 300 perform integration and leakage functions, respectively. Operational amplifiers 303 and 307 clamp the bit line operating voltage of the memory array to a fixed value. The column current corresponding to the positive weight charges the capacitor C through the positive current mirror 305, and the column current corresponding to the negative weight discharges the capacitor C through the negative current mirror 306 composed of two current mirror circuits. In addition, a pre-charge resistor R... pre A first switching transistor S1 is connected to the capacitor C, allowing the capacitor C to retain enough initial electrons for discharge by the column current corresponding to the negative weight. The capacitor C is also connected to a constant current source CS and a voltage comparator 304 via a second switching transistor S2. When the voltage across the capacitor C is less than the threshold voltage V of the voltage comparator 304... th Furthermore, when the rising edge of the clock arrives, the neuron circuit 300 will trigger an output pulse, which is temporarily stored in register 308. Therefore, the neuron circuit 300 can control the accuracy of the single-pulse output signal based on discrete delay time encoding by adjusting the constant current source CS.

[0087] Completing in-memory computation of a neural network based on discrete-time encoding requires operations on the neuron circuit, which may involve: pre-charging capacitance, vector-matrix multiplication calculation processing, and encoding of the vector-matrix multiplication result.

[0088] The Leakage Integral Triggering Model (LIF neuron model) is a model describing the dynamic behavior of neurons. This LIF neuron model obtains the membrane voltage by integrating the stimulated current. When the membrane voltage reaches a threshold voltage, the neuron triggers a pulse, and the membrane voltage is reset simultaneously. The LIF model describes the dynamic behavior of neurons as shown in equations (3) and (4).

[0089]

[0090]

[0091] Where C is the membrane capacitance, V(t) is the membrane voltage, and G and V r R represents synaptic strength and stimulus amplitude. leak This is the leakage resistance. In the absence of continuous stimulation, the membrane voltage spontaneously returns to its resting state through the leakage resistance. The above-described leakage integral triggering model is a prototype of the neuron model designed in this disclosure.

[0092] like Figures 2-3C As shown, according to an embodiment of this disclosure, before controlling the on / off states of the first and second switching transistors of the neuron circuit in response to the bit line current signal, such that the neuron circuit outputs the single-pulse output signal in response to the on / off state, the method further includes:

[0093] The control state is such that the first switching transistor is on and the second switching transistor is off, and the pre-charge capacitor voltage of the neuron circuit is realized in response to the on / off state. This on / off state is a combination of transistor on / off states formed by the respective on / off states of the first switching transistor S1 and the second switching transistor S2 of the neuron circuit. The first switching transistor S1 and the second switching transistor S2 can be transistor control units with circuit switching functions, and the operation process of the neuron circuit can be well realized through these first switching transistors S1 and the second switching transistor S2.

[0094] First, capacitor C in the neuron circuit is pre-charged. The first switching transistor S1 is set to ON, while the second switching transistor S2 is set to OFF, thus pre-charging capacitor C to ensure that the pre-charge capacitance of C satisfies the capacitor voltage V. c step1 This allows the capacitor C to retain enough initial electrons for the column current corresponding to the negative weight to discharge it. Pre-charge voltage V c step1 The expression for is shown in equation (5):

[0095]

[0096] Among them, Rpre For the equivalent pre-charge resistance, T pre For pre-charge time, V dd This is the power supply voltage.

[0097] like Figures 2-3C As shown, according to an embodiment of this disclosure, in controlling the on / off states of the first and second switching transistors of the neuron circuit in response to the bit line current signal, such that the neuron circuit outputs the single-pulse output signal in response to the on / off state, the method includes:

[0098] The control state is such that both the first and second switching transistors are off. In response to the on / off state and the bit line current signal, the neuron circuit generates a first capacitor voltage based on the bit line current signal and the pre-charge capacitor voltage.

[0099] The control state is such that the first switching transistor is off and the second switching transistor is on, and the first capacitor voltage is encoded and output as a single pulse output signal with discrete delay time.

[0100] After the capacitor C of the neuron circuit completes the pre-charging operation described above, the vector matrix multiplication calculation is further performed. The first switching transistor S1 is set to OFF, and the second switching transistor S2 is also set to OFF. The encoded neural network input vector signal is applied to the algorithm weight conductance (G) in the form of a single-pulse input signal with discrete delay time. weight At the same time, the single-pulse input signal with the longest delay time will be applied to the weight difference conductance (G). diff The memory array mapped by the weight matrix performs a multiply-accumulate operation in response to the single-pulse input signal, generating a bit line current signal.

[0101] Among them, the weighted conductivity value G ij For a single-pulse input signal X i ·T code The contribution of the response current to the capacitor voltage of the neuron circuit, V mul As shown in equation (6):

[0102]

[0103] Corresponding to the above formula (6), the capacitor voltage V c step2 Indicates H1-H i+c The single-pulse input signal of the row and the H1-H of the j-th and (j+1)-th (j is an odd number) columns of the memory array. i+c The result of multiplying and summing the conductivity values ​​of the rows, the weighted conductivity value G ij For a single-pulse input signal X i·T code The contribution of the response current to the capacitor voltage of the neuron circuit, V mul The sum is shown in equation (7):

[0104]

[0105] in, V r It is the bit line control voltage of the memory array, k leak This represents the leakage coefficient of the LIF neuron model.

[0106] Rearranging the capacitor voltage expression of the above formula (7) yields formula (8):

[0107]

[0108] in, K = k leak (1-k sense ).

[0109] Furthermore, based on the above formula (8), the operation of encoding the result of vector matrix multiplication involves setting the first switching transistor S1 = OFF, while the second switching transistor S2 = ON. At this time, capacitor C flows through the constant current source CS (whose current I... tran ) and leakage resistance R leak Discharge encodes the capacitor voltage, representing the result of vector-matrix multiplication, into a single-pulse signal with a discrete delay. During this process, the capacitor voltage V... c step3 and discharge time T out The relationship between them is shown in equation (9) below.

[0110]

[0111] Where, when the capacitor voltage V c step3 Less than the threshold voltage V th When the rising edge of the clock arrives, the neuron circuit 300 will trigger an output pulse, as shown in equation (10).

[0112]

[0113] Therefore, when the threshold voltage is set to V th =k leak ·k sense ·V c step1 At that time, the voltage change V caused during the discharge process is... vmm As shown in equation (11) below.

[0114]

[0115] When (2) is satisfied N -1)T code <<R leak When C, the leakage process of capacitor C can be equivalent to a linear process, that is, formula (11) can be approximated by the following formula (12).

[0116]

[0117] Wherein, the voltage difference V vmm It can approximate the result of vector-matrix multiplication.

[0118] Therefore, the capacitor voltage V in the neuron circuit 300 changes. vmm Required discharge time T out As shown in equation (13) below.

[0119]

[0120] Wherein, when (2) N -1)T code <<R leak When C, the above formula (13) can be approximated by the following formula (14):

[0121]

[0122] Therefore, the result of vector-matrix multiplication V vmm This is encoded as the delay time T of the single-pulse input signal. out .

[0123] like Figure 4A and Figure 4B As shown, the above-mentioned in-memory computation implementation of the neural network based on discrete-time encoding can be simulated using tools such as Hspice. Both the input and weights are derived from a convolutional neural network that recognizes handwritten digit datasets. Figure 4A The graphs show the node waveforms for the capacitor voltage V(pm) at node pm in the neuron circuit and the voltage V(so) at node so of comparator 304, respectively. The waveforms for nodes pm and so are shown below. Figure 3C As shown. During the pre-charging operation, the capacitor voltage is pre-charged to 1.4V. During the vector matrix multiplication calculation, the capacitor voltage is determined by both the array charging / discharging current and the neuron leakage current. In earlier time steps, the charging current from the weight array is greater than the neuron leakage current; in later time steps, the charging current from the weight array gradually becomes less than the neuron leakage current. Therefore, during the vector matrix multiplication calculation, the capacitor voltage first increases and then decreases. Furthermore, during the encoding operation of the vector matrix multiplication result, the constant current source CS and the leakage resistor R... leakSimultaneously, the capacitor is discharged, and when the capacitor voltage drops to the threshold voltage, the comparator 304 triggers an output pulse.

[0124] like Figure 4B As shown, the discrete delay time T of the output pulse (i.e., the single-pulse output signal) is obtained through simulation. out The result of multiplying with the target vector matrix ∑G·X·T code The relationship between them. Specifically, 50 sets of weights and inputs were randomly selected from the convolutional neural network for recognizing handwritten digit datasets, and the target vector matrix multiplication result ∑G·X·T was obtained respectively. code Then, the delay time T of the output pulse of the neuron circuit is simulated using tools such as Hspice. out Simulation results show that the pulse delay time T out It can represent the results of vector-matrix multiplication very approximately, demonstrating excellent simulation results.

[0125] Therefore, the method described in this embodiment of the present disclosure, through a neural network in-memory computation method based on discrete-time coding, can significantly reduce the number of input pulses, thereby greatly reducing the dynamic power consumption of the memory array, including the NVM array, and the corresponding neuron circuit. This neural network in-memory computation method based on discrete-time coding can be flexibly applied to directly trained or converted time-coded multilayer perceptrons and convolutional neural networks. Therefore, the method described in this embodiment of the present disclosure proposes a neural network in-memory computation implementation scheme based on discrete-time coding, which has high energy efficiency and can be applied to large-scale neural networks.

[0126] Based on the above-described operating method for in-memory computing architectures applied to neural networks, this disclosure also provides an operating apparatus for in-memory computing architectures applied to neural networks. The following will be combined with... Figure 5 The device is described in detail.

[0127] Figure 5 The diagram schematically illustrates a structural block diagram of an operating device for an in-memory computing architecture applied to a neural network according to an embodiment of the present disclosure.

[0128] like Figure 5 As shown, the operating device 500 for the in-memory computing architecture of the neural network in this embodiment includes an input signal generation module 510, a bit line signal generation module 520, and a control output module 530.

[0129] The input signal generation module 510 is used to generate a single-pulse input signal based on discrete-time encoding. In one embodiment, the input signal generation module 510 can be used to perform the operation S201 described above, which will not be repeated here.

[0130] The bit line signal generation module 520 is used to input the single-pulse input signal into the memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array. In one embodiment, the bit line signal generation module 520 can be used to perform the operation S202 described above, which will not be repeated here.

[0131] The control output module 530 is used to control the neuron circuit of the in-memory computing architecture to output a single-pulse output signal based on discrete-time encoding according to the bit line current signal. The single-pulse output signal serves as the single-pulse input signal of the memory array of the next layer of the neural network in the next in-memory computing cycle. In one embodiment, the control output module 530 can be used to perform the operation S203 described above, which will not be repeated here.

[0132] According to embodiments of this disclosure, any plurality of modules among the input signal generation module 510, bit line signal generation module 520, and control output module 530 may be combined into one module, or any one of these modules may be split into multiple modules. Alternatively, at least a portion of the functionality of one or more of these modules may be combined with at least a portion of the functionality of other modules and implemented in one module. According to embodiments of this disclosure, at least one of the input signal generation module 510, bit line signal generation module 520, and control output module 530 may be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or implemented in hardware or firmware by any other reasonable means of integrating or packaging the circuitry, or implemented in software, hardware, or firmware, or in any suitable combination of any of these three implementation methods. Alternatively, at least one of the input signal generation module 510, the bit line signal generation module 520, and the control output module 530 may be implemented at least partially as a computer program module, which can perform corresponding functions when the computer program module is run.

[0133] Figure 6 A block diagram schematically illustrates an electronic device suitable for implementing an in-memory computing architecture applied to a neural network, according to an embodiment of the present disclosure.

[0134] like Figure 6As shown, an electronic device 600 according to an embodiment of this disclosure includes a processor 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage portion 608 into a random access memory (RAM) 603. The processor 601 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 601 may also include onboard memory for caching purposes. The processor 601 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of this disclosure.

[0135] RAM 603 stores various programs and data required for the operation of electronic device 600. Processor 601, ROM 602, and RAM 603 are interconnected via bus 604. Processor 601 performs various operations of the method flow according to embodiments of the present disclosure by executing programs in ROM 602 and / or RAM 603. It should be noted that the programs may also be stored in one or more memories other than ROM 602 and RAM 603. Processor 601 may also perform various operations of the method flow according to embodiments of the present disclosure by executing programs stored in said one or more memories.

[0136] According to embodiments of this disclosure, the electronic device 600 may further include an input / output (I / O) interface 605, which is also connected to a bus 604. The electronic device 600 may also include one or more of the following components connected to the I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 610 as needed so that computer programs read from it can be installed into the storage section 608 as needed.

[0137] This disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of this disclosure.

[0138] According to embodiments of this disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this disclosure, the computer-readable storage medium may include ROM 602 and / or RAM 603 and / or one or more memories other than ROM 602 and RAM 603 described above.

[0139] The embodiments of the present disclosure also include a computer program product, which includes a computer program containing program code for executing the method shown in the flowchart. When the computer program product is run in a computer system, the program code is used to enable the computer system to implement the method provided by the embodiments of the present disclosure.

[0140] When the computer program is executed by the processor 601, it performs the functions defined in the system / apparatus of this disclosure embodiments. According to embodiments of this disclosure, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0141] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via the communication section 609, and / or installed from the removable medium 611. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0142] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 609, and / or installed from the removable medium 611. When the computer program is executed by the processor 601, it performs the functions defined in the system of this disclosure embodiment. According to embodiments of this disclosure, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0143] According to embodiments of this disclosure, program code for executing the computer programs provided in embodiments of this disclosure can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can execute entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0144] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0145] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0146] The embodiments of this disclosure have now been described in detail with reference to the accompanying drawings.

[0147] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. An operational method for an in-memory computing architecture applied to neural networks, wherein, include: Generate a single-pulse input signal based on discrete-time coding; The single-pulse input signal is input into the memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array; as well as The neuron circuit controlling the in-memory computing architecture outputs a single-pulse output signal based on discrete-time encoding according to the bit line current signal. The single-pulse output signal serves as the single-pulse input signal of the memory array of the next layer of the neural network in the next in-memory computing cycle. The single-pulse signal generated by discrete-time encoding includes: The extracted neural network input vector signal is quantized to generate the corresponding quantized input signal; The quantized input signal is encoded according to a preset discrete delay time encoding rule to generate a single pulse input signal based on discrete time encoding; Specifically, before inputting the single-pulse input signal into the memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array, the method further includes: Mapping the weight matrix corresponding to the extracted neural network input vector signal to each memory cell of the memory array includes: The weight matrix is ​​mapped, according to its weight sign, to the conductance values ​​of two adjacent columns representing positive and negative values ​​in the memory array; and The weight difference between two adjacent columns is mapped to the conductance values ​​of the two adjacent columns in the memory array, representing positive and negative values ​​respectively, according to the sign of the weight difference. The weight difference is the difference between the sum of the weights of the adjacent negative columns and the sum of the weights of the positive columns.

2. The operating method according to claim 1, wherein, The preset discrete delay time encoding rule is a rule that encodes the single pulse as the single pulse input signal based on the delay time between the start time of the enable signal corresponding to the in-memory calculation cycle and the arrival time of the single pulse of the single pulse input signal in response to the enable signal, wherein the length of the delay time is the magnitude of the quantized input signal.

3. The method according to claim 1, wherein, The process of inputting the single-pulse input signal into the memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array includes: The single-pulse input signal is input into the memory array of the in-memory computing architecture; The memory array that completes the weight matrix mapping performs a multiply-accumulate operation based on the input single-pulse input signal to generate a bit line current signal.

4. The method according to claim 1, wherein, The neuron circuit controlling the in-memory computing architecture outputs a single-pulse output signal based on discrete-time encoding according to the bit line current signal, including: In response to the bit line current signal, the opening and closing states of the first and second switching transistors of the neuron circuit are controlled, so that the neuron circuit outputs the single pulse output signal in response to the opening and closing state.

5. The method according to claim 4, wherein, Before controlling the on / off states of the first and second switching transistors of the neuron circuit in response to the bit line current signal, so that the neuron circuit outputs the single-pulse output signal in response to the on / off state, the method further includes: The control state is such that the first switching transistor is on and the second switching transistor is off, and the pre-charge capacitor voltage of the neuron circuit is realized in response to the on / off state.

6. The method according to claim 5, wherein, The process of controlling the on / off states of the first and second switching transistors of the neuron circuit in response to the bit line current signal, so that the neuron circuit outputs the single-pulse output signal in response to the on / off state, includes: The control state is such that both the first and second switching transistors are off. In response to the on / off state and the bit line current signal, the neuron circuit generates a first capacitor voltage based on the bit line current signal and the pre-charge capacitor voltage. The control state is such that the first switching transistor is off and the second switching transistor is on, and the first capacitor voltage is encoded and output as a single pulse output signal with discrete delay time.

7. An operating device for an in-memory computing architecture applied to neural networks, wherein, include: The input signal generation module is used to generate a single-pulse input signal based on discrete-time coding. The bit line signal generation module is used to input the single pulse input signal into the memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array. as well as The control output module is used to control the neuron circuit of the in-memory computing architecture to output a single pulse output signal based on discrete time encoding according to the bit line current signal. The single pulse output signal serves as the single pulse input signal of the memory array of the next layer of the neural network in the next in-memory computing cycle. The input signal generation module is further used for: The extracted neural network input vector signal is quantized to generate the corresponding quantized input signal; The quantized input signal is encoded according to a preset discrete delay time encoding rule to generate a single pulse input signal based on discrete time encoding; The bit line signal generation module is further used for: Mapping the weight matrix corresponding to the extracted neural network input vector signal to each memory cell of the memory array includes: The weight matrix is ​​mapped, according to its weight sign, to the conductance values ​​of two adjacent columns representing positive and negative values ​​in the memory array; and The weight difference between two adjacent columns is mapped to the conductance values ​​of the two adjacent columns in the memory array, representing positive and negative values ​​respectively, according to the sign of the weight difference. The weight difference is the difference between the sum of the weights of the adjacent negative columns and the sum of the weights of the positive columns.

8. An electronic device, wherein, include: One or more processors; Storage device for storing one or more programs. Wherein, when the one or more programs are executed by the one or more processors, the one or more processors perform the method according to any one of claims 1 to 6.

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