Pixel driving circuit and display panel

Abstract

The application provides a pixel driving circuit and a display panel, which comprise: a driving transistor, which is connected in series between a first power supply line and a second power supply line and has a source electrode electrically connected to a light-emitting element; a data transistor, which has a source electrode electrically connected to a data line, a drain electrode electrically connected to a gate electrode of the driving transistor, and a gate electrode loaded with a data control signal; and a voltage boosting module, which has an input end for loading a voltage boosting input signal and an output end electrically connected to the gate electrode of the driving transistor; wherein the voltage boosting module is arranged to be in a second stage after a first stage, so that the gate electrode of the driving transistor has a second voltage greater than a first voltage, and a connection point between a first capacitor and a second capacitor is connected to the gate electrode of the driving transistor, so as to increase a driving current flowing through the light-emitting element, improve the luminous brightness of the light-emitting element, and improve the brightness of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to the technical field of display panel manufacturing, and specifically to a pixel driving circuit and a display panel. BACKGROUND

[0002] Compared with liquid crystal displays, self-luminous displays have the advantages of high color gamut, high contrast, short response time, and bendability, and are recognized by the industry as having great development potential in the field of new generation displays.

[0003] At present, the light emitting elements in the self-luminous display are all current-driven, that is, the luminance of the light emitting element depends on the current flowing through the light emitting element. Among them, the luminance of the light emitting element is generally adjusted by adjusting the size of the data voltage after the panel is produced, and the gate-source voltage of the driving transistor does not change in the light emitting stage, that is, the luminance of the light emitting element cannot be changed. However, due to the influence of the hardware of the data driving chip, and considering the influence of threshold voltage and picture uniformity compensation, the gate-source voltage of the driving transistor in the light emitting stage is small, so that the current flowing through the light emitting element is small, resulting in low luminance of the light emitting element and the self-luminous display formed thereby.

[0004] Therefore, the existing self-luminous display has low luminance due to the influence of the hardware of the data driving chip, and needs to be improved. SUMMARY

[0005] The embodiments of the present application provide a pixel driving circuit and a display panel to solve the technical problem of low luminance of the existing self-luminous display due to the influence of the hardware of the data driving chip.

[0006] The pixel driving circuit provided by the embodiments of the present application comprises:

[0007] A driving transistor is connected in series between the first power supply line and the second power supply line, and the source electrode of the driving transistor is electrically connected to the light emitting element;

[0008] A data transistor, the source electrode of the data transistor is electrically connected to the data line, the drain electrode of the data transistor is electrically connected to the gate electrode of the driving transistor, and the gate electrode of the data transistor is loaded with a data control signal;

[0009] A boost module, the input end of the boost module is used to load a boost input signal, and the output end of the boost module is electrically connected to the gate electrode of the driving transistor;

[0010] The voltage boosting module controls the gate of the driving transistor to rise from a first voltage in a first stage to a second voltage in a second stage, the second stage being subsequent to the first stage, and the driving transistor is configured to generate a driving current according to at least the second voltage to drive the light emitting element to emit light.

[0011] The voltage boosting module comprises:

[0012] A first capacitor, a first plate of the first capacitor being electrically connected to the input terminal of the voltage boosting module to load the voltage boosting input signal, and a second plate of the first capacitor being electrically connected to the gate of the driving transistor.

[0013] A second capacitor, a first plate of the second capacitor being electrically connected to the gate of the driving transistor to serve as the output terminal of the voltage boosting module, and a second plate of the second capacitor loading a first signal.

[0014] In an embodiment, the voltage boosting module further comprises:

[0015] A voltage boosting sub-module, an input terminal of the voltage boosting sub-module being configured as the input terminal of the voltage boosting module, and the first plate of the first capacitor being electrically connected to an output terminal of the voltage boosting sub-module.

[0016] In an embodiment, the voltage boosting sub-module comprises:

[0017] A first voltage boosting transistor, a drain of the first voltage boosting transistor being electrically connected to the first plate of the first capacitor to serve as the output terminal of the voltage boosting sub-module, a source of the first voltage boosting transistor being electrically connected to the input terminal of the voltage boosting module, and a gate of the first voltage boosting transistor loading a first voltage boosting control signal, the first voltage boosting transistor being turned on in both the first stage and the second stage.

[0018] The voltage boosting input signal has a first voltage boosting input voltage in the first stage, and has a second voltage boosting input voltage in the second stage, the second voltage boosting input voltage being greater than the first voltage boosting input voltage.

[0019] In an embodiment, the voltage boosting sub-module further comprises:

[0020] A second voltage boosting transistor, a drain of the second voltage boosting transistor being electrically connected to the source of the first voltage boosting transistor, a source of the second voltage boosting transistor being electrically connected to the input terminal of the voltage boosting module, and a gate of the second voltage boosting transistor loading a second voltage boosting control signal.

[0021] The gate of the first boost transistor is electrically connected to the gate of the driving transistor, and the second boost transistor is turned on in the first stage and the second stage.

[0022] In an embodiment, the first signal maintains a constant voltage in the first stage and the second stage.

[0023] In an embodiment, the second plate of the first capacitor is electrically connected to the source of the driving transistor or the drain of the driving transistor.

[0024] In an embodiment, the second plate of the second capacitor is electrically connected to the drain of the driving transistor, and the boost module further comprises:

[0025] a third capacitor;

[0026] a boost switch connected in series between the gate of the driving transistor and the source of the driving transistor;

[0027] In the first stage and a third stage before the first stage, the boost switch is turned on to control the gate of the driving transistor to rise from a third voltage of the third stage to the first voltage of the first stage.

[0028] In an embodiment, the display panel further comprises:

[0029] a reset transistor, a source of the reset transistor being electrically connected to a reset line, a drain of the reset transistor being electrically connected to the source of the driving transistor, and a gate of the reset transistor being loaded with a reset control signal.

[0030] In an embodiment, the capacitance of the first capacitor is greater than the capacitance of the second capacitor.

[0031] The display panel provided by the embodiments of the present application comprises a plurality of pixel driving circuits as described in any of the above embodiments.

[0032] In an embodiment, the display panel further comprises:

[0033] a data generation chip located on at least one side of the plurality of pixel driving circuits, and a plurality of data lines being electrically connected to the data generation chip to obtain data signals.

[0034] In an embodiment, the pixel driving circuits far away from the data generation chip have a greater absolute value of voltage of the corresponding data signals than the pixel driving circuits close to the data generation chip.

[0035] In an embodiment, the display panel further comprises:

[0036] A signal generation chip is located at at least one side of the plurality of pixel driving circuits, and input ends of the plurality of voltage boosting modules are electrically connected to the signal generation chip to obtain the voltage boosting input signal.

[0037] The voltage boosting input signal has a first voltage boosting input voltage in the first stage, and has a second voltage boosting input voltage in the second stage, the second voltage boosting input voltage being greater than the first voltage boosting input voltage.

[0038] The difference between the corresponding second voltage boosting input voltage and the corresponding first voltage boosting input voltage is greater for the pixel driving circuit far away from the data generation chip than for the pixel driving circuit close to the data generation chip.

[0039] The embodiment of the present application also provides a display panel, comprising a pixel driving circuit, the pixel driving circuit comprising:

[0040] A first transistor is connected in series between a first power supply line and a second power supply line and a light emitting element, and a source of the first transistor is electrically connected to the light emitting element.

[0041] A second transistor, a source of the second transistor is electrically connected to a first signal line, a drain of the second transistor is electrically connected to the gate of the first transistor, and a gate of the second transistor is electrically connected to a second signal line.

[0042] A first module, an input end of the first module is electrically connected to a third signal line, an output end of the first module is electrically connected to the gate of the first transistor, and a control end of the voltage boosting module is electrically connected to a fourth signal line.

[0043] The first module comprises:

[0044] A first capacitor, a first plate of the first capacitor is electrically connected to the input end of the first module, and a second plate of the first capacitor is electrically connected to the gate of the first transistor.

[0045] A second capacitor, a first plate of the second capacitor is electrically connected to the gate of the first transistor as the output end of the first module, and a second plate of the second capacitor is electrically connected to the source or drain of the first transistor.

[0046] In an embodiment, the first module further comprises:

[0047] A first sub-module, an input end of the first sub-module is configured as the input end of the first module, and a first plate of the first capacitor is electrically connected to an output end of the first module.

[0048] In an embodiment, the first sub-module comprises:

[0049] a third transistor, a drain of the third transistor is electrically connected to the first plate of the first capacitor as the output terminal of the first sub-module, a source of the third transistor is electrically connected to the input terminal of the first module, and a gate of the third transistor is electrically connected to a fifth signal line.

[0050] In an embodiment, the first sub-module further comprises:

[0051] a fourth transistor, a drain of the fourth transistor is electrically connected to the source of the third transistor, a source of the fourth transistor is electrically connected to the input terminal of the first module, and a gate of the fourth transistor is electrically connected to a sixth signal line different from the gate of the first transistor.

[0052] wherein the gate of the third transistor is electrically connected to the gate of the first transistor.

[0053] In an embodiment, a second plate of the second capacitor is electrically connected to the drain of the first transistor, and the first module further comprises:

[0054] a third capacitor;

[0055] a first switch connected in series between the gate of the first transistor and the source of the first transistor and the third capacitor.

[0056] wherein the first switch is configured to control the third capacitor to be electrically connected between the gate of the first transistor and the source of the first transistor.

[0057] In an embodiment, the first module further comprises:

[0058] a fifth transistor, a source of the fifth transistor is electrically connected to a seventh signal line, a drain of the fifth transistor is electrically connected to the source of the first transistor, and a gate of the fifth transistor is electrically connected to an eighth signal line.

[0059] The application provides a pixel driving circuit and a display panel, the pixel driving circuit comprises: a driving transistor, which is connected in series between a first power supply line and a second power supply line, and a light emitting element, a source electrode of the driving transistor is electrically connected to the light emitting element; a data transistor, a source electrode of the data transistor is electrically connected to a data line, a drain electrode of the data transistor is electrically connected to a gate electrode of the driving transistor, and a gate electrode of the data transistor is loaded with a data control signal; a voltage boosting module, an input end of the voltage boosting module is used for loading a voltage boosting input signal, and an output end of the voltage boosting module is electrically connected to the gate electrode of the driving transistor; wherein the voltage boosting module controls the gate electrode of the driving transistor to rise from a first voltage of a first stage to a second voltage of a second stage, the second stage is located after the first stage, and the driving transistor is used for generating a driving current according to at least the second voltage to drive the light emitting element to emit light; wherein the voltage boosting module comprises: a first capacitor, a first plate of the first capacitor is electrically connected to the input end of the voltage boosting module to load the voltage boosting input signal, and a second plate of the first capacitor is electrically connected to the gate electrode of the driving transistor; and a second capacitor, a first plate of the second capacitor is electrically connected to the gate electrode of the driving transistor to serve as the output end of the voltage boosting module, and a second plate of the second capacitor is loaded with a first signal. Wherein, the application is provided with the voltage boosting module whose input end is loaded with the voltage boosting input signal, and the output end of the voltage boosting module is electrically connected to the gate electrode of the driving transistor, and the voltage boosting module is combined with the voltage division of the first capacitor and the second capacitor, so that the gate voltage of the driving transistor is modulated to rise from the first voltage to the second voltage, thereby increasing the driving current flowing through the light emitting element, improving the light emitting brightness of the light emitting element, and improving the brightness of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0060] The application will be further described below with reference to the drawings. It should be noted that the drawings in the following description are only used to explain some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of the drawings.

[0061] Figure 1 A circuit diagram of a first pixel driving circuit provided by an embodiment of the application.

[0062] Figure 2 A circuit diagram of a second pixel driving circuit provided by an embodiment of the application.

[0063] Figure 3 A circuit diagram of a third pixel driving circuit provided by an embodiment of the application.

[0064] Figure 4 A circuit diagram of a fourth pixel driving circuit provided by an embodiment of the application.

[0065] Figure 5 A circuit diagram of a fifth pixel driving circuit provided by an embodiment of the present application.

[0066] Figure 6 A circuit diagram of a sixth pixel driving circuit provided by an embodiment of the present application.

[0067] Figure 7 A circuit diagram of a seventh pixel driving circuit provided by an embodiment of the present application.

[0068] Figure 8 A circuit diagram of an eighth pixel driving circuit provided by an embodiment of the present application.

[0069] Figure 9 A circuit diagram of a ninth pixel driving circuit provided by an embodiment of the present application.

[0070] Figure 10 A waveform diagram of partial signals provided by an embodiment of the present application. DETAILED DESCRIPTION

[0071] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0072] The terms "first", "second", "third" and the like in the present application are used to distinguish different objects, but are not used to describe a particular order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but can optionally include other steps or modules not listed, or can optionally include other steps or modules inherent to the process, method, product or device. In addition, the terms "source" and "drain" can be called interchangeably, as long as the corresponding transistor has at least one source and at least one drain.

[0073] In this document, the term "embodiment" means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears at various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0074] The embodiments of the present application provide pixel driving circuits, including but not limited to the following embodiments and combinations of the following embodiments.

[0075] In an embodiment, as shown in Figures 1 to 9 The pixel driving circuit 100 includes a driving transistor T1, a light emitting element L connected in series between a first power supply line and a second power supply line, a source S of the driving transistor T1 electrically connected to the light emitting element L, a data transistor T4, a source of the data transistor T4 electrically connected to a data line, a drain of the data transistor T4 electrically connected to the gate G of the driving transistor T1, and a gate of the data transistor T4 loaded with a data control signal Scan, a boost module 10, an input of the boost module 10 loaded with a boost input signal CK, and an output of the boost module 10 electrically connected to the gate G of the driving transistor T1. The boost module 10 controls the gate G of the driving transistor T1 to rise from a first voltage Vg1 of a first stage to a second voltage Vg2 of a second stage, the second stage being located after the first stage, and the driving transistor T1 is configured to generate a driving current according to at least the second voltage Vg2 to drive the light emitting element L to emit light. The boost module 10 includes a first capacitor C1, a first plate of the first capacitor C1 electrically connected to the input of the boost module 10 to load the boost input signal CK, a second capacitor C2, a second plate of the first capacitor C1 and a first plate of the second capacitor C2 electrically connected to the gate G of the driving transistor T1 to serve as the output of the boost module 10, and a second plate of the second capacitor C2 loaded with a first signal.

[0076] In an embodiment, as shown in Figures 1 to 9 The first power supply line can be loaded with a first power supply signal VSS, and the second power supply line can be loaded with a second power supply signal VDD. The voltage of the first power supply signal VSS and the voltage of the second power supply signal VDD can be two constant voltage values respectively, and the voltage value corresponding to the first power supply signal VSS can be less than the voltage value corresponding to the second power supply signal VDD. The driving transistor T1 can be an N-type transistor or a P-type transistor, and the light emitting element L can be, but is not limited to, an organic light emitting semiconductor, a light emitting diode, a micro light emitting diode, or a sub-millimeter light emitting diode.

[0077] Specifically, as shown in Figures 1 to 6As shown, here taking the driving transistor T1 as an N-type transistor as an example for illustration, in combination with the foregoing description, the drain D of the driving transistor T1 can be electrically connected to the second power supply line to be loaded with the second power supply signal VDD, the source S of the driving transistor T1 can be electrically connected to the anode of the light emitting element L, and the cathode of the light emitting element L can be electrically connected to the first power supply line to be loaded with the first power supply signal VSS, for example, the voltage value corresponding to the first power supply signal VSS can be 0 volt, that is, the cathode of the light emitting element L can be grounded. Specifically, the gate-source voltage Vgs between the gate G of the driving transistor T1 and the source S of the driving transistor T1 drives the light emitting element L to emit light, and when the driving transistor T1 is turned on, a driving current flowing to the light emitting element L can be generated under the action of the first power supply signal VSS and the second power supply signal VDD, wherein the size of the driving current is positively correlated with the gate-source voltage Vgs between the gate G of the driving transistor T1 and the source S of the driving transistor T1, and the voltage loaded to the gate G of the driving transistor T1 can be generally determined according to the voltage value corresponding to the expected gray scale of the light emitting element L, that is, it can be considered that the voltage value corresponding to the expected gray scale of the light emitting element L determines the size of the driving current flowing to the light emitting element L, thereby determining the luminance of the light emitting element L.

[0078] It should be noted that when the pixel driving circuit 100 is in the light emitting stage, due to the relatively stable voltage drop of the light emitting element L, the source voltage Vs of the source S of the driving transistor T1 can be a relatively stable value, that is, it can be considered that the luminance of the light emitting element L at this time can be determined by the gate voltage Vg of the gate G of the driving transistor T1. In combination with the foregoing description, it can be known that the gate voltage Vg loaded to the gate G of the driving transistor T1 can be generally determined according to the voltage value corresponding to the expected gray scale of the light emitting element L, however, limited by the hardware of the data driving chip, and considering the influence of threshold voltage and picture uniformity compensation, the voltage loaded to the gate G of the driving transistor T1 according to the voltage value corresponding to the expected gray scale of the light emitting element L is actually smaller, so that the driving current flowing through the light emitting element L is smaller, causing the luminance of the light emitting element L to be lower.

[0079] It can be understood that, in the embodiment, the boosting module 10 is arranged, and the input end of the boosting module 10 is loaded with the boosting input signal CK, and the output end of the boosting module 10 is electrically connected to the gate G of the driving transistor T1. Compared with the above description, that is, the gate voltage Vg of the gate G of the driving transistor T1 can also be determined by the boosting input signal CK. In the first stage, the gate G of the driving transistor T1 has a first voltage Vg1. In combination with the above description, the first stage can be considered as the “light-emitting stage” mentioned above, and the first voltage Vg1 can be determined by at least the voltage loaded to the gate G of the driving transistor T1 according to the voltage value corresponding to the expected gray scale of the light-emitting element L, and the first voltage Vg1 makes the gate-source voltage Vgs of the driving transistor T1 drive the light-emitting element L to emit light at a first brightness. The “voltage value corresponding to the expected gray scale of the light-emitting element L” can be understood as the data signal transmitted by the corresponding data line above. Further, in the embodiment, the boosting module 10 is arranged to have a second voltage Vg2 related to the boosting input signal CK in the second stage, and the second voltage Vg2 is greater than the first voltage Vg1. The second stage can be understood as a “brightness increasing stage” after the first stage (light-emitting stage). That is, the gate voltage Vg of the driving transistor T1 can rise from the first voltage Vg1 to the second voltage Vg2 under the action of the boosting module 10 and the boosting input signal CK, so as to increase the driving current flowing through the light-emitting element L. The second voltage Vg2 makes the gate-source voltage Vgs of the driving transistor T1 drive the light-emitting element L to emit light at a second brightness greater than the first brightness, so as to improve the light-emitting brightness of the light-emitting element L. The specific structure of the boosting module 10 and the waveform of the boosting input signal CK can be reasonably set according to actual conditions, so as to better improve the light-emitting brightness of the light-emitting element L.

[0080] Specifically, the second plate of the second capacitor C2 can be electrically connected to the first wire to load the first signal. For example, in combination with the first capacitor C1 and the second capacitor C2, the boosting input signal CK can be reasonably set to meet the requirement that the gate of the driving transistor rises from the first voltage in the first stage to the second voltage in the second stage. Figures 1 to 9As shown, the boost module 10 further comprises a boost sub-module 101, an input end of the boost sub-module 101 is configured as the input end of the boost module 10, and the input end of the boost sub-module 101 can load a boost input signal CK, so that the node A (i.e. the output end of the boost sub-module 101) has a signal related to the boost input signal CK; further, due to the series connection of the first capacitor C1 and the second capacitor C2, and the second plate of the first capacitor C1 and the first plate of the second capacitor C2 are both electrically connected to the gate G of the driving transistor T1, and the second plate of the second capacitor C2 is electrically connected to the first wire to load the first signal, i.e. the first capacitor C1 and the second capacitor C2 can share the voltage difference between the first wire and the node A, so that the gate G of the driving transistor T1 has a voltage value related to the voltage difference between the first wire and the node A, i.e. through the action of the boost module 10 and the boost input signal CK, the gate voltage Vg of the driving transistor T1 rises from the first voltage Vg1 to the second voltage Vg2.

[0081] In an embodiment, as shown in Figures 2 to 9 The boost sub-module 101 comprises: a first boost transistor T2, a drain of the first boost transistor T2 is electrically connected to the first plate of the first capacitor C1 as the output end of the boost sub-module 101, a source of the first boost transistor T2 is electrically connected to the input end of the boost module 10, and a gate of the first boost transistor T2 loads a first boost control signal, the first boost transistor T2 is turned on in the first phase and the second phase; wherein the boost input signal CK has a first boost input voltage Vcl in the first phase, and the boost input signal CK has a second boost input voltage Vch in the second phase, the second boost input voltage is greater than the first boost input voltage.

[0082] The first boost transistor T2 can be an N-type transistor or a P-type transistor, and here the first boost transistor T2 is taken as an N-type transistor as an example for illustration. Specifically, as shown in Figure 2As shown, the gate of the first boost transistor T2 can be electrically connected to the gate G of the driving transistor T1 to obtain the gate voltage Vg of the gate G of the driving transistor T1 as the first boost control signal. As discussed above, in the first stage, i.e. in the light emitting stage, the gate voltage Vg of the gate G of the driving transistor T1 has a larger first voltage Vg1 to turn on the driving transistor T1, which can also be considered to turn on the first boost transistor T2 at the same time, so that the boost input signal CK is loaded to the second plate of the first capacitor C1 through the first boost transistor T2 to make the voltage of the node A equal to the first boost input voltage Vcl. In the second stage, the first boost transistor T2 can still be driven by the gate voltage Vg of the gate G of the driving transistor T1 to turn on at the initial moment, so that the boost input signal CK is loaded to the second plate of the first capacitor C1 through the first boost transistor T2 to make the voltage of the node A equal to the second boost input voltage Vch, i.e. the change value ΔVa of the voltage of the node A can be positively correlated with (Vch-Vcl), or even equal to (Vch-Vcl). When the change of the first signal on the first wire is not considered, since the voltage difference between the first electrode of the first capacitor C1 and the second electrode of the second capacitor C2 cannot be abruptly changed, the change value of the gate voltage Vg of the gate G of the driving transistor T1 electrically connected to the second plate of the first capacitor C1 is also positively correlated with (Vch-Vcl), or even equal to (Vch-Vcl), so that the gate voltage Vg of the gate G of the driving transistor T1 rises from the first voltage Vg1 to the second voltage Vg2, thereby increasing the driving current flowing through the light emitting element L to improve the light emitting brightness of the light emitting element L.

[0083] Of course, as Figure 3 shown, the gate of the first boost transistor T2 can also be electrically connected to the boost control line to be loaded with the first boost control signal, which can be but is not limited to the light emitting control signal EM. The waveform of the signal transmitted on the boost control line can be the same as or different from the waveform of the gate voltage Vg of the gate G of the driving transistor T1, as long as the first boost transistor T2 can be controlled to be turned on in the first stage and the second stage. The specific principle of the gate voltage Vg of the gate G of the driving transistor T1 can be the same as the principle of the gate voltage Vg of the gate G of the driving transistor T1 in the above “the gate of the first boost transistor T2 can be electrically connected to the gate G of the driving transistor T1”.

[0084] In particular, for example, when the voltage value of the boost input signal CK remains unchanged, i.e. the voltage of the node A remains unchanged, the gate G of the driving transistor T1 is switched from being loaded with the first voltage Vg1 to being in a suspended state, since the voltage difference between the two ends of the first capacitor C1 cannot be abruptly changed, the gate voltage Vg of the gate G of the driving transistor T1 also does not change.

[0085] Specifically, the voltage value of the first signal in the first time period is the same as that in the second time period. In combination with the above description, in the first time period to the second time period, the voltage value corresponding to the boost input signal CK rises from the first boost input voltage Vcl to the second boost input voltage Vch. Due to the voltage division of the first capacitor C1 and the second capacitor C2, the gate voltage Vg of the gate G of the driving transistor T1 can rise by ΔVa*C1 / (C1+C2), that is, the gate voltage Vg of the driving transistor T1 rises from the first voltage Vg1 to the second voltage Vg2 through the action of the boost module 10 and the boost input signal CK, thereby increasing the driving current flowing through the light emitting element L to improve the luminous brightness of the light emitting element L. The specific structure and parameters of the boost module 10 and the waveform of the boost input signal CK can be reasonably set according to actual conditions to better improve the luminous brightness of the light emitting element L.

[0086] Further, as shown in Figure 4 , the first trace can be connected to the source S of the driving transistor T1 (that is, the second plate of the second capacitor C2 is electrically connected to the source S of the driving transistor T1), or as shown in Figure 5 , the first trace can also be connected to the drain D of the driving transistor T1 (that is, the second plate of the second capacitor C2 is electrically connected to the drain D of the driving transistor T1) to keep the voltage of the first signal constant in the first stage and the second stage. Specifically, as shown in Figure 4 , the light emitting element L is in a light emitting state in the first stage and the second stage, and based on the first power signal VSS being a constant voltage signal, it can be considered that the source S of the driving transistor T1 has a relatively stable voltage (that is, the sum of the voltage value corresponding to the first power signal VSS and the voltage drop of the light emitting element L), and it can be approximately considered that the voltage on the first trace is constant; as shown in Figure 5 , based on the second power signal VDD being a constant voltage signal, it can be considered that the drain D of the driving transistor T1 has a relatively stable voltage, and it can be approximately considered that the voltage on the first trace is constant, which is approximately the voltage corresponding to the second power signal VDD. Of course, the first trace can also be directly connected to other traces or signal sources to load corresponding voltage signals or even constant voltage signals.

[0087] In combination with the above analysis, the first signal can also have different voltages in the first stage and the second stage, for example, when the voltage value of the first signal in the second stage is greater than the voltage value in the first stage, the absolute value of the change value of the voltage of the first signal acting on the gate G of the driving transistor T1 in the first stage and the second stage needs to be less than the absolute value of the change value of the voltage of the boost input signal CK acting on the gate G of the driving transistor T1 from the first stage to the second stage (i.e. ΔVa*C1 / (C1+C2)), and for example, when the voltage value of the first signal in the second stage is less than the voltage value in the first stage, ΔVa*C1 / (C1+C2) can be less than or even equal to 0.

[0088] In an embodiment, as shown in Figure 6 The boost submodule 101 further includes a second boost transistor T3, the drain of the second boost transistor T3 is electrically connected to the source of the first boost transistor T2, the source of the second boost transistor T3 is electrically connected to the input end of the boost module 10, and the gate of the second boost transistor T3 is loaded with a second boost control signal; wherein the gate of the first boost transistor T2 is electrically connected to the gate of the driving transistor T1, and the second boost transistor T3 is turned on in the first stage and the second stage.

[0089] Specifically, in combination with the above discussion, based on the embodiment that the gate of the first boost transistor T2 can be electrically connected to the gate G of the driving transistor T1 to obtain the gate voltage Vg of the gate G of the driving transistor T1 as the first boost control signal, this embodiment is equivalent to adding a second boost transistor T3 controlled by a second boost control signal in series between the input end of the boost module 10 and the source of the first boost transistor T2, that is, it can be considered that the first boost control signal and the second boost control signal jointly determine whether the boost input signal CK can be loaded to the node A, wherein the second boost control signal can be but is not limited to the light emission control signal EM. In combination with the above discussion, that is, on the basis of controlling the first boost transistor T2 to be turned on in the first stage and the second stage by the first boost control signal, the newly added second boost control signal and the second boost transistor T3 in this embodiment can also realize further control of whether the boost input signal CK can be loaded to the node A, thereby improving the accuracy of the operation of the boost module 10.

[0090] In an embodiment, as shown in Figure 7As shown, the first trace is different from the source S of the driving transistor T1, for example, the second plate of the second capacitor C2 is electrically connected to the drain D of the driving transistor T1, and the boost module 10 further comprises: a third capacitor C3; a boost switch K, which is connected in series with the third capacitor C3 between the gate G of the driving transistor T1 and the source S of the driving transistor T1; wherein, in the first stage and a third stage before the first stage, the boost switch K is turned on to control the gate G of the driving transistor T1 to rise from a third voltage of the third stage to the first voltage of the first stage.

[0091] Similarly, in combination with the above discussion, in the first stage, the gate G of the driving transistor T1 has a first voltage Vg1, which can be considered as the "light-emitting stage" mentioned above, and the first voltage Vg1 can be determined by the voltage loaded to the gate G of the driving transistor T1 according to the voltage value corresponding to the expected gray scale of the light-emitting element L. Specifically, in this embodiment, the boost module 10 is further configured to have a third voltage Vg3 at the gate G of the driving transistor T1 in the third stage, which can be understood as a data writing stage before the light-emitting stage, that is, the third voltage Vg3 can be equal to the voltage loaded to the gate G of the driving transistor T1 according to the voltage value corresponding to the expected gray scale of the light-emitting element L, and at this time, the source S of the driving transistor T1 has a lower voltage. Further, in combination with the above discussion, in the light-emitting stage after the third stage, since the light-emitting element L is turned on, the voltage of the source S of the driving transistor T1 is increased, and since the voltage difference across the third capacitor C3 cannot be abruptly changed, the gate voltage Vg of the gate G of the driving transistor T1 can also be increased from the third voltage Vg3 to the first voltage Vg1 to increase the gate-source voltage Vgs of the driving transistor T1, thereby increasing the driving current flowing through the light-emitting element L to improve the luminance of the light-emitting element L.

[0092] Therefore, under the condition that the third voltage Vg3 is constant, the change amount of the gate voltage Vg of the gate G of the driving transistor T1 is related to the voltage of the source S of the driving transistor T1, specifically, the difference between the voltage of the source S of the driving transistor T1 in the third stage and the first stage. It should be noted that, in combination with the above discussion, the boost switch K in this embodiment can at least satisfy the following conditions: being closed in the third stage and the first stage to electrically connect the third capacitor C3 between the gate G and the source S of the driving transistor T1, so that the gate voltage Vg of the gate G of the driving transistor T1 changes with the change of the source voltage Vs of the source S of the driving transistor T1; and being opened in the second stage to avoid the change of the gate voltage Vg of the gate G of the driving transistor T1 causing the source voltage Vs of the source S of the driving transistor T1 to change synchronously, so that the gate-source voltage Vgs cannot be increased, thereby failing to increase the driving current flowing through the light-emitting element L.

[0093] In an embodiment, as shown in FIG. 1, the pixel driving circuit 100 further comprises a reset transistor T5, a source electrode of the reset transistor T5 is electrically connected to a reset line, a drain electrode of the reset transistor T5 is electrically connected to the source electrode of the driving transistor T1, and a gate electrode of the reset transistor T5 is loaded with a reset control signal Sense Gate. Figure 8 and Figure 9 In an embodiment, as shown in FIG. 1, the pixel driving circuit 100 further comprises a reset transistor T5, a source electrode of the reset transistor T5 is electrically connected to a reset line, a drain electrode of the reset transistor T5 is electrically connected to the source electrode of the driving transistor T1, and a gate electrode of the reset transistor T5 is loaded with a reset control signal Sense Gate.

[0094] It should be noted that the pixel driving circuit 100 in the present application can comprise the boost module 10 and the driving transistor T1 as described above, and further can comprise a data writing module and a reset module electrically connected to the driving transistor T1, the data writing module can be electrically connected to one of the gate electrode G and the source electrode S of the driving transistor T1, and the reset module can be electrically connected to the other of the gate electrode G and the source electrode S of the driving transistor T1. Specifically, in the present embodiment, the data writing module is electrically connected to the gate electrode G of the driving transistor T1, the reset module is electrically connected to the source electrode S of the driving transistor T1, the data writing module comprises the data transistor T4 mentioned above, and the reset module comprises the reset transistor T5 mentioned above, that is, the present embodiment is described based on the pixel driving circuit 100 comprising the 3T1C circuit composed of the driving transistor T1, the data transistor T4, the reset transistor T5 and the second capacitor C2, of course, the circuit comprised by the pixel driving circuit 100 is not limited to the 3T1C circuit, for example, can also comprise a 6T1C circuit, a 7T1C circuit or other circuits.

[0095] It can be understood that, in combination with the above description, in the present embodiment, the data control signal Scan can at least control the data transistor T4 to be turned on in the third stage, so as to load the data signal Data on the data line to the gate electrode G of the driving transistor T1 to turn on the driving transistor T1, and the reset control signal Sense Gate can at least control the reset transistor T5 to be turned on in the stage before the third stage, so as to load the reset signal Vref on the reset line to the source electrode S of the driving transistor T1 to reset the source electrode S of the driving transistor T1.

[0096] In an embodiment, the first capacitor C1 has a capacitance value greater than that of the second capacitor C2. Specifically, in combination with the above discussion, since the first capacitor C1 and the second capacitor C2 are connected in series, and the second plate of the first capacitor C1 and the first plate of the second capacitor C2 are electrically connected to the gate G of the driving transistor T1, and the second plate of the second capacitor C2 is electrically connected to the first wire to load the first signal, further, based on the amount of change in the voltage corresponding to the first signal being less than the amount of change (greater than 0) in the voltage output by the output end of the boost sub-module 101 in the first stage to the second stage, the capacitance value of the first capacitor C1 can be set to be greater than that of the second capacitor C2, so that the voltage drop on the first capacitor C1 is greater than that on the second capacitor C2, so that the rising value of the gate voltage Vg of the driving transistor T1 can be greater, to further improve the driving current generated by the driving transistor T1.

[0097] The display panel provided by the embodiment of the present application comprises a pixel driving circuit, and the pixel driving circuit comprises: a first transistor connected in series between a first power supply line and a second power supply line and a light emitting element, wherein the source of the first transistor is electrically connected to the light emitting element; a second transistor, wherein the source of the second transistor is electrically connected to a first signal line, the drain of the second transistor is electrically connected to the gate of the first transistor, and the gate of the second transistor is electrically connected to a second signal line; a first module, wherein the input end of the first module is electrically connected to a third signal line, the output end of the first module is electrically connected to the gate of the first transistor, and the control end of the boost module is electrically connected to a fourth signal line; and the first module comprises: a first capacitor, wherein the first plate of the first capacitor is electrically connected to the input end of the first module; and a second capacitor, wherein the second plate of the first capacitor and the first plate of the second capacitor are electrically connected to the gate of the first transistor to serve as the output end of the first module, and the second plate of the second capacitor is electrically connected to the source or the drain of the first transistor.

[0098] Specifically, the first module can further comprise a first sub-module, the input end of the first sub-module is configured as the input end of the first module, and the first plate of the first capacitor is electrically connected to the output end of the first module. Further, in combination with the above discussion, the first sub-module can comprise: a third capacitor, wherein the first plate of the third capacitor is electrically connected to the input end of the first sub-module; and a fourth capacitor, wherein the second plate of the third capacitor and the first plate of the fourth capacitor are electrically connected to the gate of the first transistor to serve as the output end of the first sub-module, and the second plate of the fourth capacitor is electrically connected to the source or the drain of the first transistor. Figures 1 to 9As shown, the first transistor can refer to the above description about the driving transistor T1, the second transistor can refer to the above description about the data transistor T4, the first module can refer to the above description about the boosting module 10, the first sub-module can refer to the above description about the boosting sub-module 101, the first capacitor can refer to the above description about the first capacitor C1, the second capacitor can refer to the above description about the second capacitor C2, based on which, the first signal line can be the data line mentioned above, the second signal line can load the data control signal mentioned above, the third signal line can load the boosting input signal mentioned above, and the fourth signal line can load at least one of the first boosting control signal and the second boosting control signal mentioned above.

[0099] In an embodiment, the first sub-module comprises: a third transistor, a drain of the third transistor being electrically connected to the first plate of the first capacitor to serve as the output terminal of the first sub-module, a source of the third transistor being electrically connected to the input terminal of the first module, and a gate of the third transistor being electrically connected to a fifth signal line.

[0100] Further, in combination with Figures 1 to 9 As shown, the third transistor can refer to the above description about the first boosting transistor T2, and the fifth signal line can load the first boosting control signal mentioned above.

[0101] In an embodiment, the first sub-module further comprises: a fourth transistor, a drain of the fourth transistor being electrically connected to the source of the third transistor, a source of the fourth transistor being electrically connected to the input terminal of the first module, and a gate of the fourth transistor being electrically connected to a sixth signal line different from the gate of the first transistor; wherein the gate of the third transistor is electrically connected to the gate of the driving transistor.

[0102] Further, in combination with Figure 6 As shown, the fourth transistor can refer to the above description about the second boosting transistor T3, and the sixth signal line can load the second boosting control signal mentioned above.

[0103] In an embodiment, a second plate of the second capacitor is electrically connected to the drain of the driving transistor, and the first module further comprises: a third capacitor; and a first switch connected in series between the gate of the first transistor and the source of the first transistor; wherein the first switch is configured to control the third capacitor to be electrically connected between the gate of the first transistor and the source of the first transistor.

[0104] Further, in combination with Figure 7As shown, the third capacitor can refer to the above description about the third capacitor C3, and the first switch can refer to the above description about the boost switch K.

[0105] In an embodiment, further comprising: a fifth transistor, a source of the fifth transistor being electrically connected to a seventh signal line, a drain of the fifth transistor being electrically connected to the source of the first transistor, and a gate of the fifth transistor being electrically connected to an eighth signal line.

[0106] Further, in combination with Figure 8 and Figure 9 As shown, the fifth transistor can refer to the above description about the reset transistor T5, and the eighth signal line can load the reset control signal mentioned above.

[0107] Embodiments of the present application provide a driving method, in combination with Figures 1 to 9 As shown, for driving the pixel driving circuit 100 as described in any of the above, comprising: configuring the boost input signal CK according to the source voltage Vs of the source S of the driving transistor T1 in the first stage; controlling the gate G of the driving transistor T1 to have a second voltage Vg2 related to the boost input signal CK through the boost input signal CK and the boost module 10, the second voltage Vg2 being greater than a first voltage Vg1 that the gate of the driving transistor T1 has in the first stage.

[0108] Specifically, in combination with the above analysis, the size of the driving current flowing through the light emitting element L is positively correlated with the gate-source voltage Vgs between the gate G and the source S of the driving transistor T1, and the first stage is the light emitting stage, and in the process of subsequent light emitting of the light emitting element L, the source voltage Vs of the source S of the driving transistor T1 can be considered to be approximately equal to its voltage in the first stage, so in this embodiment, the boost input signal CK is configured according to the source voltage Vs of the source S of the driving transistor T1 in the first stage, which can make the second voltage Vg2 according to the source voltage Vs of the source S of the driving transistor T1, for example, the greater the source voltage Vs of the source S of the driving transistor T1, in the case of determining the first boost input voltage Vcl in the first stage in the corresponding boost input signal CK (for example, equal to 0), the second boost input voltage Vch of the boost input signal CK in the second stage can be set to be larger, so that the second voltage Vg2 of the gate G of the driving transistor T1 in the second stage is larger, thereby making the size of the gate-source voltage Vgs between the gate G and the source S of the driving transistor T1 in the second stage appropriate.

[0109] Specifically, here based on Figure 8 As shown in the circuit diagram, in combination with Figure 10The working process of the pixel driving circuit 100 can include, but is not limited to, the following stages according to the illustrated timing diagram.

[0110] In the reset stage t1, the data control signal Scan is equal to a corresponding high level to control the data transistor T4 to be turned on, the data signal Data on the data line is equal to a corresponding low level to be transmitted to the gate G of the driving transistor T1 through the data transistor T4 to reset the gate G of the driving transistor T1, meanwhile, the reset control signal Sense Gate is equal to a corresponding high level to control the reset transistor T5 to be turned on, and the reset signal Vref on the reset line is equal to a corresponding low level to be transmitted to the source S of the driving transistor T1 through the reset transistor T5 to reset the source S of the driving transistor T1;

[0111] In the data writing stage t2, the data control signal Scan is maintained at a corresponding high level to maintain the data transistor T4 to be turned on, the data signal Data on the data line is equal to a corresponding high level Vdata to be transmitted to the gate G of the driving transistor T1 through the data transistor T4, so that the gate voltage Vg of the gate G of the driving transistor T1 is equal to Vdata, and the second boost control signal (for example, the light-emitting control signal EM) is maintained at a corresponding high level, the boost input signal CK on the input end of the boost module 10 is equal to a corresponding low level Vcl to be transmitted to the node A through the first boost transistor T2, meanwhile, the reset control signal Sense Gate is maintained at a corresponding high level to maintain the reset transistor T5 to be turned on, the reset signal Vref on the reset line is equal to a corresponding low level to be transmitted to the source S of the driving transistor T1 through the reset transistor T5, and the light-emitting element L is kept off;

[0112] In the light emitting stage t3, the data control signal Scan is equal to the corresponding low potential to control the data transistor T4 to be closed, the reset control signal Sense Gate is equal to the corresponding low potential to control the reset transistor T5 to be closed, first, the gate voltage Vg of the gate G of the driving transistor T1 is still equal to Vdata at the initial moment, the reset transistor T5 is closed, the path formed by the first capacitor C1 keeps the gate voltage Vg of the driving transistor T1 still equal to Vdata to keep the driving transistor T1 still open, the second power signal VDD on the second power line is always equal to the corresponding high potential, the first power signal VSS on the first power line is always equal to the corresponding low potential, the light emitting element L is turned on, the driving current I flows through the light emitting element L at the first current value I1, the source voltage Vs of the source S of the driving transistor T1 is equal to the on voltage drop VL of the light emitting element L, and the second boost control signal (for example, the light emitting control signal EM) is still maintained at the corresponding high potential, so that the first boost transistor T2 is still maintained to be open, so that the boost input signal CK is equal to the corresponding low potential Vcl to be transmitted to the node A, further, since the voltage of the node A does not change, the source voltage Vs of the source S of the driving transistor T1 rises by Δs, and the gate voltage Vg of the gate G of the driving transistor T1 rises by ΔVs*C2 / (C1+C2) combined with the voltage division effect of the first capacitor C1 and the second capacitor C2.

[0113] In the light emitting stage t3, the data control signal Scan is equal to the corresponding low potential to control the data transistor T4 to be closed, the reset control signal Sense Gate is equal to the corresponding low potential to control the reset transistor T5 to be closed, first, the gate voltage Vg of the gate G of the driving transistor T1 is still equal to Vdata at the initial moment, the reset transistor T5 is closed, the path formed by the first capacitor C1 keeps the gate voltage Vg of the driving transistor T1 still equal to Vdata to keep the driving transistor T1 still open, the second power signal VDD on the second power line is always equal to the corresponding high potential, the first power signal VSS on the first power line is always equal to the corresponding low potential, the light emitting element L is turned on, the driving current I flows through the light emitting element L at the first current value I1, the source voltage Vs of the source S of the driving transistor T1 is equal to the on voltage drop VL of the light emitting element L, and the second boost control signal (for example, the light emitting control signal EM) is still maintained at the corresponding high potential, so that the first boost transistor T2 is still maintained to be open, so that the boost input signal CK is equal to the corresponding low potential Vcl to be transmitted to the node A, further, since the voltage of the node A does not change, the source voltage Vs of the source S of the driving transistor T1 rises by Δs, and the gate voltage Vg of the gate G of the driving transistor T1 rises by ΔVs*C2 / (C1+C2) combined with the voltage division effect of the first capacitor C1 and the second capacitor C2.

[0114] It can be understood that, in combination with the above description, the pixel driving circuit 100 has the "brightening stage" mentioned above by setting the boost module 10 and the corresponding boost input signal CK. Further, the first capacitor C1 and the second capacitor C2 are provided to divide the voltage, and the gate voltage Vg of the gate G of the driving transistor T1 is increased in the "brightening stage", so that the gate-source voltage Vgs between the gate G and the source S of the driving transistor T1 is increased, and thus the driving current I flowing through the light emitting element L is also increased, thereby increasing the luminous brightness of the light emitting element L, and thus the brightness of the display panel is increased.

[0115] It should be noted that after the brightening stage t4 of the current frame, even if the boost input signal CK maintains a corresponding high potential for a period of time to realize other functions for other devices loaded with the boost input signal CK, that is, to improve the multiplexing rate of the boost input signal CK, but the second boost control signal (such as the light emitting control signal EM) is equal to the corresponding low potential, which can control the second boost transistor T3 to be closed to make the node A suspended, so as to end the modulation of the gate voltage Vg of the gate G of the driving transistor T1. In addition, in combination with the above description, in the reset stage t1, the data writing stage t2 and the light emitting stage t3 in some frames, since the voltage of the node A does not need to change to modulate the gate voltage Vg of the gate G of the driving transistor T1, the second boost control signal (such as the light emitting control signal EM) can also be a corresponding low voltage in the reset stage t1 and the data writing stage t2 to control the second boost transistor T3 to be closed to save energy.

[0116] The display panel provided by the embodiment of the present application comprises a plurality of pixel driving circuits 100 as described in any of the above embodiments. Figures 1 to 9 As shown in the figure, the display panel comprises a plurality of pixel driving circuits 100 as described in any of the above embodiments. Specifically, the display panel can comprise a display area and a non-display area surrounding the display area, and a plurality of pixel driving circuits 100 can be arranged in the display area, and further, at least part of the pixel driving circuits 100 can be arranged in an array.

[0117] In an embodiment, in combination with the above description, the display panel further comprises a data generating chip located on at least one side of the plurality of pixel driving circuits 100, and a plurality of data lines are electrically connected to the data generating chip to obtain data signals Data. Figures 1 to 9 As shown in the figure, the display panel further comprises a data generating chip located on at least one side of the plurality of pixel driving circuits 100, and a plurality of data lines are electrically connected to the data generating chip to obtain data signals Data. Specifically, in combination with the above description, when the data transistor T4 is turned on, the data signal Data obtained by the corresponding data line can be loaded to the gate G of the driving transistor T1 through the data transistor T4 to turn on the driving transistor T1, and later in combination with the voltage stabilizing effect of the second capacitor C2 and the source voltage Vs of the driving transistor T1, the light emitting element L can be controlled to emit light at a first brightness.

[0118] In an embodiment, the absolute value of the voltage of the corresponding data signal Data received by the pixel driving circuit 100 far away from the data generating chip is larger than that of the pixel driving circuit 100 close to the data generating chip. It should be noted that the data generating chip is arranged close to at least one side of the plurality of pixel driving circuits 100, i.e., the distance between the plurality of pixel driving circuits 100 and the data generating chip is different, resulting in different degrees of attenuation of the data signal Data received by the pixel driving circuits 100 at different positions. For example, if the data signal Data loaded to each data line is the same, the voltage of the data signal Data finally loaded on the pixel driving circuits 100 at different positions will be different, which will affect the uniformity of the display picture.

[0119] It can be understood that, in the embodiment, the pixel driving circuit 100 far away from the data generating chip receives a data signal Data with a larger degree of attenuation than the pixel driving circuit 100 close to the data generating chip. Based on this, the embodiment increases the absolute value of the voltage of the data signal Data loaded by the pixel driving circuit 100 far away from the data generating chip, so as to compensate for the excessive data signal Data caused by the large distance from the data generating chip, thereby reducing the difference in the degree of attenuation of the data signal Data loaded by the pixel driving circuits 100 at different positions, and improving the uniformity of the display picture of the display panel.

[0120] In an embodiment, in combination with Figures 1 to 9 As shown in FIG. 1, the display panel further comprises a signal generating chip arranged on at least one side of the plurality of pixel driving circuits 100, and the input end of the plurality of boost modules 10 is electrically connected to the signal generating chip to obtain the boost input signal CK. The boost input signal has a first boost input voltage in the first stage, and has a second boost input voltage in the second stage, and the second boost input voltage is larger than the first boost input voltage. The absolute value of the difference between the corresponding second boost input voltage and the corresponding first boost input voltage of the pixel driving circuit 100 far away from the data generating chip is larger than that of the pixel driving circuit 100 close to the data generating chip.

[0121] Specifically, the signal generation chip and the data generation chip can be fixed on the non-display area of the front surface of the display panel or the back surface by, but not limited to, COF (Chip On Film), COG (Chip On Glass), COP (Chip On Pi) or other packaging technologies. Among them, the signal generation chip and the data generation chip can be arranged close to at least one side of the plurality of pixel driving circuits 100, that is, the distance between the pixel driving circuit 100 at different positions and the signal generation chip can be different, and the distance between the pixel driving circuit 100 at different positions and the data generation chip can also be different. It should be noted that, in combination with the above description, the distance between the pixel driving circuit 100 at different positions and the data generation chip is different, which will cause the attenuation degree of the data signal Data received by the pixel driving circuit 100 at different positions to be different, for example, the data signal Data loaded to each data line is the same, which will cause the size of the voltage of the data signal Data finally loaded to the pixel driving circuit 100 at different positions to have differences and affect the uniformity of the picture display, and the attenuation degree of the data signal Data is also different, which will cause the size of the corresponding first voltage to be different.

[0122] It can be understood that in the present embodiment, the pixel driving circuit 100 far away from the data generation chip has a greater attenuation degree of the data signal Data received than the pixel driving circuit 100 close to the data generation chip, and based on this, the present embodiment sets the boost input signal CK loaded by the pixel driving circuit 100 far away from the data generation chip as the difference between the second boost input voltage Vch and the corresponding first boost input voltage Vcl is greater, that is, the change value ΔVa of the voltage of the node A (positively correlated with (Vch-Vcl)) can also be greater, to make up for the loss of the first brightness caused by the first voltage being too small due to the large distance from the data generation chip, by setting a larger ΔVa, thereby reducing the difference between the second voltage and the first voltage in the pixel driving circuit 100 at different positions, so that the difference between the second brightness of the light emitting element L at different positions can be smaller, and the uniformity of the display picture of the display panel is improved.

[0123] The application provides a pixel driving circuit and a display panel, the pixel driving circuit comprising: a driving transistor, which is connected in series between a first power supply line and a second power supply line, and a light emitting element, a source electrode of the driving transistor being electrically connected to the light emitting element; a data transistor, a source electrode of the data transistor being electrically connected to a data line, a drain electrode of the data transistor being electrically connected to a gate electrode of the driving transistor, and a gate electrode of the data transistor being loaded with a data control signal; a voltage boosting module, an input end of the voltage boosting module being used for loading a voltage boosting input signal, and an output end of the voltage boosting module being electrically connected to the gate electrode of the driving transistor; wherein the voltage boosting module controls the gate electrode of the driving transistor to rise from a first voltage in a first stage to a second voltage in a second stage, the second stage being located after the first stage, and the driving transistor is used for generating a driving current according to at least the second voltage to drive the light emitting element to emit light; wherein the voltage boosting module comprises: a first capacitor, a first plate of the first capacitor being electrically connected to the input end of the voltage boosting module to load the voltage boosting input signal, and a second plate of the first capacitor being electrically connected to the gate electrode of the driving transistor; and a second capacitor, a first plate of the second capacitor being electrically connected to the gate electrode of the driving transistor to serve as the output end of the voltage boosting module, and a second plate of the second capacitor being loaded with a first signal. Wherein, the application is provided with the voltage boosting module, the input end of which is loaded with the voltage boosting input signal, and the output end of which is electrically connected to the gate electrode of the driving transistor, and the voltage boosting module is combined with the voltage dividing effect of the first capacitor and the second capacitor to modulate the gate voltage of the driving transistor to rise from the first voltage to the second voltage, so as to increase the driving current flowing through the light emitting element, to improve the light emitting brightness of the light emitting element, and to improve the brightness of the display panel.

[0124] The pixel driving circuit and the display panel provided by the embodiments of the application are described in detail above, and the principles and implementation manners of the application are described by using specific examples in this paper, and the above description of the embodiments is only used to help understand the technical solutions and the core ideas of the application; those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the application.

Claims

1. A pixel driving circuit, characterized in that, include: A driving transistor is connected in series with a light-emitting element between a first power line and a second power line, and the source of the driving transistor is electrically connected to the light-emitting element; A data transistor, wherein the source of the data transistor is electrically connected to a data line, the drain of the data transistor is electrically connected to the gate of the driving transistor, and a data control signal is loaded onto the gate of the data transistor; A boost module, wherein the input terminal of the boost module is used to load a boost input signal, and the output terminal of the boost module is electrically connected to the gate of the driving transistor; The boost module controls the gate of the driving transistor to rise from a first voltage in a first stage to a second voltage in a second stage, the second stage being after the first stage. The driving transistor is used to generate a driving current based at least on the second voltage to drive the light-emitting element to emit light. The boost module includes: A first capacitor, wherein the first plate of the first capacitor is electrically connected to the input terminal of the boost module to load the boost input signal, and the second plate of the first capacitor is electrically connected to the gate of the driving transistor; The second capacitor has its first plate electrically connected to the gate of the driving transistor to serve as the output terminal of the boost module, and its second plate is loaded with a first signal. Wherein, the second plate of the second capacitor is electrically connected to the drain of the driving transistor, and the boost module further includes: Third capacitor; A boost switch is connected in series with the third capacitor between the gate and the source of the driving transistor; In the first stage and the third stage preceding the first stage, the boost switch is turned on to control the gate of the driving transistor to rise from the third voltage of the third stage to the first voltage of the first stage.

2. The pixel driving circuit according to claim 1, characterized in that, The boost module also includes: A boost submodule, wherein the input terminal of the boost submodule is configured as the input terminal of the boost module, and the first plate of the first capacitor is electrically connected to the output terminal of the boost submodule.

3. The pixel driving circuit according to claim 2, characterized in that, The boost submodule includes: The first boost transistor has its drain electrically connected to the first plate of the first capacitor as the output terminal of the boost submodule, and its source electrically connected to the input terminal of the boost module. The gate of the first boost transistor is loaded with a first boost control signal, and the first boost transistor is turned on in both the first and second stages. Wherein, the boost input signal has a first boost input voltage in the first stage, and the boost input signal has a second boost input voltage in the second stage, wherein the second boost input voltage is greater than the first boost input voltage.

4. The pixel driving circuit according to claim 1, characterized in that, The first signal maintains a constant voltage during the first and second phases.

5. The pixel driving circuit according to any one of claims 1 to 4, characterized in that, Also includes: A reset transistor, wherein the source of the reset transistor is electrically connected to a reset line, the drain of the reset transistor is electrically connected to the source of the driving transistor, and a reset control signal is applied to the gate of the reset transistor.

6. The pixel driving circuit according to any one of claims 1 to 4, characterized in that, The capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

7. A display panel, characterized in that, It includes multiple pixel driving circuits as described in any one of claims 1 to 6.

8. The display panel according to claim 7, characterized in that, Also includes: A data generation chip is located on at least one side of the plurality of pixel driving circuits, and the plurality of data lines are electrically connected to the data generation chip to obtain data signals.

9. The display panel according to claim 8, characterized in that, The pixel driving circuit farther away from the data generation chip has a larger absolute value of the voltage value of the corresponding data signal compared to the pixel driving circuit closer to the data generation chip.

10. The display panel according to claim 8, characterized in that, Also includes: A signal generation chip is located on at least one side of the plurality of pixel driving circuits, and the input terminals of the plurality of boost modules are electrically connected to the signal generation chip to obtain the boost input signal; Wherein, the boost input signal has a first boost input voltage in the first stage, and the boost input signal has a second boost input voltage in the second stage, wherein the second boost input voltage is greater than the first boost input voltage; Specifically, the pixel driving circuit farther from the data generating chip has a larger difference between the second boost input voltage and the first boost input voltage compared to the pixel driving circuit closer to the data generating chip.

11. A display panel, characterized in that, Includes a pixel driving circuit, the pixel driving circuit comprising: A driving transistor is connected in series with a light-emitting element between a first power line and a second power line, and the source of the driving transistor is electrically connected to the light-emitting element; A data transistor, wherein the source of the data transistor is electrically connected to a first signal line, the drain of the data transistor is electrically connected to the gate of the driving transistor, and the gate of the data transistor is electrically connected to a second signal line. A boost module, wherein the input terminal of the boost module is electrically connected to a third signal line, the output terminal of the boost module is electrically connected to the gate of the driving transistor, and the control terminal of the boost module is electrically connected to a fourth signal line. The boost module controls the gate of the driving transistor to rise from a first voltage in a first stage to a second voltage in a second stage, wherein the second stage is located after the first stage. The boost module includes: A first capacitor, wherein the first plate of the first capacitor is electrically connected to the input terminal of the boost module, and the second plate of the first capacitor is electrically connected to the gate of the driving transistor; The second capacitor has its first plate electrically connected to the gate of the driving transistor to serve as the output terminal of the boost module, and its second plate electrically connected to the drain of the driving transistor. Third capacitor; A boost switch is connected in series with the third capacitor between the gate and the source of the driving transistor; In the first stage and the third stage preceding the first stage, the boost switch is turned on to control the gate of the driving transistor to rise from the third voltage of the third stage to the first voltage of the first stage.

12. The display panel according to claim 11, characterized in that, The boost module also includes: The first submodule has its input terminal configured as the input terminal of the boost module, and the first plate of the first capacitor is electrically connected to the output terminal of the boost module.

13. The display panel according to claim 12, characterized in that, The first submodule includes: The third transistor has its drain electrically connected to the first plate of the first capacitor as the output terminal of the first submodule, its source electrically connected to the input terminal of the boost module, and its gate electrically connected to the fifth signal line.

14. The display panel according to any one of claims 11 to 13, characterized in that, Also includes: A reset transistor, wherein the source of the reset transistor is electrically connected to a reset line, the drain of the reset transistor is electrically connected to the source of the driving transistor, and the gate of the reset transistor is electrically connected to an eighth signal line for transmitting a reset control signal.

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