A light-emitting control circuit, display panel and display device

Abstract

The application discloses a light-emitting control circuit, a display panel and a display device. The light-emitting control circuit comprises a first control module, a second control module and an output module. The first control module is used for controlling the potentials of a first node and a second node according to an input signal of a signal input end, a first clock signal of a first clock end and a second clock signal of a second clock end. The second control module is used for controlling the potential of a third node under the control of the first control module, the first clock signal, the second clock signal, a first level signal of a first level end and a second level signal of a second level end. The output module is used for controlling an enable level of a light-emitting control signal output by a signal output end according to the first level signal and the potential of the first node, and controlling a non-enable level of the light-emitting control signal output by the signal output end according to the second level signal of the second level end and the potential of the third node. The filter module has a one-way conduction characteristic. The above scheme can improve the display effect of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a light emitting control circuit, a display panel and a display device. BACKGROUND

[0002] In the existing display, the organic electroluminescent display (OLED) as an active light emitting display, with its low power consumption, high color saturation, wide viewing angle and other characteristics, has gradually become the mainstream in the display field; in order to realize the display function of OLED display, it is usually necessary to input light emitting control signal to the display area of OLED display, so as to help realize the display of picture.

[0003] The light emitting control signal is output by the light emitting control circuit, and the light emitting control circuit is connected with the pixel circuit, so as to control the light emitting of the pixel. Stable light emitting control signal is helpful for stable display of OLED display, and stable light emitting control signal is also helpful for accurate display of OLED display.

[0004] Therefore, how to control the light emitting control circuit to stably output the light emitting control signal to meet the accurate and stable display requirement is a technical problem to be solved by those skilled in the art. SUMMARY

[0005] The present application provides a light emitting control circuit, a display panel and a display device to meet the accurate and stable display requirement.

[0006] According to an aspect of the present application, a light emitting control circuit is provided, characterized in that it comprises a filtering module, a first control module, a second control module and an output module.

[0007] The first control module is electrically connected with the signal input end, the first clock end and the second clock end respectively; the first control module is also electrically connected with the output module at the first node, and is electrically connected with the filtering module at the second node; the first control module is used for controlling the electric potential of the first node and the second node respectively according to the input signal of the signal input end, the first clock signal of the first clock end and the second clock signal of the second clock end.

[0008] The second control module is electrically connected with the first clock end, the second clock end, the first level end, the second level end and the first control module respectively; the second control module is also electrically connected with the output module at a third node; the second control module is used for controlling the potential of the third node under the control of the first control module, the first clock signal, the second clock signal, the first level signal of the first level end and the second level signal of the second level end.

[0009] The output module is also electrically connected with the first level end, the second level end and a signal output end respectively; the output module is used for controlling the signal output end to output an enable level of a light-emitting control signal according to the first level signal and the potential of the first node, and controlling the signal output end to output a disable level of the light-emitting control signal according to the second level signal of the second level end and the potential of the third node; wherein the enable level and the disable level of the light-emitting control signal are output in time division.

[0010] The filter module is also electrically connected with the first node; the filter module has a one-way conduction characteristic.

[0011] According to another aspect of the present application, a display panel is provided, characterized in that comprising: a plurality of pixel circuits arranged in an array and a plurality of light-emitting control circuits cascaded.

[0012] The signal output end of each light-emitting control circuit is electrically connected with at least part of the pixel circuits in the same row; the signal output end of each light-emitting control circuit except the last one is electrically connected with the signal input end of the next light-emitting control circuit, and the signal input end of the first light-emitting control circuit receives a start pulse signal.

[0013] According to another aspect of the present application, a display device is provided, characterized in that comprising: the display panel.

[0014] The technical scheme of the embodiment of the present application controls the potentials of the first node and the second node through the first control module, and sets the filter module electrically connected between the first node and the second node to stabilize the potential of the first node, so that the first node is immune to the potential of the second node at some time, and the stability of the potential of the first node is improved, so that when the output module outputs the enable level of the light-emitting control signal to the signal output end according to the potential of the first node, the stability of the light-emitting control signal output by the signal output end is improved, so that when the light-emitting state of the light-emitting element in the display panel is controlled by using the light-emitting control signal, the light-emitting stability of the light-emitting element is improved, and the display effect of the display panel is further improved; meanwhile, the potential of the third node is controlled by the second control module, so that in the non-light-emitting stage of the light-emitting element in the display panel, the output module can output the non-enable level of the light-emitting control signal to the signal output end according to the potential of the third node, so that the corresponding light-emitting element is in the non-light-emitting state, that is, the second control module and the first control module work cooperatively to control the light-emitting element in the display panel to emit light stably and accurately, and the display effect is further improved.

[0015] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0017] Figure 1 A structural schematic diagram of a display panel provided by the embodiment of the present application is shown in the figure.

[0018] Figure 2 A structural schematic diagram of a light-emitting control circuit provided by the embodiment of the present application is shown in the figure.

[0019] Figure 3 Another structural schematic diagram of a light-emitting control circuit provided by the embodiment of the present application is shown in the figure.

[0020] Figure 4 Another structural schematic diagram of a light-emitting control circuit provided by the embodiment of the present application is shown in the figure.

[0021] Figure 5 Another structural schematic diagram of a light-emitting control circuit provided by the embodiment of the present application is shown in the figure.

[0022] Figure 6A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in Fig. 6;

[0023] Figure 7 is a signal simulation diagram corresponding to the light emitting control circuit shown in Fig. 1; Figure 6 is a driving timing diagram of a corresponding light emitting control circuit;

[0024] Figure 8 A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in Fig. 6;

[0025] Figure 9 A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in Fig. 6;

[0026] Figure 10 A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in Fig. 6;

[0027] Figure 11 is a signal simulation diagram corresponding to the light emitting control circuit shown in Fig. 1;

[0028] Figure 12 A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in Fig. 6;

[0029] Figure 13 is a signal simulation diagram corresponding to the light emitting control circuit shown in Fig. 1; Figure 12 is a signal simulation diagram corresponding to the light emitting control circuit shown in Fig. 1;

[0030] Figure 14 A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in Fig. 6;

[0031] Figure 15 A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in Fig. 6;

[0032] Figure 16 is a signal simulation diagram corresponding to the light emitting control circuit shown in Fig. 1; Figure 15 is a driving timing diagram of a corresponding light emitting control circuit;

[0033] Figure 17 A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in Fig. 6;

[0034] Figure 18 A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in Fig. 6;

[0035] Figure 19 A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in Fig. 6;

[0036] Figure 20 A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in Fig. 6;

[0037] Figure 21A schematic structural diagram of another light emitting control circuit provided by an embodiment of the present invention;

[0038] Figure 22 A schematic structural diagram of another light emitting control circuit provided by an embodiment of the present invention;

[0039] Figure 23 A schematic structural diagram of a light-emitting driver provided by an embodiment of the present invention;

[0040] Figure 24 This is a driving timing diagram of a light-emitting driver provided by an embodiment of the present invention.

[0041] Figure 25 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0042] Figure 26 is with Figure 25 A corresponding driving timing diagram of a pixel circuit;

[0043] Figure 27 is a structural diagram of another display panel provided by an embodiment of the present invention;

[0044] Figure 28 is with Figure 25 A corresponding driving timing diagram of another pixel circuit;

[0045] Figure 29 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0047] It is to be understood that the terminology "first", "second", and the like used in the specification and the claims of the application as well as the foregoing drawings is merely intended to distinguish between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the use of data herein so designated is not meant to limit, and will not serve to limit, the described embodiments of the application to only such potentially applications as can there be described or otherwise ined herein. Further, the terms "include" and "comprise," and variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, product, or apparatus that comprises a list of steps or units are not necessarily limited to those steps or units specifically listed, but can include additional steps or units not expressly listed or inherent to such process, method, product, or apparatus.

[0048] Figure 1 A structural schematic diagram of a display panel according to an embodiment of the application is disclosed. As shown in Figure 1 The display panel 10 can include a display area 11 and a non-display area 12 surrounding the display area 11, the display area 11 including a plurality of pixels P, and a plurality of scan lines SL1 to SLn, a plurality of data lines DL1 to DLm and a plurality of light-emitting control lines EL1 to ELn connected to the plurality of pixels P; the non-display area 12 is provided with a scan driver 20, a light-emitting driver 30, a data driver 40 and a timing controller 50. Wherein the number of the plurality of scan lines SL1 to SLn and the number of the plurality of light-emitting control lines EL1 to ELn can be n, or the number of the plurality of scan lines SL1 to SLn and the number of the plurality of light-emitting control lines EL1 to ELn can be set according to requirements, such as each row of pixels P being connected to a plurality of scan lines, a plurality of rows of pixels P sharing a light-emitting control line, etc., the number of the plurality of data lines DL1 to DLm can be m, n and m are natural numbers greater than zero, at this time, the number of the plurality of pixels P can be n x m.

[0049] The timing controller 50 can receive an input control signal and an input image signal from an image source of an external graphics device. The timing controller 50 generates image data RGB and data drive control signal DCS corresponding to the operating conditions of the display panel 10 based on the input image signal, and supplies the image data RGB and the data drive control signal to the data driver 40. Wherein the data drive control signal DCS can include a source start pulse signal and a clock signal, the source start pulse signal can control the sampling start time point of the data, and the clock signal is used to control the sampling operation, so that the data driver 40 responds to the data drive control signal DCS, and converts the image data RGB into an analog format data signal (data voltage) supplied to the plurality of data lines DL1 to DLm.

[0050] The timing controller 50 can further generate a scan driving control signal SCS for controlling the driving timing of the scan driver 20 and an emission driving control signal ECS for controlling the driving timing of the emission driver 30 based on the input control signal. The scan driving control signal SCS can include a scan start pulse signal for controlling the first timing of the scan signal and a clock signal for shifting the scan start pulse so that the scan signal can be supplied to the plurality of scan lines SL1-SLn when the scan driver 20 responds to the scan driving control signal SCS; the emission driving control signal ECS can include an emission control start pulse signal for controlling the first timing of the emission control signal and a clock signal for shifting the emission control start pulse so that the emission control signal can be supplied to the plurality of emission control lines EL1-ELn when the emission driver 30 responds to the emission driving control signal ECS.

[0051] In the display stage of a frame of image, the scan driver 20 sequentially provides the enable level of the scan signal to each of the scan lines SL1-SLn so that the data signal provided by the data driver 40 can be correspondingly provided to each of the pixels P through each of the data lines DL1-DLm; each of the pixels P of the display panel 10 can further receive the first driving power PVDD and the second driving power PVEE from the outside (e.g. a power supply) so that when the emission driver 30 sequentially starts to provide the enable level of the emission control signal to each of the emission control lines EL1-ELn, the pixel P receiving the enable level of the emission control signal can form a path from the first driving power PVDD to the second driving power PVEE so that the driving current generated according to the data signal controls the light emitting element therein to emit light.

[0052] The emission driver 30 can include a plurality of cascaded emission control circuits, the signal output end of each of the emission control circuits can correspond to an emission control line, when the emission control circuit provides the enable level of the emission control signal to the emission control line, the light emitting element in the pixel P electrically connected to the emission control line is controlled to emit light; when the emission control circuit provides the non-enable level of the emission control signal to the emission control line, the light emitting element in the pixel P electrically connected to the emission control line is controlled to be in a non-emission state. In order to improve the display effect of the display panel 10, it is required that the light emitting element in the pixel P is in a non-emission state in the non-emission stage and can stably emit light in the emission stage.

[0053] To improve the display effect of the display panel 10, the embodiment of the present application provides a light emitting control circuit, comprising: a filtering module, a first control module, a second control module and an output module. The first control module is electrically connected with a signal input end, a first clock end and a second clock end respectively; the first control module is further electrically connected with the output module at a first node and with the filtering module at a second node; the first control module is used for controlling the potentials of the first node and the second node respectively according to the input signal of the signal input end, the first clock signal of the first clock end and the second clock signal of the second clock end. The second control module is electrically connected with the first clock end, the second clock end, a first level end, a second level end and the first control module respectively; the second control module is further electrically connected with the output module at a third node; the second control module is used for controlling the potential of the third node under the control of the first control module, the first clock signal, the second clock signal, the first level signal of the first level end and the second level signal of the second level end. The output module is further electrically connected with the first level end, the second level end and a signal output end respectively; the output module is used for controlling the signal output end to output the enable level of the light emitting control signal according to the first level signal and the potential of the first node, and to output the disable level of the light emitting control signal according to the second level signal of the second level end and the potential of the third node. The enable level and the disable level of the light emitting control signal are output at different times. The filtering module is further electrically connected with the first node; the filtering module has a one-way conduction characteristic.

[0054] By the above technical solution, the first control module is used for controlling the potentials of the first node and the second node respectively, and the filtering module electrically connected between the first node and the second node is arranged to stabilize the potential of the first node, so that the first node is immune to the potential of the second node at some time, the stability of the potential of the first node is improved, the stability of the light emitting control signal output by the signal output end can be improved when the output module outputs the enable level of the light emitting control signal to the signal output end according to the potential of the first node, the light emitting stability of the light emitting element can be improved when the light emitting element in the display panel is controlled by the light emitting control signal, and the display effect of the display panel is further improved. Meanwhile, the second control module is used for controlling the potential of the third node, so that the output module can output the disable level of the light emitting control signal to the signal output end according to the potential of the third node in the non-light emitting stage of the light emitting element in the display panel, so that the corresponding light emitting element is in the non-light emitting stage, that is, the first control module and the second control module work cooperatively to control the light emitting element in the display panel to emit light stably and accurately, and the display effect is further improved.

[0055] The above is the core idea of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application. The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the accompanying drawings of the embodiments of the present application.

[0056] Figure 2 A structural schematic diagram of a light-emitting control circuit provided by an embodiment of the present application is shown in FIG. 3, which includes a filtering module 300, a first control module 100, a second control module 200 and an output module 400. Figure 2

[0057] The first control module 100 is electrically connected with a signal input end IN, a first clock end CK and a second clock end CKB respectively; the first control module 100 is also electrically connected with the output module 400 at a first node N1 and with the filtering module 300 at a second node N2; the first control module 100 is configured to control the potentials of the first node N1 and the second node N2 respectively according to an input signal Vin of the signal input end IN, a first clock signal ck1 of the first clock end CK and a second clock signal ck2 of the second clock end CKB.

[0058] The second control module 200 is electrically connected with the first clock end CK, the second clock end CKB, a first level end VGL, a second level end VGH and the first control module 100 respectively; the second control module 200 is also electrically connected with the output module 400 at a third node N3; the second control module 200 is configured to control the potential of the third node N3 under the control of the first control module 100, the first clock signal ck1, the second clock signal ck2, a first level signal Vgl of the first level end VGL and a second level signal Vgh of the second level end VGH.

[0059] The output module 400 is also electrically connected with the first level end VGL, the second level end VGH and a signal output end OUT respectively; the output module 400 is configured to control the signal output end OUT to output an enable level of a light-emitting control signal EM according to the first level signal Vgl and the potential of the first node N1, and to control the signal output end OUT to output a disable level of the light-emitting control signal EM according to the second level signal Vgh of the second level end VGH and the potential of the third node N3. The enable level and the disable level of the light-emitting control signal EM are output at different times.

[0060] ​The filter module 300 is also electrically connected with the first node N1; the filter module 300 is used for stabilizing the potential of the first node N1, so that the output module 400 controls the enable level of the light-emitting control signal EM to be stably output from the signal output end OUT according to the first level signal Vgl and the potential of the first node N1, and then when the pixel in the display panel receives the enable level of the light-emitting control signal which is stable, the light-emitting element of the pixel can be controlled to stably emit light, and the display light stability of the display panel is improved.

[0061] The first clock signal ck1 can be a pulse signal in which a high level signal (for example, vgh) and a low level signal (for example, vgl) are alternately performed; similarly, the second clock signal ck2 can also be a pulse signal in which a high level signal vgh and a low level signal vgl are alternately performed; generally, a high level signal vgh and a low level signal vgl which are continuous constitute a pulse period, the second clock signal ck2 can be different from the first clock signal ck1 by half a period, that is, when the first clock signal ck1 is a high level signal vgh, the second clock signal ck2 can be a low level signal vgl, and vice versa, when the first clock signal ck1 is a low level signal vgl, the second clock signal ck2 can be a high level signal vgh. The low level signal vgl can be an enable level of the first clock signal ck1 and the second clock signal ck2, and the high level signal vgh can be a non-enable level of the first clock signal ck1 and the second clock signal ck2; or, the high level signal vgh can be an enable level of the first clock signal ck1 and the second clock signal ck2, and the low level signal vgl can be a non-enable level of the first clock signal ck1 and the second clock signal ck2. It can be understood that the high and low of the enable level and the non-enable level of the first clock signal ck1 and the second clock signal ck2 can be set according to needs, and the embodiment of the present application does not make specific limitation thereto.

[0062] The first level signal Vgl of the first level terminal VGL and the second level signal Vgh of the second level terminal VGH can be fixed signals. For example, when the first level signal Vgl of the first level terminal VGL is a low level signal (e.g., vgl), the second level signal Vgh of the second level terminal VGH can be a high level signal (e.g., vgh). Conversely, when the first level signal Vgl of the first level terminal VGL is a high level signal vgh, the second level signal Vgh of the second level terminal VGH can be a low level signal vgl. It can be understood that the first level signal Vgl of the first level terminal VGL and the second level signal Vgh of the second level terminal VGH can be set as needed, and embodiments of the present application do not make specific limitations thereto. In an optional embodiment, the enable level of the light emitting control signal EM is a low level, and the non-enable level of the light emitting control signal EM is a high level. At this time, the first level signal Vgl of the first level terminal VGL is a low level signal vgl, and the second level signal Vgh of the second level terminal VGH is a high level signal vgh. The voltage value of the low level signal vgl is less than the voltage value of the high level signal vgh. Further, the voltage value of the low level signal vgl is a negative value, and the voltage value of the high level signal vgh is a positive value, so as to match the enable level and the non-enable level of the light emitting control signal EM.

[0063] For example, the first control module 100 can control the input signal Vin to be transmitted to the first node N1 under the control of the enable level of the first clock signal ck1, so that the potential of the first node N1 matches the input signal Vin. The first control module 100 can also control the potential of the second node N2, and when the input signal Vin is transmitted to the first node N1 under the control of the first clock signal ck1, the potential of the second node N2 can also match the input signal Vin. When the first clock signal ck1 is a non-enable level, the input signal Vin cannot be transmitted to the first node N1, and the potential of the second node N2 can match the second clock signal ck2. At the same time, since the first clock signal ck1 is opposite to the second clock signal ck2, that is, when the first clock signal ck1 is a non-enable level, the second clock signal ck2 is an enable level, therefore, when the input signal Vin cannot be transmitted to the first node N1, the potential of the second node N2 will match the enable level of the second clock signal ck2.

[0064] The filter module 300 is electrically connected between the first node N1 and the second node N2, has a one-way conduction characteristic, and can selectively connect the second node N2 and the first node N1 according to a voltage relationship between a potential of the first node N1 and a potential of the second node N2, to selectively feed back a potential of the second node N2 that meets a requirement to the first node N1, to achieve the effect of stabilizing the potential of the first node N1. For example, when the input signal Vin cannot be transmitted to the first node N1 and the second node N2 is at a potential that matches an enable level of the second clock signal ck2, the filter module 300 controls the potential of the first node N1 to also match the enable level of the second clock signal ck2. In this way, when the first clock signal ck1 is at the enable level to control the enable level of the input signal Vin to be transmitted to the first node N1, the first node N1 can be at the enable level of the input signal Vin, and when the first clock signal ck1 is at the non-enable level and the enable level of the input signal Vin cannot be transmitted to the first node N1, the filter module 300 controls the first node N1 to be at a potential that matches the enable level of the second clock signal ck2, so that the potential of the first node N1 does not change to the non-enable level over time, and the first node N1 can be at a continuously stable enable level, achieving the effect of stabilizing the potential of the first node N1. At the same time, when the first node N1 is at a continuously stable enable level, the output module 400 can control the first level signal Vgl of the first level end VGL to be transmitted to the signal output end OUT under the control of the enable level of the first node N1, so that the signal output end OUT can stably output the enable level of the light-emitting control signal EM, thereby improving the light-emitting stability of the pixels in the display panel when the enable level of the light-emitting control signal EM controls the pixels in the display panel to emit light, and further improving the display effect of the display panel.

[0065] Correspondingly, the second control module 200 controls the potential of the third node N3 under the control of the first control module 100, the first clock signal ck1, the second clock signal ck2, the first level signal Vgl, and the second level signal Vgh, so that when the potential of the third node N3 is at the enable level, the output module 400 can be controlled to transmit the second level signal Vgh of the second level end VGH to the signal output end OUT, so that the signal output end OUT outputs the non-enable level of the light-emitting control signal EM. In this way, when the pixels in the display panel do not need to emit light, the non-enable level of the light-emitting control signal EM can control the pixels in the display panel to be in a non-light-emitting state.

[0066] The embodiment of the present application controls the potential of the first node N1 to match the input signal Vin through the first control module 100, controls the potential of the second node N2 to match the input signal Vin, and when the input signal Vin cannot be transmitted to the first node N1 and the second node N2, the potential of the second node N2 can match the enable level of the second clock signal ck2, through the filtering module 300, when the input signal Vin cannot be transmitted to the first node N1, the potential of the first node N1 can match the enable level of the second clock signal ck2, so that the potential of the first node N1 does not change to the non-enable level with the passage of time, and the first node N1 can provide a continuous and stable enable level. In this way, the output module 400 can transmit the first level signal Vgl of the first level end VGL to the signal output end OUT according to the enable level of the first node N1, so that the signal output end OUT can stably output the enable level of the light-emitting control signal EM, thereby improving the light-emitting stability of the light-emitting element when the light-emitting element in the display panel is controlled to emit light by using the enable level of the light-emitting control signal EM, and further improving the display effect of the display panel. The embodiment of the present application further controls the potential of the third node N3 through the second control module 200, and when the potential of the third node N3 is the enable level, the output module 400 can transmit the first level signal Vgh of the second level end VGH to the signal output end OUT according to the enable level of the second node N2, so that the output end OUT outputs the non-enable level of the light-emitting control signal EM, and the corresponding light-emitting element in the display panel can be in the non-light-emitting stage; through the cooperation of the second control module 200 and the first control module 100 and the filtering module 300, the light-emitting element in the display panel can be controlled to stably and accurately emit light, thereby improving the display effect.

[0067] It can be understood that the high and low of the enable level and the non-enable level are related to the structure of the module controlled thereby, for example, when the module includes a transistor and the transistor is a P-channel transistor, the enable level is a low level and the non-enable level is a high level; and when the module includes a transistor and the transistor is an N-channel transistor, the enable level is a high level and the non-enable level is a low level. In the embodiment of the present application, the high and low of the enable level and the non-enable level can be limited according to actual needs. For ease of description, in the absence of special instructions, the embodiment of the present application takes the enable level as a low level and the non-enable level as a high level as an example.

[0068] Optionally, Figure 3 Another structure diagram of a light-emitting control circuit provided by the embodiment of the present application is shown in FIG. 4. Figure 3 As shown in FIG. 4, the filtering module 300 includes a filtering transistor M300, the filtering transistor M300 is electrically connected between the first node N1 and the second node N2, and the gate and the source of the filtering transistor M300 are electrically connected.

[0069] For example, Figure 3 As shown, the filter transistor M300 may be a P-channel transistor, whose active layer may include low-temperature polysilicon. In this case, the drain of the filter transistor M300 is electrically connected to the first node N1, and the gate and source of the filter transistor M300 are both electrically connected to the second node N2. When the potential of the second node N2 is lower than the potential of the first node N1, the filter transistor M300 may be in an on state, forming a path from the first node N1 to the second node N2, and the potential of the second node N2 can pull down the potential of the first node N1. In this way, when the input signal Vin and the first clock signal ck1 are both at the enable level, the potential of the first node N1 is a low level that matches the enable level of the input signal Vin, and when the first clock signal ck1 is at the non-enable level, the second clock signal ck2 is at the enable level, and the potential of the second node N2 matches the enable level of the second clock signal ck2, so that the potential of the second node N2 can be lower than the potential of the first node N1, and the filter transistor M300 can be in the on state, forming a path from the first node N1 to the second node N2. The filter transistor M300 can pull down the potential of the first node N1 to match the potential of the second node N2, so that even if the enable level of the input signal Vin is not transmitted to the first node N1, the potential of the first node N1 can be maintained at the enable level, so that the signal output terminal OUT can stably output the light-emitting control signal EM.

[0070] It is understandable that if Figure 4 As shown, the filter transistor M300 may also be an N-channel transistor, whose active layer may include metal oxide. In this case, its drain is electrically connected to the second node N2, and its gate and source are both electrically connected to the first node N1. In this way, when the potential of the second node N2 is lower than the potential of the first node N1, the filter transistor M300 can be turned on, and the same effect as when the filter transistor M300 is a P-channel transistor can be achieved. The similarities can be referred to the above description and will not be repeated here.

[0071] It should be noted that the above description uses the example of the enable level being low and the disable level being high as an example to illustrate the case where the filter module 300 is specifically a P-channel filter transistor M300. In this case, when the potential of the second node N2 is lower than the potential of the first node N1, the filter transistor M300 is turned on. Accordingly, in the embodiment of the present invention, the enable level may also be high and the disable level be low. In this case, the filter transistor M300 of the filter module 300 is turned on when the potential of the second node N2 is higher than the potential of the first node N1. This also achieves the purpose of stabilizing the potential at the first node N1. The technical principle is similar to the case where the enable level is low and the disable level is high. Please refer to the above description and will not be repeated here.

[0072] Optional, such as Figure 5 As shown, the first control module 100 includes a first node control unit 110, a second node control unit 120, and a charge pump unit 130. The first node control unit 110 is electrically connected to the signal input terminal IN, the first clock terminal CK, and the first node N1 respectively; the first node control unit 110 is used to control the potential of the first node N1 according to the input signal Vin and the first clock signal ck1; the second node control unit 120 is electrically connected to the first clock terminal CK and the second node N2; the second node control unit 120 is used to control the potential of the second node N2 according to the first clock signal ck1; the charge pump unit 130 is electrically connected to the second node N2 and the second clock terminal CKB respectively; the charge pump unit 130 is used to control the amount of the signal coupled from the second clock terminal CKB to the second node N2.

[0073] Specifically, the first node control unit 110 can control the transmission path of the input signal Vin of the input signal terminal IN to the first node N1 under the control of the first clock signal ck1 of the first clock terminal CK, and when the first clock signal ck1 is at an enable level, the input signal Vin can be transmitted to the first node N1 through the first node control unit 110, and when the first clock signal ck1 is at a non-enable level, the input signal Vin cannot be transmitted to the first node N1 through the first node control unit 110. The second node control unit 120 can also control the potential of the second node N2 under the control of the first clock signal ck1. In an exemplary embodiment, the second node control unit 120 is also electrically connected to the signal input terminal IN, so that the second node control unit 120 controls the transmission path of the input signal Vin to the second node N2 according to the first clock signal ck1. That is, when the first clock signal ck1 is at an enable level, the input signal Vin can be transmitted to the second node N2 through the second node control unit 120, so that the potential of the second node N2 is equivalent to the potential of the first node N1; and when the first clock signal ck1 is at a non-enable level vgh, the input signal Vin cannot be transmitted to the second node N2 through the second node control unit 120, and the potential of the second node N2 is no longer controlled by the second node control unit 120. At this time, the second clock signal ck2 of the second clock terminal CKB can be controlled by the charge pump unit 130. It is coupled to the second node N2 and controls the amount of the signal coupled from the second clock terminal CKB to the second node N2 so that the potential of the second node N2 can be lower than the potential of the first node N1. When the potential of the second node N2 is lower than the potential of the first node N1, the potential of the first node N1 is pulled down by the filtering module 300, so that the potential of the first node N1 can be maintained within an enable level range less than or equal to the low level vgl.

[0074] For example, Figure 6As shown, the charge pump unit 130 can include a first capacitor C1, a first pole of the first capacitor C1 being electrically connected with the second clock terminal CKB, and a second pole of the first capacitor C1 being electrically connected with the second node N2.

[0075] Wherein, when the potential of the second node N2 is controlled by the second node control unit 120, the first clock signal ck1 of the first clock terminal CK is at the enable level vgl, and the second clock signal ck2 of the second clock terminal CKB is at the non-enable level vgh, i.e. the first pole of the first capacitor C1 is kept at the non-enable level of the second clock signal ck2, and the potential of the second pole of the first capacitor C1 and the second node N2 can be equivalent to the potential of the first node N1, for example, the potential of the second node N2 is Va; and when the potential of the second node N2 is no longer controlled by the second node control unit 120, the first clock signal ck1 of the first clock terminal CK is at the non-enable level vgh, and the second clock signal ck2 of the second clock terminal CKB is at the enable level vgl, i.e. the second clock terminal CKB jumps from the non-enable level vgh to the enable level vgl, so that the voltage variation ΔV of the first pole of the first capacitor C1 is -(vgh-vgl), and due to the coupling effect of the first capacitor C1, the voltage of the second pole of the first capacitor C1 will change by ΔV, i.e. the potential of the second node N2 will change by ΔV, at this time, the potential of the second node N2 will be reduced to Va-(vgh-vgl), so that the potential of the second node N2 Va-(vgh-vgl) is lower than the potential of the first node N1 Va, and the filtering transistor M300 of the filtering module 300 is turned on, so that the potential of the first node N1 approaches the potential of the second node N2, so that the potential of the first node N1 will not change to the non-enable level over time, thereby being able to maintain the potential of the first node N1 in the range of less than or equal to the non-enable level for a long time, and further being able to improve the stability of the potential of the first node N1.

[0076] It should be noted that, Figure 6 The charge pump unit 130 is only exemplarily shown to include the first capacitor C1, and in the embodiment of the present application, the charge pump unit 130 can also include other active and / or passive devices, and the structure of the charge pump unit 130 is not specifically limited in the embodiment of the present application as long as the charge pump unit 130 can function. Correspondingly, the first node control unit 110 and the second node control unit 130 in the first control module 100 can also include active devices and / or passive devices, which are not specifically limited in the embodiment of the present application. The active devices include transistors and the like, and the passive devices include but are not limited to capacitors, resistors, inductors and the like. The embodiment of the present application will be exemplarily described below based on typical examples of the first node control unit 110 and the second node control unit 130.

[0077] Optionally, continuing to refer toFigure 6 The first node control unit 110 comprises a first transistor M1, a gate of the first transistor M1 is electrically connected with the first clock end CK, a first pole of the first transistor M1 is electrically connected with the signal input end IN, and a second pole of the first transistor M1 is electrically connected with the first node N1. In this way, the first clock signal ck1 of the first clock end CK can control the first transistor M1 to be turned on or turned off, so as to transmit the input signal Vin of the signal input end IN to the first node N1 when the first transistor M1 is in the turned-on state.

[0078] The first transistor M1 can be a P-channel transistor or an N-channel transistor. When the first transistor M1 is a P-channel transistor, the enabled level of the first clock signal ck1 is a low level vgl capable of controlling the first transistor M1 to be in the turned-on state, and the disabled level of the first clock signal ck1 is a high level vgh capable of controlling the first transistor M1 to be in the turned-off state; when the first transistor M1 is an N-channel transistor, the enabled level of the first clock signal ck1 is a high level vgh capable of controlling the first transistor M1 to be in the turned-on state, and the disabled level of the first clock signal ck1 is a low level vgl capable of controlling the first transistor M1 to be in the turned-off state.

[0079] As shown in Figure 6 , taking the first transistor M1 as a P-channel transistor as an example, when the first clock signal ck1 is at the low level vgl, the first transistor M1 is turned on, and the input signal Vin of the signal input end IN is transmitted to the first node N1; when the first clock signal ck1 is at the high level vgh, the first transistor M1 is turned off, and the input signal Vin of the signal input end IN cannot be transmitted to the first node N1.

[0080] Optionally, continuing to refer to Figure 6 , when the second node control unit 120 is also electrically connected with the signal input end IN and is configured to provide the input signal in to the second node N2 according to the first clock signal ck1, the second node control unit 120 can comprise a second transistor M2, a gate of the second transistor M2 is electrically connected with the first clock end CK, a first pole of the second transistor M2 is electrically connected with the signal input end IN, and a second pole of the second transistor M2 is electrically connected with the second node N2. In this way, the second transistor M2 can also be turned on or turned off under the control of the first clock signal ck1 of the first clock end CK, and when the second transistor M2 is in the turned-on state, the input signal Vin of the signal input end IN can be transmitted to the second node N2.

[0081] The channel type of the second transistor M2 is the same as that of the first transistor M1, that is, when the first transistor M1 is an N-channel transistor, the second transistor M2 is also an N-channel transistor, and when the first transistor M1 is a P-channel transistor, the second transistor M2 is also a P-channel transistor, so that when the first clock signal ck1 is an enable level, the first transistor M1 and the second transistor M2 can be simultaneously controlled to be in a conductive state, so that the input signal of the signal input terminal IN is transmitted to the first node N1 and the second node N2 through the first transistor M1 and the second transistor M2, respectively; and when the first clock signal ck1 is a non-enable level, the first transistor M1 and the second transistor M2 are simultaneously controlled to be in a closed state, and the input signal of the signal input terminal IN cannot be transmitted to the first node N1 and the second node N2, and the first node N1 and the second node N2 are maintained stable under the common control of the charge pump unit 130 and the filtering module 300.

[0082] Optionally, with reference to Figure 5 , the output module 400 can include a first output unit 410 and a second output unit 420; the first output unit 410 is electrically connected with the first node N1, the first level terminal VGL and the signal output terminal OUT, respectively; the first output unit 410 is used for controlling the signal output terminal OUT to output an enable level of the light-emitting control signal EM according to the potential of the first node N1; the second output unit 420 is electrically connected with the third node N3, the second level terminal VGH and the signal output terminal OUT, respectively; the second output unit 420 is used for controlling the signal output terminal OUT to output a non-enable level of the light-emitting control signal EM according to the potential of the third node N3.

[0083] Specifically, the first output unit 410 can control the transmission path of the first level signal Vgl of the first level terminal VGL to the signal output terminal OUT under the control of the potential of the first node N1, and when the potential of the first node N1 is an enable level of the first output unit 410, the first output unit 410 can transmit the first level signal Vgl to the signal output terminal OUT, so that the signal output terminal OUT outputs an enable level of the light-emitting control signal EM. The second output unit 420 can control the transmission path of the second level signal Vgh of the second level terminal VGH to the signal output terminal OUT under the control of the potential of the third node N3, and when the potential of the third node N3 is an enable level of the second output unit 420, the second output unit 420 can transmit the second level signal Vgh to the signal output terminal OUT, so that the signal output terminal OUT outputs a non-enable level of the light-emitting control signal EM.

[0084] For example, Figure 6As shown, the first output unit 410 may include a first output transistor M410, and the second output unit 420 may include a second output transistor M420; the gate of the first output transistor M410 is electrically connected to the first node N1, the first electrode of the first output transistor M410 is electrically connected to the first level terminal VGL, and the second electrode of the first output transistor M410 is electrically connected to the signal output terminal OUT; the gate of the second output transistor M420 is electrically connected to the third node N3, the first electrode of the second output transistor M420 is electrically connected to the second level terminal VGH, and the second electrode of the second output transistor M420 is electrically connected to the signal output terminal OUT. In this manner, the first output transistor M410 can be turned on or off under the control of the potential of the first node N1, and the second output transistor M420 can be turned on or off under the control of the third node N3. In this case, when the signal output terminal OUT needs to output the enable level of the light-emission control signal EM, the potential of the first node N1 can control the first output transistor M410 to be in a conductive state, and when the signal output terminal OUT needs to output the disable level of the light-emission control signal EM, the potential of the third node N3 can control the second output transistor M420 to be in a conductive state. The first output transistor M410 can be either an N-channel transistor or a P-channel transistor; similarly, the second output transistor M420 can be either an N-channel transistor or a P-channel transistor, and this is not specifically limited in this embodiment of the present invention.

[0085] For example, taking the first transistor M1, the second transistor M2, the first output transistor M410 and the second output transistor M420 as P-channel transistors, Figure 7 is with Figure 6 The corresponding driving timing diagram of a light emitting control circuit, combined with reference Figure 6 and Figure 7 In the stage t1, the input signal Vin is at a high level, the first clock signal ck1 is at a high level vgh, the first transistor M1 and the second transistor M2 are both turned off, and the high-level input signal Vin cannot be transmitted to the first node N1 and the second node N2. At this time, under the coordinated action of the first capacitor C1 and the filtering module 300, the potentials of the first node N1 and the second node N2 may jump to a low level, but the potential of the third node N3 is controlled by the second control module 200, and the second output transistor M420 is controlled by the potential of the third node N3, so that the second level signal Vgh can be transmitted to the signal output terminal OUT through the second output transistor M410, and the signal output terminal OUT is controlled to output the non-enable level of the light-emitting control signal EM.

[0086] At the t2 stage, the input signal Vin is at a high level, the first clock signal ck1 is at a low level vgl, the first transistor M1 and the second transistor M2 are both turned on, and the high-level input signal Vin can be transmitted to the first node N1 and the second node N2 respectively. At this time, the potentials of the first node N1 and the second node N2 are both at a high level, the first output transistor M410 cannot transmit the first-level signal Vgl at the first level end VGL to the signal output end OUT under the control of the high-level first node N1, at this time, the potential of the third node N3 is controlled by the second control module 200, and the second output transistor M420 is controlled by the potential of the third node N3, so that the non-enabled level of the light-emitting control signal EM output by the signal output end OUT can be controlled.

[0087] At the t3 stage, the input signal Vin is at a low level, the first clock signal ck1 is at a high level vgh, the first transistor M1 and the second transistor M2 are both turned off, at this time, the potential of the third node N3 is controlled by the second control module 200, and the second output transistor M420 is controlled by the potential of the third node N3, so that the non-enabled level of the light-emitting control signal EM output by the signal output end OUT can be controlled.

[0088] At the t4 stage, the input signal Vin is still at a low level, the first clock signal ck1 is again at a low level vgl, the first transistor M1 and the second transistor M2 are turned on, and the input signal Vin is transmitted to the first node N1 and the second node N2 through the first transistor M1 and the second transistor M2 respectively, so that the potentials of the first node N1 and the second node N2 are equivalent to the input signal Vin, that is, the potentials of the first node N1 and the second node N2 change from a high level to a low level, and the first output transistor M410 can transmit the first-level Vgl at the first level end VGL to the signal output end OUT under the control of the low-level first node N1, so that the signal output end OUT starts to output the enabled level of the light-emitting control signal EM; at this time, the potential of the first pole of the first capacitor C1 is consistent with the high level vgh of the second clock signal ck2, and the potential of the second pole of the first capacitor C1 is consistent with the potential of the second node N2; at the same time, since the potentials of the first node N1 and the second node N2 are equivalent, the filtering transistor M300 of the filtering module 300 is in an off state.

[0089] In the t5 stage, the input signal in is still low, the first clock signal ck1 becomes high vgh, the first transistor M1 and the second transistor M2 are both closed; at this time, the second clock signal ck2 jumps from the high vgh in the t4 stage to the low vgl, so that the potential of the first pole of the first capacitor C1 changes by -(vgh-vgl), and due to the coupling effect of the first capacitor C1, the potential of the second node N2 will change by -(vgh-vgl), so that the potential of the second node N2 changes from being equivalent to the potential of the first node N1 to being lower than the potential of the first node N1 (vgh-vgl), thereby meeting the conduction condition of the filtering transistor M300 in the filtering module 300; and when the filtering transistor M300 is turned on, the filtering transistor M300 can pull the potential of the first node N1 to be equivalent to the potential of the second node N2, so that the first output transistor M410 keeps transmitting the first level signal Vgl of the first level end VGL to the signal output end OUT under the control of the lower potential of the first node N1, thereby making the signal output end OUT keep outputting the enable level of the light-emitting control signal EM.

[0090] After the t5 stage, as long as the input signal in remains low, the potential of the first node N1 will alternate between the low level and the lower level with the alternating changes of the first clock signal ck1 and the second clock signal ck2, thereby enabling the signal output end OUT to stably and continuously output the enable level of the light-emitting control signal EM, and further enabling the pixels in the display panel to stably and continuously emit light, thereby improving the display effect of the display panel.

[0091] To ensure that the potential of the third node N3 can control the second output transistor M420 to be in the on state in the t1-t3 stage, or even a longer stage, the second output unit 420 can further include a capacitor C400, which is electrically connected between the second level end VGH and the third node N3, to store the potential of the third node N3 and maintain the stability of the potential of the third node N3.

[0092] It can be understood that in the t4 stage, the t5 stage, and other stages after the t5 stage, by controlling the first node N1 to remain low, the output module 300 can accurately transmit the first level signal Vgl of the first level end VGL, so that the signal output end OUT can stably output the enable level of the light-emitting control signal EM. However, due to the existence of free electrons in the transistor, even when the transistor is in the off state, there will be a small current flowing through the first pole and the second pole of the transistor, that is, when the first transistor M1 is in the off state, there will be a small current flowing through the first transistor M1, which will affect the potential of the first node N1.

[0093] In an optional embodiment,Figure 8 A structure diagram of another light-emitting control circuit provided by an embodiment of the present application is shown in FIG. 4. As shown in FIG. 4, the first transistor M1 can include a first sub-transistor M11 and a second sub-transistor M12. The first electrode of the first sub-transistor M11 is electrically connected with the signal input terminal IN, the second electrode of the first sub-transistor M11 is electrically connected with the first electrode of the second sub-transistor M12, and the second electrode of the second sub-transistor M12 is electrically connected with the first node N1. The gate of the first sub-transistor M11 and the gate of the second sub-transistor M12 are both electrically connected with the first clock terminal CK. At this time, the first transistor M1 is a double-gate transistor composed of the first sub-transistor M11 and the second sub-transistor M12, and both the first sub-transistor M11 and the second sub-transistor M12 can be turned on or turned off under the control of the first clock signal ck1 of the first clock terminal CK. When the first clock signal ck1 of the first clock terminal CK controls the first sub-transistor M11 and the second sub-transistor M12 to be in the turned-off state, the first transistor M1 can have a smaller leakage current, thereby being able to reduce the influence of the leakage current on the potential of the first node N1 when the first transistor M1 is in the turned-off state, and further being able to stabilize the potential of the first node N1 and improve the stability of the light-emitting control signal EM output by the signal output terminal OUT. Figure 8

[0094] Optionally, continuing to refer to FIG. 4, the second transistor M2 can also include a third sub-transistor M21 and a fourth sub-transistor M22. The first electrode of the third sub-transistor M21 is electrically connected with the signal input terminal IN, the second electrode of the third sub-transistor M21 is electrically connected with the first electrode of the fourth sub-transistor M22, the second electrode of the fourth sub-transistor M22 is electrically connected with the second node N2, and the gate of the third sub-transistor M21 and the gate of the fourth sub-transistor M22 are both electrically connected with the first clock terminal CK. At this time, the second transistor M2 is also a double-gate transistor composed of the third sub-transistor M21 and the fourth sub-transistor M22, so as to have a smaller leakage current when the second transistor M2 is in the turned-off state, thereby being able to improve the problem that the leakage current influences the potential of the second node N2, improve the stability of the potential of the second node N2, and also be able to improve the stability of the light-emitting control signal EM output by the signal output terminal OUT. Figure 8

[0095] For the convenience of description of the drawings and technical solutions, without special description, the transistors in the first node control unit and the second node control unit are taken as single-gate transistors as an example, and the technical solutions of the embodiments of the present application are exemplarily described.

[0096] It can be understood that the above description of the working condition of the first control module is exemplarily described by taking the second node control unit 120 as an example which is directly electrically connected with the signal input terminal IN, and the connection mode of the second node control unit is not limited to this in the embodiments of the present application.​​

[0097] Optional, Figure 9 A structural diagram of another light emitting control circuit provided by an embodiment of the present invention is shown. Figure 9 and Figure 5 The similarities can be found in the above Figure 5 Description of Figure 9 and Figure 5 The differences are exemplified. Figure 9 As shown, the second node control unit 120 can also be electrically connected to the first clock terminal CK, the first level terminal VGL, and the first node N1 respectively, so that it can provide the first level signal vgl to the second node N2 according to the first clock signal ck1 and the potential of the first node N1.

[0098] Specifically, when the light-emitting control circuit is the first-level light-emitting control circuit in the light-emitting driver, the input signal Vin of the signal input terminal IN is the light-emitting control start pulse signal, which is provided by the timing controller; and when the light-emitting control circuit is the other-level light-emitting control circuit in the light-emitting driver, the input signal Vin of its signal input terminal IN is the light-emitting control signal output by the signal output terminal of the previous-level light-emitting control circuit of the current-level light-emitting control circuit. Since the potential of the second node N2 to which one end of the second node control unit 120 is electrically connected is a signal that changes with the jump of the second clock signal ck2, and the change of the second node N2 may affect the oscillation of the signals at other ends of the second node control unit 120; therefore, by electrically connecting the second node control unit 120 to the first clock end CK, the first level end VGL, and the first node N1 respectively, so that the second node control unit 120 is not directly electrically connected to the signal input end IN, it is possible to improve the influence of the potential change of the second node N2 on the input signal Vin of the signal input end IN, and also reduce the load capacity of the signal input end IN, so that when the input signal Vin is the light-emitting control signal output by the signal output end of the upper-level light-emitting control circuit, it is possible to improve the accuracy and stability of the light-emitting control signal output by the upper-level light-emitting control circuit. At the same time, the second node control unit 120 is controlled by the potential of the first node N1. Under the control of the first clock signal ck1 and the potential of the first node N1, the second node control unit 120 transmits the first level signal Vgl to the second node N2, so that the potential of the second node N2 will not be directly affected by the input signal Vin, thereby ensuring the potential accuracy and stability of the second node N2 of the current level light-emitting control circuit.

[0099] Optional, Figure 10 A structural diagram of another light emitting control circuit provided by an embodiment of the present invention is shown. Figure 10 and Figure 6 The similarities can be found in the aboveFigure 6 Description of Figure 10 and Figure 6 The differences are exemplarily described. Figure 10 As shown, the second node control unit 120 may include a third transistor M3 and a fourth transistor M4; a first electrode of the third transistor M3 is electrically connected to the first level terminal VGL, a second electrode of the third transistor M3 is electrically connected to the first electrode of the fourth transistor M4, and a second electrode of the fourth transistor M4 is electrically connected to the second node N2; a gate of the third transistor M3 is electrically connected to the first node N1, and a gate of the fourth transistor M4 is electrically connected to the first clock terminal CK.

[0100] In this way, the third transistor M3 can be turned on or off under the control of the potential of the first node N1, and the fourth transistor M4 can be turned on or off under the control of the first clock signal ck1, and when the third transistor M3 and the fourth transistor M4 are turned on at the same time, the first level Vgl can be transmitted to the second node N2 through the third transistor M3 and the fourth transistor M4 in sequence.

[0101] For example, the first node control unit 110 includes a first transistor M1, and the first transistor M1, the third transistor M3, and the fourth transistor M4 are all PMOS transistors. When the first clock signal ck1 is at a low level vgl, the first transistor M1 and the fourth transistor M4 are turned on, and the input signal Vin is transmitted to the first node N1 through the turned-on first transistor M1. If the input signal Vin is also at a low level at this time, the third transistor M3 will be turned on under the control of the low-level input signal Vin, so that the first-level signal Vgl is transmitted to the second node N2 through the third transistor M3 and the fourth transistor M4 in sequence, so that the potential of the second node N2 and the potential of the first node N1 are both at a low level; and when the first clock signal ck1 is at a high level, the first transistor M1 and the fourth transistor M4 are turned on. When the charge pump unit 130 and the second clock signal ck2 are controlled by the charge pump unit 130, the potential of the first node N2 can be reduced. When the potential of the second node N2 is reduced, the potential of the first node N1 can be pulled down by the filter module 300, so that the potential of the first node N1 is at a lower level. Therefore, the output module 400 can accurately and quickly transmit the first-level signal Vgl to the signal output terminal OUT under the control of the potential of the first node N1 with a lower level, so that the signal output terminal OUT can stably output the enable level of the light-emitting control signal EM.

[0102] In addition, when the first clock signal ck1 is at low level and the input signal Vin is at high level, the high level input signal Vin is transmitted to the first node N1 through the first transistor M1, so that the potential of the first node N1 controls the third transistor M3 to be in the off state, and the first level signal Vgl cannot be transmitted to the second node N2; at this time, the second node N2 is equivalent to the second clock signal ck2, that is, the second node N2 is at the high level of the second clock signal ck2, so that the potentials of the first node N1 and the second node N2 can both be at high level. When the first clock signal ck1 is at high level and the input signal Vin is at high level, the first transistor M1 and the third transistor M3 are both in the off state, and the first level signal Vgl also cannot be transmitted to the second node N2; at this time, the second node N2 will still change with the change of the second clock signal ck2.

[0103] Therefore, when the second node control unit 120 is electrically connected to the first node N1 without being directly electrically connected to the signal input end IN, by making the second node control unit 120 include the third transistor M3 and the fourth transistor M4, the influence of the potential change of the second node N2 on the input signal Vin of the signal input end IN can be improved, and the load capacity of the signal input end IN can be reduced under the premise that the same function as when the second node control unit 120 is directly electrically connected to the signal input end IN can be achieved. It should be noted that, since the second node control unit 120 is directly electrically connected to the first node N1 or not, they both have similar functions, therefore, for the convenience of description, the following will be exemplarily described by taking the second node control unit 120 as being directly electrically connected to the signal input end IN without special description.

[0104] It can be understood that when the first output unit 410 of the output module 400 comprises a first output transistor M410, due to the characteristics of the transistor, the first level signal Vgl of the first level terminal VGL will become Vgl-Vth4 (Vth4 is the threshold voltage of the first output transistor M410) after being transmitted via the first output transistor M410, which makes the enable level of the light-emitting control signal EM of the signal output end OUT of the light-emitting control circuit of the previous stage received by the signal input end IN of the light-emitting control circuit of the current stage not the first level signal Vgl, but Vgl-Vth4, that is, the input signal Vin is Vgl-Vth4; and when the first node control unit 110 comprises a first transistor M1, the input signal Vin of the signal input end IN is transmitted to the first node N1 via the first transistor M1, and the potential of the first node N1 is Vin-Vth1 (Vth1 is the threshold voltage of the first transistor M1). When the first transistor M1 and the first output transistor M410 are N-channel transistors, and Vth1=Vth4=Vth, Vth is a positive value, the enable level of the input signal Vin is high, and the potential of the first node N1 is 2Vth lower than the first level signal Vgl, which will make the first output transistor M410 unable to be in a normal conduction state, and the first level signal Vgl of the first level terminal VGL cannot be accurately transmitted to the signal output end OUT, so that when the light-emitting control signal output by the signal output end OUT jumps from the non-enable level to the enable level, a jump step occurs, and the light-emitting control signal cannot directly jump to the enable level, which will affect the light-emitting stability of the pixels in the display panel; when the first transistor M1 and the first output transistor M410 are P-channel transistors, and Vth1=Vth4=Vth, Vth is a negative value, the enable level of the input signal Vin is low, and the potential of the first node N1 is 2|Vth| higher than the first level signal Vgl, so that the first output transistor M410 cannot be in a normal conduction state, which also makes the potential of the first node N1 unable to accurately control the first output transistor M410 to transmit the first level signal Vgl of the first level terminal VGL to the signal output end OUT, so that when the light-emitting control signal output by the signal output end OUT jumps from the non-enable level to the enable level, a jump step occurs, and the light-emitting control signal cannot directly jump to the enable level, which affects the light-emitting stability of the pixels in the display panel.

[0105] Exemplary, Figure 11 is a signal simulation diagram corresponding to a light-emitting control circuit of the related art, as Figure 11The first output transistor in the previous light-emitting control circuit has a threshold voltage Vth, so that when the signal output end OUT of the previous light-emitting control circuit starts to output the enable level of the light-emitting control signal, a falling edge step occurs due to the threshold voltage of the first output transistor in the previous light-emitting control circuit, and the light-emitting control signal at the falling edge step is Vgl+|Vth|, that is, the input signal Vin received by the signal input end of the current light-emitting control circuit has a falling edge step. After the input signal Vin passes through the first transistor, the step height of the falling edge step is further increased due to the first transistor, the potential Vn1' of the first node becomes Vgl+2*|Vth|, so that the potential Vn1' of the first node cannot control the first output transistor to normally turn on, thereby the light-emitting control signal EM' output by the current light-emitting control circuit also has a falling edge step, which further affects the accuracy of the light-emitting control signal output by the light-emitting control circuit.

[0106] To solve the above problems, optionally, Figure 12 Another structure diagram of a light-emitting control circuit is provided for the embodiment of the present application, as shown in Figure 12 The light-emitting control circuit 30 further includes a bootstrap module 500; the bootstrap module 500 is electrically connected between the signal output end OUT and the first node N1; the bootstrap module 500 is used to control the potential of the first node N1 according to the light-emitting control signal of the signal output end OUT, so that when the light-emitting control signal EM output by the signal output end OUT changes, the bootstrap module 500 drives the first node N1 to change accordingly, thereby ensuring that the potential of the first node N1 can accurately control the output module 400 to transmit the first level signal Vgl to the signal output end OUT, so that the signal output end OUT can stably and accurately output the light-emitting control signal EM, and the situation that the signal output end OUT jumps when changing from the non-enable level to the enable level is improved, thereby the light-emitting stability of the pixels in the display panel can be improved.

[0107] Optionally, continuing to refer to Figure 12 The bootstrap module 500 can include a bootstrap capacitor C500; the first pole of the bootstrap capacitor C500 is electrically connected with the signal output end OUT, and the second pole of the bootstrap capacitor C500 is electrically connected with the first node N1.

[0108] For example, the first node control unit 110 includes the first transistor M1, the output module 400 includes the first output transistor M410, and the first transistor M1 and the first output transistor M410 are both P-channel transistors, for example, in combination with reference to Figure 11 and Figure 7In the t4 stage, when the first clock signal ck1 is at low level and the output signal Vin is also at low level, the first transistor M1 is turned on, the input signal Vin is input to the first node N1, so that the potential of the first node N1 becomes Vgl+2|vth|, at this time, the first output transistor M410 is between the on state and the off state, so that the first level signal Vgl of the first level end VGL starts to be transmitted to the signal output end OUT, so that the light-emitting control signal EM output by the signal output end OUT changes from high level in the t3 stage to low level, and due to the coupling effect of the bootstrap capacitor C500, the potential of the first node N1 changes with the potential of the signal output end OUT, that is, the potential of the first node N1 decreases, so that the potential of the first node N1 is sufficient to control the first output transistor M410 to be in the fully on state, and the first output transistor M410 can accurately transmit the first level signal Vgl to the signal output end OUT, so that the signal output end OUT accurately outputs the enable level of the light-emitting control signal EM, thereby improving the problem that the light-emitting control signal EM output by the signal output end OUT appears a jump step because the potential of the first node N1 is insufficient to control the first output transistor M410 to be in the fully on state, and further improving the display stability of the display panel when the light-emitting control signal EM is used to control the pixels in the display panel to emit light.

[0109] Exemplary, Figure 13 is a signal simulation diagram corresponding to the light-emitting control circuit shown in Figure 12 FIG. 1, Figure 12 and Figure 13When the input signal Vin received at the signal output end IN of the light-emitting control circuit 310 becomes low and the first clock signal ck is at the enable level, the input signal Vin is transmitted to the first node N1 through the first transistor M1 and to the second node N2 through the second transistor M2; at this time, the potential Vn1 of the first node N1 and the potential Vn2 of the second node N2 drop, the first level signal Vgl is transmitted to the signal output end OUT, and the light-emitting control signal EM output by the signal output end OUT jumps to the enable level, the bootstrap module 500 generates a bootstrap effect, the potential Vn1 of the first node N1 further drops, and the potential Vn1 of the first node N1 can be lower than the input signal Vin, for example, the potential Vn1 of the first node N1 is lower than the first level signal Vgl, so that the potential of the first node N1 can control the first output transistor M410 to normally turn on and accurately output the light-emitting control signal EM, eliminating the step of the falling edge of the light-emitting control signal EM, and the potential Vn2 of the second node N2 remains at Vin+Vth, so that the filter module does not conduct, and the potential Vn2 of the second node N2 does not affect the potential Vn1 of the first node N1; when the first clock signal ck jumps to the non-enable level and the second clock signal ckb jumps to the enable level, the potential of the second node N2 changes with the change of the second clock signal ckb due to the existence of the charge pump unit 130, and the potential Vn2 of the second node N2 drops; when the potential Vn2 of the second node N2 drops to be lower than the potential Vn1 of the first node N1, the filter module 300 conducts, so that the potential Vn1 of the first node N1 approaches the potential Vn2 of the second node N2, i.e., the potential Vn1 of the first node N1 further drops; when the first clock signal ck again becomes the enable level, the potential Vn1 of the first node N1 will have a rising trend under the joint action of the input signal Vin transmitted by the first transistor M1 and the bootstrap module 500, but its rising potential is limited, so that the potential Vn1 of the first node N1 can remain at a lower potential; and the potential of the second node N2 will again become Vin+Vth under the action of the input signal Vin transmitted by the second transistor M2, and only when the second clock signal ckb jumps to the enable level next time, the potential Vn2 of the second node N2 will drop under the action of the charge pump unit 130.Thus, the connection node between the charge pump unit 130 and the gate of the first output transistor M410 is divided into the first node N1 and the second node N2 by using the filtering module 300, so that the potential of the first node N1 directly connected with the first output transistor M410 can be kept as a lower potential, the falling edge step problem of the potential Vn1 of the first node N1 and the falling edge step problem of the output light-emitting control signal EM are eliminated or improved, so that the first output transistor M410 can keep a normal conduction state, the signal output terminal OUT can stably and accurately output the light-emitting control signal EM, and the potential Vn1 of the second node N2 directly connected with the charge pump unit 130 changes with the second clock signal ckb, which is used to eliminate the bias state of a specific transistor.

[0110] Optionally, Figure 14 A structure diagram of still another light-emitting control circuit provided by the embodiment of the present application is shown in FIG. 6, which is based on the above-mentioned embodiment and further comprises an interlocking module 600. Figure 14 The interlocking module 600 is electrically connected with the first node N1, the third node N3, the second level terminal VGH and the second control module 200, respectively, and is used to control the transmission of the second level signal Vgh to the first node N1 under the control of the second control module 200 and control the transmission of the second level signal Vgh to the third node N3 under the control of the potential of the first node N1.

[0111] Specifically, when the signal output OUT needs to output the enable level of the light-emitting control signal EM, the potential of the first node N1 should be the enable level capable of controlling the output module 400 to transmit the first level signal Vgl to the signal output OUT, at this time, in order to ensure the accuracy of the enable level of the light-emitting control signal EM output by the signal output OUT, the potential of the third node N3 should be the non-enable level incapable of controlling the output module 400 to transmit the second level signal Vgh to the signal output OUT; when the signal output OUT needs to output the non-enable level of the light-emitting control signal EM, the potential of the third node N3 should be the enable level capable of controlling the output module 400 to transmit the second level signal Vgh to the signal output OUT, at this time, in order to ensure the accuracy of the non-enable level of the light-emitting control signal EM output by the signal output OUT, the potential of the first node N1 should be the non-enable level incapable of controlling the output module 400 to transmit the first level signal Vgl to the signal output OUT. In this way, when the signal output OUT needs to output the enable level of the light-emitting control signal EM, the interlocking module 600 transmits the second level signal Vgh to the third node N3 under the control of the potential of the first node N1, so that the potential of the third node N3 remains the non-enable level; and when the signal output OUT needs to output the non-enable level of the light-emitting control signal EM, the interlocking module 600 transmits the second level signal Vgh to the first node N1 under the control of the second control module 200, so that the potential of the first node N1 remains the non-enable level, thereby clamping the potential of the first node N1 and the potential of the third node N3 with each other, ensuring the orderly work of the light-emitting control circuit 310 and improving the accuracy and stability of the light-emitting control signal EM output by the light-emitting control circuit 310.

[0112] Optionally, Figure 15 A structure diagram of still another light-emitting control circuit provided by the embodiment of the present application is shown in FIG. 6. Figure 15As shown, the interlocking module 600 includes a seventh transistor M7 and an eighth transistor M8; the gate of the seventh transistor M7 is electrically connected with the second control module 200, the first electrode of the seventh transistor is electrically connected with the second level terminal VGH, the second electrode of the seventh transistor M7 is electrically connected with the first node N1; the gate of the eighth transistor M8 is electrically connected with the first node N1, the first electrode of the eighth transistor M8 is electrically connected with the second level terminal VGH, the second electrode of the eighth transistor M8 is electrically connected with the third node N3. In this way, the seventh transistor M7 can be turned on or off under the control of the second control module 200, and when it is turned on, the second level signal Vgh is transmitted to the first node N1; the eighth transistor M8 can be turned on or off under the control of the potential of the first node N1, and when it is turned on, the second level signal Vgh is transmitted to the third node N3, realizing the mutual clamping of the first node N1 and the third node N3, so that the first output transistor M410 controlled by the potential of the first node N1 and the second output transistor M420 controlled by the third node N3 will not be turned on at the same time when the output module 400 includes the first output transistor M410 and the second output transistor M420, so that a path will not be formed from the second level terminal VGH to the first level terminal VGL, preventing the short circuit of the second level terminal VGH and the first level terminal VGL, thereby preventing flicker of the display panel when displaying and emitting light. Wherein, the seventh transistor M7 and the eighth transistor M8 can be N-channel transistors or P-channel transistors, which can be designed as needed, and the embodiments of the present application do not make specific limitations thereto.

[0113] Optionally, with reference to Figure 14 , the second control module 200 can include a third node control unit 230, a fourth node control unit 240 and a fifth node control unit 250; the third node control unit 230 is electrically connected with the third node N3 and the first level terminal VGL respectively, and the third node control unit 230 is also electrically connected with the fourth node control unit 240 at the fourth node N4; the third node control unit 230 is used to control the potential of the third node N4 according to the potential of the fourth node N4 and the first level signal vgl; the fourth node control unit 240 is electrically connected with the second clock terminal CKB, the second level terminal VGH and the first clock terminal CK respectively, and the fourth node control unit 240 is also electrically connected with the fifth node control unit 250 at the fifth node N5; the fourth node control unit 240 is used to control the potential of the fourth node N4 according to the potential of the fifth node N5, the second clock signal ck2, the first clock signal ck1 and the second level signal Vgh; the fifth node control unit 250 is electrically connected with the first control module 100 and the first clock terminal CK respectively; the fifth node control unit 250 is used to control the potential of the fifth node N5 under the control of the first control module 100 and the first clock signal ck1.

[0114] Specifically, the fifth node control unit 250 can control the transmission path of the first clock signal ck1 to the fifth node N5 under the control of the first control module 100 and the first clock signal ck1; the fourth node control unit 240 controls the transmission path of the second clock signal ck2 or the second level signal Vgh to the fourth node N4 under the control of the potential of the fifth node N5 and the first clock signal ck1; the third node control unit 230 controls the transmission path of the first level signal Vgl to the third node N3 under the control of the fourth node N4.

[0115] Wherein, since the potential of the first node N1 is the enable level, the potential of the third node N3 needs to be the non-enable level, that is, when the first node N1 is the enable level, the third node control unit 230 should not be able to transmit the first level signal Vgl to the third node N3, at this time, the potential of the fourth node N4 should be the non-enable level to control the third node control unit 230 to not transmit the first level signal Vgl to the third node N3, that is, at this time, the fourth node control unit 240 needs to transmit the non-enable level of the second clock signal ck2 or the second level signal Vgh to the fourth node, at this time, the potential of the fifth node N5 or the first clock signal ck1 should be the enable level, therefore, during this period, the fifth node control unit 250 controlled by the first control module 100 and the first clock signal ck1 should transmit the enable level of the first clock signal ck1 to the fifth node N5, so that the potential of the fifth node N5 is sufficient to control the fourth node control unit 240 to transmit the non-enable level of the second clock signal ck2 or the second level signal Vgh.

[0116] In an optional embodiment, continuing to refer to Figure 14 , the first control module 100 can be electrically connected to the first node N1 with the second control module 200. At this time, the fifth node control unit 250 of the second control module 200 can control the transmission of the first clock signal ck1 to the fifth node N5 under the control of the potential of the first node N1, ensuring that when the potential of the first node N1 is the enable level, the potential of the third node N3 remains the non-enable level.

[0117] Optionally, continuing to refer to Figure 15 , the fifth node control unit 250 can include a fifth transistor M5 and a sixth transistor M6; the gate and the first electrode of the fifth transistor M5 are electrically connected to the first clock terminal CK, and the second electrode of the fifth transistor M5 is electrically connected to the fifth node N5; the gate of the sixth transistor M6 is electrically connected to the first control module 100, the first electrode of the sixth transistor M6 is electrically connected to the first clock terminal CK, and the second electrode of the sixth transistor M6 is electrically connected to the fifth node N5.

[0118] Specifically, the fifth transistor M5 can be turned on or turned off under the joint control of the first clock signal ck1 of the first clock terminal CK and the potential of the fifth node N5, and when the fifth transistor M5 is turned on, the first clock signal ck1 of the first clock terminal CK can be transmitted to the fifth node N5; the sixth transistor M6 can be turned on or turned off under the control of the potential of the first node N1 of the first control module 100, and when the sixth transistor M6 is turned on, the first clock signal ck1 of the first clock terminal CK can be transmitted to the fifth node N5. The fifth transistor M5 and the sixth transistor M6 can be N-channel transistors or P-channel transistors, which can be designed as needed, and the embodiments of the present application do not make specific limitations thereto.

[0119] Optionally, continuing to refer to Figure 15 , the fourth node control unit 240 can include a ninth transistor M9, a tenth transistor M10 and a second capacitor C2; the gate of the ninth transistor M9 is electrically connected with the fifth node N5; the first pole of the ninth transistor M9 is electrically connected with the second clock terminal CKB, and the second pole of the ninth transistor M9 is electrically connected with the fourth node N4; the gate of the tenth transistor M10 is electrically connected with the first clock terminal CK, the first pole of the tenth transistor M10 is electrically connected with the second level terminal VGH, and the second pole of the tenth transistor M10 is electrically connected with the fourth node N4; the first pole of the second capacitor C2 is electrically connected with the fifth node N5, and the second pole of the second capacitor C2 is electrically connected with the fourth node N4.

[0120] Specifically, the ninth transistor M9 is turned on or turned off under the control of the potential of the fifth node N5, and when the ninth transistor M9 is in the on state, the second clock signal ck2 can be transmitted to the fourth node N4; the tenth transistor M10 is turned on or turned off under the control of the first clock signal ck1, and when the tenth transistor M10 is in the on state, the second level signal Vgh can be transmitted to the fourth node N4; the second capacitor C2 can maintain the potential difference between the fifth node N5 and the fourth node N4. The ninth transistor M9 and the tenth transistor M10 can be N-channel transistors or P-channel transistors, which can be designed as needed, and the embodiments of the present application do not make specific limitations thereto.

[0121] Optionally, continuing to refer to Figure 15The third node control unit 230 can include an eleventh transistor M11; a gate of the eleventh transistor M11 is electrically connected with the fourth node N4; a first pole of the ninth transistor M9 is electrically connected with the first voltage level terminal VGL, and a second pole of the eleventh transistor M11 is electrically connected with the third node N3. In this way, the eleventh transistor M11 can be turned on or off under the control of the potential of the fourth node N4, and when the eleventh transistor M11 is in the on state, the first voltage level signal vgl can be transmitted to the third node N3. The eleventh transistor M11 can also be an N-channel transistor or a P-channel transistor, which can be designed as needed, and the embodiments of the present application do not make specific limitations thereto.

[0122] For example, in the light-emitting control circuit, each transistor is a P-channel transistor. FIG. 16 is a driving timing diagram of a corresponding light-emitting control circuit, which is combined with reference to FIG. 1 and FIG. 2. Figure 15 Figure 15 and Figure 16 In the t1' stage, the first clock signal ck1 is at a low level, the second clock signal ck2 is at a high level, and the input signal Vin is at a high level. The first transistor M1 and the second transistor M2 are both turned on, and the input signal Vin is transmitted to the first node N1 and the second node N2 through the first transistor M1 and the second transistor M2 respectively, so that the potential of the first node N1 and the potential of the second node N2 are both equivalent to the high level of the input signal Vin, and the first output transistor M410, the sixth transistor M6, and the eighth transistor M8 are all in the off state. At the same time, the fifth transistor M5 is in the on state under the control of the first clock signal ck1, and the fifth transistor M5 transmits the low level of the first clock signal ck1 to the fifth node N5, so that the potential of the fifth node N5 controls the ninth transistor M9 to be in the on state, and the high level of the second clock signal ck2 is transmitted to the fourth node N4 through the ninth transistor M9. At the same time, the tenth transistor M10 is also in the on state under the control of the first clock signal ck1, so as to transmit the second voltage level signal Vgh to the fourth node N4, so that the fourth node N4 remains at a high level, and the eleventh transistor M11 and the seventh transistor M7 are both in the off state, and cannot transmit the first voltage level signal Vgl to the third node N3. The second output transistor M420 is in the off state, and the signal output terminal OUT remains at the same enable level of the light-emitting control signal EM as in the last stage.

[0123] ​In the t2' stage, the first clock signal ck1 becomes high level, the second clock signal ck2 becomes low level, the input signal Vin is still high level, and the first transistor M1 and the second transistor M2 are both in the off state; due to the existence of the second capacitor C2, even if the fifth node N5 has no signal input, the ninth transistor M9 can be maintained in the on state, the low level of the second clock signal ck2 is transmitted to the fourth node M4 through the ninth transistor M9, so that the potential of the fourth node N4 controls the eleventh transistor M11 and the seventh transistor M7 to be in the on state respectively, the first level signal Vgl is transmitted to the third node N3 through the on seventh transistor M7, so that the second output transistor M420 is turned on, the second level signal Vgh is transmitted to the signal output end OUT through the second output transistor M420, so that the luminescence control signal EM output by the signal output end OUT jumps from the enable level to the non-enable level; at the same time, due to the on state of the seventh transistor M7, the second level signal Vgh is transmitted to the first node N1 through the seventh transistor M7, and the first node N1 remains high level; while the second node N2 will jump to low level with the jump of the second clock signal ck, at this time, although the on state of the filter transistor M300 can be met, but the seventh transistor M7 will provide the first node N1 with the first level signal Vgh, so that the first node N1 will not change to a lower potential due to the change of the second node N2, that is, the first node N1 remains high level, while the second node N2 jumps to low level.

[0124] At the t3' stage, the first clock signal ck1 becomes low again, the second clock signal ck2 becomes high again, the input signal Vin remains high, the first transistor M1 and the second transistor M2 are in the on state again, the input signal Vin is transmitted to the first node N1 and the second node N2 through the first transistor M1 and the second transistor M2 respectively, so that the potential of the first node N1 and the potential of the second node N2 are equivalent to the high level of the input signal Vin, the first output transistor M410, the sixth transistor M6 and the eighth transistor M8 are still in the off state; the fifth transistor M5 is in the on state under the control of the first clock signal ck1, the low-level first clock signal ck1 is transmitted to the fifth node N5 through the on fifth transistor M5 to supplement the signal of the fifth node N5, the ninth transistor M9 remains in the on state, the high level of the second clock signal ckb is transmitted to the fourth node N4 through the ninth transistor M9, and the tenth transistor M10 is also turned on under the control of the first clock signal ck to transmit the second level signal Vgh to the fourth node N4, so that the fourth node N4 changes from low to high, the seventh transistor M7 and the eleventh transistor M11 are turned off, the first node N1 is only controlled by the input signal Vin transmitted by the first transistor M1, the third node N3 remains at the low level of the previous stage, the second output transistor M420 remains in the on state, and the signal output end OUT remains at the non-enabled level of the output light emission control signal EM.

[0125] In the period of time after the t3' stage and before the t4' stage, the input signal Vin remains high, and the first clock signal ck and the second clock signal ckb change between high and low, so that the working process of the t2' stage and the t3' stage is repeated in this period of time; until the t4' stage, the input signal Vin becomes low, the first clock signal ck1 is high, the second clock signal ck2 is low, the first transistor M1 and the second transistor M2 remain in the off state, the potential of the second node N2 changes to low with the jump of the second clock signal ckb, and the potential of the first node N1 is controlled by the second level signal Vgh transmitted by the seventh transistor M7, so that the potential of the first node N1 remains high; the working states of the transistors in the second control module 200 and the working states of the first output transistor M410 and the second output transistor M420 are the same as those in the t2' stage, and the signal output end OUT remains at the enabled level of the output light emission control signal EM.

[0126] In the t5' stage, the input signal Vin remains at a low level, the first clock signal ck becomes low, the second clock signal ckb becomes high, the first transistor M1 and the second transistor M2 are in the on state, the low-level input signal Vin is transmitted to the first node N1 through the on first transistor M1, and is transmitted to the second node N2 through the on second transistor M2, so that the potentials of the first node N1 and the second node N2 are both Vin+Vth (Vth is the threshold voltage of the first transistor M1 and the second transistor M2), the first output transistor M410 is on to transmit the first-level signal Vgl to the signal output terminal OUT, so that the light-emitting control signal EM output by the signal output terminal OUT changes from the non-enabled level to the enabled level, that is, the light-emitting control signal EM changes from the high level to the low level, and due to the existence of the bootstrap capacitor C500, the potential of the first node N1 also decreases, the potential of the first node N1 changes to a voltage lower than Vin+Vth, so that the potential of the gate of the first output transistor M410 further decreases, the first output transistor M410 is further on, and the light-emitting control signal EM output by the signal output terminal OUT quickly changes to the non-enabled level; at the same time, the eighth transistor M8 is in the on state under the control of the potential of the first node N1, so that the second-level signal Vgh is transmitted to the third node N3 through the eighth transistor M8, so that the potential of the third node N3 becomes high, the second output transistor M420 is in the off state, and the second-level signal Vgh cannot be transmitted to the signal output terminal OUT through the second output transistor M420; the sixth transistor M6 is also in the on state under the control of the potential of the first node N1 to transmit the first clock signal ck to the fifth node N5, so that the ninth transistor M9 transmits the high level of the second clock signal ckb to the fourth node N4 under the control of the low level of the fifth node, and the tenth transistor M10 is in the on state under the control of the first clock signal ck to transmit the second-level signal Vgh to the fourth node N4, so that the potential of the fourth node N4 is high, and the eleventh transistor M11 is in the off state, and the potential of the third node N3 is only controlled by the second-level signal Vgh transmitted by the eighth transistor M8.

[0127] In the t6' stage, the input signal Vin remains low, the first clock signal ck becomes high, the second clock signal ckb becomes low, and the first transistor M1 and the second transistor M2 are in the off state; because the second clock signal ck of the second clock terminal CKB connected to the first pole of the first capacitor C1 jumps from the high level vgh to the low level vgl, the potential of the first pole of the first capacitor C1 drops by ΔV (ΔV = vgh-vgl), and due to the coupling effect of the first capacitor C1, the potential of the second node N2 also drops by ΔV, so that the potential of the second node N2 is lower than that of the first node N1, the filter transistor M300 is in the on state, and the potential of the first node N1 is pulled down to a lower level comparable to that of the second node N2 through the filter transistor M300, further controlling the on state of the first output transistor M410, the sixth transistor M6, and the eighth transistor M8, and further improving the speed of the first level signal Vgl transmitted by the first output transistor M410; at the same time, because the eighth transistor M8 remains in the on state, the eighth transistor M8 remains to provide the second level signal Vgh to the third node N3, and the potential of the third node N3 controls the second output transistor M420 to remain in the off state, and the signal output terminal OUT remains to output the enable level of the light-emitting control signal EM.

[0128] After the t6' stage, if the input signal Vin remains low, the first clock signal ck and the second clock signal ckb change between high and low, so that the working process of the t5' stage and the t6' stage will be repeated until the input signal Vin becomes high, and the next driving period will be entered, that is, the working process of the t1'-t6' stages will be repeated.

[0129] Among them, because of the stability of the potential of the fifth node N5, the stability of the signal transmitted by the fourth node control unit 240 will be affected, thereby affecting the stability of the signal transmitted by the third node control unit 230, affecting the stability of the potential of the third node N3, and further affecting the stability of the light-emitting control signal output by the signal output terminal OUT, so improving the potential stability signal of the fifth node N5 can also improve the stability of the light-emitting control signal output by the signal output terminal OUT.

[0130] Optionally, Figure 17 Another structure diagram of a light-emitting control circuit is provided for the embodiment of the present application. As shown in Figure 17As shown, the fifth transistor M5 includes a fifth sub-transistor M51 and a sixth sub-transistor M52; the first pole of the fifth sub-transistor M51, the gate of the sixth sub-transistor M52 and the gate of the sixth sub-transistor M52 are electrically connected with the first clock terminal CK, the second pole of the fifth sub-transistor M51 is electrically connected with the first pole of the sixth sub-transistor M52, and the second pole of the sixth sub-transistor M52 is electrically connected with the fifth node N5. At this time, the fifth transistor M5 is a double-gate transistor composed of the fifth sub-transistor M51 and the sixth sub-transistor M52, and the fifth sub-transistor M51 and the sixth sub-transistor M52 can be turned on or turned off under the control of the first clock signal ck1 of the first clock terminal CK; when the first clock signal ck1 of the first clock terminal CK controls the fifth sub-transistor M51 and the sixth sub-transistor M52 to be in the turned-off state, the fifth transistor M5 can have a smaller leakage current, thereby being able to reduce the influence of the leakage current on the potential of the fifth node N5 when the fifth transistor M5 is in the turned-off state, and further being able to stabilize the potential of the third node N3 and improve the stability of the light-emitting control signal EM output by the signal output terminal OUT.

[0131] Optionally, continuing to refer to Figure 17 , the sixth transistor M6 includes a seventh sub-transistor M61 and an eighth sub-transistor M62; the first pole of the seventh sub-transistor M61 is electrically connected with the first clock terminal CK, the second pole of the seventh sub-transistor M61 is electrically connected with the first pole of the eighth sub-transistor M62, the second pole of the eighth sub-transistor M62 is electrically connected with the fifth node N5, and the gate of the seventh sub-transistor M61 and the gate of the eighth sub-transistor M62 are electrically connected with the first control module 100. At this time, the sixth transistor M6 is also a double-gate transistor composed of the seventh sub-transistor M61 and the eighth sub-transistor M62, so as to have a smaller leakage current when the sixth transistor M6 is in the turned-off state, thereby improving the problem that the leakage current influences the potential of the fifth node N3, improving the stability of the potential of the third node N3, and also being able to improve the stability of the light-emitting control signal EM output by the signal output terminal OUT.

[0132] For the convenience of description of the drawings and technical solutions, without special description, the technical solutions of the embodiments of the present application are exemplarily described by taking the fifth transistor M5 and the sixth transistor M6 as single-gate transistors.

[0133] It can be understood that the working conditions of the light-emitting control circuit of the present application are exemplarily described by taking the first control module 100 and the second control module 200 as examples of being electrically connected with the first node N1. However, the connection mode of the first control module 100 and the second control module 200 in the embodiments of the present application is not limited to this.

[0134] Optionally, Figure 18A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in FIG. 3. As shown in FIG. 3, the first control module 100 and the second control module 200 are electrically connected to the second node N2. Figure 16

[0135] For example, when the fifth control unit 250 of the second control module 200 includes the fifth transistor M5 and the sixth transistor M6, the gate of the sixth transistor M6 is electrically connected to the second node N2, so that the sixth transistor M6 transmits the first clock signal ck1 to the fifth node N5 under the control of the potential of the second node N2, so that the sixth transistor M6 is no longer controlled by the potential of the first node N1, which can reduce the load of the first node N1, improve the potential stability of the first node N1, and further improve the stability of the light emitting control signal EM output by the signal output terminal OUT, thereby improving the display quality. In addition, since the first node N1 needs to be at a potential that can control the first output transistor M410 to be turned on when the enable level of the light emitting control signal needs to be output, and the first node N1 needs to be at a potential that can control the first output transistor M410 to be turned off when the non-enable level of the light emitting control signal needs to be output, the first node N1 needs to remain at a fixed potential for a long period of time. Therefore, when the gate of the sixth transistor M6 is electrically connected to the first node N1, there will be a potential difference between the gate and the second electrode of the sixth transistor M6, so that the sixth transistor M6 is in a long-term bias state under the condition that the potential of the first node N1 remains unchanged, which causes the threshold voltage of the sixth transistor M6 to drift and affects the characteristics of the sixth transistor M6. However, when the gate of the sixth transistor M6 is electrically connected to the second node N2, the potential of the second node N2 is controlled by the first clock signal ck1 and the second clock signal ck2, and alternates between high and low or between low and lower levels, i.e. the potential of the gate of the first transistor M6 alternates between different levels, so that the gate and the second electrode of the sixth transistor M6 do not maintain a certain potential difference for a long time, and the sixth transistor M6 is prevented from being in a long-term bias state, which can improve the stability of the sixth transistor M6 and further improve the stability of the light emitting control circuit 310.

[0136] Optionally, Figure 19 A structure diagram of another light emitting control circuit provided by the embodiment of the present application is shown in FIG. 3. As shown in FIG. 3, the first control module 100 and the second control module 200 are electrically connected to the second node N2. Figure 17 ​As shown, when the light-emitting control circuit 30 comprises the interlocking module 600, the interlocking module 600 can also not be directly electrically connected with the first node N1, but is electrically connected with the second node N2, the third node N3, the second level terminal VGH and the second control module 200 respectively; at this time, the interlocking module 600 can also control the transmission of the second level signal vgh to the second node N3 under the control of the second control module 200, and control the transmission of the second level signal vgh to the third node N3 under the control of the potential of the second node N2.

[0137] Optionally, continuing to refer to Figure 19 When the interlocking module 600 comprises the seventh transistor M7 and the eighth transistor M8, the gate of the seventh transistor M6 is electrically connected with the second control module 200, the first pole of the seventh transistor M7 is electrically connected with the second level terminal VGH, and the second pole of the seventh transistor M7 is electrically connected with the second node N2; the gate of the eighth transistor M8 is electrically connected with the second node N2, the first pole of the eighth transistor M8 is electrically connected with the second level terminal VGH, and the second pole of the eighth transistor M8 is electrically connected with the third node N3. In this way, the gate of the eighth transistor M8 is electrically connected with the second node N2, and the second pole of the seventh transistor M7 is electrically connected with the second node N2, which can also reduce the load of the first node N1, improve the potential stability of the first node N1, and further improve the stability of the light-emitting control signal EM output by the signal output terminal OUT, and improve the display quality; at the same time, it can prevent the eighth transistor M8 and the seventh transistor M7 from being in a long-term bias state due to the first node N1 being at a fixed potential for a long time, so as to prevent the threshold value of the eighth transistor M8 and the seventh transistor M7 from drifting, thereby improving the stability of the eighth transistor M8 and the seventh transistor M7, and further improving the stability of the light-emitting control circuit.

[0138] Optionally, Figure 20 Another structure schematic diagram of a light-emitting control circuit provided by the embodiment of the present application is provided. As shown in Figure 20 As shown, the light-emitting control circuit 30 further comprises a reset module 700; the reset module 700 is electrically connected with the reset signal terminal RSET, the second level terminal VGH and the first node N1 respectively; the reset module 700 is used for controlling the on-off state of the charge release path from the first node N1 to the second level terminal VGH according to the reset signal rset of the reset signal terminal RSET.

[0139] Illustratively, the reset signal rset of the reset signal terminal RSET can control the charge release path from the first node N1 to the second level terminal VGH to be turned on when the light-emitting control circuit 30 is not working, or before the light-emitting control circuit 30 stops working, thereby releasing the charge of the first node N1, preventing the potential of the first node N1 from being in the enable level state for a long time, causing the load connected to the first node N1 to be in the working state for a long time, thereby reducing the service life of the device; in addition, releasing the low level of the first node N1 can also control the load connected to the first node N1 to stop consuming power when the light-emitting control circuit 30 is not working, which is beneficial to low power consumption of the light-emitting control circuit 30.

[0140] Optional, continue to refer to Figure 20 The reset module 700 may include a reset transistor M700; the gate of the reset transistor M700 is electrically connected to the reset signal terminal RSET, the first electrode of the reset transistor M700 is electrically connected to the second level terminal VGH, and the second electrode of the reset transistor M14 is electrically connected to the first node N1. In this manner, the reset transistor M14 can be turned on or off under the control of a reset signal rset from the reset signal terminal RSET. When the reset signal rset controls the reset transistor M14 to be in the on state, the reset transistor M700 can release the charge at the first node N1. The reset transistor M700 may be an N-channel transistor or a P-channel transistor, and its design may be tailored to actual needs, and is not specifically limited in this embodiment of the present invention.

[0141] Optional, Figure 21 FIG. 1 is a structural diagram of another light emitting control circuit provided by an embodiment of the present invention. Figure 19 As shown, the light-emitting control circuit 30 further includes a voltage-stabilizing transistor M12. In this case, the first node N1 includes a first subnode N11 and a second subnode N12. The first electrode of the voltage-stabilizing transistor M12 is electrically connected to the first subnode N11 by the first control module 100, and the second electrode of the voltage-stabilizing transistor M12 is electrically connected to the second subnode N12 by the output module 400. The gate of the voltage-stabilizing transistor M12 is electrically connected to the first level terminal VGL. The voltage-stabilizing transistor M12 is in an on state under the control of the first level signal VGL. In this case, the voltage-stabilizing transistor M12 can be in an on state under the control of the first level signal VGL, so that the potentials of the first subnode N11 and the second subnode N12 are equal.

[0142] For example, the first level signal Vgl controls the voltage stabilizing transistor M12 to be in the on state, and the potential of the first node N1 is shared in the first sub-node N11 and the second sub-node N12, so that the voltage stabilizing transistor M12 can avoid the influence of the first control module 100, the filter module 300 and the bootstrap module 500 on the potential of the first node N1, and the light emitting control circuit can work normally. In addition, due to the threshold voltage of the voltage stabilizing transistor M12, when the difference between the first level signal Vgl and the potential of the first sub-node N11 or the second sub-node N12 connected with the voltage stabilizing transistor M12 is less than the threshold voltage of the voltage stabilizing transistor M12, the voltage stabilizing transistor M15 is in the on state, and when the condition is not met, the voltage stabilizing transistor M15 is in the off state. At this time, the voltage stabilizing transistor M15 can protect the device connected with the other node when the potential of one of the first sub-node N11 and the second sub-node N12 is abnormal.

[0143] Optionally, Figure 22 For another structure of the light emitting control circuit provided by the embodiment of the present application, as shown in Figure 22As shown, when the first node N1 includes the first sub-node N11 and the second sub-node N12, the output module 400 can include a first output unit 410, a second output unit 420, and a third output unit 430; the first output unit 410 is electrically connected with the second sub-node N12, the first voltage level terminal VGL, and the signal output terminal OUT respectively; the first output unit 410 is configured to control the signal output terminal OUT to output an enable level of the light-emitting control signal EM according to the potential of the second sub-node N12 and the first voltage level signal vgl; the third output unit 430 is electrically connected with the first sub-node N11, the first voltage level terminal VGL, and the signal output terminal OUT respectively; the third output unit 430 is configured to control the signal output terminal OUT to output an enable level of the light-emitting control signal EM according to the potential of the first sub-node N11 and the first voltage level signal vgl; the second output unit 420 is electrically connected with the third node N3, the second voltage level terminal VGH, and the signal output terminal OUT respectively; the second output unit 420 is configured to control the signal output terminal OUT to output a non-enable level of the light-emitting control signal EM according to the potential of the third node N3. At this time, the first output unit 410 can control the first voltage level signal Vgl of the first voltage level terminal VGL to be transmitted to the signal output terminal OUT under the control of the second sub-node N12, the third output unit 430 can control the first voltage level signal Vgl of the first voltage level terminal VGL to be transmitted to the signal output terminal OUT under the control of the first sub-node N11, and the second output unit 430 can control the second voltage level signal Vgh of the second voltage level terminal VGH to be transmitted to the signal output terminal OUT under the control of the third node N3. In this way, after the potential of the original first node N1 is distributed to the first sub-node N11 and the second sub-node N12, the first output unit 410 and the third output unit 430 are set to correspond to the second sub-node N12 and the first sub-node N11 respectively, and the light-emitting control signal EM output by the signal output terminal OUT is controlled together, so as to improve the accuracy and stability of the signal output by the signal output terminal OUT, and further improve the stability of the light-emitting control circuit.

[0144] For example, the first output unit 410 can include a first output transistor M410, the second output unit 420 can include a second output transistor M420, and the third output unit 430 can include a third output transistor M430. The gate of the first output transistor M410 is electrically connected to the second sub-node N12, the first electrode of the first output transistor M410 is electrically connected to the first voltage level terminal VGL, and the second electrode of the first output transistor M410 is electrically connected to the signal output terminal OUT. The gate of the second output transistor M420 is electrically connected to the third node N3, the first electrode of the second output transistor M420 is electrically connected to the second voltage level terminal VGH, and the second electrode of the second output transistor M420 is electrically connected to the signal output terminal OUT. The gate of the third output transistor M430 is electrically connected to the first sub-node N11, the first electrode of the third output transistor M430 is electrically connected to the first voltage level terminal VGL, and the second electrode of the third output transistor M430 is electrically connected to the signal output terminal OUT. At this time, the first output transistor M410 can be turned on or turned off under the control of the potential of the second sub-node N12, the third output transistor M430 can be turned on or turned off under the control of the potential of the first sub-node N11, and the second output transistor M420 can be turned on or turned off under the control of the potential of the third node N3. Thus, when the signal output terminal OUT needs to output the enable level of the light-emitting control signal EM, the potentials of the second sub-node N12 and the first sub-node N11 control the first output transistor M410 and the third output transistor M430 to be in the on state, respectively. When the signal output terminal OUT needs to output the non-enable level of the light-emitting control signal EM, the potential of the third node N3 controls the second output transistor M420 to be in the on state. It can be understood that the first output transistor M410, the second output transistor M420, and the third output transistor M430 can be N-channel transistors or P-channel transistors, which can be set as needed, and the embodiments of the present application do not make specific limitations thereto.

[0145] It should be noted that when the first control module 100 and the second control module 200 are electrically connected to the first node, the first control module 100 and the second control module 200 can be electrically connected to the first sub-node N11 or the second sub-node N12; similarly, when the light-emitting control circuit 310 includes the interlocking module 600, and the first control module 100 and the interlocking module 600 are electrically connected to the first node, the first control module 100 and the interlocking module 600 can also be electrically connected to the first sub-node N11 or the second sub-node N12; in addition, when the light-emitting control circuit includes the reset module 700, the reset module 700 can be electrically connected to the reset signal end RSET, the second level end VGH and the first sub-node N11 respectively, or can also be electrically connected to the reset signal end RSET, the second level end VGH and the second sub-node N12 respectively, or the reset module 700 can include a first reset transistor electrically connected to the first sub-node N11 and a second reset transistor electrically connected to the second sub-node N12, so as to be able to simultaneously release the potentials of the first sub-node N11 and the second sub-node N12. On the premise of being able to realize the core invention points of the embodiments of the present application, the embodiments of the present application do not limit the connection modes of other modules and the first sub-node N11 and the second sub-node N12 in the first node N1.

[0146] Based on the same inventive concept, the embodiments of the present application also provide a display panel, which comprises a display area and a non-display area surrounding the display area; the non-display area comprises the light-emitting control circuit provided by any one of the above embodiments, so that the display panel provided by the embodiments of the present application comprises the technical features of the light-emitting control circuit provided by the embodiments of the present application, and can achieve the beneficial effects of the shift register circuit provided by the embodiments of the present application, and the same parts can be referred to the above description of the light-emitting control circuit provided by the embodiments of the present application, which will not be described here.

[0147] Optionally, Figure 23 is a structural schematic diagram of a light-emitting driver provided by the embodiments of the present application, Figure 24 is a driving timing diagram of a light-emitting driver provided by the embodiments of the present application, which is combined with reference to Figure 1 , Figure 21 and Figure 22 , the display panel 10 comprises a plurality of pixels P arranged in an array and a plurality of light-emitting control circuits 310 cascaded, and the plurality of light-emitting control circuits 310 constitute a light-emitting driver 30; the signal output end OUT of each light-emitting control circuit 310 is electrically connected to at least part of the pixels P located in the same row; the signal output end OUT of each light-emitting control circuit 310 except the last light-emitting control circuit 310 is electrically connected to the signal input end IN of the next light-emitting control circuit 310, and the signal input end IN of the first light-emitting control circuit 310 receives a light-emitting control start pulse signal Vstv.

[0148] For example, the light emitting driver 30 includes n light emitting control circuits 30 (301, 302, 303, 304, …, 30n-1, 30n) arranged in cascade, wherein the signal input end IN of the first light emitting control circuit 301 is electrically connected with the light emitting control start signal line STV transmitting the start pulse signal Vstv, the signal input end IN of each light emitting control circuit 30n from the second light emitting control circuit 302 to the nth light emitting control circuit is electrically connected with the signal output end OUT of the light emitting control circuit of the previous stage, so that the start pulse signal Vstv transmitted by the light emitting control start signal line STV controls the start time and the end time of the enable level of the light emitting control signal EM1 output by the first light emitting control circuit 301, and the light emitting control signal EM output by the light emitting control circuit of the previous stage controls the start time and the end time of the light emitting control signal EM (EM2, EM3, EM4, …, EMn-1, EMn) output by the light emitting control circuit, so that the enable level of the light emitting control signal EM output by each light emitting control circuit starts and ends in turn.

[0149] In addition, each light emitting control circuit 310 is also electrically connected with the clock signal line CK1 transmitting the clock signal ck1 and the clock signal line CK2 transmitting the clock signal ck2, the first level line Lg transmitting the first level signal Vgl, and the second level line Hg transmitting the second level signal Vgh. Meanwhile, in order to ensure that the odd-stage light emitting control circuit 30 and the even-stage light emitting control circuit 30 can work normally and the structure of the display panel 10 is simplified, the first clock signal ck of the odd-stage light emitting control circuit 30 is usually multiplexed as the second clock signal ckb of the even-stage light emitting control circuit 30, and the second clock signal ckb of the odd-stage light emitting control circuit 30 is usually multiplexed as the first clock signal ck of the even-stage light emitting control circuit 30; at this time, in the odd-stage light emitting control circuit, the first clock end CK is electrically connected with the clock signal line CK1, and the second clock end CKB is electrically connected with the clock signal line CK2; while in the even-stage light emitting control circuit 310, the first clock end CK is electrically connected with the clock signal line CK2, and the second clock end CKB is electrically connected with the clock signal line CK1.

[0150] In the embodiment of the present application, the light emitting control circuits arranged in cascade can control the start time and the end time of the enable level of the light emitting control signal output by each light emitting control circuit, so as to realize the line-by-line control of each pixel circuit; and when each light emitting control circuit can stably and accurately output the light emitting control signal, each pixel circuit can control the light emitting element electrically connected therewith to stably emit light, thereby improving the display quality.

[0151] Optionally, Figure 25 A structure diagram of a pixel circuit provided by an embodiment of the present application is shown in combination with reference to Figure 1 、 Figure 23 and Figure 25 The display panel 10 further includes a plurality of light-emitting control signal lines EL. The light-emitting control lines EL are used to transmit light-emitting control signals EM to the pixels P, the pixels P include pixel circuits, at least part of the pixel circuits in the same row are electrically connected to the same light-emitting control signal line EL, and the signal output terminals OUT of the light-emitting control circuits 310 at each stage are electrically connected to the light-emitting control signal lines EL one by one, that is, the signal output terminal OUT of the first-stage light-emitting control circuit 301 is electrically connected to the light-emitting control signal line EL1, the signal output terminal OUT of the second-stage light-emitting control circuit 302 is electrically connected to the light-emitting control signal line EL2, the signal output terminal OUT of the third-stage light-emitting control circuit 303 is electrically connected to the light-emitting control signal line EL3, the signal output terminal OUT of the fourth-stage light-emitting control circuit 304 is electrically connected to the light-emitting control signal line EL4, …, the signal output terminal OUT of the (n-1)th-stage light-emitting control circuit 30n-1 is electrically connected to the light-emitting control signal line ELn-1, and the signal output terminal OUT of the nth-stage light-emitting control circuit 302 is electrically connected to the light-emitting control signal line ELn. In this way, the light-emitting control circuits 310 at each stage output the enable level of the light-emitting control signals EM in turn to control the pixel circuits of the pixels P in each row to control the light-emitting elements OLED to start emitting light in turn.

[0152] For example, Figure 25As shown, the pixel circuit can include a positive power supply end PVDD, a negative power supply end PVEE, a data signal end DATA, an initialization signal end Ref1, a reset signal end Ref2, an emission control end Emit, a first scan end S1N, a second scan end S1P, a third scan end S2N, a fourth scan end S2P, a driving transistor T1, a light-emitting element OLED, an initialization module 014, a threshold compensation module 013, a data writing module 011, an emission control module 012, and an anode reset module 015; wherein the initialization module 014 is electrically connected to the first scan end S1N, the initialization signal end Ref1, and the gate of the driving transistor T1, respectively; a first scan signal S1n of the first scan end S1N controls the initialization module 014 to transmit an initialization signal Vref1 of the initialization signal end Ref1 to the gate of the driving transistor T1 in an initialization stage, so as to reset the gate of the driving transistor T1 and prevent the influence of the last driving period on the writing of the data signal in the current period; the data writing module 011 is electrically connected to the second scan end S1P, the data signal end DATA, and the first electrode of the driving transistor T1, respectively; a second scan signal S1p of the second scan end S1P controls the data writing module 011 to write a data signal Vdata of the data signal end DATA to the gate of the driving transistor T1 in a data writing stage; the threshold compensation module 013 is electrically connected to the third scan end S2N, the second electrode of the driving transistor T1, and the gate of the driving transistor T1, respectively; a third scan signal S2n of the third scan end S2N controls the threshold compensation module 013 to compensate the threshold voltage of the driving transistor T1 to the gate of the driving transistor T1 in the data writing stage, so as to make the driving current generated by the driving transistor T1 in the light-emitting stage irrelevant to the threshold voltage of the driving transistor T1, and prevent the threshold voltage drift of the driving transistor T1 from affecting the light-emitting accuracy of the light-emitting element OLED; the anode reset module 015 is electrically connected to the fourth scan end S2P, the reset signal end Ref2, and the anode of the light-emitting element OLED, respectively; a fourth scan signal S2p of the fourth scan end S2P controls the anode reset module 015 to transmit a reset signal Vref2 of the reset signal end Ref2 to the anode of the light-emitting element OLED in a reset stage, so as to reset the anode of the light-emitting element OLED; the emission control module 012 is connected in series between the positive power supply end PVDD and the negative power supply end PVEE with the driving transistor T1 and the light-emitting element OLED; the emission control module 012 is also electrically connected to the emission control end Emit; an emission control signal EM of the emission control end Emit controls the emission control module 012 to form a current path between the positive power supply end PVDD and the negative power supply end PVEE in a light-emitting stage, so as to make the driving current provided by the driving transistor T1 according to the potential of the gate thereof provided to the light-emitting element OLED, and drive the light-emitting element OLED to emit light.

[0153] It can be understood that, under the premise that the gate of the driving transistor T1 can be initialized and the anode of the light emitting element OLED can be reset, the initialization signal Vref1 of the initialization signal terminal Ref1 can be the same as or different from the reset signal Vref2 of the reset signal terminal Ref2, and the embodiments of the present application do not make specific limitation on this. Meanwhile, in the embodiments of the present application, the anode reset stage is located before the light emitting stage, at this time, the time of the anode reset stage can overlap with the time of the initialization stage, and / or the time of the anode reset stage can also overlap with the time of the data writing stage, and the embodiments of the present application do not make specific limitation on this. For the convenience of description, the embodiments of the present application take the time of the anode reset stage overlapping with the time of the data writing stage as an example for instance.

[0154] Optionally, the initialization module 014 can include an initialization transistor T4, the gate of the initialization transistor T4 is electrically connected with the first scan terminal S1N, the first electrode is electrically connected with the initialization signal terminal Ref1, and the second electrode is electrically connected with the gate of the driving transistor T1; the first scan signal S1n of the first scan terminal S1N can control the initialization transistor T4 to be turned on or turned off, and in the initialization stage, the first scan signal S1n controls the initialization transistor T4 to be turned on; and in other stages, the first scan signal S1n controls the initialization transistor T4 to be turned off, and when the initialization transistor T4 is in the off state, the drain current of the initialization transistor T4 should be as small as possible to ensure the potential stability of the gate of the driving transistor T1, at this time, the active layer of the initialization transistor T4 can be a metal oxide semiconductor with small mobility, and the active layer including the metal oxide semiconductor usually has an N-type channel, so that the initialization transistor T4 is an N-channel transistor.

[0155] Optionally, the data writing module 011 can include a data writing transistor T2, the gate of the data writing transistor T2 is electrically connected with the second scan terminal S1P, the first electrode is electrically connected with the data signal terminal DATA, and the second electrode is electrically connected with the first electrode of the driving transistor T1; the second scan signal S1p of the second scan terminal S1P can control the data writing transistor T2 to be turned on or turned off, and in the data writing stage, the second scan signal S1p controls the data writing transistor T2 to be turned on; and in other stages, the second scan signal S1p controls the data writing transistor T2 to be turned off. In order to reduce power consumption, the active layer of the data writing transistor T2 and the driving transistor T1 can both include low temperature poly-silicon, and the active layer including the low temperature poly-silicon usually has a P-type channel, so that the data writing transistor T2 and the driving transistor T1 are P-channel transistors.

[0156] Optionally, the threshold compensation module 013 can include a threshold compensation transistor T3, the gate of the threshold compensation transistor T3 is electrically connected with the third scan end S2N, the first pole is electrically connected with the second pole of the driving transistor, and the second pole is electrically connected with the gate of the driving transistor T1; the third scan signal S2n of the third scan end S2N can control the threshold compensation transistor T3 to be turned on or turned off, and in the data writing stage, the third scan signal S2n controls the threshold compensation transistor T3 to be turned on; and in other stages, the third scan signal S2n controls the threshold compensation transistor T3 to be turned off; and in order to make the threshold compensation transistor T3 have a smaller leakage current when it is in the off state, the threshold compensation transistor T3 can also be an N-channel transistor.

[0157] Optionally, the anode reset module 015 can include an anode reset transistor T7, the gate of the anode reset transistor T7 is electrically connected with the fourth scan end S2P, the first pole is electrically connected with the reset signal end Ref2, and the second pole is electrically connected with the anode of the light emitting element OLED; the fourth scan signal S2p of the fourth scan end S2P can control the anode reset transistor T7 to be turned on or turned off, and in the anode reset stage, the fourth scan signal S2p controls the anode reset transistor T7 to be turned on; and in other stages, the fourth scan signal S2p controls the anode reset transistor T7 to be turned off. Similarly, in order to reduce power consumption, the anode reset transistor T7 can be a P-channel transistor. At this time, when the anode reset transistor T7 and the channel type of the data writing transistor T2 are the same, the second scan end S1P can be reused as the fourth scan end S1N.

[0158] Optionally, the light emitting control module 012 can include a first light emitting control transistor T5 and a second light emitting control transistor T6, the gate of the first light emitting control transistor T5 and the gate of the second light emitting control transistor T6 are both electrically connected with the light emitting control end Emit; the first pole of the first light emitting control transistor T5 is electrically connected with the positive power supply end PVDD, and the second pole is electrically connected with the first pole of the driving transistor T1; the first pole of the first light emitting control transistor T5 is electrically connected with the second pole of the driving transistor T1, and the second pole is electrically connected with the anode of the light emitting element OLED; the light emitting control signal EM of the light emitting control end Emit can control the first light emitting control transistor T5 and the second light emitting control transistor T6 to be turned on or turned off, and in the light emitting stage, the light emitting control signal EM controls the first light emitting control transistor T5 and the second light emitting control transistor T6 to be turned on; and in other stages, the light emitting control signal EM controls the first light emitting control transistor T5 and the second light emitting control transistor T6 to be turned off. Similarly, in order to reduce power consumption, the first light emitting control transistor T5 and the second light emitting control transistor T6 can both be P-channel transistors.

[0159] Optionally, the pixel circuit further comprises a storage capacitor Cst, which is connected between the positive power supply terminal PVDD and the gate of the driving transistor T1, and is used for storing the potential of the gate of the driving transistor T1, so that the driving transistor T1 can continuously provide the driving current to the light emitting element OLED in the light emitting stage, and the light emitting element can continuously emit light.

[0160] Exemplarily, Figure 26 is corresponding to Figure 25 the driving timing diagram of a pixel circuit, which is combined with reference to Figure 25 and Figure 26 In the initialization stage t1", the first scan signal S1n controls the initialization transistor T4 to be turned on, so that the initialization signal Vref1 is transmitted to the gate of the driving transistor T1, and the gate of the driving transistor T1 and the storage capacitor Cst are initialized; in the data writing stage t2", the second scan signal S1p controls the data writing transistor T2 to be turned on, the third scan signal S2n controls the threshold compensation transistor T3 to be turned on, and the data signal Vdata is transmitted to the gate of the driving transistor T1 through the data writing transistor T2, the driving transistor T1 and the threshold compensation transistor T3 in sequence, and the threshold voltage VTH of the driving transistor T1 is compensated to the gate of the driving transistor T1 at the same time, so that the potential of the gate of the driving transistor T1 is Vdata+VTH; at the same time, the data writing stage t2" is also the anode reset stage, and the fourth scan signal S2p controls the anode reset transistor T7 to be turned on, so that the reset signal Vref2 is transmitted to the anode of the light emitting element OLED, and the anode of the light emitting element OLED is reset; in the light emitting stage t3", the light emitting control signal EM controls the first light emitting control transistor T5 and the second light emitting control transistor T6 to be turned on, and the driving transistor T1 provides the driving current Id of k*(Vgs-VTH) according to the potential Vdata+VTH of the gate of the driving transistor T1, because the voltage difference Vgs between the gate and the first electrode of the driving transistor T1 is (Vdata+VTH)-PVDD, and the threshold voltage VTH of the driving transistor T1 is negative because the driving transistor T1 is a P-channel transistor, so the driving current Id provided by the driving transistor T1 is k*(PVDD-Vdata) 2 , wherein k is a coefficient related to the material and size of the driving transistor T1, so that the driving current provided by the driving transistor T1 to the light emitting element OLED is irrelevant to the threshold voltage VTH of the driving transistor T1, so that the light emitting element OLED can accurately emit light.

[0161] It should be noted that, Figure 25 is only an exemplary pixel structure diagram of the embodiment of the present application, and the structure of the pixel is not specifically limited in the premise of being able to realize the core invention point of the embodiment of the present application. For the convenience of description, the embodiment of the present application is all taken as Figure 23The structure of the pixel shown is an example, and the technical solutions of the embodiments of the present application are exemplarily described.

[0162] In an optional embodiment, Figure 27 is a structural schematic diagram of still another display panel provided by the embodiments of the present application, which is described in combination with reference to Figure 27 and Figure 25 The display panel 10 can include a plurality of light-emitting control signal lines EL; when the pixel circuit includes a data signal terminal DATA, a driving transistor T1, a light-emitting element OLED, a light-emitting control module 012, and a data writing module 011, and the data writing module 011 is configured to write a data signal Vdata of the data signal terminal DATA to a gate of the driving transistor T1, the driving transistor T1 is configured to generate a driving current according to a potential of the gate thereof, and the light-emitting control module 012 is configured to control the driving transistor T1 to provide the driving current to the light-emitting element OLED, the light-emitting control module 012 can include at least one light-emitting control transistor, for example, the light-emitting control module 012 can include two light-emitting control transistors (a first light-emitting control transistor T5 and a second light-emitting control transistor T6); at this time, the gates of the light-emitting control transistors (T5 and T6) of at least part of the pixel circuits in the same row are electrically connected to the same light-emitting control signal line EL; and the signal output terminals OUT of the light-emitting control circuits 310 at each stage are electrically connected to the light-emitting control signal lines EL one by one. In this way, the light-emitting control circuits 310 at each stage can provide a light-emitting control signal EM to the light-emitting control terminals Emit of the pixel circuits in each row through the light-emitting control lines EL, so as to control the light-emitting control transistors (T5 and T6) in the pixel circuits in each row to be turned on or turned off.

[0163] Optionally, the above description is continued in combination with reference to Figure 27 and Figure 25, the display panel 10 can further include a plurality of first scan signal lines SL1; when the pixel circuit includes a threshold compensation module 013 and the threshold compensation module 013 is configured to compensate the threshold voltage of the driving transistor T1 to the gate of the driving transistor T1, the threshold compensation module 013 can include a threshold compensation transistor T3, and the channel type of the threshold compensation transistor T3 can be different from the channel type of the light-emitting control transistor (T5 and T6); at this time, the gates of the threshold compensation transistors T3 of at least some pixel circuits in the same row are electrically connected to the same first scan signal line SL1, and the signal output end OUT of each stage of light-emitting control circuit 310 is also electrically connected to each first scan signal line SL1 one by one. In this way, the light-emitting control signal EM output by the signal output end OUT of each light-emitting control circuit 310 can also provide the third scan signal S2n to the third scan end S2N of each row of pixel circuits through each first scan signal line SL1, control the threshold compensation transistor T3 in each row of pixel circuits to turn on or off, so that the light-emitting control signal EM provided to each pixel circuit is multiplexed as the third scan signal S2n of the pixel circuit, thereby eliminating the need to additionally set a scan circuit for providing the third scan signal S2n, which is conducive to simplifying the structure of the display panel 10 and facilitating the narrow frame of the display panel 10.

[0164] Optionally, continuing to combine reference Figure 27 and Figure 25 , the display panel 10 can further include a plurality of second scan signal lines SL2; when the pixel circuit includes an initialization module 014 and an initialization signal end Ref1, and the initialization module 014 is configured to control the initialization signal Vref1 of the initialization signal end Ref1 to initialize the gate of the driving transistor T1, the initialization module 014 can include an initialization transistor T4, and the channel type of the initialization transistor T4 is different from the channel type of the light-emitting control transistor (T5 and T6); at this time, the gates of the initialization transistors T4 of at least some pixel circuits in the same row are electrically connected to the same second scan signal line SL2; the signal output end OUT of each stage of light-emitting control circuit 310 is also electrically connected to each second scan signal line SL2 one by one; in this way, the light-emitting control signal EM output by the signal output end OUT of each light-emitting control circuit 310 can also provide the first scan signal S1n to the first scan end S1N of each row of pixel circuits through each second scan signal line SL2, control the initialization transistor T4 in each row of pixel circuits to turn on or off, so that the light-emitting control signal EM provided to each pixel circuit is multiplexed as the first scan signal S1n, thereby eliminating the need to additionally set a scan circuit for providing the first scan signal S1n, which is conducive to simplifying the structure of the display panel 10 and facilitating the narrow frame of the display panel 10.

[0165] Among the first scan signal line SL1 and the second scan signal line SL2 electrically connected with the same pixel circuit, the first scan signal line SL1 is electrically connected with the current stage light-emitting control circuit 310, and the second scan signal line SL2 is electrically connected with the previous stage light-emitting control circuit 310.

[0166] Exemplarily, Figure 28 is electrically connected with the current stage light-emitting control circuit 310, and the second scan signal line SL2 is electrically connected with the previous stage light-emitting control circuit 310. Figure 25 The driving timing diagram of another pixel circuit corresponding thereto is shown in FIG. 6, which is described in combination with reference to FIG. 1. Figure 28 and Figure 25 Taking the threshold compensation transistor T3 and the initialization transistor T4 as N-channel transistors and the other transistors as P-channel transistors as an example, the working process of the pixel circuit in the i-th row is as follows:

[0167] When the pixel circuit in the i-th row is in the initialization stage t1", the pixel circuit in the i-1-th row is in the data writing stage. At this time, the gate of the light-emitting control transistor (T5 and T6) of the pixel circuit in the i-1-th row should receive the non-enabled level of the light-emitting control signal EMi-1, i.e., the light-emitting control signal EMi-1 is at a high level. When the light-emitting control signal EMi-1 is transmitted to the gate of the initialization transistor T4 of the pixel circuit in the i-th row through the second scan signal line SL2, the initialization transistor T4 of the pixel circuit in the i-th row is in a conductive state, so that the initialization signal Vref1 of the initialization signal end Ref1 is transmitted to the gate of the driving transistor T1 in the pixel circuit in the i-th row to initialize the gate of the driving transistor T1 in the pixel circuit in the i-th row. At the same time, the gate of the light-emitting control transistor (T5 and T6) of the pixel circuit in the i-th row also receives the high level of the light-emitting control signal EMi, and the light-emitting control transistor (T5 and T6) of the pixel circuit in the i-th row is also in a closed state. When the light-emitting control signal Emi is transmitted to the threshold compensation transistor T3 of the pixel circuit in the i-th row through the first scan signal line SL1, the threshold compensation transistor T3 of the pixel circuit in the i-th row is in a conductive state. However, since the gate of the data writing transistor T2 of the pixel circuit in the i-th row receives the second scan signal S1pi to control the data writing transistor T2 to be in a closed state, the data signal Vdata of the data signal end DATA of the pixel circuit in the i-th row will not be transmitted to the gate of the driving transistor T1 of the pixel circuit in the i-th row.

[0168] When the i-th row of pixel circuit is in the data writing stage t2", the i-1-th row of pixel circuit can enter the light emitting stage, the gate of the light emitting control transistor (T5 and T6) of the i-1-th row of pixel circuit receives the light emitting control signal EMi-1 which becomes low, the light emitting control transistor (T5 and T6) of the i-1-th row of pixel circuit is in the on state, the initialization transistor T4 of the i-th row of pixel circuit is in the off state; while the gate of the light emitting control transistor (T5 and T6) of the i-th row of pixel circuit still receives the light emitting control signal Emi which remains high, the threshold compensation transistor T3 of the i-th row of pixel circuit remains in the on state, at the same time, the gate of the data writing transistor T2 of the i-th row of pixel circuit receives the second scanning signal S1pi which becomes low, so that the data writing transistor T2 of the i-th row of pixel circuit is also in the on state, the data signal Vdata of the data signal end DATA of the i-th row of pixel circuit is transmitted to the gate of the driving transistor T1 through the data writing transistor T2, the driving transistor T1 and the threshold compensation transistor T3 of the i-th row of pixel circuit in turn, and the threshold voltage VTH of the driving transistor T1 is compensated to the gate thereof.

[0169] When the i-th row of pixel circuit is in the light emitting stage t3", the gate of the light emitting control transistor (T5 and T6) of the i-th row of pixel circuit receives the light emitting control signal Emi which becomes low, the light emitting control transistor (T5 and T6) of the i-th row of pixel circuit is in the on state, the threshold compensation transistor T3 of the i-th row of pixel circuit is in the off state, and the driving transistor T1 provides driving current to the light emitting element OLED according to the gate potential thereof to drive the light emitting element OLED to emit light.

[0170] In this way, by multiplexing the light emitting control signal Emi provided to the i-th row of pixel circuit as the third scanning signal S2ni of the i-th row of pixel circuit, and multiplexing the light emitting control signal Emi-1 provided to the i-1-th row of pixel circuit as the first scanning signal S1ni of the i-th row of pixel circuit, the structure of the display panel 10 can be simplified under the premise of controlling the normal work of the pixel circuit, which is conducive to the narrow frame of the display panel 10.

[0171] In addition, the scan driver 20 in the display panel 10 can include a plurality of scan driving circuits 201 arranged in cascade; each stage of the scan driving circuit 201 receives the scan timing control signals transmitted by the timing control signal lines (STV', CK', EN', Hg', Lg'), and sequentially outputs the enable level of the second scan signal S1p under the control of each scan timing control signal. At this time, the display panel 10 should also include a plurality of third scan signal lines SL3, the second scan end S1P of at least part of the pixel circuits in the same row is electrically connected with the same third scan signal line SL3; the scan output end of each stage of the scan driving circuit 201 is electrically connected with each third scan signal line SL3 one by one, so as to provide the second scan signal S1p to each third scan signal line SL3, and control the data writing transistor T2 of each row of pixel circuits to be turned on or off.

[0172] The display panel 10 can also include an initialization signal bus RL transmitting an initialization signal Vref1 and a plurality of initialization signal lines RL1, at least part of the pixel circuits in the same row are electrically connected with the same initialization signal line RL1, so that the initialization signal Vref1 provided by the data driver 40 is transmitted to the initialization signal end Ref1 of each row of pixel circuits through the initialization signal bus RL and each initialization signal line RL1 in sequence; the display panel 10 also includes a reset signal bus RL' transmitting a reset signal Vref2 and a plurality of reset signal lines RL2, at least part of the pixel circuits in the same row are electrically connected with the same reset signal line RL2, so that the reset signal Vref2 provided by the data driver 40 is transmitted to the reset signal end Ref2 of each row of pixel circuits through the reset signal bus RL' and each reset signal line RL2 in sequence; the display panel 10 also includes a plurality of data signal lines DL, a positive power terminal, a power bus PL' and a plurality of positive power signal lines PL, at least part of the pixel circuits in the same column share the data signal line DL, and at least part of the pixel circuits in the same column share the positive power signal line PL, so that the data signal Vdata provided by the data driver 40 can be transmitted to the data signal end DATA of each pixel circuit through the data signal line DL one by one, and the positive power signal PVDD of the positive power terminal is provided to each pixel circuit through the power bus PL' and each positive power signal line PL in sequence; the display panel 10 can also include a negative power terminal and a negative power bus (not shown in the figure), the negative power signal PVEE of the negative power terminal is transmitted to the cathode of the light emitting element OLED in each pixel circuit through the negative power bus, so as to form a current path from the positive power terminal PVDD to the negative power terminal PVEE.

[0173] It can be understood that other structures can also be included in the display panel to diversify the functions of the display panel, such as touch control, fingerprint identification, and the like, and the embodiments of the present application do not limit this on the premise that the core inventive points of the present application can be achieved.

[0174] Based on the same inventive concept, the embodiments of the present application also provide a display device, Figure 29 A structural schematic diagram of a display device provided by the embodiments of the present application is shown in Figure 20 The display device 1 includes the display panel 10 provided by any of the embodiments of the present application, and thus the display device 1 provided by the embodiments of the present application includes the technical features of the display panel 10 provided by the embodiments of the present application, can achieve the beneficial effects of the display panel 10 provided by the embodiments of the present application, and the same parts can refer to the description of the display panel 10 provided by the embodiments of the present application above, which will not be described here again. The display device 1 provided by the embodiments of the present application can be a mobile phone as shown in Figure 28 The display device 1 provided by the embodiments of the present application can be a mobile phone as shown in

[0175] It should be noted that the above are only the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the inventive concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A light emission control circuit characterized by comprising: The application relates to a filter module, a first control module, a second control module and an output module. The first control module is electrically connected with a signal input end, a first clock end and a second clock end respectively; the first control module is also electrically connected with the output module at a first node and electrically connected with the filter module at a second node; the first control module is used for controlling the electric potential of the first node and the second node respectively according to the input signal of the signal input end, the first clock signal of the first clock end and the second clock signal of the second clock end. The second control module is electrically connected with the first clock end, the second clock end, a first level end, a second level end and the first control module respectively; the second control module is also electrically connected with the output module at a third node. The second control module is used for controlling the electric potential of the third node under the control of the first control module, the first clock signal, the second clock signal, the first level signal of the first level end and the second level signal of the second level end. The output module is also electrically connected with the first level end, the second level end and a signal output end respectively; the output module is used for controlling the signal output end to output the enable level of the light-emitting control signal according to the first level signal and the electric potential of the first node and controlling the signal output end to output the disable level of the light-emitting control signal according to the second level signal of the second level end and the electric potential of the third node; wherein the enable level and the disable level of the light-emitting control signal are output in time division. The filter module is also electrically connected with the first node; the filter module has a one-way conduction characteristic; the filter module is used for selectively writing the electric potential of the second node into the first node. The filter module comprises a filter transistor; the filter transistor is electrically connected between the first node and the second node and the gate and the source of the filter transistor are electrically connected.

2. The light emission control circuit according to claim 1, wherein The first control module comprises a first node control unit, a second node control unit and a charge pump unit.

3. The light emission control circuit according to claim 1, characterized by The first node control unit is electrically connected with the signal input end, the first clock end and the first node respectively. The first node control unit is used for controlling the electric potential of the first node according to the input signal and the first clock signal. The second node control unit is electrically connected with the first clock end and the second node. The second node control unit is used for controlling the electric potential of the second node according to the first clock signal. The charge pump unit is electrically connected with the second node and the second clock end respectively. The charge pump unit is used for controlling the signal amount coupled from the second clock end to the second node. The first node control unit comprises a first transistor; the gate of the first transistor is electrically connected with the first clock end, the first pole of the first transistor is electrically connected with the signal input end and the second pole of the first transistor is electrically connected with the first node.

4. The light emission control circuit according to claim 3, wherein The first transistor comprises a first sub-transistor and a second sub-transistor.

5. The light emission control circuit according to claim 4, wherein ​ The first pole of the first sub-transistor is electrically connected with the signal input end, the second pole of the first sub-transistor is electrically connected with the first pole of the second sub-transistor, and the second pole of the second sub-transistor is electrically connected with the first node; the gate of the first sub-transistor and the gate of the second sub-transistor are electrically connected with the first clock end.

6. The light emission control circuit according to claim 3, wherein The second node control unit is also electrically connected with the signal input end, and is configured to provide the input signal to the second node according to the first clock signal. The second node control unit comprises a second transistor; the gate of the second transistor is electrically connected with the first clock end, the first pole of the second transistor is electrically connected with the signal input end, and the second pole of the second transistor is electrically connected with the second node.

7. The light emission control circuit according to claim 6, wherein The second transistor comprises a third sub-transistor and a fourth sub-transistor. The first pole of the third sub-transistor is electrically connected with the signal input end, the second pole of the third sub-transistor is electrically connected with the first pole of the fourth sub-transistor, the second pole of the fourth sub-transistor is electrically connected with the second node, and the gate of the third sub-transistor and the gate of the fourth sub-transistor are electrically connected with the first clock end.

8. The light emission control circuit according to claim 3, wherein The second node control unit is also electrically connected with the first level end and the first node, and is configured to provide the first level signal to the second node according to the first clock signal and the potential of the first node.

9. The light emission control circuit according to claim 8, wherein The second node control unit comprises a third transistor and a fourth transistor. The first pole of the third transistor is electrically connected with the first level end, the second pole of the third transistor is electrically connected with the first pole of the fourth transistor, and the second pole of the fourth transistor is electrically connected with the second node; the gate of the third transistor is electrically connected with the first node, and the gate of the fourth transistor is electrically connected with the first clock end.

10. The light emission control circuit according to claim 3, wherein The charge pump unit comprises a first capacitor; the first pole of the first capacitor is electrically connected with the second clock end, and the second pole of the first capacitor is electrically connected with the second node.

11. The light emission control circuit according to claim 1, characterized by The second control module comprises a third node control unit, a fourth node control unit and a fifth node control unit. The third node control unit is electrically connected with the third node and the first level end respectively; the third node control unit is also electrically connected with the fourth node control unit at the fourth node. The third node control unit is configured to control the potential of the third node according to the potential of the fourth node and the first level signal. The fourth node control unit is electrically connected with the second clock end, the second level end and the first clock end respectively; the fourth node control unit is also electrically connected with the fifth node control unit at the fifth node. The fourth node control unit is configured to control the potential of the fourth node according to the potential of the fifth node, the second clock signal, the first clock signal and the second level signal. The fifth node control unit is electrically connected with the first control module and the first clock end respectively. The fifth node control unit is configured to control the potential of the fifth node under the control of the first control module and the first clock signal.

12. The light emission control circuit according to claim 11, wherein The fifth node control unit comprises a fifth transistor and a sixth transistor. The gate and the first electrode of the fifth transistor are electrically connected to the first clock terminal, and the second electrode of the fifth transistor is electrically connected to the fifth node. The gate of the sixth transistor is electrically connected to the first control module, the first electrode of the sixth transistor is electrically connected to the first clock terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node.

13. The light emission control circuit according to claim 12, wherein The fifth transistor comprises a fifth sub-transistor and a sixth sub-transistor; the first electrode of the fifth sub-transistor, the gate of the fifth sub-transistor, and the gate of the sixth sub-transistor are electrically connected to the first clock terminal; the second electrode of the fifth sub-transistor is electrically connected to the first electrode of the sixth sub-transistor; and the second electrode of the sixth sub-transistor is electrically connected to the fifth node.

14. The light emission control circuit according to claim 12, wherein The sixth transistor comprises a seventh sub-transistor and an eighth sub-transistor. The first electrode of the seventh sub-transistor is electrically connected to the first clock terminal, the second electrode of the seventh sub-transistor is electrically connected to the first electrode of the eighth sub-transistor, the second electrode of the eighth sub-transistor is electrically connected to the fifth node, and the gate of the seventh sub-transistor and the gate of the eighth sub-transistor are electrically connected to the first control module.

15. The light emission control circuit according to claim 1, wherein The first control module and the second control module are electrically connected to the first node.

16. The light emission control circuit according to claim 1, wherein The first control module and the second control module are electrically connected to the second node.

17. The light emission control circuit according to claim 1, characterized by Further comprising: a bootstrap module; The bootstrap module is electrically connected between the signal output terminal and the first node; The bootstrap module is configured to control the potential of the first node according to the light-emitting control signal of the signal output terminal.

18. The light emission control circuit according to claim 17, wherein The bootstrap module comprises a bootstrap capacitor; the first electrode of the bootstrap capacitor is electrically connected to the signal output terminal, and the second electrode of the bootstrap capacitor is electrically connected to the first node.

19. The light emission control circuit of claim 1, wherein Further comprising: an interlocking module; The interlocking module is electrically connected to the first node, the third node, the second level terminal, and the second control module, respectively; The interlocking module is configured to control the transmission of the second level signal to the first node under the control of the second control module and to control the transmission of the second level signal to the third node under the control of the potential of the first node.

20. The light emission control circuit of claim 19, wherein, The interlocking module comprises a seventh transistor and an eighth transistor; The gate of the seventh transistor is electrically connected to the second control module, the first electrode of the seventh transistor is electrically connected to the second level terminal, and the second electrode of the seventh transistor is electrically connected to the first node; The gate of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the second level terminal, and the second electrode of the eighth transistor is electrically connected to the third node.

21. The light emission control circuit according to claim 1, characterized by Further comprising: an interlocking module; The interlocking module is electrically connected to the second node, the third node, the second level terminal, and the second control module, respectively; The interlocking module is configured to control transmission of the second level signal to the second node under control of the second control module, and control transmission of the second level signal to the third node under control of the potential of the second node.

22. The light emission control circuit of claim 21, wherein, The interlocking module comprises a seventh transistor and an eighth transistor. The gate of the seventh transistor is electrically connected with the second control module, the first pole of the seventh transistor is electrically connected with the second level terminal, and the second pole of the seventh transistor is electrically connected with the second node. The gate of the eighth transistor is electrically connected with the second node, the first pole of the eighth transistor is electrically connected with the second level terminal, and the second pole of the eighth transistor is electrically connected with the third node.

23. The light emission control circuit of claim 1, wherein Further comprising: a reset module; The reset module is electrically connected with a reset signal terminal, the second level terminal and the first node respectively; The reset module is configured to control the on-off state of the charge release path from the first node to the second level terminal according to the reset signal of the reset signal terminal.

24. The light emission control circuit of claim 23, wherein, The reset module comprises a reset transistor; the gate of the reset transistor is electrically connected with the reset signal terminal, the first pole of the reset transistor is electrically connected with the second level terminal, and the second pole of the reset transistor is electrically connected with the first node.

25. The light emission control circuit of claim 1, wherein, The output module comprises a first output unit and a second output unit; The first output unit is electrically connected with the first node, a first level terminal and the signal output terminal respectively; the first output unit is configured to control the signal output terminal to output the enable level of the light-emitting control signal according to the potential of the first node; The second output unit is electrically connected with the third node, a second level terminal and the signal output terminal respectively; The second output unit is configured to control the signal output terminal to output the non-enable level of the light-emitting control signal according to the potential of the third node.

26. The light emission control circuit of claim 1, wherein Further comprising: a voltage stabilizing transistor; The first node comprises a first sub-node and a second sub-node; the first pole of the voltage stabilizing transistor is electrically connected with the first control module at the first sub-node, the second pole of the voltage stabilizing transistor is electrically connected with the output module at the second sub-node; the gate of the voltage stabilizing transistor is electrically connected with the first level terminal; the voltage stabilizing transistor is in the on state under control of the first level signal.

27. The light emitting control circuit according to claim 26, wherein: The output module comprises a first output unit, a second output unit and a third output unit; The first output unit is electrically connected with the second sub-node, the first level terminal and the signal output terminal respectively; The first output unit is configured to control the signal output terminal to output the enable level of the light-emitting control signal according to the potential of the second sub-node and the first level signal; The third output unit is electrically connected with the first sub-node, the first level terminal and the signal output terminal respectively; The third output unit is configured to control the signal output terminal to output the enable level of the light-emitting control signal according to the potential of the first sub-node and the first level signal; The second output unit is electrically connected with the third node, a second level terminal and the signal output terminal respectively; The second output unit is configured to control the signal output end to output a non-enabled level of the light-emitting control signal according to the potential of the third node.

28. A display panel comprising: The display panel comprises: a plurality of pixel circuits arranged in an array and a plurality of light-emitting control circuits connected in series, each of the light-emitting control circuits being as claimed in any one of claims 1 to 27; a signal output end of each of the light-emitting control circuits is electrically connected to at least part of the pixel circuits in the same row; a signal output end of each of the light-emitting control circuits, except the last one, is electrically connected to a signal input end of the light-emitting control circuit in the next stage; and a signal input end of the first light-emitting control circuit receives a start pulse signal.

29. The display panel of claim 28, wherein, The display panel further comprises: a plurality of light-emitting control signal lines; each of the pixel circuits comprises a data signal end, a driving transistor, a light-emitting element, a light-emitting control module, and a data writing module; the data writing module is configured to write a data signal on the data signal end to a gate of the driving transistor; and the driving transistor is configured to generate a driving current according to a potential of the gate thereof; the light-emitting control module is configured to control the driving transistor to provide the driving current to the light-emitting element; the light-emitting control module comprises at least one light-emitting control transistor; a gate of the light-emitting control transistor of at least part of the pixel circuits in the same row is electrically connected to the same light-emitting control signal line; a signal output end of each of the light-emitting control circuits is electrically connected to one of the light-emitting control signal lines.

30. The display panel of claim 29, wherein, The display panel further comprises: a plurality of first scan signal lines; each of the pixel circuits further comprises a threshold compensation module; the threshold compensation module is configured to compensate a threshold voltage of the driving transistor to the gate of the driving transistor; the threshold compensation module comprises a threshold compensation transistor; a channel type of the threshold compensation transistor is different from a channel type of the light-emitting control transistor; a gate of the threshold compensation transistor of at least part of the pixel circuits in the same row is electrically connected to the same first scan signal line; a signal output end of each of the light-emitting control circuits is further electrically connected to one of the first scan signal lines.

31. The display panel of claim 30, wherein, The display panel further comprises: a plurality of second scan signal lines; each of the pixel circuits further comprises an initialization module and an initialization signal end; the initialization module is configured to control an initialization signal on the initialization signal end to initialize the gate of the driving transistor; the initialization module comprises an initialization transistor; a channel type of the initialization transistor is different from the channel type of the light-emitting control transistor; a gate of the initialization transistor of at least part of the pixel circuits in the same row is electrically connected to the same second scan signal line; a signal output end of each of the light-emitting control circuits is further electrically connected to one of the second scan signal lines; and among the first scan signal line and the second scan signal line electrically connected to the same pixel circuit, the first scan signal line is electrically connected to the light-emitting control circuit in the current stage, and the second scan signal line is electrically connected to the light-emitting control circuit in the previous stage.

32. A display device, characterized in that: The display panel comprises: the display panel of any one of claims 28 to 31.

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