Method for improving over-etching of contact holes

Abstract

The present invention provides a method for improving over-etching of contact holes. A substrate is provided, and shallow trench isolation is formed on the substrate. First and second semiconductor structures are formed on the shallow trench isolation. A first etch stop layer covering the first and second semiconductor structures is formed on the shallow trench isolation. An interlayer dielectric layer is formed on the first etch stop layer, and a second etch stop layer is formed on the interlayer dielectric layer; through photolithography and etching, a first contact hole is formed that penetrates the first and second etch stop layers and the interlayer dielectric layer and is connected to the first semiconductor structure; and a second contact hole is formed that penetrates the second etch stop layer and the interlayer dielectric layer and is not connected to the second semiconductor structure; a protective layer is formed to fill the first and second contact holes, and the protective layer is etched back until the first contact hole is connected to the second semiconductor structure below it. The present invention can avoid over-etching caused by different etching rates, avoid the generation of device defects, and improve the yield of devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for improving over-etching of contact holes. Background Art

[0002] Due to devices with different regions on the substrate, and due to the influence of factors such as the mask material and thickness on the devices, the etching rates are different when etching contact holes in different regions.

[0003] In the prior art, when forming an etching stop layer and an interlayer dielectric layer covering different devices by deposition, and then grinding until the surface of the interlayer dielectric layer is flat, and then forming contact holes through photolithography and etching, it is easy to over-etch the etching stop layer on the surface of the device, thereby generating defects and causing the device to open circuit.

[0004] Therefore, a method for improving over-etching of contact holes is needed. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for improving over-etching of contact holes, which is used to solve the problem that when etching contact holes communicated with devices of different heights in the prior art, it is easy to over-etch the second etching stop layer at the higher device, generate defects, and cause the device to be prone to open circuit.

[0006] To achieve the above purpose and other related purposes, the present invention provides a method for improving over-etching of contact holes, including:

[0007] Step 1: Provide a substrate, on which shallow trench isolation is formed, on which first and second semiconductor structures are formed, on which a first etching stop layer covering the first and second semiconductor structures is formed, on which an interlayer dielectric layer is formed, and a second etching stop layer formed on the interlayer dielectric layer, and the etching rate for forming a contact hole at the first semiconductor structure is greater than the etching rate at the second semiconductor structure;

[0008] Step 2: Through photolithography and etching, form a first contact hole that penetrates through the first and second etching stop layers and the interlayer dielectric layer and is communicated with the first semiconductor structure; and

[0009] Form a second contact hole that penetrates through the second etching stop layer and the interlayer dielectric layer and is not communicated with the second semiconductor structure;

[0010] Step 3: Form a protective layer filling the first and second contact holes, and back-etch the protective layer until the first contact hole is communicated with the second semiconductor structure below it;

[0011] Step 4: Remove the protective layer, then fill the first and second contact holes with a conductive material, and then polish the conductive material until it is above the interlayer dielectric layer.

[0012] Preferably, the substrate in Step 1 is a silicon substrate.

[0013] Preferably, the materials of the first and second etch stop layers in Step 1 are both silicon nitride.

[0014] Preferably, the material of the first interlayer dielectric layer in Step 1 is silicon dioxide.

[0015] Preferably, the protective layer in Step 3 is an anti-reflection coating.

[0016] Preferably, the method of the back etching in Step 3 is dry etching.

[0017] Preferably, the conductive material in Step 4 is tungsten.

[0018] Preferably, the method of polishing the conductive material in Step 4 is chemical mechanical planarization.

[0019] As described above, the method for improving over-etching of contact holes in the present invention has the following beneficial effects:

[0020] In the present invention, by adding a step of SIN deposition as a barrier layer for subsequent back etching after the interlayer dielectric layer is polished; then, through the contact hole etching process, the contact hole design structure with a faster etching rate is etched to meet the requirements; then, an anti-reflection coating is deposited, and the anti-reflection coating in the region with a slower etching rate is etched away through back etching; the contact holes that are not etched to the target are etched to meet the requirements through etching; by depositing and polishing to fill the contact holes while removing the SIN barrier layer, over-etching caused by different etching rates can be avoided, the generation of device defects can be avoided, and the yield of the device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It shows a schematic diagram of the substrate of the present invention;

[0022] Figure 2 It shows a schematic diagram of forming contact holes by the first etching of the present invention;

[0023] Figure 3 It shows a schematic diagram of forming a protective layer for filling contact holes of the present invention;

[0024] Figure 4 It shows a schematic diagram of forming contact holes by the second etching of the present invention;

[0025] Figure 5 It shows a schematic diagram of filling contact holes with a conductive material of the present invention;

[0026] Figure 6 Schematic diagram after grinding of the device according to the present invention;

[0027] Figure 7 Schematic diagram of the process flow according to the present invention. Specific embodiments

[0028] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] Please refer to Figure 7 , the present invention provides a method for improving over-etching of contact holes, including:

[0030] Step 1, please refer to Figure 1 , provide a substrate 01, a shallow trench isolation 02 is formed on the substrate 01, a first semiconductor structure 03 and a second semiconductor structure 04 with a height greater than that of the first semiconductor structure 03 are formed on the shallow trench isolation 02, a first etch stop layer 05 covering the first and second semiconductor structures is formed on the shallow trench isolation 02, an interlayer dielectric layer 06 is formed on the first etch stop layer 05, and a second etch stop layer 07 is formed on the interlayer dielectric layer 06. The second etch stop layer 07 is used as a barrier layer for subsequent back-etching. When etching the contact holes, due to the different material thicknesses on the first and second semiconductor structures, the etching rate for forming the contact holes at the first semiconductor structure 03 is greater than that at the second semiconductor structure 04;

[0031] In an embodiment of the present invention, the material of the shallow trench isolation 02 in Step 1 is usually silicon dioxide.

[0032] In an embodiment of the present invention, the substrate 01 in Step 1 is a silicon substrate 01, and a shallow trench isolation 02 and different semiconductor structures can be formed on the silicon substrate 01.

[0033] In an embodiment of the present invention, the materials of the first and second etch stop layers in Step 1 are both silicon nitride.

[0034] In an embodiment of the present invention, the material of the first interlayer dielectric layer 06 in Step 1 is silicon dioxide.

[0035] Step 2, please refer to Figure 2 , through photolithography and etching, form a first contact hole that penetrates the first and second etch stop layers and the interlayer dielectric layer 06 and is connected to the first semiconductor structure 03; and

[0036] Form a second contact hole that penetrates the second etch stop layer 07 and the interlayer dielectric layer 06 and is not connected to the second semiconductor structure 04. The structure here can be formed by controlling the etching time according to different etching rates;

[0037] Specifically, a photoresist layer can be formed on the second etch stop layer 07, and then the position of the contact hole pattern can be defined through steps such as exposure, development, standing film, and baking, and then the contact hole can be formed by dry etching.

[0038] Step 3: Form a protective layer 09 that fills the first and second contact holes to form the structure as shown in Figure 3 Etch back the protective layer 09 until the first contact hole is connected to the second semiconductor structure 04 below;

[0039] In an embodiment of the present invention, the protective layer 09 in Step 3 is an anti-reflection coating. Specifically, an anti-reflection coating (ARC) is a substance spin-coated at the interface between the photoresist and the Si substrate 01 to absorb the reflected light of lithography. Anti-reflection coatings mainly include: bottom anti-reflection coatings, top anti-reflection coatings, developable bottom anti-reflection coatings, spin-on Si-containing anti-reflection coatings, carbon coatings, etc. A bottom anti-reflection coating (BARC) is a coating located between the Si substrate 01 and the photoresist. The main components are crosslinkable resins, thermally induced acid generators, surfactants, and solvents;

[0040] The main material of the spin-on Si-containing anti-reflection coating (SiARC) is organosiloxane;

[0041] The carbon coating (Spin-On-Carbon, SOC) mainly consists of polymers with a high C content;

[0042] Organic anti-reflection coatings reduce reflection by absorbing light and are spin-coated on the silicon wafer in the same way as photoresist. Inorganic anti-reflection coatings are formed by plasma-enhanced chemical vapor deposition. Inorganic anti-reflection coatings do not absorb light but act by phase cancellation of specific wavelengths and are based on refractive index, film thickness, and other parameters;

[0043] One factor in selecting an anti-reflection coating is the ability of the anti-reflection coating to be removed after the lithography process step is completed. In some cases, organic anti-reflection coatings (mainly top anti-reflection coatings) are water-soluble and can be easily removed by flushing in the development step. Inorganic anti-reflection coatings are more difficult to remove, especially when their chemical composition is similar to that of the underlying layer. This anti-reflection coating is sometimes left on the silicon wafer surface to become part of the device;

[0044] In addition, an anti-reflection coating is adopted. Since the anti-reflection coating has good fluidity, it can fully fill the contact holes with relatively small critical dimensions.

[0045] In an embodiment of the present invention, the method of back etching in step three is dry etching. Dry etching is anisotropic etching. When etching the protective layer 09 at the second contact hole, the protective layer 09 in the first contact hole can prevent over-etching at this location, and the second etching stop layer 07 can play a protective role for the device.

[0046] Step four, please refer to Figure 4 , remove the protective layer 09, and then fill the first and second contact holes with the conductive material 08 to form a structure as shown in Figure 5 . Then grind the conductive material 08 above the interlayer dielectric layer 06 to form a structure as shown in Figure 6 . By controlling the grinding time, the second etching stop layer 07 can be removed simultaneously, avoiding the influence of the existence of the second etching stop layer 07 on subsequent processes.

[0047] In an embodiment of the present invention, the method of dry etching is adopted to remove the remaining protective layer 09 in step four, that is, the protective layer 09 remaining at the first contact hole.

[0048] In an embodiment of the present invention, the conductive material 08 in step four is tungsten.

[0049] In an embodiment of the present invention, the method of chemical mechanical planarization is adopted to grind the conductive material 08 in step four.

[0050] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0051] In summary, the present invention adds a step of SIN deposition as a barrier layer for subsequent back etching after the interlayer dielectric layer grinding process; then designs and etches the contact hole structure with a faster etching rate through the contact hole etching process to meet the requirements; deposits an anti-reflection coating again, and etches the anti-reflection coating in the area with a slower etching rate through back etching; etches the contact holes that have not been etched to the target to meet the requirements; and removes the SIN barrier layer while depositing and grinding to fill the contact holes, which can avoid over-etching caused by different etching rates, avoid the generation of device defects, and improve the yield of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0052] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving over-etching of contact holes, characterized in that, At least including: Step 1: Provide a substrate, on which shallow trench isolation is formed. On the shallow trench isolation, first and second semiconductor structures are formed. On the shallow trench isolation, a first etch stop layer covering the first and second semiconductor structures is formed. On the first etch stop layer, an interlayer dielectric layer is formed and a second etch stop layer formed on the interlayer dielectric layer. The etching rate for forming a contact hole at the first semiconductor structure is greater than the etching rate at the second semiconductor structure; Step 2: Through photolithography and etching, form a first contact hole that penetrates the first and second etch stop layers and the interlayer dielectric layer and is connected to the first semiconductor structure; and Form a second contact hole that penetrates the second etch stop layer and the interlayer dielectric layer and is not connected to the second semiconductor structure; Step 3: Form a protective layer filling the first and second contact holes, and back-etch the protective layer until the second contact hole is connected to the second semiconductor structure below it; Step 4: Remove the protective layer, then fill the first and second contact holes with a conductive material, and then polish the conductive material to above the interlayer dielectric layer.

2. The method for improving over-etching of contact holes according to claim 1, characterized in that: The substrate in Step 1 is a silicon substrate.

3. The method for improving over-etching of contact holes according to claim 1, wherein: The materials of the first and second etch stop layers in Step 1 are both silicon nitride.

4. The method for improving over-etching of contact holes according to claim 1, wherein: The material of the interlayer dielectric layer in Step 1 is silicon dioxide.

5. The method for improving over-etching of contact holes according to claim 1, characterized in that: The protective layer in Step 3 is an anti-reflection coating.

6. The method for improving over-etching of contact holes according to claim 1, characterized in that: The method of the back-etching in Step 3 is dry etching.

7. The method for improving over-etching of contact holes according to claim 1, characterized in that: The method of dry etching is used to remove the protective layer in Step 4.

8. The method for improving over-etching of contact holes according to claim 1, characterized in that: The conductive material in Step 4 is tungsten.

9. The method for improving over-etching of contact holes according to claim 1, wherein: The method of chemical mechanical planarization is used to polish the conductive material in Step 4.

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