Multi-channel control composite function device

Abstract

The present invention discloses a multi-channel control composite functional device, which mainly solves the problem that the existing gallium nitride-based power transistors can only block unidirectionally. It includes, from bottom to top: a substrate, a transition layer, a channel layer, and a barrier layer. The channel layer and the barrier layer are divided into multiple strip structures by internal isolation deep grooves; each strip structure is sequentially provided with a left electrode, a left P-type block, a left groove, a node, a right P-type block, a right groove, and a right electrode from left to right; on the upper parts of the left and right P-type blocks of the barrier layer are respectively left and right dielectric blocks; on the left and right dielectric blocks are respectively left and right gates; both the left and right grooves are composed of n rectangular grooves arranged in parallel at equal intervals, and their lower sides are both located in the channel layer; on the inside of the left and right grooves and on the barrier layers on both sides of their grooves are respectively provided with a first electrode and a second electrode, and both of these electrodes are composed of n T-shaped metal blocks of the same size. The present invention can achieve bidirectional blocking, has a high chip area utilization rate, and can be used as a power electronic system.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and particularly relates to a composite functional device, which can be used as a basic unit of a power electronic system. Technical Background

[0002] With the development of wide bandgap semiconductor materials, the performance of traditional silicon-based power transistors has approached the theoretical limit, and it is difficult to meet the urgent requirements of the next generation of high-performance power electronic systems for high temperature, high voltage, high frequency, high efficiency, and high power density. The enhancement-mode high electron mobility transistor based on the P-type cap layer GaN-based heterojunction structure, that is, the gallium nitride-based power transistor, can achieve excellent characteristics such as lower on-resistance, faster switching speed, and higher power density, which helps to greatly improve the performance and reliability of the power electronic system and significantly reduce power consumption. Therefore, vigorously researching and developing high-performance and high-reliability gallium nitride-based power devices plays a crucial role in China's realization of energy conservation, emission reduction, and green development.

[0003] The traditional gallium nitride-based power transistor is based on the GaN-based heterojunction structure, which includes: a substrate 1, a transition layer 2, a channel layer 3, a barrier layer 4, a P-GaN gate 5, a drain 6, a source 7, and a gate metal 8; the drain 6 is deposited on the upper left side of the barrier layer 4, the source 7 is deposited on the upper right side of the barrier layer 4, the P-GaN gate 5 is deposited in the middle part of the upper part of the barrier layer 4, and the gate metal 8 is deposited on the upper part of the P-GaN gate 5, as Figure 1 shown. Due to the limitations of material epitaxy technology and device manufacturing process level, a large number of defects will be generated on the surface and inside of this traditional gallium nitride-based power transistor. The existence of these defects will capture charges, resulting in a serious current collapse problem, further attenuating the reliability and power characteristics of the device, and this structure only allows the drain potential to be higher than the source, and can only achieve unidirectional blocking. See Effects of hole traps on the temperature dependence of current collapse in a normally-OFF gate-injection transistor, Japanese Journal of Applied Physics, 55(5), 2016. In many current technical fields of power management systems, it is often necessary for power switching devices to have strong reverse blocking capabilities. Since the drain of the traditional GaN-based HEMT power switching device is an ohmic contact, a reverse voltage cannot be applied. Therefore, there is an urgent need to develop functional devices with excellent reverse blocking capabilities. Summary of the Invention

[0004] The object of the present invention is to provide a multi-channel control composite functional device aiming at the deficiencies of the above-mentioned existing technologies, so as to achieve bidirectional blocking characteristics, improve the reliability of the device, greatly reduce the occupied area, and improve the chip area utilization rate and integration degree.

[0005] To achieve the above object, the technical solution of the present invention is realized as follows:

[0006] I. Device structure

[0007] A multi-channel control composite functional device includes, from bottom to top: a substrate 1, a transition layer 2, a channel layer 3, and a barrier layer 4, and is characterized in that:

[0008] An isolation deep groove 5 is provided inside the channel layer 3 and the barrier layer 4, and the isolation deep groove 5 is composed of m deep grooves with the same size and distributed front and back, the distance between adjacent two deep grooves is equal, and m>1;

[0009] The isolation deep groove 5 divides the channel layer 3 and the barrier layer 4 into m + 1 strip-shaped structures. On each strip-shaped structure, a left electrode 10, a left P-type block 6, a left groove 13, a node 12, a right P-type block 7, a right groove 14, and a right electrode 11 are sequentially arranged from left to right;

[0010] The left P-type block 6 and the right P-type block 7 are both located on the upper part of the barrier layer 4, and a left dielectric block 8 and a right dielectric block 9 are respectively provided on their upper sides;

[0011] The left groove 13 and the right groove 14 are both composed of n rectangular grooves, and these n rectangular grooves are arranged in parallel at equal intervals, and their lower sides are all located in the channel layer 3;

[0012] A first electrode 15 is provided in the left groove 13, and a second electrode 16 is provided in the right groove 14. The first electrode and the second electrode are both composed of n T-shaped metal blocks with the same size. The lower sides of the vertical parts of these T-shaped metal blocks are all located inside the channel layer 3, and the lower sides of the horizontal parts are located on the upper surface of the barrier layer 4, and n>1;

[0013] A left gate 17 and a right gate 18 are respectively provided on the upper parts of the left dielectric block 8 and the right dielectric block 9.

[0014] Further, the Al component of the barrier layer 4 is 0.1 to 0.4, and its thickness a is 1 nm to 40 nm.

[0015] Further, the left P-type block 6 and the right P-type block 7 are made of P-GaN or CuO or NiO materials, their thickness is 5 nm to 500 nm, and the doping concentration is 5×10 15 cm -3 ~1×10 22 cm -3 .

[0016] Further, the left dielectric block 8 and the right dielectric block 9 are made of Al2O3 or HfO2 or Si3N4, and their thickness is 5 nm to 100 nm.

[0017] Further, the depths of the n rectangular grooves in the left groove 13 and the right groove 14 on each strip structure are all h, where h > a and a is the thickness of the barrier layer 4.

[0018] Further, on each strip structure, among the n T-shaped metal blocks included in the first electrode 15 and the second electrode 16 respectively, the distance between the first T-shaped metal block and the second T-shaped metal block is t1, the distance between the second T-shaped metal block and the third T-shaped metal block is t2,..., and the distance between the (n - 1)-th T-shaped metal block and the n-th T-shaped metal block is t n-1 , and it satisfies t1 = t2 =... = t n-1 , and the distance between the lower side of the vertical part of each T-shaped metal block and the upper surface of the barrier layer is all h;

[0019] Further, for each T-shaped metal block in the first electrode 15, the distance between the left end of the horizontal part and the right end of the left P-type block 6 is x1, and the distance between the right end of the horizontal part and the node 12 is u1; for each T-shaped metal block in the second electrode 16, the distance between the left end of the horizontal part and the right end of the right P-type block 7 is x2, and the distance between the right end of the horizontal part and the right electrode 11 is u2; and it satisfies x1 = x2 = x, u1 = u2 = u, where x is much smaller than u and u > 1 μm.

[0020] Further, the lengths of the left gate 17 and the right gate 18 are both smaller than the lengths of the corresponding left dielectric block 8 and right dielectric block 9.

[0021] Further, the left electrode 10, the right electrode 11 and the node 12 are all in ohmic contact with the barrier layer 4; the first electrode 15 forms Schottky contacts with the barrier layer 4 and the channel layer 3 respectively; the second electrode 16 forms Schottky contacts with the barrier layer 4 and the channel layer 3 respectively.

[0022] II. Manufacturing method

[0023] A method for manufacturing the multi-channel control composite functional device of the present invention is characterized by including the following steps:

[0024] A) Epitaxially grow a GaN-based wide-bandgap semiconductor material on the substrate 1 to form a transition layer 2;

[0025] B) Epitaxially grow GaN material on the transition layer 2 to form a channel layer 3;

[0026] C) Epitaxially grow a GaN-based wide-bandgap semiconductor material on the channel layer 3 to form a barrier layer 4 with a thickness of a;

[0027] D) Epitaxially grow a P-type semiconductor material on the barrier layer 4 to form a P-type layer with a thickness of 5 - 500 nm and a doping concentration of 5×10 15 ~1×10 22 cm -3 ;

[0028] E) Epitaxially grow a dielectric material on the P-type layer to form a dielectric layer with a thickness of 5 nm - 100 nm;

[0029] F) Make a mask for the first time on the dielectric layer, and use this mask to etch the dielectric layer, P-type layer, barrier layer 4, and channel layer 3 in sequence until reaching the inside of the channel layer 3, forming m deep grooves with the same size and equally spaced and arranged in parallel. These m deep grooves together form the isolation deep groove 5; these m deep grooves divide the channel layer 3 and the barrier layer 4 into m + 1 strip-shaped structures;

[0030] G) Etch to form the left P-type block 6, right P-type block 7, left dielectric block 8, and right dielectric block 9:

[0031] G1) Make a mask for the second time on the etched dielectric layer, P-type layer, channel layer 3, barrier layer 4, and isolation deep groove 5, and use this mask to etch the etched dielectric layer again until reaching the upper surface of the P-type layer, forming the left dielectric block 8 and the right dielectric block 9;

[0032] G2) Use this mask again to etch the P-type layer until reaching the upper surface of the barrier layer 4, forming the left P-type block 6 and the right P-type block 7;

[0033] H) Make a mask for the third time on the channel layer 3, barrier layer 4, isolation deep groove 5, left dielectric block 8, and right dielectric block 9, and use this mask to deposit multiple layers of metal on the left, right, and middle sides of the upper part of the barrier layer 4 respectively, and perform rapid thermal annealing in an N2 atmosphere to form the left electrode 10, right electrode 11, and node 12;

[0034] I) Fabricate the first electrode 15 and the second electrode 16:

[0035] I1) Make a mask for the fourth time on the channel layer 3, barrier layer 4, isolation deep groove 5, left dielectric block 8, right dielectric block 9, left electrode 10, right electrode 11, and node 12, and use this mask to etch the barrier layer 4 and the channel layer 3 on the right side of the left P-type block 6 and the right side of the right P-type block 7 in sequence. The total etching depth is h, and n rectangular grooves with the same size are formed on the right side of each left P-type block 6 and each right P-type block 7. The distances between adjacent two of the n rectangular grooves are t1, t2,..., t n-1 and t1 = t2 =... = t n-1 ; The n rectangular grooves on the right side of each left P-type block 6 form the left groove 13, and the n rectangular grooves on the right side of each right P-type block 7 form the right groove 14;

[0036] I2) A mask is fabricated for the fifth time on the channel layer 3, the barrier layer 4, the isolation deep trench 5, the left dielectric block 8, the right dielectric block 9, the left electrode 10, the right electrode 11, the node 12, the left groove 13, and the right groove 14. Using this mask, metal is deposited on the upper part of the barrier layer 4 on both sides of each left groove 13 and inside each left groove 13 to form the first electrode 15; metal is deposited on the upper part of the barrier layer 4 on both sides of each right groove 14 and inside each right groove 14 to form the second electrode 16;

[0037] J) A mask is fabricated for the sixth time on the channel layer 3, the barrier layer 4, the isolation deep trench 5, the left dielectric block 8, the right dielectric block 9, the left electrode 10, the right electrode 11, the node 12, the first electrode 15, and the second electrode 16. Using this mask, metal is deposited on the upper parts of the left dielectric block 8 and the right dielectric block 9 to form the left gate 17 and the right gate 18 respectively, completing the fabrication of the entire device.

[0038] Compared with traditional gallium nitride-based power transistors, the device of the present invention has the following advantages:

[0039] First, it can provide bidirectional blocking and the device has strong reliability.

[0040] In the device of the present invention, due to the provision of the first electrode and the second electrode, the T-shaped metal blocks constituting these electrodes are connected to the two-dimensional electron gas formed between the barrier layer and the channel layer. When the device is conducting, the potential of the left electrode is higher than the potential of the node. Electrons first conduct electricity through the gaps between each T-shaped metal block in the first electrode. When the potential of the T-shaped metal block increases, it will also participate in conduction; the conduction process of the right electrode and the second electrode is similar to this process. Compared with the traditional conduction process, this process has little impact on the current. When the device is blocking, no voltage is applied to the left and right gates, that is, zero potential, which is divided into two cases: First, when the potential of the left electrode is higher than the potential of the node, at this time, since the device is in the off state, the two-dimensional electron gas cannot reach the surface density required for conduction and cannot conduct, realizing forward blocking; Second, when the potential of the left electrode is lower than the potential of the node, the Schottky diodes formed between each T-shaped metal block in the first electrode and the node are reverse-biased, and the two-dimensional electron gas near the T-shaped metal block is further depleted, realizing reverse blocking; the blocking process of the right electrode and the second electrode is similar to this process; therefore, the device can achieve bidirectional blocking and has strong reliability.

[0041] Second, it saves area and improves the chip area utilization rate and integration level.

[0042] In the device of the present invention, there is a strict translational repetition relationship. Although the structure is slightly complex, multiple parts can be fabricated synchronously. For example: the left electrode, the right electrode, and the node, the left P-type block and the right P-type block, the left dielectric block and the right dielectric block, the first electrode and the second electrode, etc. Therefore, the process steps of the device of the present invention will not increase; in the structure of the present invention, the isolation deep trench divides the device into (m + 1) strip-shaped structures, and the nodes on each strip-shaped structure replace the traditional wire interconnection to realize the connection between the left and right parts; the left and right electrodes connect all the strip-shaped structures to achieve multi-channel control. Each node is discrete and is used to connect the load according to actual requirements. Therefore, on the basis of ensuring good reliability and output power characteristics of the device, the connection can be realized through sharing at the device level, avoiding the traditional PCB board-level interconnection, greatly improving the chip area utilization rate and integration degree, and significantly reducing the parasitic parameters. Description of the Drawings

[0043] Figure 1 is the structural diagram of a traditional gallium nitride-based power transistor;

[0044] Figure 2 is the structural diagram of the multi-channel control composite function device of the present invention;

[0045] Figure 3 is Figure 2 the top view of

[0046] Figure 4 is Figure 3 the structural diagram of a unit on the left side of the node on the strip-shaped structure;

[0047] Figure 5 is the preparation Figure 2 flow chart of the realization of the device of the present invention;

[0048] Figure 6 is the blocking characteristic diagram obtained by testing the device of the present invention. Detailed Embodiments

[0049] The embodiments and effects of the present invention will be further described in detail below with reference to the accompanying drawings.

[0050] Referring to Figure 2 , Figure 3 and Figure 4 , the multi-channel control composite function device given in this embodiment includes: a substrate 1, a transition layer 2, a channel layer 3, a barrier layer 4, an isolation deep trench 5, a left P-type block 6, a right P-type block 7, a left dielectric block 8, a right dielectric block 9, a left electrode 10, a right electrode 11, a node 12, a left groove 13, a right groove 14, a first electrode 15, a second electrode 16, a left gate 17, and a right gate 18. Among them:

[0051] The substrate 1 is made of sapphire or silicon carbide or silicon or other materials;

[0052] The transition layer 2 is located on the upper part of the substrate 1 and is composed of a GaN-based wide-bandgap semiconductor material;

[0053] The channel layer 3 is located on the upper part of the transition layer 2 and is composed of GaN material;

[0054] The barrier layer 4 is located on the upper part of the channel layer 3 and is composed of several layers of the same or different GaN-based wide-bandgap semiconductor materials, with its Al component being 0.1 to 0.4 and the thickness a being 1 nm to 40 nm;

[0055] The isolation deep trench 5 is located inside the channel layer 3 and the barrier layer 4 and is composed of m deep trenches with the same size and distributed front and back. The distance between adjacent two deep trenches is equal, m > 1. The isolation deep trench 5 divides the channel layer 3 and the barrier layer 4 into m + 1 strip-shaped structures;

[0056] The left P-type block 6 and the right P-type block 7 are located on the upper part of the barrier layer 4 and are made of P-GaN or CuO or NiO or other materials, with a thickness of 5 nm to 500 nm and a doping concentration of 5×10 15 cm -3 ~1×10 22 cm -3 ;

[0057] The left dielectric block 8 and the right dielectric block 9 are respectively located on the upper parts of the left P-type block 6 and the right P-type block 7 and are made of Al2O3 or HfO2 or Si3N4 or other dielectric materials, with a thickness of 5 nm to 100 nm;

[0058] The left electrode 10 and the right electrode 11 are respectively located on the left and right sides of the upper part of the barrier layer 4 and are both in ohmic contact with the barrier layer 4;

[0059] The node 12 is located at the middle position on each strip-shaped structure and is made of multiple layers of metal and is in ohmic contact with the barrier layer 4;

[0060] The left groove 13 is located in the barrier layer 4 and the channel layer 3 on the right side of the left P-type block 6 on each strip-shaped structure, and the right groove 14 is located in the barrier layer 4 and the channel layer 3 on the right side of the right P-type block 7 on each strip-shaped structure; The left groove 13 and the right groove 14 on each strip-shaped structure are both composed of n rectangular grooves, and these n rectangular grooves are arranged in parallel at equal intervals. The depth of each rectangular groove is h, h > a, where a is the thickness of the barrier layer 4, and n > 1;

[0061] The first electrode 15 is located inside the left groove 13 and above the barrier layer 4, and the second electrode 16 is located inside the right groove 14 and above the barrier layer 4; on each strip structure, the first electrode 15 and the second electrode 16 are both composed of n T-shaped metal blocks of the same size and arranged in parallel at equal intervals. The lower sides of the vertical parts of these T-shaped metal blocks are all located inside the channel layer 3, and the lower sides of the horizontal parts are located on the upper surface of the barrier layer 4; among these n T-shaped metal blocks, the distance between the first T-shaped metal block and the second T-shaped metal block is t1, the distance between the second T-shaped metal block and the third T-shaped metal block is t2, …, the distance between the (n - 1)-th T-shaped metal block and the n-th T-shaped metal block is t n-1 , and it satisfies t1 = t2 = … = t n-1 ; for each T-shaped metal block in the first electrode 15, the distance between the left end of the horizontal part and the right end of the left P-type block 6 is x1, and the distance between it and the node 12 is u1; for each T-shaped metal block in the second electrode 16, the distance between the left end of the horizontal part and the right end of the right P-type block 7 is x2, and the distance between it and the right electrode 11 is u2, and it satisfies x1 = x2 = x, u1 = u2 = u, where x is much smaller than u, and u > 1 μm;

[0062] The left gate 17 and the right gate 18 are respectively located above the left dielectric block 8 and the right dielectric block 9, and their lengths are both smaller than the lengths of the corresponding dielectric blocks.

[0063] Referring to Figure 5 , the following three embodiments are given for the multi-channel control composite functional device prepared by the present invention.

[0064] Embodiment 1: Fabricate on a silicon carbide substrate with m = 5, the thickness a of the barrier layer 4 is 22 nm, the Al component is 0.3, the materials of the left P-type block 6 and the right P-type block 7 are P-type CuO, the doping concentrations are both 3×10 20 cm -3 , the thicknesses are both 230 nm, the dielectric block is selected as Si3N4 with a thickness of 45 nm, and a multi-channel control composite functional device with three T-shaped metal blocks corresponding to the first electrode 15 and the second electrode 16.

[0065] Step A. Epitaxially grow AlN material on the silicon carbide substrate 1 to fabricate the transition layer 2.

[0066] Set the process conditions of a temperature of 1050 °C, a pressure of 45 Torr, a hydrogen flow rate of 4500 sccm, an ammonia flow rate of 4500 sccm, and an aluminum source flow rate of 7 μmol / min. Use metal organic chemical vapor deposition technology to epitaxially grow 70-nm-thick AlN material on the silicon carbide substrate 1 to form the transition layer 2.

[0067] Step B. Epitaxially grow GaN material on the transition layer 2 to form the channel layer 3.

[0068] Set the process conditions as follows: temperature is 1020 °C, pressure is 48 Torr, hydrogen flow rate is 4800 sccm, ammonia flow rate is 4800 sccm, and gallium source flow rate is 100 μmol / min. Use metalorganic chemical vapor deposition technology to epitaxially grow a GaN material with a thickness of 9.93 μm on the transition layer 2 to form the channel layer 3.

[0069] Step C. Deposit Al 0.3 Ga 0.7 N to fabricate the barrier layer 4.

[0070] Set the process conditions as follows: temperature is 980 °C, pressure is 46 Torr, hydrogen flow rate is 4500 sccm, ammonia flow rate is 4500 sccm, gallium source flow rate is 36 μmol / min, and aluminum source flow rate is 7 μmol / min. Use metalorganic chemical vapor deposition technology to deposit an Al 0.3 Ga 0.7 N barrier layer 4 with a thickness of 22 nm and an aluminum component of 0.3 on the channel layer 3.

[0071] Step D. Fabricate a P-type layer on the barrier layer 4.

[0072] Select copper with a purity of 99.999% as the target material, high-purity argon as the sputtering gas, and high-purity oxygen with the same purity as the reaction gas. Set the vacuum degree of the reaction chamber before sputtering to 2.0×10 -4 Pa, maintain the argon flow rate at 20 sccm and the oxygen flow rate at 10 sccm during sputtering, the pressure in the deposition chamber is 0.5 Pa, the RF power is 35 W, and the substrate temperature is 200 °C. Use magnetron sputtering technology to epitaxially grow CuO with a thickness of 230 nm and a doping concentration of 3×10 20 cm -3 on the barrier layer 4 to form the P-type layer.

[0073] Step E. Epitaxially grow the dielectric material Si3N4 on the P-type layer.

[0074] Set the process conditions as follows: NH3 flow rate is 2.5 sccm, N2 flow rate is 950 sccm, SiH4 flow rate is 250 sccm, temperature is 300 °C, RF power is 50 W, and pressure is 950 mT. Use plasma-enhanced chemical vapor deposition technology to deposit a Si3N4 material with a thickness of 45 nm on the P-type CuO layer to form the dielectric layer.

[0075] Step F. Etch to form the isolation deep trench 5.

[0076] Set the process conditions for etching the dielectric Si3N4 as follows: CF4 flow rate is 45 sccm, O2 flow rate is 5 sccm, pressure is 15 mT, and power is 250 W;

[0077] Set the process conditions for etching other layers of semiconductor material as follows: the flow rate of Cl2 is 18 sccm, the pressure is 14 mTorr, and the power is 120 W;

[0078] A mask is fabricated for the first time on the Si3N4 dielectric layer. Using this mask and reactive ion etching technology, the dielectric layer, P-type layer, barrier layer 4, and channel layer 3 are etched in sequence until the inside of the channel layer 3 is reached. The total etching depth is 370 nm, forming five deep grooves, and these five deep grooves constitute the isolation deep groove 5; the isolation deep groove 5 divides the channel layer 3 and the barrier layer 4 into six strip-shaped structures.

[0079] Step G. Etch to form the left P-type block 6, right P-type block 7, left dielectric block 8, and right dielectric block 9.

[0080] G1) Set the etching process conditions with a CF4 flow rate of 45 sccm, an O2 flow rate of 5 sccm, a pressure of 15 mT, and a power of 250 W. Fabricate a mask for the second time on the Si3N4 dielectric layer, P-type layer, channel layer 3, barrier layer 4, and isolation deep groove 5 etched in step F. Using this mask and reactive ion etching technology, etch the etched dielectric layer again until the upper surface of the P-type layer is reached, forming the left dielectric block 8 and the right dielectric block 9;

[0081] G2) Set the process conditions with a Cl2 flow rate of 18 sccm, a pressure of 13 mTorr, and a power of 130 W. Using the mask fabricated for the second time again and reactive ion etching technology, etch the P-type layer until the upper surface of the barrier layer 4 is reached, forming the left P-type block 6 and the right P-type block 7.

[0082] Step H. Fabricate the left electrode 10, right electrode 11, and node 12 on the barrier layer 4.

[0083] Set the vacuum degree to be less than 1.8×10 -3 Pa, the power is 400 W, and the evaporation rate is less than Under the process conditions, fabricate a mask for the third time on the channel layer 3, barrier layer 4, isolation deep groove 5, left dielectric block 8, and right dielectric block 9. Using this mask and electron beam evaporation technology, deposit multiple layers of metal on the upper left, upper right, and middle parts of the barrier layer 4 respectively. The metal combination from bottom to top is Ti / Al / Mo / Au, and their thicknesses are 0.015 μm / 0.132 μm / 0.048 μm / 0.056 μm respectively, and perform rapid thermal annealing for 35 s in an N2 atmosphere at a temperature of 870 °C, forming the left electrode 10, node 12, and right electrode 11 from left to right in sequence.

[0084] Step I. Fabricate the first electrode 15 and the second electrode 16.

[0085] I1) Set the process conditions of Cl2 flow rate to 18 sccm, pressure to 15 mTorr, and power to 110 W. Fabricate the mask for the fourth time on the channel layer 3, barrier layer 4, isolation deep trench 5, left dielectric block 8, right dielectric block 9, left electrode 10, right electrode 11, and node 12. Using this mask and reactive ion etching, etch the barrier layer 4 and channel layer 3 on the right side of the left P-type block 6 and the right side of the right P-type block 7 on each strip structure in sequence. The total etching depth h is 105 nm, and three rectangular grooves with the same size and equally spaced are formed on the right side of each left P-type block 6 and the right side of each right P-type block 7; The three rectangular grooves on the right side of each left P-type block 6 form the left groove 13, and the three rectangular grooves on the right side of each right P-type block 7 form the right groove 14;

[0086] I2) Set the vacuum degree to be less than 1.8×10 -3 Pa, the power to be 520 W, and the evaporation rate to be less than The process conditions are as follows. Fabricate the mask for the fifth time on the channel layer 3, barrier layer 4, isolation deep trench 5, left dielectric block 8, right dielectric block 9, left electrode 10, right electrode 11, node 12, left groove 13, and right groove 14. Using this mask and electron beam evaporation technology, deposit the metal combination Ta / Au with thicknesses of 0.223 μm / 0.137 μm respectively on the upper part of the barrier layer 4 inside each left groove 13 and on both sides of the left groove 13, and on the upper part of the barrier layer 4 inside each right groove 14 and on both sides of the right groove 14, respectively, to form three T-shaped metal strips, which successively constitute the first electrode 15 and the second electrode 16.

[0087] Step J. Fabricate the gate 17 and gate 18 on the left dielectric block 8 and the right dielectric block 9 respectively.

[0088] Set the process conditions of the sputtering gas pressure to be about 0.1 Pa, the flow rate of Ar to be 8 sccm, the substrate temperature to be fixed at 200 °C, and the target radio frequency power to be 150 W. Fabricate the mask for the sixth time on the channel layer 3, barrier layer 4, isolation deep trench 5, left dielectric block 8, right dielectric block 9, left electrode 10, right electrode 11, node 12, first electrode 15, and second electrode 16. Using this mask, sputter the metal combination Ta / Au with thicknesses of 0.025 μm / 0.45 μm respectively on the upper parts of the left dielectric block 8 and the right dielectric block 9 by sputtering technology to form the left gate 17 and the right gate 18 respectively, and complete the fabrication of the entire device.

[0089] Example 2: Fabricate on the sapphire substrate with m = 1, the thickness a of the barrier layer 4 is 1 nm, the Al component is 0.4, the materials of the left P-type block 6 and the right P-type block 7 are P-type GaN, and the doping concentrations are both 1×10 22 cm -3, a multi-channel control composite functional device with a thickness of 5 nm. The dielectric block is made of Al2O3 with a thickness of 5 nm, and the number of T-shaped metal blocks corresponding to the first electrode 15 and the second electrode 16 is two.

[0090] Step 1. Epitaxially grow GaN material on the sapphire substrate 1 to fabricate the transition layer 2.

[0091] Use metal organic chemical vapor deposition technology to epitaxially grow GaN material with a thickness of 30 nm on the sapphire substrate 1 to form the transition layer 2;

[0092] The deposition process conditions are: temperature is 500 °C, pressure is 46 Torr, hydrogen flow rate is 4300 sccm, ammonia flow rate is 4300 sccm, and gallium source flow rate is 21 μmol / min.

[0093] Step 2. Epitaxially grow GaN material on the transition layer 2 to form the channel layer 3.

[0094] Use metal organic chemical vapor deposition technology to epitaxially grow GaN material with a thickness of 1.94 μm on the transition layer 2 to form the undoped channel layer 3;

[0095] The process conditions are: temperature is 960 °C, pressure is 48 Torr, hydrogen flow rate is 4600 sccm, ammonia flow rate is 4600 sccm, and gallium source flow rate is 110 μmol / min.

[0096] Step 3. Deposit Al 0.4 Ga 0.6 N to fabricate the barrier layer 4.

[0097] Use metal organic chemical vapor deposition technology to deposit an undoped Al 0.4 Ga 0.6 N barrier layer 4 with a thickness of 1 nm and an aluminum component of 0.4 on the channel layer 3;

[0098] The deposition process conditions are: temperature is 980 °C, pressure is 43 Torr, hydrogen flow rate is 4200 sccm, ammonia flow rate is 4200 sccm, gallium source flow rate is 35 μmol / min, and aluminum source flow rate is 7 μmol / min.

[0099] Step 4. Fabricate the P-type layer on the barrier layer 4.

[0100] Use metal organic chemical vapor deposition technology to epitaxially grow P-type GaN with a thickness of 5 nm and a doping concentration of 1×10 22 cm -3 on the barrier layer 4 to form the P-type GaN layer;

[0101] The process conditions for deposition are as follows: the temperature is 950 °C, the pressure is 42 Torr, the hydrogen flow rate is 4100 sccm, a high-purity Mg source is used as the dopant, the ammonia flow rate is 4100 sccm, and the gallium source flow rate is 100 μmol / min.

[0102] Step 5. Epitaxially grow a dielectric material Al2O3 on the P-type layer to form a dielectric layer.

[0103] On the P-type GaN layer, using atomic layer deposition technology, deposit an Al2O3 material with a thickness of 5 nm to form a dielectric layer;

[0104] The process conditions for atomic layer deposition technology are as follows: the reaction sources are trimethylaluminum (TMA) and deionized water, the reaction temperature is 300 °C, the reaction chamber pressure is 5 Torr, and a single reaction cycle includes 1.5 s of trimethylaluminum gas introduction, 3 s of nitrogen purge, 1 s of deionized water vapor introduction, and 3 s of nitrogen purge.

[0105] Step 6. Etch to form isolation deep trench 5.

[0106] A mask is fabricated on the Al2O3 dielectric layer for the first time. Using this mask and reactive ion etching technology, etch the dielectric layer, P-type layer, barrier layer 4, and channel layer 3 in sequence until the inside of the channel layer 3 is reached. The total etching depth is 20 nm to form a deep trench, which is the isolation deep trench 5; this isolation deep trench 5 divides the channel layer 3 and the barrier layer 4 into two strip-shaped structures;

[0107] The process conditions for etching are as follows: the Cl2 flow rate is 18 sccm, the pressure is 14 mTorr, and the power is 120 W.

[0108] Step 7. Etch to form left P-type block 6, right P-type block 7, left dielectric block 8, and right dielectric block 9.

[0109] 7a) Fabricate a mask on the etched dielectric layer, P-type layer, channel layer 3, barrier layer 4, and isolation deep trench 5 for the second time. Using this mask and reactive ion etching technology, etch the etched dielectric layer again until the upper surface of the P-type layer is reached to form left dielectric block 8 and right dielectric block 9;

[0110] The process conditions for etching are as follows: the Cl2 flow rate is 18 sccm, the pressure is 14 mTorr, and the power is 120 W;

[0111] 7b) Use this mask again and use reactive ion etching technology to etch the P-type layer until the upper surface of the barrier layer 4 is reached to form left P-type block 6 and right P-type block 7;

[0112] The process conditions for etching are as follows: the Cl2 flow rate is 15 sccm, the pressure is 12 mTorr, and the power is 80 W.

[0113] Step 8. Fabricate the left electrode 10, right electrode 11 and node 12 on the barrier layer 4.

[0114] Fabricate a mask for the third time on the channel layer 3, barrier layer 4, isolation deep trench 5, left dielectric block 8 and right dielectric block 9. Using this mask and the electron beam evaporation technique, deposit multiple layers of metal on the upper left, right and middle parts of the barrier layer 4. The metal combination is Al, Ni and Au from bottom to top, with thicknesses of 0.153 μm / 0.045 μm / 0.052 μm respectively, and perform rapid thermal annealing in an N2 atmosphere to form the left electrode 10, node 12 and right electrode 11 from left to right in sequence;

[0115] The process conditions of the electron beam evaporation technique are: the vacuum degree is less than 1.8×10 -3 Pa, the power is 500W, and the evaporation rate is less than

[0116] The process conditions for rapid thermal annealing are: the temperature is 870 °C and the time is 35 s.

[0117] Step 9. Fabricate the first electrode 15 and the second electrode 16.

[0118] 9a) Fabricate a mask for the fourth time on the channel layer 3, barrier layer 4, isolation deep trench 5, left dielectric block 8, right dielectric block 9, left electrode 10, right electrode 11 and node 12. Using this mask and the reactive ion etching technique, etch the barrier layer 4 and the channel layer 3 on the right side of the left P-type block 6 and the right side of the right P-type block 7 on each strip structure in sequence. The total etching depth h is 9 nm, and two rectangular grooves of the same size are formed on the right side of each left P-type block 6 and on the right side of each right P-type block 7; The two rectangular grooves on the right side of each left P-type block 6 form the left groove 13, and the two rectangular grooves on the right side of each right P-type block 7 form the right groove 14;

[0119] The process conditions of the reactive ion etching are: the Cl2 flow rate is 15 sccm, the pressure is 12 mTorr, and the power is 95W.

[0120] 9b) Fabricate a mask for the fifth time on the channel layer 3, barrier layer 4, isolation deep trench 5, left dielectric block 8, right dielectric block 9, left electrode 10, right electrode 11, node 12, left groove 13 and right groove 14. Using this mask and the electron beam evaporation technique, deposit the metal combination Ni / Au with thicknesses of 0.003 μm / 0.017 μm respectively on the inside of each left groove 13 and on the upper part of the barrier layer 4 on both sides of the left groove 13, and on the inside of each right groove 14 and on the upper part of the barrier layer 4 on both sides of the right groove 14 to form two T-shaped metal strips, which in sequence constitute the first electrode 15 and the second electrode 16;

[0121] The process conditions for evaporating the metal are as follows: the vacuum degree is less than 1.8×10 -3 Pa, the power is 200W, and the evaporation rate is less than

[0122] Step 10. Fabricate the gate 17 and the gate 18 on the left dielectric block 8 and the right dielectric block 9 respectively.

[0123] A mask is fabricated for the sixth time on the channel layer 3, the barrier layer 4, the isolation deep trench 5, the left dielectric block 8, the right dielectric block 9, the left electrode 10, the right electrode 11, the node 12, the first electrode 15, and the second electrode 16. Using this mask, a metal combination Ni / Au is deposited on the upper parts of the left dielectric block 8 and the right dielectric block 9 by electron beam evaporation technology, with thicknesses of 0.063μm / 0.037μm respectively, to form the left gate 17 and the right gate 18 respectively, thus completing the fabrication of the entire device.

[0124] The process conditions for electron beam evaporation technology are as follows: the vacuum degree is less than 1.8×10 -3 Pa, the power is 500W, and the evaporation rate is less than

[0125] Example 3: Fabricate a multi-channel control composite functional device with m = 4 on a silicon substrate, where the thickness a of the barrier layer 4 is 40nm, the Al component is 0.1, the materials of the left P-type block 6 and the right P-type block 7 are P-type NiO, the doping concentrations are both 5×10 15 cm -3 , the thicknesses are both 500nm, the dielectric block is selected as HfO2 with a thickness of 100nm, and the number of T-shaped metal blocks corresponding to the first electrode 15 and the second electrode 16 is six.

[0126] The first step. Epitaxially grow an AlN material on the silicon substrate 1 to fabricate the transition layer 2.

[0127] Using metal organic chemical vapor deposition technology under the process conditions of a temperature of 820°C, a pressure of 42 Torr, a hydrogen flow rate of 4300 sccm, an ammonia flow rate of 4300 sccm, and an aluminum source flow rate of 21 μmol / min, epitaxially grow an AlN material with a thickness of 400nm on the silicon substrate 1 to form the transition layer 2.

[0128] The second step. Epitaxially grow a GaN material on the transition layer 2 to form the channel layer 3.

[0129] Using metal organic chemical vapor deposition technology under the process conditions of a temperature of 970°C, a pressure of 44 Torr, a hydrogen flow rate of 4400 sccm, an ammonia flow rate of 4400 sccm, and a gallium source flow rate of 110 μmol / min, epitaxially grow a GaN material with a thickness of 6.6μm on the transition layer 2 to form the channel layer 3.

[0130] Step 3. Deposit undoped Al on the channel layer 3 0.1 Ga 0.9 N to fabricate the barrier layer 4.

[0131] Using metalorganic chemical vapor deposition technology, deposit undoped Al with a thickness of 40 nm and an Al composition of 0.1 on the GaN channel layer 3 under the process conditions of a temperature of 990 °C, a pressure of 44 Torr, a hydrogen flow rate of 4500 sccm, an ammonia flow rate of 4500 sccm, a gallium source flow rate of 36 μmol / min, and an aluminum source flow rate of 8 μmol / min 0.1 Ga 0.9 N barrier layer 4.

[0132] Step 4. Fabricate a P-type layer on the barrier layer 4.

[0133] Using magnetron sputtering technology, epitaxially dope a NiO material with a doping concentration of 5×10 15 cm -3 and a thickness of 500 nm on the barrier layer 4 to form a P-type NiO layer.

[0134] Step 5. Epitaxially deposit a dielectric material HfO2 on the P-type layer to form a dielectric layer.

[0135] Using radio frequency magnetron reactive sputtering technology, epitaxially deposit an HfO2 material with a thickness of 100 nm on the P-type NiO layer under the process conditions of a sputtering gas pressure in the reaction chamber maintained at about 0.1 Pa, O2 and Ar flow rates of 1 sccm and 8 sccm respectively, a substrate temperature fixed at 200 °C, and an Hf target radio frequency power of 150 W to form a dielectric layer.

[0136] Step 6. Etch to form isolation deep trenches 5.

[0137] 6.1) Fabricate a mask on the HfO2 dielectric layer for the first time. Using this mask, employ reactive ion etching technology to etch the HfO2 dielectric layer under the process conditions of a CF4 flow rate of 45 sccm, an O2 flow rate of 5 sccm, a pressure of 15 mT, and a power of 250 W until reaching the upper surface of the P-type layer;

[0138] 6.2) Under the process conditions of a Cl2 flow rate of 18 sccm, a pressure of 14 mTorr, and a power of 120 W, use the mask fabricated for the first time to etch the P-type layer, the barrier layer 4, and the channel layer 3 in sequence until reaching the inside of the channel layer 3. The total etching depth is 600 nm to form four deep trenches, and these four deep trenches constitute the isolation deep trenches 5; the isolation deep trenches 5 divide the channel layer 3 and the barrier layer 4 into five strip-shaped structures.

[0139] Step 7. Etch to form the left P-type block 6, right P-type block 7, left dielectric block 8, and right dielectric block 9.

[0140] 7.1) Fabricate a mask for the second time on the dielectric layer, P-type layer, channel layer 3, barrier layer 4, and isolation trench 5 after the etching in Step 6. Using this mask, under the etching process conditions of a CF4 flow rate of 45 sccm, an O2 flow rate of 5 sccm, a pressure of 15 mT, and a power of 250 W, use reactive ion etching technology to etch the dielectric layer again until reaching the upper surface of the P-type layer, forming the left dielectric block 8 and right dielectric block 9;

[0141] 7.2) Again use the mask fabricated for the first time. Under the process conditions of a Cl2 flow rate of 18 sccm, a pressure of 14 mTorr, and a power of 120 W, etch the P-type layer until reaching the upper surface of the barrier layer 4, forming the left P-type block 6 and right P-type block 7;

[0142] Step 8. Fabricate the left electrode 10, right electrode 11, and node 12 on the barrier layer 4.

[0143] Fabricate a mask for the third time on the channel layer 3, barrier layer 4, isolation trench 5, left dielectric block 8, and right dielectric block 9. Using this mask, on the left, right, and middle parts above the barrier layer 4, use electron beam evaporation technology under the process conditions of a vacuum degree less than 1.9×10 - 3 Pa, a power of 510 W, and an evaporation rate less than to deposit multiple layers of metals Ta, Pt, and Au with thicknesses of 0.122 μm / 0.317 μm / 0.161 μm respectively, and perform rapid thermal annealing for 30 s in an N2 atmosphere at a temperature of 880 °C to form the left electrode 10, node 12, and right electrode 11 from left to right in sequence.

[0144] Step 9. Fabricate the first electrode 15 and second electrode 16.

[0145] 9.1) Fabricate a mask for the fourth time on the channel layer 3, barrier layer 4, isolation trench 5, left dielectric block 8, right dielectric block 9, left electrode 10, right electrode 11, and node 12. Using this mask, use reactive ion etching. Under the process conditions of a Cl2 flow rate of 18 sccm, a pressure of 14 mTorr, and a power of 120 W, etch the barrier layer 4 and channel layer 3 on the right side of the left P-type block 6 and the right side of the right P-type block 7 in sequence. The total etching depth h is 70 nm, and six rectangular grooves with the same size and equally spaced are formed on the right side of each left P-type block 6 and each right P-type block 7; The six rectangular grooves on the right side of each left P-type block 6 form the left groove 13, and the six rectangular grooves on the right side of each right P-type block 7 form the right groove 14;

[0146] 9.2) A mask is fabricated for the fifth time on the channel layer 3, the barrier layer 4, the isolation trench 5, the left dielectric block 8, the right dielectric block 9, the left electrode 10, the right electrode 11, the node 12, the left groove 13 and the right groove 14. Using this mask and the electron beam evaporation technique, in a vacuum less than 1.8×10 -3 Pa, with a power of 500 W and an evaporation rate less than Under the process conditions, metal combinations Ti / Au with thicknesses of 0.063 μm / 0.037 μm are respectively deposited on the upper part of the barrier layer 4 inside each left groove 13 and on both sides of the left groove 13, and on the upper part of the barrier layer 4 inside each right groove 14 and on both sides of the right groove 14, forming six T-shaped metal strips, which successively constitute the first electrode 15 and the second electrode 16.

[0147] Step ten. Gates 17 and 18 are respectively fabricated on the left dielectric block 8 and the right dielectric block 9.

[0148] A mask is fabricated for the sixth time on the channel layer 3, the barrier layer 4, the isolation trench 5, the left dielectric block 8, the right dielectric block 9, the left electrode 10, the right electrode 11, the node 12, the first electrode 15 and the second electrode 16. Using this mask and the electron beam evaporation technique, in a vacuum less than 1.8×10 -3 Pa, with a power of 530 W and an evaporation rate less than Under the process conditions, metal combinations Pt / Au are evaporated on the upper parts of the left dielectric block 8 and the right dielectric block 9, with thicknesses of 0.528 μm / 0.262 μm respectively, forming the left gate 17 and the right gate 18; the fabrication of the entire device is completed.

[0149] The effects of the present invention can be further illustrated by the following simulations.

[0150] Simulation content: The output characteristics and blocking characteristics of the first embodiment of the present invention are respectively simulated, and the results are as Figure 6 , where:

[0151] Figure 6 (a) is the output characteristic curve graph, Figure 6 (b) is the bi-directional blocking characteristic graph. It can be seen from Figure 6 that the turn-on voltage of the device of the present invention is less than 0.2 V, and the forward blocking voltage is 1437 V, and the reverse blocking voltage is -1401 V, indicating that the device of the present invention has good unidirectional conduction characteristics and bi-directional blocking characteristics.

[0152] The above description is only three specific embodiments of the present invention and does not constitute a limitation to the present invention. Obviously, for professionals in the field, after understanding the content and principle of the present invention, various modifications and changes in form and details can be made according to the method of the present invention without departing from the principle and scope of the present invention. However, these modifications and changes based on the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A multi-channel control composite function device, comprising, from bottom to top: The substrate (1), the transition layer (2), the channel layer (3) and the barrier layer (4) are characterized by: Isolation deep trenches (5) are provided inside the channel layer (3) and the barrier layer (4), and the isolation deep trenches (5) are composed of m deep trenches of the same size and distributed frontally and rearwardly, and the distance between two adjacent deep trenches is equal, and m>1; The isolation deep trench (5) divides the channel layer (3) and the barrier layer (4) into m+1 strip structures, and on each strip structure, a left electrode (10), a left P-type block (6), a left groove (13), a node (12), a right P-type block (7), a right groove (14), and a right electrode (11) are sequentially arranged from left to right; The left P-type block (6) and the right P-type block (7) are both located on the upper portion of the barrier layer (4), and a left dielectric block (8) and a right dielectric block (9) are respectively provided on the upper side thereof; The left groove (13) and the right groove (14) are both composed of n rectangular grooves, which are arranged in parallel at equal intervals, and their lower sides are all located in the channel layer (3); A first electrode (15) is provided in the left groove (13), and a second electrode (16) is provided in the right groove (14), wherein the first electrode and the second electrode are both composed of n T-shaped metal blocks of the same size, wherein the lower sides of the vertical parts of the T-shaped metal blocks are located inside the channel layer (3), and the lower sides of the horizontal parts are located on the upper surface of the barrier layer (4), and n>1; A left grid (17) and a right grid (18) are respectively provided on the upper parts of the left dielectric block (8) and the right dielectric block (9).

2. The device according to claim 1, characterized in that, The Al component of the barrier layer (4) is 0.1-0.4, and its thickness a is 1 nm-40 nm.

3. The device according to claim 1, characterized in that, The left P-type block (6) and the right P-type block (7) are made of P-GaN or CuO or NiO materials, with a thickness of 5 nm to 500 nm and doping concentrations of 5×10 15 cm -3 ~1×10 22 cm -3 .

4. The device according to claim 1, wherein The left dielectric block (8) and the right dielectric block (9) are made of Al2O3, HfO2 or Si3N4, and have a thickness of 5nm to 100nm.

5. The device according to claim 1, wherein The depths of the n rectangular grooves in the left groove (13) and the right groove (14) on each strip structure are both h, h>a, where a is the thickness of the barrier layer (4).

6. The device according to claim 1, wherein: On each strip structure, among the n T-shaped metal blocks respectively included in the first electrode (15) and the second electrode (16), the distance between the first T-shaped metal block and the second T-shaped metal block is t1, the distance between the second T-shaped metal block and the third T-shaped metal block is t2, ..., the distance between the n-1th T-shaped metal block and the nth T-shaped metal block is t n-1 , and satisfies t1=t2=…=t n-1 , the distance between the lower side of the vertical part of each T-shaped metal block and the upper surface of the barrier layer is h; The distance between the left end of the horizontal part of the T-shaped metal block in each first electrode (15) and the right end of the left P-shaped block (6) is x1, and the distance between the right end of the horizontal part and the node (12) is u1; The distance between the left end of the horizontal part of the T-shaped metal block in each second electrode (16) and the right end of the right P-type block (7) is x2, and the distance between the right end of the horizontal part and the right electrode (11) is u2; and x1=x2=x, u1=u2=u, where x is much smaller than u, and u>1μm.

7. The device according to claim 1, characterized in that, The left grid (17) and the right grid (18) are both shorter than the lengths of the corresponding left dielectric block (8) and right dielectric block (9).

8. The device according to claim 1, wherein: The left electrode (10), the right electrode (11) and the node (12) are all in ohmic contact with the barrier layer (4); The first electrode (15) forms Schottky contacts with the barrier layer (4) and the channel layer (3) respectively; The second electrode (16) forms Schottky contacts with the barrier layer (4) and the channel layer (3) respectively.

9. A method for manufacturing a multi-channel control composite function device as claimed in claim 1, characterized in that: The steps include: A) Epitaxially grow a GaN-based wide bandgap semiconductor material on a substrate (1) to form a transition layer (2); B) Epitaxially grow a GaN material on the transition layer (2) to form a channel layer (3); C) Epitaxially grow a GaN-based wide bandgap semiconductor material on the channel layer (3) to form a barrier layer (4) with a thickness of a; D) Epitaxially grow a P-type semiconductor material on the barrier layer (4) to form a P-type layer with a thickness of 5 nm to 500 nm and a doping concentration of 5×10 15 ~1×10 22 cm -3 . E) Epitaxially grow a dielectric material on the P-type layer to form a dielectric layer with a thickness of 5 nm to 100 nm; F) Fabricate a mask for the first time on the dielectric layer, and use the mask to etch the dielectric layer, P-type layer, barrier layer (4), and channel layer (3) in sequence until reaching the inside of the channel layer (3), forming m deep grooves with the same size and equally spaced and arranged in parallel. These m deep grooves together form an isolation deep groove (5); these m deep grooves divide the channel layer (3) and the barrier layer (4) into m + 1 strip-shaped structures; G) Etch to form a left P-type block (6), a right P-type block (7), a left dielectric block (8), and a right dielectric block (9): G1) Fabricate a mask for the second time on the etched dielectric layer, P-type layer, channel layer (3), barrier layer (4), and isolation deep groove (5), and use the mask to etch the etched dielectric layer again until reaching the upper surface of the P-type layer, forming a left dielectric block (8) and a right dielectric block (9); G2) Use the mask again to etch the P-type layer until reaching the upper surface of the barrier layer (4), forming a left P-type block (6) and a right P-type block (7); H) Fabricate a mask for the third time on the channel layer (3), barrier layer (4), isolation deep groove (5), left dielectric block (8), and right dielectric block (9), and use the mask to deposit multiple layers of metal on the upper left and right sides and the middle part of the barrier layer (4), and perform rapid thermal annealing in an N2 atmosphere to form a left electrode (10), a right electrode (11), and a node (12); I) Fabricate a first electrode (15) and a second electrode (16): I1) A mask is fabricated for the fourth time on the channel layer (3), the barrier layer (4), the isolation deep trench (5), the left dielectric block (8), the right dielectric block (9), the left electrode (10), the right electrode (11), and the node (12). Using this mask, the barrier layer (4) and the channel layer (3) on the right side of the left P-type block (6) and the right side of the right P-type block (7) are etched successively, with a total etching depth of h. n rectangular grooves of the same size are formed on the right side of each left P-type block (6) and the right side of each right P-type block (7). The distances between adjacent two of the n rectangular grooves are t1, t2, …, t n-1 , and t1 = t2 = … = t n-1 ; The n rectangular grooves on the right side of each left P-type block (6) form the left groove (13), and the n rectangular grooves on the right side of each right P-type block (7) form the right groove (14); I2) Fabricate a mask for the fifth time on the channel layer (3), barrier layer (4), isolation deep groove (5), left dielectric block (8), right dielectric block (9), left electrode (10), right electrode (11), node (12), left groove (13), and right groove (14), and use the mask to deposit metal inside each left groove (13) and on the upper part of the barrier layer (4) on both sides of the left groove (13) to form a first electrode (15); deposit metal inside each right groove (14) and on the upper part of the barrier layer (4) on both sides of the right groove (14) to form a second electrode (16); J) Fabricate a mask for the sixth time on the channel layer (3), barrier layer (4), isolation deep groove (5), left dielectric block (8), right dielectric block (9), left electrode (10), right electrode (11), node (12), first electrode (15), and second electrode (16), and use the mask to deposit metal on the upper parts of the left dielectric block (8) and the right dielectric block (9) to form a left gate (17) and a right gate (18) respectively, completing the fabrication of the entire device.

10. The method for fabricating a multi-channel control composite function device as claimed in claim 1 according to claim 9, wherein: The epitaxial techniques used in steps A), B), C), D), and E) include: metalorganic chemical vapor deposition technique, plasma-enhanced chemical vapor deposition technique, atomic layer deposition technique, and magnetron sputtering technique; The metal deposition processes used in steps H), I), and J) include: electron beam evaporation process and sputtering process.

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