Method for forming a semiconductor device having a memory cell, a high voltage device and a logic device on a substrate

Abstract

The present invention relates to a method for forming a semiconductor device, which is carried out by the following steps: making the upper surface of a semiconductor substrate in a first region and a second region but not in a third region recessed; forming a first conductive layer in the third region; forming a second conductive layer in all three regions; removing the first conductive layer and the second conductive layer from the second region and removing parts of the first conductive layer and the second conductive layer from the first region, thereby forming a stacked structure pair, each stacked structure pair having a control gate above a floating gate; forming a third conductive layer in all three regions; forming a protective layer in the first region and the second region; and then removing the third conductive layer from the third region; then forming a pseudo conductive material block in the third region; then etching in the first region and the second region to form a select gate and an HV gate; and then replacing these pseudo conductive material blocks with metal material blocks.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having an embedded non-volatile memory cell. Background Art

[0002] Non-volatile memory semiconductor devices formed on silicon semiconductor substrates are well known. For example, U.S. Patents 6,747,310, 7,868,375, and 7,927,994 disclose memory cells formed on semiconductor substrates with four gates (floating gate, control gate, select gate, and erase gate), which are incorporated herein by reference for all purposes. The source region and the drain region are formed as diffusion implantation regions into the substrate, thereby defining the channel region in the substrate between the source region and the drain region. The floating gate is disposed above a first portion of the channel region and controls the conductivity of the first portion, the select gate is disposed above a second portion of the channel region and controls the conductivity of the second portion, the control gate is disposed above the floating gate, and the erase gate is disposed above the source region and is laterally adjacent to the floating gate.

[0003] It is also known to form low voltage logic devices and high voltage logic devices on the same substrate as non-volatile memory cells. See, for example, U.S. Pat. No. 9,276,005, which is incorporated herein by reference for all purposes. New gate materials (such as high-K dielectric gates and metal gates) are also used to improve performance. However, the processing steps to form memory cells may adversely affect currently manufactured logic devices, and vice versa.

[0004] What is needed is an improved method of fabricating devices including memory cells, low voltage logic devices, and high voltage devices on the same substrate. Summary of the invention

[0005] The foregoing problems and needs are addressed by a method of forming a semiconductor device, the method comprising:

[0006] Providing a substrate of semiconductor material, the substrate of semiconductor material comprising a first region, a second region and a third region;

[0007] SST 351913-980220-MTI-20155.CN01

[0008] causing an upper surface of the substrate in the first region and an upper surface of the substrate in the second region to be recessed relative to an upper surface of the substrate in the third region;

[0009] forming a first conductive layer disposed above the upper surface in the first region, the second region, and the third region and insulated from the upper surface;

[0010] forming an insulating layer on the first conductive layer in the first region, the second region, and the third region;

[0011] thinning the insulating layer in the third region, but not thinning the insulating layer in the first region and the second region;

[0012] forming trenches in the first region, the second region, and the third region that pass through the insulating layer and the first conductive layer and enter the substrate;

[0013] filling the trench with an insulating material;

[0014] After filling the trench, removing the insulating layer from the first region, the second region, and the third region;

[0015] forming a second conductive layer, the second conductive layer being disposed above the first conductive layer in the first region, the second region, and the third region and being insulated from the first conductive layer;

[0016] performing one or more etches to selectively remove portions of the first conductive layer and the second conductive layer in the first region to completely remove the first conductive layer and the second conductive layer from the second region and the third region, wherein the one or more etches result in forming a pair of stacked structures in the first region, wherein each of the stacked structures includes a control gate of the second conductive layer, the control gate of the second conductive layer being disposed above a floating gate of the first conductive layer and insulated from the floating gate of the first conductive layer;

[0017] forming first source regions in the substrate, each first source region being disposed between one of the stacked structure pairs;

[0018] forming a third conductive layer disposed above the upper surface of the substrate in the first region, the second region, and the third region and insulated from the upper surface of the substrate;

[0019] forming a protective insulating layer over the third conductive layer in the first region and the second region;

[0020] After forming the protective insulating layer, removing the third conductive layer from the third region;

[0021] SST 351913-980220-MTI-20155.CN01

[0022] After removing the third conductive layer from the third region, forming a dummy conductive material block, the dummy conductive material block being disposed above the upper surface in the third region and insulated from the upper surface;

[0023] After forming the pseudo conductive material block in the third region, etching portions of the protective insulating layer and portions of the third conductive layer in the first region and the second region to form a plurality of select gates of the third conductive layer, each select gate being disposed adjacent to one of the stack structures, and forming a plurality of HV gates of the third conductive layer, each HV gate being disposed above the upper surface of the substrate in the second region and insulated from the upper surface of the substrate;

[0024] forming first drain regions in the substrate, each first drain region being adjacent to one of the select gates;

[0025] forming second source regions in the substrate, each second source region being adjacent to one of the HV gates;

[0026] forming second drain regions in the substrate, each second drain region being adjacent to one of the HV gates;

[0027] forming third source regions in the substrate, each third source region being adjacent to one of the dummy conductive material blocks;

[0028] forming third drain regions in the substrate, each third drain region being adjacent to one of the dummy conductive material blocks; and

[0029] Each of the dummy conductive material blocks is replaced with a metal material block.

[0030] A method of forming a semiconductor device may include:

[0031] Providing a substrate of semiconductor material, the substrate of semiconductor material comprising a first region, a second region and a third region;

[0032] causing an upper surface of the substrate in the first region and an upper surface of the substrate in the second region to be recessed relative to an upper surface of the substrate in the third region;

[0033] forming an insulating layer over the substrate;

[0034] thinning the insulating layer in the third region, but not thinning the insulating layer in the first region and the second region;

[0035] forming trenches through the insulating layer and into the substrate in the first region, the second region, and the third region;

[0036] filling the trench with an insulating material;

[0037] SST 351913-980220-MTI-20155.CN01

[0038] After filling the trench, removing the insulating layer from the first region and the second region;

[0039] forming a first conductive layer disposed above the upper surface in the first region and the second region and insulated from the upper surface;

[0040] forming a second conductive layer disposed above the first conductive layer in the first region and the second region and insulated from the first conductive layer;

[0041] performing one or more etches to selectively remove portions of the first conductive layer and the second conductive layer in the first region to completely remove the first conductive layer and the second conductive layer from the second region, wherein the one or more etches result in forming a pair of stacked structures in the first region, wherein each of the stacked structures includes a control gate of the second conductive layer, the control gate of the second conductive layer being disposed above a floating gate of the first conductive layer and insulated from the floating gate of the first conductive layer;

[0042] forming first source regions in the substrate, each first source region being disposed between one of the stacked structure pairs;

[0043] forming a third conductive layer disposed above the upper surface of the substrate in the first region and the second region and insulated from the upper surface of the substrate;

[0044] forming a protective insulating layer over the third conductive layer in the first region and the second region;

[0045] After said forming said protective insulating layer, removing said protective insulating layer from said third region;

[0046] After removing the protective insulating layer from the third region, forming a dummy conductive material block, the dummy conductive material block being disposed above the upper surface in the third region and insulated from the upper surface;

[0047] After forming the pseudo conductive material block in the third region, etching portions of the protective insulating layer and portions of the third conductive layer in the first region and the second region to form a plurality of select gates of the third conductive layer, each select gate being disposed adjacent to one of the stack structures, and forming a plurality of HV gates of the third conductive layer, each HV gate being disposed above the upper surface in the second region and insulated from the upper surface;

[0048] forming first drain regions in the substrate, each first drain region being adjacent to one of the select gates;

[0049] SST 351913-980220-MTI-20155.CN01

[0050] forming second source regions in the substrate, each second source region being adjacent to one of the HV gates;

[0051] forming second drain regions in the substrate, each second drain region being adjacent to one of the HV gates;

[0052] forming third source regions in the substrate, each third source region being adjacent to one of the dummy conductive material blocks;

[0053] forming third drain regions in the substrate, each third drain region being adjacent to one of the dummy conductive material blocks; and

[0054] Each of the dummy conductive material blocks is replaced with a metal material block.

[0055] Other objects and features of the present invention will become apparent by examining the specification and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figures 1A to 16A is a cross-sectional view of a memory cell region, illustrating the steps of forming a memory cell.

[0057] Figures 1B to 16B is a cross-sectional view of the HV region, illustrating the steps of forming the HV device.

[0058] Figures 1C to 16C is a cross-sectional view of a logic area, illustrating the steps of forming a logic device.

[0059] Fig.17 is a cross-sectional view of a memory cell area showing a finished memory cell.

[0060] Fig.18 is a cross-sectional view of the HV area, showing the finished HV device.

[0061] Fig.19 is a cross-sectional view of the logic area, showing the finished logic device.

[0062] FIG. 20A to FIG. 25A is a cross-sectional view of a memory cell region illustrating steps in forming a memory cell in an alternative embodiment.

[0063] FIG. 20B to FIG. 25B is a cross-sectional view of the HV region showing the steps of forming the HV device in an alternative embodiment.

[0064] FIG. 20C to FIG. 25C is a cross-sectional view of a logic region illustrating steps in forming a logic device in an alternative embodiment. DETAILED DESCRIPTION

[0065] The present invention is a process for forming a semiconductor device by simultaneously forming a memory cell, a low voltage logic device, and a high voltage logic device on the same semiconductor substrate. The process described below involves forming a memory cell in one or more memory cell regions 2 (also referred to as a first region or MC region 2) of a substrate 10, forming a memory cell in one or more high voltage logic device regions 4 (also referred to as a first region or MC region 2) of the substrate 10, forming a memory cell in one or more high voltage logic device regions 4 (also referred to as a second region or MC region 2) of the substrate 10, forming a memory cell in one or more memory cell regions 2 ... memory cell regions 2 (also referred to as a first region or MC region 2) of the substrate 10, forming a memory cell in

[0066] The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon. The substrate 10 is a semiconductor material such as silicon.

[0067] MC Region 2 See Figures 1A to 16A , HV zone 4 see Figures 1B to 16B , and logical area 6 see Figures 1C to 16C, showing a cross-sectional view of the process steps for manufacturing a semiconductor device. The process initially causes the upper surface 10a of the silicon substrate 10 in the MC region 2 and the HV region 4 to be recessed by an amount R relative to the logic region 6. The recessing of the substrate upper surface 10a may preferably be performed by forming a silicon dioxide (also referred to herein as "oxide") layer on the substrate upper surface 10a and forming a silicon nitride (also referred to herein as "nitride") layer on the oxide layer. A photolithography masking step is performed to cover the logic region 6 with a photoresist without covering the MC region 2 and the HV region 4 (i.e., a photoresist is formed on all three regions, portions of the photoresist are selectively exposed, and portions of the photoresist are selectively removed, thereby exposing portions of the underlying structure (in this case, the nitride layer in the MC region 2 and the HV region 4), while leaving other portions of the underlying structure covered by the photoresist (in this case, the nitride layer in the logic region 6)). Nitride etching and oxide etching are performed to remove these layers from the MC region 2 and the HV region 4, thereby exposing the upper surface 10a in these regions. After removing the photoresist, thermal oxidation is then performed to form an oxide layer on the exposed portions of the upper surface 10a in the MC region 2 and the HV region 4, while not affecting the upper surface 10a in the logic region 6 (which is protected by the nitride and oxide layers). This thermal oxidation process consumes some silicon of the substrate 10 in the MC region 2 and the HV region 4, thereby effectively lowering the upper surface 10a in these regions by an amount of recess R. Nitride and oxide etching is then used to remove all of the oxide and nitride layers, thereby obtaining Figure 1A , Figure 1B and Figure 1C The upper surface 10 a in the MC region 2 and the HV region 4 is recessed by an amount R (eg, about 300 Å) relative to the upper surface 10 a in the logic region 6 .

[0068] Next, an oxide layer 12 is formed on the upper surface 10a (e.g., by deposition or by thermal growth, etc.). Thereafter, a conductive layer 14 (i.e., a first conductive layer), such as a polysilicon layer, is formed on the oxide layer 12. The conductive layer 14 may alternatively be in-situ doped or undoped amorphous silicon. If polysilicon or amorphous silicon is used for the conductive layer 14, implantation and annealing are performed. An oxide layer 18 is formed on the conductive layer 14, and then a nitride layer 20 is formed on the oxide layer 18. Then, a photolithography mask step is performed SST 351913-980220-MTI-20155.CN01

[0069] The MC region 2 and the HV region 4 are covered with the photoresist 21, but the logic region 6 is exposed (i.e., the photoresist 21 is removed from the logic region 6 as part of the masking step). The nitride layer 20 in the logic region 6 is then thinned (i.e., the thickness of the nitride layer is reduced) using a nitride etch (e.g., the etching time is preferably set so that the etching thins the nitride layer 20 in the logic region 6 by an amount approximately equal to the recess amount R, so that the top surface of the nitride layer 20 in all three regions 2 / 4 / 6 is substantially uniform), as shown in FIG. Figure 2A , Figure 2B and Figure 2C shown.

[0070] After removing the photoresist 21, a photolithographic masking step is used to selectively cover portions of each region with photoresist. Nitride etching, oxide etching, polysilicon etching, and / or silicon etching are used to form trenches through the nitride layer 20, the oxide layer 18, the conductive layer 14, the oxide layer 12, and into the silicon substrate 10. These trenches are then filled with oxide 22 by oxide deposition on the nitride layer 20 and chemical mechanical polishing (CMP) termination, as shown in FIG. Figure 3A and Figure 3B The trench filled with oxide 22 extends parallel to the active area in MC region 2, and because Figure 3A FIG. 1 is a cross-sectional view of one of the active areas, so the trench filled with oxide 22 is not in FIG. Figure 3A The oxide 22 is an insulating material which may also be referred to as an STI (shallow trench isolation) oxide 22. The STI oxide 22 may include a liner oxide formed by thermal oxidation prior to oxide deposition.

[0071] A series of implants may be performed to form the desired wells in the substrate 10 in each of the regions 2 / 4 / 6 (where the photoresist protects one or more of the other regions during each implant), followed by oxide etchback to recess the STI oxide 22 below the top of the nitride layer 20. Nitride etching is then used to remove the nitride layer 20. An insulating layer 24 is then formed over the structure. Preferably, the insulating layer 24 is an ONO composite layer having oxide / nitride / oxide sublayers (formed by oxide, nitride, oxide deposition and annealing). However, the insulating layer 24 may alternatively be formed by a composite of other dielectric layers or a single dielectric material without sublayers. Then, in one example, a conductive layer 26 (i.e., a second conductive layer), such as a polysilicon layer, is formed on the structure by deposition. The conductive layer 26 may alternatively be in-situ doped or undoped amorphous silicon. If the conductive layer 26 uses polysilicon or undoped amorphous silicon, implantation and annealing are performed. Then, a hard mask layer 28 is formed on the conductive layer 26. The hard mask layer 28 may be a nitride, SiCN, or a composite of oxide, nitride and / or SiCN layers. Figure 4A , Figure 4B and Figure 4C Shown in.

[0072] A photolithography masking step is used to form a photoresist 30 on the structure, wherein the photoresist is removed from the HV region 4 and the logic region 6 and the photoresist is selectively removed from the MC region 2 to expose the hard mask layer 28 in the HV region 4 and the logic region 6 and to expose the hard mask layer 28 in the MC region 2 SST 351913-980220-MTI-20155.CN01

[0073] Only a portion of layer 28 is exposed. A series of etches are used to remove the exposed portions of hard mask layer 28, conductive layer 26, and insulating layer 24, leaving a spaced-apart stacked structure S1 and S2 pair of hard mask layer 28, conductive layer 26, and insulating layer 24 in MC region 2, and completely removing these layers from HV region 4 and logic region 6. The resulting structure is Figure 5A , Figure 5B and Figure 5C Shown in.

[0074] After removing the photoresist 30, oxide deposition or thermal oxidation and etching are used to form oxide spacers 32 along the sides of the stacks S1 and S2 in the MC region 2. Nitride deposition and etching are used to form nitride spacers 34 along the sides of the oxide spacers 32. The oxide etching and nitride etching can be combined. Etching (such as polysilicon etching or silicon etching, depending on the material of the conductive layer 14) is performed to remove the exposed portions of the conductive layer 14, so that each spaced-apart stack structure S1 / S2 includes a conductive material block 14a from the remaining portion of the conductive layer 14 in the MC region 2, and the conductive layer 14 is completely removed from the HV region 4 / logic region 6. By oxide deposition and oxide anisotropic etching, oxide spacers 36 are formed on the sides of the stack structures S1 / S2 (including along the exposed ends of the conductive layer 14a blocks), as shown in FIG. Fig. 6A , Figure 6B and Figure 6C shown.

[0075] A photolithographic masking step is used to cover the MC region 2 and the logic region 6 with a photoresist, but to expose the HV region 4. Oxide etching is used to remove the oxide layer 12 from the HV region 4. After removing the photoresist, an insulating layer 38 is then formed on the substrate upper surface 10a and on the structure in the MC region 2 and on the top of the insulating layer 38 in the logic region 6 in the HV region 4 by thermal growth and / or deposition. The insulating layer 38 can be an oxide and / or an oxynitride and will be used as a gate oxide of the HV device. However, it should be noted that it is optional to remove and replace the oxide layer 12 with the insulating layer 38, and the oxide layer 12 can be used as part or all of the gate oxide of the HV device alternatively. After removing the photoresist, a photoresist 40 is formed on the structure and is removed only from the region between the stacks S1 and S2 in the MC region 2 (referred to herein as the inner stack region). An implantation process is performed to form a (first) source region 42 in the substrate between the stacks S1 and S2. Then, an oxide etch is used to remove the insulating layer 38, oxide spacers 36, and oxide layer 12 in the inner stack region. The resulting structure is Fig. 7A , Figure 7B and Figure 7C Shown in.

[0076] After removing the photoresist 40, a tunnel oxide 44 is formed on the structure. The tunnel oxide 44 may be an oxide and / or oxynitride formed by deposition and / or thermal growth. Due to the catalytic effect of the higher dopant level in the source region 42, the tunnel oxide 44 may have a thicker portion 44a on the source region 42. A photolithography masking step is used to cover the HV region 4 and the logic region 6, as well as the inner stacking region in the MC region 2 with photoresist. The region on the other side of the stacked structures S1 and S2 relative to the inner stacking region (referred to herein as the outer stacking region) remains exposed. At this point, the substrate SST 351913-980220-MTI-20155.CN01 can be

[0077] The implantation is performed on the portions of the oxide layer 10 in the outer stack region (i.e., those portions of the substrate below the select gates that will be formed later). An oxide etch is used to remove the exposed portions of the oxide layer 12 in the outer stack region. After removing the photoresist, an insulating layer 46 is then formed on the structure. The insulating layer 46 may be an oxide and / or oxynitride formed by deposition and / or thermal growth or any other suitable dielectric material. The formation of the insulating layer 46 thickens or becomes part of the tunnel oxide 44 and the insulating layer 38. The resulting structure is Fig. 8A , Figure 8B and Figure 8C Shown in.

[0078] A conductive layer 48 (i.e., a third conductive layer), such as a polysilicon layer, is formed on the structure. Conductive layer 48 may be in-situ doped or undoped, and may alternatively be amorphous silicon. If undoped polysilicon or amorphous silicon is used for conductive layer 48, doping and annealing are performed. Chemical mechanical polishing (CMP) is performed to planarize the top surface of the structure. An additional etch-back process is used to recess the upper surface of conductive layer 48 below the top of stacks S1 and S2, as shown in FIG. Fig.9A , Fig. 9B and Fig. 9C shown.

[0079] At this stage, the formation of most memory cells is completed. A protective insulating layer 54 is formed over the structure. The protective insulating layer 54 can be an oxide, a nitride, SiCN, or a combination thereof. A photolithographic masking step is used to cover the MC region 2 and the HV region 4 with photoresist while leaving the logic region 6 exposed. One or more etching steps are used to remove the protective layer 54, the conductive layer 48, the insulating layer 38, and the oxide layer 12 in the logic region 6, such as Fig. 10A , Fig. 10B and Fig. 10C As shown (after removing the photoresist), the protective layer 54 protects the MC region 2 and the HV region 4 from this series of etchings.

[0080] At this point, implantation may be performed to form doped P-wells and N-wells in the substrate 10 in the logic region 6. A dielectric layer 56 (which may be used as a gate dielectric for a logic device) is formed on the exposed upper substrate surface 10a in the logic region 6. The dielectric layer 56 may be silicon oxide, silicon oxynitride, a high-K dielectric layer, or a composite thereof. A high-K insulating material is an insulating material having a dielectric constant K greater than that of silicon dioxide. Examples of high-K insulating materials include HfO2, ZrO2, TiO2, Ta2O5, and combinations thereof. A pseudo conductive layer 58 such as a polysilicon layer is then formed over the structure. An insulating layer 59 (also referred to herein as a logic insulating layer 59) such as a nitride and a hard mask layer 60 are then formed on the pseudo conductive layer 58. A photolithographic masking step is used to cover selected portions of the logic region 6 with photoresist, thereby exposing the insulating layer 59 and the hard mask layer 60 in the entire MC region 2 and the HV region 4 and in a portion of the logic region 6. Then, etching is used to remove the exposed areas of the insulating layer 59 and the hard mask layer 60 in the MC region 2, the HV region 4, and the logic region 6. After removing the photoresist, etching is used to remove the exposed portions of the dummy conductive layer 58 and the dielectric layer 56 (i.e., all portions of the logic region 6 that are not protected by the remaining portions of the hard mask layer 60), thereby SST 351913-980220-MTI-20155.CN01 in the logic region 6

[0081] The logic stack structures LS1 and LS2 are left, which include a block of dummy conductive material 58 disposed on dielectric layer 56. Dielectric spacers 62 (e.g., nitride) are formed on the sides of the logic stack structures LS1 / LS2 by deposition and etching. At this point, implantation into substrate 10 can be performed in logic region 6. The resulting structure is Fig.11A , Fig. 11B and Fig. 11C Shown in.

[0082] A photolithographic masking step is used to cover the logic region 6, a portion of the HV region 4, and a portion of the MC region 2 (i.e., covering the inner stacking region, the stacking structures S1 and S2, and those portions of the outer stacking region immediately adjacent to the stacking structures S1 and S2) with photoresist 64. Etching is used to remove the exposed portions of the protective layer 54 and the conductive layer 48, such as Fig. 12A , Fig. 12B and Fig. 12CAs shown. After removing the photoresist 64, additional selective implantation and etching (i.e., through additional photolithography masking steps and implantation) may be performed in different exposed portions of the substrate 10. For example, the logic region 6 may be covered by photoresist to expose the MC region 2 and the HV region 4, and the portion of the substrate 10 covered only by the insulating layers 38 and 46 may be implanted. The logic region 6 is covered using a photolithography masking step, thereby exposing the MC region 2 and the HV region 4. Etching is then used to thin the exposed portions of the insulating layers 38 and 46 (which also thins the protective insulating layer 54), which may provide better implant penetration in the HV region 4 later in the process. The resulting structure is shown in FIG. Fig.13A , Fig. 13B and Fig. 13C (after removing the photoresist).

[0083] A semi-non-conformal layer 70 is formed over the structure. The layer has some conformality to the underlying topography, but the top of the underlying topography is thinner than where the vertical and horizontal surfaces intersect. In order to achieve this varying thickness, it is preferred to use a material that can flow to form layer 70. A non-limiting exemplary material for the semi-non-conformal layer 70 is a BARC material (bottom anti-reflective coating), which is typically used to reduce reflectivity at the resist interface during photolithography. BARC materials are flowable and wettable, and are easily etched and removed with minimal process damage due to their high selectivity relative to oxides. Other materials that can be used for the semi-non-conformal layer 70 include photoresists or spin-on glass (SOG). Etching (e.g., anisotropic) is used to remove and expose the semi-non-conformal layer 70 from the protective insulating layer 54 on the remaining portion of the stacked structure S1 / S2 and the conductive layer 48 and the hard mask layer 60 on the logic stacked structure LS1 / LS2, while leaving the semi-non-conformal layer 70 covering the insulating layers 38 and 46 (i.e., the portion of the semi-non-conformal layer 70 is used as a hard mask for the next etching step). Etching is used to remove the hard mask layer 60 on the logic stacked structure LS1 / LS2. The resulting structure is Fig.14A , Fig. 14B and Fig. 14C Shown in.

[0084] After removing the semi-non-conformal layer 70, oxide deposition and nitride deposition are used, followed by spacer etching to form SST 351913-980220-MTI-20155.CN01 on the sides of the stacked structures S1 / S2 in the MC region 2 and in the logic region 6

[0085] Oxide spacers 66 and nitride spacers (not shown) are formed on the sides of the stacked structures LS1 / LS2 and on the sides of these structures in the HV region 4. Implantation is performed to form a (first) drain region 74 in the substrate adjacent to the oxide spacer 66 in the MC region 2, a (second) source region 76 and a (second) drain region 78 adjacent to the oxide spacer 66 in the HV region 4, and a (third) source region 80 and a (third) drain region 82 adjacent to the oxide spacer 66 in the logic region 6. Implantation into any given region may be performed by forming a photoresist to block implantation into other regions to be implanted. For example, the drain region 74 in the MC region 2, the source region 76 / drain region 78 in the HV region 4, and the source region 80 / drain region 82 of the same doping type in the logic region 6 can be formed simultaneously by the following operations: a photoresist is formed on the regions of the opposite source / drain doping type, and then a single implantation is performed in the MC region 2, the HV region 4, and the logic region 6. At this time, a barrier layer 84 can be formed by deposition, masking steps, and etching to block any silicide in the next step. During the above-mentioned etching, any remaining portion of the protective insulating layer 54 in the MC region 2 and the HV region 4 that is not protected by the barrier layer 84 is also removed, thereby exposing the conductive layer 48 to subsequent silicide. Then, metal deposition and annealing are performed to form silicide 86 on the top surface of the exposed portions of the conductive layer 48, the source region 76 / 80, and the drain region 74 / 78 / 82. The barrier layer 84 prevents any portion that does not need to form silicide from forming silicide. Optionally, a barrier layer 84 may be maintained in selected portions of source / drain regions 74 / 76 / 78 / 80 / 82 and / or portions of conductive layer 48 to block silicide formation in these selected regions. An etch such as a nitride etch is then used to remove oxide spacers 66 in logic region 6 and nitride spacers on insulating layer 59 (thereby exposing the bulk of dummy conductive layer 58) and hard mask layer 28 in MC region 2. The resulting structure is Fig.15A , Fig. 15B and Fig. 15C Shown in.

[0086] A layer 88 (e.g., nitride) is formed over the structure. A thick interlayer dielectric (ILD) insulating material layer 90 is then formed over the layer 88. CMP is performed to planarize the ILD insulating material 90 and recess the thick layer, thereby exposing the dummy conductive layer 58 in the logic region 6. A photolithography masking step is used to cover the MC region 2 and the HV region 4 with photoresist while exposing the logic region 6. An etch such as a polysilicon etch is then used to remove the blocks of the dummy conductive layer 58 in the logic region 6. A metal material layer such as Al, Ti, TiAlN, TaSiN, TaN, TiN, or other suitable metal materials (non-limiting) or composites thereof is formed over the structure. CMP is then performed to remove the metal gate material layer, thereby leaving blocks of metal material 94 on the dielectric layer 56 in the logic region 6. The final structure is Fig.16A , Fig. 16B and Fig. 16C Shown in.

[0087] SST 351913-980220-MTI-20155.CN01

[0088] Fig.17 The final memory cell structure in the MC region 2 is shown, comprising pairs of memory cells, each pair of memory cells sharing a source region 42 spaced apart from two drain regions 74, with a channel region 96 in the silicon 10 extending therebetween. Each memory cell includes: a floating gate 14a (i.e., a block of conductive material remaining from the conductive layer 14), which is disposed over a first portion of the channel region 96 and insulated from the first portion of the channel region for controlling the conductivity of the first portion; a select gate 48a (i.e., it may also be referred to as a word line gate and is a block of conductive material remaining from the conductive layer 48), which is disposed over a second portion of the channel region 96 and insulated from the second portion of the channel region for controlling the conductivity of the second portion; a control gate 26a (i.e., a block of conductive material remaining from the conductive layer 26), which is disposed over the floating gate 14a and insulated from the floating gate; and an erase gate 48b (i.e., a block of conductive material remaining from the conductive layer 48), which is disposed over a source region 42 and insulated from the source region (shared by the memory cell pair). The memory cell pair extends in a column direction (BL direction) and forms a column of memory cells with an STI oxide 22 between adjacent columns. A row of control gates is formed as a continuous control gate line that connects the control gates 26a of an entire row of memory cells together. A row of select gates 48a is formed as a continuous select gate line (also called a word gate line) that connects the select gates 48a of an entire row of memory cells together. A row of erase gates 48b is formed as a continuous erase gate line that connects the erase gates of an entire row of memory cell pairs together.

[0089] The final HV equipment Fig.18 Each HV device includes a source region 76 and a drain region 78 spaced apart, with a channel region 98 of the silicon substrate 10 extending therebetween. An HV gate 48c (i.e., a block of conductive material remaining from the conductive layer 48) is disposed over and insulated from the channel region 98 for controlling the conductivity of the channel region.

[0090] The final logic device is Fig.19 Each logic device includes a source region 80 and a drain region 82 spaced apart, with a channel region 100 of the silicon substrate 10 extending therebetween. The metal material block 94 is a metal gate 94 disposed above the channel region 100 and insulated from the channel region (through a dielectric layer 56) for controlling the conductivity of the channel region.

[0091] The method described above for forming memory cells, HV devices, and logic devices on the same substrate has many advantages. The formation of the memory cells and HV devices is completed before the metal gate 94 is formed in the logic region 6, so that the metal gate 94 in the logic region 6 is not adversely affected by the formation of the memory cells and HV devices. The process steps for forming the gate in the MC region 2 and the HV region 4 are separate and independent from the process steps for forming the gate in the logic region 6 (and can be customized relative to the process steps for forming the gate in the logic region). In most storage SST351913-980220-MTI-20155.CN01

[0092] After formation of the memory cells and HV devices is complete and before processing in the logic region 6 (i.e., before removing the layers left by the formation of the memory cells and HV devices in the logic region 6 and before depositing and removing the layers used to form the logic devices (including removal of the dummy polysilicon layer), without limitation), the MC region 2 and the HV region 4 are covered by a protective insulating layer 54. The upper surface 10a of the substrate 10 is recessed in the MC region 2 and the HV region 4 relative to the upper surface of the substrate in the logic region 6 to accommodate taller structures in the MC region 2 / HV region 4 (i.e., so that the top of the shorter logic device in the logic region 6 is substantially uniform with the top of the taller memory cells and HV devices in the MC region 2 / HV region 4, and so that processing can be performed using CMP across all three regions, for example, during CMP of the ILD 90, the top of the select gate 48a and the HV gate 48c is substantially uniform with the dummy conductive layer 58). Layer 88 protects the silicide conductive layer 48 from the CMP used to form the metal gate 94, and the conductive layer 26 assists as a stop layer for this CMP. The silicide 86 improves the conductivity of the drain region 74 as well as the source region 76 / drain region 78, the source region 80 / drain region 82, the select gate 48a, the erase gate 48b, and the HV gate 48c. When the hard mask layer 60 is removed from the logic region 6, the semi-non-conformal layer 70 protects the oxide and silicon in the source / drain regions of the MC region 2 and the HV region. The memory cell select gate 48a, the memory cell erase gate 48b, and the HV gate 48c are formed using a single conductive material deposition (i.e., a single polysilicon layer formed by a single polysilicon deposition can be used to form all three types of gates). In addition, the same polysilicon etch can be used to define one of the edges of each select gate 48a and both edges of each HV gate 48c. The thicknesses of the various layers 46, 12, 38 and 56 (which serve as gate oxides) are independent of one another, with each layer being optimized for its respective gate operation. For example, the insulating layer 46 under the select gate 48a is preferably thinner than the oxide layer 12 under the floating gate 14a.

[0093] For the thin nitride layer 20 (see FIG. 2A to FIG. 2C and related description) perform nitride etching so that the top surface of nitride layer 20 is substantially uniform in MC region 2, HV region 4, and logic region 6, so as to perform better and more uniform subsequent processing on all three regions, even though MC region 2 and HV region 4 have recessed substrate upper surface 10a relative to logic region 6 (and oxide layer 12 / 18 and conductive layer 14 below nitride layer 20 are formed in all three regions). CMP for planarizing conductive layer 48 with the top of stacked structures S1 and S2 is then performed to etch so that conductive layer 48 is recessed below the top of stacked structures S1 and S2 (see 9A to 9Cand related description) provide reliable control of the height of the conductive layer 48 in the MC region 2 and the HV region 4 (for example, using APC (automatic process control) to measure the thickness of the conductive layer 48 before the etching process, and then deriving the etching time based on the etching rate of the etching), thereby avoiding additional mask steps. SST 351913-980220-MTI-20155.CN01

[0094] Finally, the protective insulating layer 54 in the MC region 2 and the HV region 4 and the hard mask layer 60 in the logic region 6 are etched after forming the semi-non-conformal layer 70 , thereby avoiding the need for an additional masking step before forming the silicide 86 .

[0095] FIG. 20A to FIG. 25A , FIG. 20B to FIG. 25B and FIG. 20C to FIG. 25C An alternative embodiment is disclosed, from Figures 1A to 1C The structure shown is started. An oxide layer 101 is formed on the upper surface 10a by oxide deposition or thermal oxidation. A nitride layer 102 is then formed on the oxide layer 101. A photolithography masking step is then performed to cover the MC region 2 and the HV region 4 with a photoresist 104, but to leave the logic region 6 exposed. A nitride etch is then used to thin the nitride layer 102 in the logic region 6 (i.e., reduce its thickness) so that the top surface of the nitride layer 102 is substantially uniform in all three regions (i.e., the MC region 2, the HV region 4, and the logic region 6), as shown in FIG. Fig. 20A , Fig. 20B and Fig. 20C shown.

[0096] After removing the photoresist 104, a photolithographic masking step is used to selectively cover portions of each region with photoresist. Nitride etching, oxide etching, and silicon etching are used to form trenches through the nitride 102, oxide 101, and into the silicon substrate 10. After removing the photoresist, these trenches are then filled with STI oxide 106 by oxide deposition and chemical mechanical polishing (CMP) termination on the nitride layer 102, as shown in FIG. Fig.21A , Fig. 21B and Fig. 21C The STI oxide 106 may include a liner oxide formed by thermal oxidation prior to oxide deposition.

[0097] A photolithography masking step is then performed to cover the logic region with photoresist, but to expose the MC region 2 and the HV region 4. One or more etches are then used to remove the nitride layer 102 and the oxide layer 101 from the MC region 2 and the HV region 4. After removing the photoresist, an oxide layer 108 is formed on the substrate surface 10a in the MC region 2 and the HV region 4, for example by thermal oxidation. A conductive layer 110, such as a polysilicon layer, is then formed on the structure, for example by deposition. The conductive layer 110 may alternatively be in-situ doped or undoped amorphous silicon. If undoped polysilicon or amorphous silicon is used for the layer 110, implantation and annealing are performed. Chemical-mechanical polishing and etch back are used to planarize and recess the conductive layer 110 in the MC region 2 and the HV region 4, and to remove the conductive layer 110 from the logic region 6. Oxide etching may then be used to recess the STI oxide 106. The resulting structure is Fig.22A , Fig. 22B and Fig. 22C Shown in.

[0098] Then use the above relative to FIG. 4A to FIG. 8A , FIG. 4B to FIG. 8B and Figures 4C to 8C The steps described above are used to form insulating layer 24, conductive layer 26, hard mask layer 28, stacked structures S1 and S2, oxide spacers 32, oxide spacers 36, insulating layer 38, source region 42, tunnel oxide 44, and insulating layer 46. The resulting structure is Fig.23A , Fig. 23B and Fig.23C SST 351913-980220-MTI-20155.CN01

[0099] After that, the formation of the conductive layer 48 as described above (ie, deposition, CMP and etch-back) is performed, which will result in the conductive layer 48 being completely removed from the logic region 6 by CMP due to the presence of the nitride layer 102 in the logic region 6. FIG. 24A to FIG. 24C As shown. Then, as described above, a protective insulating layer 54 is formed on the conductive layer 48 in the MC region 2 and the HV region 4, and then etching is performed to remove the insulating layer 38, the oxide layer 101, and the nitride layer 102 from the logic region 6, and to recess the STI oxide 106 in the logic region 6, as shown. FIG. 25A to FIG. 25C Then execute the above relative to FIG. 11A to FIG. 11C and FIG. 16A to FIG. 16C The advantages of this alternative embodiment are that a simpler, more efficient etch can be used to form the trenches to be filled with STI oxide 106 (because these trenches are formed by only two layers before reaching substrate 10 (see FIG. 21A to FIG. 21C ), rather than the four layers before reaching the substrate 10 (see FIG. 3A to FIG. 3C )).

[0100] It should be understood that the present invention is not limited to the embodiments described above and shown herein, but covers any and all variations that fall within the scope of the appended claims. For example, the reference to the present invention herein is not intended to limit the scope of any claim or claim term, but only refers to one or more features that can be covered by one or more of these claims. The examples of materials, processes and numerical values ​​described above are merely exemplary and should not be regarded as limiting the claims. In addition, it is obvious from the claims and the specification that not all method steps need to be performed in the exact order shown or claimed, but need to be performed in any order that allows the memory cell area and logic area of ​​the present invention to be properly formed, unless otherwise specified in the claims. Finally, a single material layer can be formed into multiple such or similar material layers, and vice versa.

[0101] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intervening material, element, or space is provided between) and "indirectly on" (intervening material, element, or space is provided between). Similarly, the term "adjacent" includes "directly adjacent" (no intervening material, element, or space is provided between) and "indirectly adjacent" (intervening material, element, or space is provided between). For example, forming an element "above" a substrate may include directly forming the element on the substrate without intervening materials / elements in between, and indirectly forming the element on the substrate with one or more intervening materials / elements in between.

Claims

1. A method of forming a semiconductor device, comprising: Providing a substrate of semiconductor material, the substrate of semiconductor material comprising a first region, a second region and a third region; causing an upper surface of the substrate in the first region and an upper surface of the substrate in the second region to be recessed relative to an upper surface of the substrate in the third region; forming a first conductive layer disposed above the upper surface in the first region, the second region, and the third region and insulated from the upper surface; forming an insulating layer on the first conductive layer in the first region, the second region, and the third region; thinning the insulating layer in the third region, but not thinning the insulating layer in the first region and the second region; forming trenches in the first region, the second region, and the third region that pass through the insulating layer and the first conductive layer and enter the substrate; filling the trench with an insulating material; After filling the trench, removing the insulating layer from the first region, the second region, and the third region; forming a second conductive layer, the second conductive layer being disposed above the first conductive layer in the first region, the second region, and the third region and being insulated from the first conductive layer; performing one or more etches to selectively remove portions of the first conductive layer and the second conductive layer in the first region to completely remove the first conductive layer and the second conductive layer from the second region and the third region, wherein the one or more etches result in forming a pair of stacked structures in the first region, wherein each of the stacked structures includes a control gate of the second conductive layer, the control gate of the second conductive layer being disposed above a floating gate of the first conductive layer and insulated from the floating gate of the first conductive layer; forming first source regions in the substrate, each first source region being disposed between one of the stacked structure pairs; forming a third conductive layer disposed above the upper surface of the substrate in the first region, the second region, and the third region and insulated from the upper surface of the substrate; forming a protective insulating layer over the third conductive layer in the first region and the second region; After forming the protective insulating layer, removing the third conductive layer from the third region; After removing the third conductive layer from the third region, forming a dummy conductive material block, the dummy conductive material block being disposed above the upper surface in the third region and insulated from the upper surface; After forming the pseudo conductive material block in the third region, etching portions of the protective insulating layer and portions of the third conductive layer in the first region and the second region to form a plurality of select gates of the third conductive layer, each select gate being disposed adjacent to one of the stack structures, and forming a plurality of HV gates of the third conductive layer, each HV gate being disposed above the upper surface of the substrate in the second region and insulated from the upper surface of the substrate; forming first drain regions in the substrate, each first drain region being adjacent to one of the select gates; forming second source regions in the substrate, each second source region being adjacent to one of the HV gates; forming second drain regions in the substrate, each second drain region being adjacent to one of the HV gates; forming third source regions in the substrate, each third source region being adjacent to one of the dummy conductive material blocks; forming third drain regions in the substrate, each third drain region being adjacent to one of the dummy conductive material blocks; as well as Each of the dummy conductive material blocks is replaced with a metal material block. 2 . The method according to claim 1 , wherein each of the metal material blocks is insulated from the upper surface of the substrate in the third region by a high-K insulating material layer.

3. The method according to claim 1, wherein before the replacement, each of the pseudo conductive material blocks is insulated from the upper surface of the substrate in the third region by a high-K insulating material layer, and wherein the replacement also includes forming each of the metal material blocks on the high-K insulating material layer.

4. The method according to claim 1, wherein for each of the stacked structure pairs, the erase gate of the third conductive layer is arranged between the stacked structure pairs and is arranged above one of the source regions and insulated from the one of the source regions. 5 . The method according to claim 1 , wherein each of the first conductive layer, the second conductive layer, and the third conductive layer is formed of polysilicon or amorphous silicon.

6. The method according to claim 1, further comprising: Silicide is formed on the first, second and third drain regions and on the second and third source regions.

7. The method according to claim 4, further comprising: Before the replacing, silicide is formed on the select gate, the erase gate, and the HV gate. 8 . The method according to claim 1 , wherein for each of the stack structures, the control gate is insulated from the floating gate by an ONO insulating layer. 9 . The method according to claim 4 , wherein the forming the dummy conductive material block comprises forming a logic insulating layer on the dummy conductive material block and forming a hard mask layer on the logic insulating layer.

10. The method according to claim 9, wherein before the replacing, it further comprises: forming a material layer capable of flowing in the first region, the second region, and the third region; removing a portion of the flowable material layer to expose the hard mask layer; removing the hard mask layer; as well as The layer of material capable of flowing is removed.

11. The method according to claim 10, further comprising: Silicide is formed on the select gate, the erase gate, and the HV gate, wherein the logic insulation layer prevents silicide from being formed on the dummy conductive material block.

12. A method of forming a semiconductor device, comprising: Providing a substrate of semiconductor material, the substrate of semiconductor material comprising a first region, a second region and a third region; causing an upper surface of the substrate in the first region and an upper surface of the substrate in the second region to be recessed relative to an upper surface of the substrate in the third region; forming an insulating layer over the substrate; thinning the insulating layer in the third region, but not thinning the insulating layer in the first region and the second region; forming trenches through the insulating layer and into the substrate in the first region, the second region, and the third region; filling the trench with an insulating material; After filling the trench, removing the insulating layer from the first region and the second region; forming a first conductive layer disposed above the upper surface in the first region and the second region and insulated from the upper surface; forming a second conductive layer disposed above the first conductive layer in the first region and the second region and insulated from the first conductive layer; performing one or more etches to selectively remove portions of the first conductive layer and the second conductive layer in the first region to completely remove the first conductive layer and the second conductive layer from the second region, wherein the one or more etches result in forming a pair of stacked structures in the first region, wherein each of the stacked structures includes a control gate of the second conductive layer, the control gate of the second conductive layer being disposed above a floating gate of the first conductive layer and insulated from the floating gate of the first conductive layer; forming first source regions in the substrate, each first source region being disposed between one of the stacked structure pairs; forming a third conductive layer disposed above the upper surface of the substrate in the first region and the second region and insulated from the upper surface of the substrate; forming a protective insulating layer over the third conductive layer in the first region, the second region, and the third region; After said forming said protective insulating layer, removing said protective insulating layer from said third region; After removing the protective insulating layer from the third region, forming a dummy conductive material block, the dummy conductive material block being disposed above the upper surface in the third region and insulated from the upper surface; After forming the pseudo conductive material block in the third region, etching portions of the protective insulating layer and portions of the third conductive layer in the first region and the second region to form a plurality of select gates of the third conductive layer, each select gate being disposed adjacent to one of the stack structures, and forming a plurality of HV gates of the third conductive layer, each HV gate being disposed above the upper surface in the second region and insulated from the upper surface; forming first drain regions in the substrate, each first drain region being adjacent to one of the select gates; forming second source regions in the substrate, each second source region being adjacent to one of the HV gates; forming second drain regions in the substrate, each second drain region being adjacent to one of the HV gates; forming third source regions in the substrate, each third source region being adjacent to one of the dummy conductive material blocks; forming third drain regions in the substrate, each third drain region being adjacent to one of the dummy conductive material blocks; as well as Each of the dummy conductive material blocks is replaced with a metal material block. 13 . The method according to claim 12 , wherein each of the metal material blocks is insulated from the upper surface in the third region by a high-K insulating material layer.

14. The method according to claim 12, wherein for each of the stacked structure pairs, the erase gate of the third conductive layer is arranged between the stacked structure pairs and is arranged above one of the source regions and insulated from the one of the source regions.

15. The method according to claim 14, further comprising: Silicide is formed on the first drain region, the second drain region, the third drain region, the second source region, the third source region, the select gate, the erase gate, and the HV gate. 16 . The method according to claim 12 , wherein for each of the stack structures, the control gate is insulated from the floating gate by an ONO insulating layer.

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