Array substrate, method for preparing array substrate, display panel and display device

Abstract

The present application discloses an array substrate, a method for preparing the array substrate, a display panel and a display device, wherein the array substrate comprises: a substrate; an active layer, which is arranged on one side of the substrate, and the active layer comprises a source-drain overlap region; a source-drain electrode, which is arranged on a side of the active layer away from the substrate, and is electrically connected to the active layer in the source-drain overlap region; wherein the source-drain electrode comprises a first conductive layer arranged close to the active layer, a third conductive layer arranged on a side of the first conductive layer away from the active layer, and a second conductive layer arranged between the first conductive layer and the third conductive layer, the light reflectivity of the second conductive layer is greater than the light reflectivity of the first conductive layer, and the light reflectivity of the second conductive layer is greater than the light reflectivity of the third conductive layer, and the orthographic projection area of ​​the first conductive layer on the substrate is smaller than the orthographic projection area of ​​the second conductive layer on the substrate. The present application improves the reflectivity of the array substrate on the basis of ensuring the electrical connection relationship between the source-drain electrode and the active layer.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular relates to an array substrate, a method for preparing the array substrate, a display panel, and a display device. Background Art

[0002] With the continuous progress and development of display technology, liquid crystal displays (LCDs) using thin film transistors (TFTs) as switching devices have become popular due to their advantages such as low cost, high resolution, and long service life.

[0003] However, TFT-LCD is a passive display panel that needs to cooperate with a backlight module to display images. The ratio of the light intensity of the backlight emitted by the backlight module to the light intensity before and after it passes through the TFT-LCD display panel is called the light efficiency. At present, the light efficiency of the TFT-LCD display panel is only 3-10%. The array substrate of the TFT-LCD display panel includes a light-transmitting area and a light-reflecting area. The light-reflecting area reflects the light emitted by the backlight source and then reflects it back to the light-transmitting area, thereby improving the light efficiency of the TFT-LCD display panel. Therefore, how to improve the reflectivity of the reflective area in the array substrate is a problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present application provide a column substrate, a method for preparing an array substrate, a display panel and a display device, which improve the reflectivity of the array substrate while ensuring the electrical connection between the source and drain electrodes and the active layer.

[0005] In a first aspect, an embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] An active layer is disposed on one side of the substrate, and the active layer includes a source-drain overlap region;

[0008] A source-drain electrode, disposed on a side of the active layer away from the substrate and electrically connected to the active layer at the source-drain overlap region;

[0009] Among them, the source-drain electrode includes a first conductive layer arranged close to the active layer, a third conductive layer arranged on a side of the first conductive layer away from the active layer, and a second conductive layer arranged between the first conductive layer and the third conductive layer, the light reflectivity of the second conductive layer is greater than the light reflectivity of the first conductive layer, and the light reflectivity of the second conductive layer is greater than the light reflectivity of the third conductive layer, and the orthographic projection area of ​​the first conductive layer on the substrate is smaller than the orthographic projection area of ​​the second conductive layer on the substrate.

[0010] Optionally, in some embodiments, the array substrate further includes a gate insulating layer and an interlayer insulating layer, the interlayer insulating layer covers the active layer, the gate insulating layer is arranged on the side of the gate insulating layer away from the active layer, and the interlayer insulating layer is arranged between the first conductive layer and the active layer, and a via is arranged between the source and drain electrode and the active layer, penetrating the gate insulating layer and the interlayer insulating layer, and the via forms a groove with the source and drain overlap area.

[0011] Optionally, in some embodiments, the source-drain electrode includes a source electrode and a drain electrode, the source-drain overlapping region includes a source overlapping region and a drain overlapping region, the via includes a first via and a second via, the first via is arranged between the source electrode and the source overlapping region, the first via and the source overlapping region form a first groove, a portion of the first conductive layer is arranged on the groove wall and bottom of the first groove, and a portion of the second conductive layer is arranged in the first groove and contacts with the first conductive layer arranged in the first groove.

[0012] Optionally, in some embodiments, the second via is disposed between the drain electrode and the drain overlapping region, the second via and the drain overlapping region form a second groove, a portion of the first conductive layer is disposed on the groove wall and bottom of the second groove, and a portion of the second conductive layer is disposed in the second groove and in contact with the first conductive layer disposed in the second groove.

[0013] Optionally, in some embodiments, the array substrate further includes a fourth conductive layer and a fifth conductive layer disposed between the substrate and the active layer, the fifth conductive layer being disposed on a side of the fourth conductive layer away from the substrate, and the light reflectivity of the fourth conductive layer being greater than the light reflectivity of the fifth conductive layer.

[0014] Optionally, in some embodiments, the orthographic projection region of the fourth conductive layer on the substrate is located within the orthographic projection region of the active layer on the substrate, and the orthographic projection region of the fourth conductive layer on the substrate is located within the orthographic projection region of the fifth conductive layer on the substrate.

[0015] Optionally, in some embodiments, the first conductive layer and the third conductive layer are made of the same material.

[0016] In a second aspect, an embodiment of the present application further provides a method for preparing an array substrate, comprising:

[0017] providing a substrate;

[0018] forming an active layer on the substrate, wherein the active layer includes a source-drain overlapping region;

[0019] forming source-drain electrodes on a side of the active layer away from the substrate, wherein the source-drain electrodes are electrically connected to the active layer in the source-drain overlapping region;

[0020] Among them, the source-drain electrode includes a first conductive layer arranged close to the active layer, a third conductive layer arranged on a side of the first conductive layer away from the active layer, and a second conductive layer arranged between the first conductive layer and the third conductive layer, the light reflectivity of the second conductive layer is greater than the light reflectivity of the first conductive layer, and the light reflectivity of the second conductive layer is greater than the light reflectivity of the third conductive layer, and the orthographic projection area of ​​the first conductive layer on the substrate is smaller than the orthographic projection area of ​​the second conductive layer on the substrate.

[0021] Optionally, in some embodiments, before forming an active layer on the substrate, the method further includes:

[0022] forming a fourth conductive layer on the substrate;

[0023] A fifth conductive layer is formed on a side of the fourth conductive layer away from the substrate, wherein the light reflectivity of the fourth conductive layer is greater than the light reflectivity of the fifth conductive layer, and the orthographic projection area of ​​the fourth conductive layer on the substrate is located within the orthographic projection area of ​​the fifth conductive layer on the substrate.

[0024] In a third aspect, an embodiment of the present application further provides a display panel, including:

[0025] An array substrate, comprising the array substrate as described in any one of the above items;

[0026] a color filter substrate, arranged opposite to the array substrate; and

[0027] The liquid crystal layer is arranged between the array substrate and the color filter substrate.

[0028] In a fourth aspect, an embodiment of the present application further provides a display device, including:

[0029] A display panel, comprising the display panel as described above;

[0030] The backlight module is arranged on the light incident side of the display panel.

[0031] The array substrate provided by the embodiment of the present application includes a substrate; an active layer, which is arranged on one side of the substrate, and the active layer includes a source-drain overlap region; a source-drain electrode, which is arranged on a side of the active layer away from the substrate, and is electrically connected to the active layer in the source-drain overlap region; wherein the source-drain electrode includes a first conductive layer arranged close to the active layer, a third conductive layer arranged on a side of the first conductive layer away from the active layer, and a second conductive layer arranged between the first conductive layer and the third conductive layer, the light reflectivity of the second conductive layer is greater than the light reflectivity of the first conductive layer, and the light reflectivity of the second conductive layer is greater than the light reflectivity of the third conductive layer, and the orthographic projection area of ​​the first conductive layer on the substrate is smaller than the orthographic projection area of ​​the second conductive layer on the substrate. The present application improves the reflectivity of the array substrate on the basis of ensuring the electrical connection relationship between the source-drain electrode and the active layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The technical solution and beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0033] Figure 1 A schematic diagram of the structure of an array substrate in the prior art provided in an embodiment of the present application.

[0034] Figure 2 A schematic diagram of the first structure of an array substrate provided in an embodiment of the present application.

[0035] Figure 3 A second structural schematic diagram of the array substrate provided in an embodiment of the present application.

[0036] Figure 4 A schematic diagram of a process for preparing an array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0038] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0039] See also Figure 1 , Figure 1 The schematic diagram of the structure of the array substrate in the prior art provided in the embodiment of the present application. The array substrate 100 may include a substrate 101, a first conductive layer 102, a first buffer layer 103, a second buffer layer 104, an active layer 105, a gate insulating layer 106, a gate layer 107, a first interlayer insulating layer 108, a second interlayer insulating layer 109, a planar layer 110, a second conductive layer 111, a third conductive layer 112 and a fourth conductive layer 113. The above-mentioned multiple film layers 102-113 are all arranged in the reflective area of ​​the array substrate 100.

[0040] The first conductive layer 102 may be made of metal materials such as molybdenum, titanium, and aluminum, wherein the reflectivity of metal molybdenum is about 52%, the reflectivity of metal titanium is about 60%, and the reflectivity of metal aluminum is about 97%. If molybdenum or titanium is selected as the material of the first conductive layer 102, the reflectivity is low, thereby affecting the reflective return rate of the array substrate 100. In comparison, it is better to select aluminum as the material of the first conductive layer 102, but the high-temperature process will cause the resistance of the aluminum material to increase sharply, and the volume of the aluminum material will expand at high temperatures, and the existence of the substrate 101 will limit the expansion, and the compressive stress generated by the limited expansion will be released by atomic diffusion, and will diffuse along the grain boundaries to form hillocks.

[0041] In addition, the second conductive layer 111, the third conductive layer 112 and the fourth conductive layer 113 are overlapped with the source-drain overlap region of the active layer 105 through vias to achieve electrical connection. The second conductive layer 111 and the fourth conductive layer 113 can both be made of metal materials such as molybdenum or titanium, and the third conductive layer 112 can be made of aluminum. The second conductive layer 111, the third conductive layer 112 and the fourth conductive layer 113 form a three-layer structure. It should be noted that direct contact between the aluminum material and the active layer 105 will produce a large resistance. Therefore, it is necessary to set the second conductive layer 111 between the third conductive layer 112 and the active layer 105 to prevent short circuit caused by excessive resistance.

[0042] It can be seen from the above that the first conductive layer 102 of the array substrate 100 provided in the prior art cannot use aluminum material with higher reflectivity to improve the reflective return rate of the array substrate 100, and the third conductive layer 112 using aluminum material needs to be in contact with the active layer 105 through the second conductive layer 111 as a spacer.

[0043] In order to solve the problems existing in the prior art, the embodiments of the present application provide an array substrate, a method for preparing the array substrate, a display panel and a display device. Figure 2 and Figure 3 , Figure 2 A schematic diagram of a first structure of an array substrate provided in an embodiment of the present application, Figure 3 A second structural schematic diagram of the array substrate provided in an embodiment of the present application.

[0044] The array substrate 200 may include a substrate 201 and a light-transmitting area 202 and a light-reflecting area 203 arranged on the light-emitting side of the substrate. The light-transmitting area 202 may include a plurality of sub-light-transmitting areas 2021, and the light-reflecting area 203 may include a plurality of sub-light-reflecting areas 2031. The plurality of sub-light-transmitting areas 2021 and the plurality of sub-light-reflecting areas 2031 are arranged adjacent to each other in sequence, that is, the plurality of sub-light-transmitting areas 2021 are arranged at intervals in sequence, the plurality of sub-light-reflecting areas 2031 are arranged at intervals in sequence, any sub-light-transmitting area 2021 is arranged between two adjacent sub-light-reflecting areas 2031, or any sub-light-transmitting area 2021 is arranged adjacent to at least one sub-light-reflecting area 2031. The orthogonal projection area of ​​each sub-light-transmitting area 2021 on the substrate 201 may be set to be larger than the orthogonal projection area of ​​each sub-light-reflecting area 2031 on the substrate 201, thereby increasing the size of the sub-light-transmitting area 2021 and improving the light transmittance of the array substrate 200.

[0045] The array substrate 200 may include a substrate 201, an active layer 31 and source-drain electrodes, wherein the active layer 31 is disposed on one side of the substrate and includes a source-drain overlap region; the source-drain electrode is disposed on a side of the active layer 31 away from the substrate 201 and is electrically connected to the active layer 31 in the source-drain overlap region. The active layer 31 and the source-drain electrode are both disposed in the reflective region 203.

[0046] The source-drain electrode may include a first conductive layer 34, a second conductive layer 35, and a third conductive layer 36, wherein the first conductive layer 34 is disposed on a side close to the active layer 31, the third conductive layer 36 is disposed on a side of the first conductive layer 34 away from the active layer 31, and the second conductive layer 35 is disposed between the first conductive layer 34 and the third conductive layer 36. The light reflectivity of the second conductive layer 35 is greater than the light reflectivity of the first conductive layer 34, the light reflectivity of the second conductive layer 35 is greater than the light reflectivity of the third conductive layer 36, and the orthographic projection area of ​​the first conductive layer 34 on the substrate 201 is smaller than the orthographic projection area of ​​the second conductive layer 35 on the substrate 201.

[0047] The active layer 31 may include a source-drain overlap region for connecting the source-drain wiring, thereby achieving electrical connection with the source-drain electrodes through the source-drain wiring.

[0048] The reflective region 203 may further include a via 32, an interlayer insulating layer 33 and a gate insulating layer 41, wherein the gate insulating layer 41 covers the active layer 31, the interlayer insulating layer 33 is disposed on the side of the gate insulating layer 41 away from the active layer 31, and the interlayer insulating layer 33 is disposed between the first conductive layer 34 and the active layer 31. The via 32 penetrates the gate insulating layer 41 and the interlayer insulating layer 33 and is located between the source-drain electrode and the active layer 31. That is, the via 32 may extend from the upper surface of the interlayer insulating layer 33 to the source-drain overlap region in the active layer 31, and the via 32 may form a groove 50 with the source-drain overlap region.

[0049] Specifically, the source-drain electrode may include a source electrode and a drain electrode, the source-drain overlapping region may include a source overlapping region and a drain overlapping region, the via 32 may include a first via 321 and a second via 322, the first via 321 may extend from the upper surface of the interlayer insulating layer 33 to the source overlapping region, that is, the first via 321 is arranged between the source electrode and the source overlapping region, the first via 321 may form a first groove 51 with the source overlapping region, a portion of the first conductive layer 34 may be arranged on the groove wall and bottom of the first groove 51, a portion of the second conductive layer 35 may be arranged in the first groove 51 and contact the first conductive layer 34 arranged in the first groove 51, thereby realizing electrical connection between the source electrode and the source overlapping region.

[0050] The second via 322 may extend from the upper surface of the interlayer insulating layer 33 to the drain overlapping region, that is, the second via 322 is arranged between the drain electrode and the drain overlapping region, the second via 322 may form a second groove 52 with the drain overlapping region, a portion of the first conductive layer 34 may be arranged on the groove wall and bottom of the second groove 52, a portion of the second conductive layer 35 may be arranged in the second groove 52 and contact the first conductive layer 34 arranged in the second groove 52, thereby realizing electrical connection between the drain electrode and the drain overlapping region.

[0051] It is understandable that a portion of the second conductive layer 35 can be disposed on the interlayer insulating layer 33, and another portion of the second conductive layer 35 can be disposed in the groove 50 and in contact with the first conductive layer 34. The second conductive layer 35 can be made of aluminum material with a high reflectivity, and the first conductive layer 34 can be made of metal materials such as titanium or molybdenum, so that the first conductive layer 34 can prevent the second conductive layer 35 made of aluminum material from directly contacting the source-drain overlap region of the active layer 31, thereby avoiding a short circuit caused by excessive resistance.

[0052] It should be noted that, compared Figure 1 and Figure 3 It can be seen that the difference between this embodiment and the prior art is that the second conductive layer 111 in the prior art is not only arranged in the via hole extending to the surface of the active layer 105, but also arranged on the second interlayer insulating layer 109, and the part arranged on the second interlayer insulating layer 109 completely blocks the third conductive layer 112, so that light cannot be directly incident on the third conductive layer 112. Since the second conductive layer 111 is made of titanium or molybdenum material, the reflectivity is low, which leads to a poor light reflection rate of the array substrate 100. In the present embodiment, a portion of the first conductive layer 34 is disposed in the groove 50, and another portion of the first conductive layer 34 is disposed on the interlayer insulating layer 33. Since the orthographic projection area of ​​the first conductive layer 34 on the substrate 201 is smaller than the orthographic projection area of ​​the second conductive layer 35 on the substrate 201, the first conductive layer 34 disposed on the interlayer insulating layer 33 will only block a portion of the light incident on the second conductive layer 35, while most of the light incident side of the second conductive layer 35 can directly receive the light. Since the second conductive layer 35 is made of aluminum material with a higher reflectivity, the reflective return rate of the array substrate 200 can be improved.

[0053] It should also be noted that if Figure 3 As shown, the first part of the second conductive layer 35 is disposed on the interlayer insulating layer 33, the second part of the second conductive layer 35 is disposed in the groove 50, and the connection position between the first part and the second part of the second conductive layer 35 is at the notch of the groove 50. In order to prevent the second conductive layer 35 from breaking due to the rigidity of the notch, part of the first conductive layer 34 can be disposed near the notch of the groove 50. Specifically, at least part of the first conductive layer 34 can be disposed on the interlayer insulating layer, and at least part of the first conductive layer 34 can be connected to the first conductive layer 34 disposed in the groove 50, so as to block the second conductive layer 35 at the notch position of the groove 50.

[0054] However, the orthographic projection area of ​​at least a portion of the first conductive layer 34 arranged at the notch position of the groove 50 on the substrate 201 needs to be located in the orthographic projection area of ​​the first portion of the second conductive layer 35 on the substrate 201, so as to avoid at least a portion of the first conductive layer 34 from significantly blocking the incident light of the first portion of the second conductive layer 35 and affecting the reflection return rate of the array substrate 200.

[0055] In addition, the third conductive layer 36 can be disposed on the first portion of the second conductive layer 35, and since the second conductive layer 35 is made of aluminum material, in order to prevent the aluminum material from forming hillocks due to high temperature, the second conductive layer 35 can be suppressed by the third conductive layer 36, so the orthographic projection area of ​​the second conductive layer 35 on the substrate 201 needs to be located within the orthographic projection area of ​​the third conductive layer 36 on the substrate 201. Among them, the first conductive layer 34 and the third conductive layer 36 can be made of the same material, such as metal materials such as titanium or molybdenum. In order to improve the reflective return rate of the array substrate 200, the reflectivity of the second conductive layer 35 can be made greater than the reflectivity of the first conductive layer 34 and the third conductive layer 36, that is, the second conductive layer 35 is made of aluminum material.

[0056] As can be seen from the above, in this embodiment, the second conductive layer 35 is set to be an aluminum material with a high reflectivity, and the first conductive layer 34 is only set in the groove 50 but not on the interlayer insulating layer 33 to affect the incident light of the second conductive layer 35, thereby improving the reflective return rate of the array substrate 200. In addition, by setting the third conductive layer 36 on the second conductive layer 35, the second conductive layer 35 made of aluminum material is prevented from forming hillocks, thereby improving the stability of the array substrate 200.

[0057] In order to further improve the reflective return rate of the array substrate 200, the array substrate 200 provided in this embodiment may also include a first buffer layer 37, a second buffer layer 38, a fourth conductive layer 39 and a fifth conductive layer 40, and the first buffer layer 37, the second buffer layer 38, the fourth conductive layer 39 and the fifth conductive layer 40 are all arranged in the reflective area 203.

[0058] The first buffer layer 37 is disposed on the substrate 201, and the second buffer layer 38 is disposed on the first buffer layer 37. The fourth conductive layer 39 is disposed on the substrate 201, and the fifth conductive layer 40 is disposed on the fourth conductive layer 39. The fourth conductive layer 39 and the fifth conductive layer 40 are patterned by a patterning process, so that the fourth conductive layer 39 and the fifth conductive layer 40 are covered in the first buffer layer 37, the fourth conductive layer 39 and the fifth conductive layer 40 are disposed between the substrate 201 and the active layer 31, the fifth conductive layer 40 is disposed on the side of the fourth conductive layer 39 away from the substrate 201, and the light reflectivity of the fourth conductive layer 39 is greater than the light reflectivity of the fifth conductive layer 40.

[0059] In order to improve the reflective return rate of the array substrate, the fourth conductive layer 39 may be made of aluminum material, but since the aluminum material will form hillocks at high temperatures, the fourth conductive layer 39 is suppressed by the fifth conductive layer 40. Therefore, the orthographic projection area of ​​the fourth conductive layer 39 on the substrate 201 needs to be located within the orthographic projection area of ​​the fifth conductive layer 40 on the substrate 201. The fifth conductive layer 40 may be made of metal materials such as titanium or molybdenum, and the reflectivity of the fourth conductive layer 39 is greater than the reflectivity of the fifth conductive layer 40, that is, the reflectivity of aluminum is greater than the reflectivity of titanium or molybdenum.

[0060] In addition, the array substrate 200 may also include a gate insulating layer 41 and a gate layer 42, wherein the gate insulating layer 41 is disposed on the second buffer layer 38; the active layer 31 is also disposed on the second buffer layer 38, and a pattern is defined by a composition process, and the active layer 31 is covered in the gate insulating layer 41.

[0061] The interlayer insulating layer 33 may include a first interlayer insulating layer 331 and a second interlayer insulating layer 332, the first interlayer insulating layer 331 is arranged on the gate insulating layer 41, and the second interlayer insulating layer 332 is arranged on the first interlayer insulating layer 331; the gate layer 42 is arranged on the gate insulating layer 41, and the gate layer 42 covers the first interlayer insulating layer 331, and the gate layer 42 has an orthographic projection area on the substrate 201 located within the orthographic projection area of ​​the active layer 31 on the substrate 201, so that the gate layer 42 serves as the gate of the thin film transistor in the array substrate 200; the fourth conductive layer 39 and the fifth conductive layer 40 can be used as a light shielding layer of the array substrate 200, so that the orthographic projection areas of the fourth conductive layer 39 and the fifth conductive layer 40 on the substrate 201 can be set within the active layer 31, so that the fourth conductive layer 39 and the fifth conductive layer 40 play a light shielding role for the thin film transistor composed of the active layer 31.

[0062] In addition, the array substrate 200 may further include a flat layer 43, which is arranged on the second interlayer insulating layer 332, and a portion of the second conductive layer 35 and the third conductive layer 36 are covered in the flat layer 43. The contact surface between a portion of the second conductive layer 35 and the second interlayer insulating layer 332 is the light incident side of a portion of the second conductive layer 35, thereby improving the reflective return rate of the array substrate 200 by adopting the second conductive layer 35 made of aluminum material.

[0063] As can be seen from the above, in this embodiment, not only the second conductive layer 35 is set to be an aluminum material with a high reflectivity, but also the orthographic projection area of ​​a portion of the first conductive layer 34 set on the interlayer insulating layer 33 on the substrate 201 is set to be smaller than the orthographic projection area of ​​the second conductive layer 35 on the substrate 201, so that the first conductive layer 34 will not affect the incident light of the second conductive layer 35, thereby improving the reflective return rate of the array substrate 200. In addition, the fourth conductive layer 39 is set to be an aluminum material with a high reflectivity, so as to further improve the reflective return rate of the array substrate 200.

[0064] In addition, the third conductive layer 36 is provided on the second conductive layer 35 to suppress the second conductive layer 35 made of aluminum material from forming hillocks, and the fifth conductive layer 40 is provided on the fourth conductive layer 39 to suppress the fourth conductive layer 39 made of aluminum material from forming hillocks, thereby improving the stability of the array substrate 200.

[0065] To further illustrate how to improve the reflective return rate of the array substrate 200, the present application also provides a method for preparing the array substrate. Figure 4 , Figure 4 A schematic flow chart of a method for preparing an array substrate provided in an embodiment of the present application. The method for preparing an array substrate may include the following steps:

[0066] 601, providing a substrate.

[0067] Please continue reading Figure 2 and Figure 3 The substrate 201 provided in this embodiment may be a glass substrate or the like.

[0068] 602, forming a fourth conductive layer on the substrate.

[0069] A first buffer layer 37 and a second buffer layer 38 are also formed on the substrate 201. The first buffer layer 37 is disposed on the substrate 201, and the second buffer layer 38 is disposed on the first buffer layer 37. A fourth conductive layer 39 is disposed on the substrate 201.

[0070] 603 , forming a fifth conductive layer on a side of the fourth conductive layer away from the substrate.

[0071] The fifth conductive layer 40 is arranged on the fourth conductive layer 39, and the fourth conductive layer 39 and the fifth conductive layer 40 are defined by a composition process so that the fourth conductive layer 39 and the fifth conductive layer 40 are covered in the first buffer layer 37, the fourth conductive layer 39 and the fifth conductive layer 40 are arranged between the substrate 201 and the active layer 31, the fifth conductive layer 40 is arranged on the side of the fourth conductive layer 39 away from the substrate 201, and the light reflectivity of the fourth conductive layer 39 is greater than the light reflectivity of the fifth conductive layer 40.

[0072] In order to improve the reflective return rate of the array substrate, the fourth conductive layer 39 may be made of aluminum material, but since the aluminum material will form hillocks at high temperatures, the fourth conductive layer 39 is suppressed by the fifth conductive layer 40. Therefore, the orthographic projection area of ​​the fourth conductive layer 39 on the substrate 201 needs to be located within the orthographic projection area of ​​the fifth conductive layer 40 on the substrate 201. The fifth conductive layer 40 may be made of metal materials such as titanium or molybdenum, and the reflectivity of the fourth conductive layer 39 is greater than the reflectivity of the fifth conductive layer 40, that is, the reflectivity of aluminum is greater than the reflectivity of titanium or molybdenum.

[0073] 604 , forming an active layer on the substrate, wherein the active layer includes a source-drain overlapping region.

[0074] It should be noted that the fourth conductive layer 39 and the fifth conductive layer 40 are located between the substrate 201 and the active layer 31 .

[0075] 605 , forming source-drain electrodes on a side of the active layer away from the substrate, the source-drain electrodes being electrically connected to the active layer in a source-drain overlapping region.

[0076] The active layer 31 is disposed on one side of the substrate, and the active layer includes a source-drain overlap region; the source-drain electrode is disposed on a side of the active layer 31 away from the substrate 201 , and is electrically connected to the active layer 31 in the source-drain overlap region.

[0077] The source-drain electrode may include a first conductive layer 34, a second conductive layer 35, and a third conductive layer 36, wherein the first conductive layer 34 is disposed on a side close to the active layer 31, the third conductive layer 36 is disposed on a side of the first conductive layer 34 away from the active layer 31, and the second conductive layer 35 is disposed between the first conductive layer 34 and the third conductive layer 36. The light reflectivity of the second conductive layer 35 is greater than the light reflectivity of the first conductive layer 34, the light reflectivity of the second conductive layer 35 is greater than the light reflectivity of the third conductive layer 36, and the orthographic projection area of ​​the first conductive layer 34 on the substrate 201 is smaller than the orthographic projection area of ​​the second conductive layer 35 on the substrate 201.

[0078] The active layer 31 may include a source-drain overlap region for connecting the source-drain wiring, thereby achieving electrical connection with the source-drain electrodes through the source-drain wiring.

[0079] The reflective region 203 may further include a via 32, an interlayer insulating layer 33 and a gate insulating layer 41, wherein the gate insulating layer 41 covers the active layer 31, the interlayer insulating layer 33 is disposed on the side of the gate insulating layer 41 away from the active layer 31, and the interlayer insulating layer 33 is disposed between the first conductive layer 34 and the active layer 31. The via 32 penetrates the gate insulating layer 41 and the interlayer insulating layer 33 and is located between the source-drain electrode and the active layer 31. That is, the via 32 may extend from the upper surface of the interlayer insulating layer 33 to the source-drain overlap region in the active layer 31, and the via 32 may form a groove 50 with the source-drain overlap region.

[0080] Specifically, the source-drain electrode may include a source electrode and a drain electrode, the source-drain overlapping region may include a source overlapping region and a drain overlapping region, the via 32 may include a first via 321 and a second via 322, the first via 321 may extend from the upper surface of the interlayer insulating layer 33 to the source overlapping region, that is, the first via 321 is arranged between the source electrode and the source overlapping region, the first via 321 may form a first groove 51 with the source overlapping region, a portion of the first conductive layer 34 may be arranged on the groove wall and bottom of the first groove 51, a portion of the second conductive layer 35 may be arranged in the first groove 51 and contact the first conductive layer 34 arranged in the first groove 51, thereby realizing electrical connection between the source electrode and the source overlapping region.

[0081] The second via 322 may extend from the upper surface of the interlayer insulating layer 33 to the drain overlapping region, that is, the second via 322 is arranged between the drain electrode and the drain overlapping region, the second via 322 may form a second groove 52 with the drain overlapping region, a portion of the first conductive layer 34 may be arranged on the groove wall and bottom of the second groove 52, a portion of the second conductive layer 35 may be arranged in the second groove 52 and contact the first conductive layer 34 arranged in the second groove 52, thereby realizing electrical connection between the drain electrode and the drain overlapping region.

[0082] It is understandable that a portion of the second conductive layer 35 can be disposed on the interlayer insulating layer 33, and another portion of the second conductive layer 35 can be disposed in the groove 50 and in contact with the first conductive layer 34. The second conductive layer 35 can be made of aluminum material with a high reflectivity, and the first conductive layer 34 can be made of metal materials such as titanium or molybdenum, so that the first conductive layer 34 can prevent the second conductive layer 35 made of aluminum material from directly contacting the source-drain overlap region of the active layer 31, thereby avoiding a short circuit caused by excessive resistance.

[0083] It should be noted that, compared Figure 1 and Figure 3It can be seen that the difference between this embodiment and the prior art is that the second conductive layer 111 in the prior art is not only arranged in the via hole extending to the surface of the active layer 105, but also arranged on the second interlayer insulating layer 109, and the part arranged on the second interlayer insulating layer 109 completely blocks the third conductive layer 112, so that light cannot be directly incident on the third conductive layer 112. Since the second conductive layer 111 is made of titanium or molybdenum material, the reflectivity is low, which leads to a poor light reflection rate of the array substrate 100. In the present embodiment, a portion of the first conductive layer 34 is disposed in the groove 50, and another portion of the first conductive layer 34 is disposed on the interlayer insulating layer 33. Since the orthographic projection area of ​​the first conductive layer 34 on the substrate 201 is smaller than the orthographic projection area of ​​the second conductive layer 35 on the substrate 201, the first conductive layer 34 disposed on the interlayer insulating layer 33 will only block a portion of the light incident on the second conductive layer 35, while most of the light incident side of the second conductive layer 35 can directly receive the light. Since the second conductive layer 35 is made of aluminum material with a higher reflectivity, the reflective return rate of the array substrate 200 can be improved.

[0084] It should also be noted that if Figure 3 As shown, the first part of the second conductive layer 35 is disposed on the interlayer insulating layer 33, the second part of the second conductive layer 35 is disposed in the groove 50, and the connection position between the first part and the second part of the second conductive layer 35 is at the notch of the groove 50. In order to prevent the second conductive layer 35 from breaking due to the rigidity of the notch, part of the first conductive layer 34 can be disposed near the notch of the groove 50. Specifically, at least part of the first conductive layer 34 can be disposed on the interlayer insulating layer, and at least part of the first conductive layer 34 can be connected to the first conductive layer 34 disposed in the groove 50, so as to block the second conductive layer 35 at the notch position of the groove 50.

[0085] However, the orthographic projection area of ​​at least a portion of the first conductive layer 34 arranged at the notch position of the groove 50 on the substrate 201 needs to be located in the orthographic projection area of ​​the first portion of the second conductive layer 35 on the substrate 201, so as to avoid at least a portion of the first conductive layer 34 from significantly blocking the incident light of the first portion of the second conductive layer 35 and affecting the reflection return rate of the array substrate 200.

[0086] In addition, the third conductive layer 36 can be disposed on the first portion of the second conductive layer 35, and since the second conductive layer 35 is made of aluminum material, in order to prevent the aluminum material from forming hillocks due to high temperature, the second conductive layer 35 can be suppressed by the third conductive layer 36, so the orthographic projection area of ​​the second conductive layer 35 on the substrate 201 needs to be located within the orthographic projection area of ​​the third conductive layer 36 on the substrate 201. Among them, the first conductive layer 34 and the third conductive layer 36 can be made of the same material, such as metal materials such as titanium or molybdenum. In order to improve the reflective return rate of the array substrate 200, the reflectivity of the second conductive layer 35 can be made greater than the reflectivity of the first conductive layer 34 and the third conductive layer 36, that is, the second conductive layer 35 is made of aluminum material.

[0087] As can be seen from the above, this embodiment provides a substrate, forms a fourth conductive layer on the substrate, forms a fifth conductive layer on the side of the fourth conductive layer away from the substrate, forms an active layer on the substrate, the active layer includes a source-drain overlap region, forms a source-drain electrode on the side of the active layer away from the substrate, and the source-drain electrode is electrically connected to the active layer in the source-drain overlap region. Not only by setting the second conductive layer 35 to an aluminum material with a high reflectivity, but also by setting the orthographic projection area of ​​a portion of the first conductive layer 34 set on the interlayer insulating layer 33 on the substrate 201 to be smaller than the orthographic projection area of ​​the second conductive layer 35 on the substrate 201, so that the first conductive layer 34 will not affect the incident light of the second conductive layer 35, thereby improving the reflective return rate of the array substrate 200. In addition, by setting the fourth conductive layer 39 to an aluminum material with a high reflectivity, the reflective return rate of the array substrate 200 is further improved.

[0088] In addition, the third conductive layer 36 is provided on the second conductive layer 35 to suppress the second conductive layer 35 made of aluminum material from forming hillocks, and the fifth conductive layer 40 is provided on the fourth conductive layer 39 to suppress the fourth conductive layer 39 made of aluminum material from forming hillocks, thereby improving the stability of the array substrate 200.

[0089] An embodiment of the present application also provides a display panel, which includes the array substrate 200, the color filter substrate and the liquid crystal layer provided in the above embodiment. The array substrate 200 is arranged opposite to the color filter substrate, and the liquid crystal layer is arranged between the array substrate 200 and the color filter substrate.

[0090] The embodiment of the present application also provides a display device, which may include the display panel provided in the above embodiment. The display device may be a full-screen display device, for example, the display device may be a wearable device such as a watch or a bracelet, or the display device may be an electronic device such as a mobile phone or a tablet computer. The display device includes the display panel provided in the above embodiment and a backlight module arranged on the light incident side of the display panel, and the backlight module is used to provide light for the display panel.

[0091] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0092] The array substrate, the method for preparing the array substrate, the display panel and the display device provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; An active layer is disposed on one side of the substrate, and the active layer includes a source-drain overlap region; A source-drain electrode, disposed on a side of the active layer away from the substrate and electrically connected to the active layer at the source-drain overlap region; The source-drain electrode comprises a first conductive layer disposed close to the active layer, a third conductive layer disposed on a side of the first conductive layer away from the active layer, and a second conductive layer disposed between the first conductive layer and the third conductive layer, the light reflectivity of the second conductive layer is greater than the light reflectivity of the first conductive layer, and the light reflectivity of the second conductive layer is greater than the light reflectivity of the third conductive layer, and the orthographic projection area of ​​the first conductive layer on the substrate is smaller than the orthographic projection area of ​​the second conductive layer on the substrate; The orthographic projection area of ​​the second conductive layer on the substrate is located within the orthographic projection area of ​​the third conductive layer on the substrate.

2. The array substrate according to claim 1, characterized in that: The array substrate also includes a gate insulating layer and an interlayer insulating layer, the gate insulating layer covers the active layer, the interlayer insulating layer is arranged on the side of the gate insulating layer away from the active layer, and the interlayer insulating layer is arranged between the first conductive layer and the active layer, and a via hole penetrating the gate insulating layer and the interlayer insulating layer is arranged between the source and drain electrodes and the active layer, and the via hole forms a groove with the source and drain overlap area.

3. The array substrate according to claim 2, characterized in that: The source-drain electrode includes a source electrode and a drain electrode, the source-drain overlapping region includes a source overlapping region and a drain overlapping region, the via includes a first via and a second via, the first via is arranged between the source electrode and the source overlapping region, the first via and the source overlapping region form a first groove, a portion of the first conductive layer is arranged on the groove wall and the bottom of the first groove, and a portion of the second conductive layer is arranged in the first groove and contacts with the first conductive layer arranged in the first groove.

4. The array substrate according to claim 3, characterized in that: The second via is arranged between the drain electrode and the drain overlapping area, the second via and the drain overlapping area form a second groove, a portion of the first conductive layer is arranged on the groove wall and bottom of the second groove, and a portion of the second conductive layer is arranged in the second groove and contacts with the first conductive layer arranged in the second groove.

5. The array substrate according to claim 1, characterized in that: The array substrate further includes a fourth conductive layer and a fifth conductive layer arranged between the substrate and the active layer. The fifth conductive layer is arranged on a side of the fourth conductive layer away from the substrate. The light reflectivity of the fourth conductive layer is greater than that of the fifth conductive layer.

6. The array substrate according to claim 5, characterized in that: The orthographic projection region of the fourth conductive layer on the substrate is located within the orthographic projection region of the active layer on the substrate, and the orthographic projection region of the fourth conductive layer on the substrate is located within the orthographic projection region of the fifth conductive layer on the substrate.

7. The array substrate according to claim 1, characterized in that: The first conductive layer and the third conductive layer are made of the same material.

8. A method for preparing an array substrate, characterized in that: Prepare the array substrate according to any one of claims 1 to 7, the preparation method of the array substrate comprising: providing a substrate; forming an active layer on the substrate, wherein the active layer includes a source-drain overlapping region; forming source-drain electrodes on a side of the active layer away from the substrate, wherein the source-drain electrodes are electrically connected to the active layer in the source-drain overlapping region; Among them, the source-drain electrode includes a first conductive layer arranged close to the active layer, a third conductive layer arranged on a side of the first conductive layer away from the active layer, and a second conductive layer arranged between the first conductive layer and the third conductive layer, the light reflectivity of the second conductive layer is greater than the light reflectivity of the first conductive layer, and the light reflectivity of the second conductive layer is greater than the light reflectivity of the third conductive layer, and the orthographic projection area of ​​the first conductive layer on the substrate is smaller than the orthographic projection area of ​​the second conductive layer on the substrate.

9. The method for preparing an array substrate according to claim 8, characterized in that: Before forming an active layer on the substrate, the method further comprises: forming a fourth conductive layer on the substrate; A fifth conductive layer is formed on a side of the fourth conductive layer away from the substrate, wherein the light reflectivity of the fourth conductive layer is greater than the light reflectivity of the fifth conductive layer, and the orthographic projection area of ​​the fourth conductive layer on the substrate is located within the orthographic projection area of ​​the fifth conductive layer on the substrate.

10. A display panel, characterized in that: include: An array substrate, comprising the array substrate according to any one of claims 1 to 7; A color filter substrate, arranged opposite to the array substrate; and The liquid crystal layer is arranged between the array substrate and the color filter substrate.

11. A display device, characterized in that: include: A display panel, comprising the display panel as claimed in claim 10; The backlight module is arranged on the light incident side of the display panel.

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