Display substrate, preparation method and repair method thereof, and display device

Abstract

Embodiments of the present disclosure provide a display substrate, a manufacturing method, a repairing method and a display device. The display substrate comprises a plurality of pixel units arranged in an array, each pixel unit comprising a plurality of sub-pixels, at least one sub-pixel comprising a driving circuit layer disposed on a substrate, the driving circuit layer comprising a spare signal line and a plurality of first signal lines insulated and crossed with the spare signal line; the first signal line comprises a spare connection electrode, and a normal projection of the spare connection electrode on the substrate and a normal projection of the spare signal line on the substrate have a first overlapping area. The technical solutions provided by the embodiments of the present disclosure overcome the problem of low repair success rate of the display substrate in the prior art.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to, but is not limited to, the technical field of display, in particular to a display substrate, a preparation method, a repair method and a display device thereof. BACKGROUND

[0002] At present, in the field of display application, electronic products with display such as TV gradually develop towards large size and high PPI (full name in English: Pixels Per Inch, also known as pixel density unit), and display devices such as liquid crystal display (LCD) and organic light emitting diode (OLED) are usually used in electronic products.

[0003] The present inventor found that the display substrate in the existing large-size display panel has the problem of low repair success rate. SUMMARY

[0004] The technical problem to be solved by the embodiment of the present disclosure is to provide a display substrate, a preparation method, and a display device to overcome the problem of low repair success rate of the display substrate in the prior art.

[0005] In order to solve the above technical problem, the present disclosure provides a display substrate, comprising a plurality of pixel units arranged in an array, each pixel unit comprising a plurality of sub-pixels, at least one sub-pixel comprising a driving circuit layer disposed on a substrate, the driving circuit layer comprising a spare signal line and a plurality of first signal lines insulated and crossed with the spare signal line;

[0006] The first signal line comprises a spare connection electrode, and the orthographic projection of the spare connection electrode on the substrate and the orthographic projection of the spare signal line on the substrate have a first overlapping area.

[0007] In an exemplary embodiment, the driving circuit layer of at least one sub-pixel comprises a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer and a third conductive layer disposed in sequence on the substrate, the spare signal line is located in the second conductive layer, and the plurality of first signal lines are located in the third conductive layer.

[0008] In an exemplary embodiment, the third insulating layer is provided with a spare half-via, the spare half-via is filled with the spare connection electrode, and the orthographic projection of the spare half-via on the substrate is located within the range of the first overlapping area.

[0009] In an exemplary embodiment, in a plane in which the display substrate is located, the plurality of sub-pixels comprises a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in sequence along a first direction; the plurality of first signal lines comprises a data signal line, and the backup connection electrode comprises a first backup connection electrode.

[0010] The data signal line is arranged in each sub-pixel respectively, and the data signal line comprises a main body portion and a first branch portion, the first branch portion comprises the first backup connection electrode, and the main body portion of the data signal line extends along a second direction; the first backup connection electrode in the first sub-pixel and the third sub-pixel extends in the opposite direction of the first direction, and the first backup connection electrode in the second sub-pixel and the fourth sub-pixel extends along the first direction.

[0011] In an exemplary embodiment, in a plane in which the display substrate is located, the plurality of sub-pixels comprises a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in sequence along a first direction; the plurality of first signal lines comprises a first power supply line, and the backup connection electrode comprises a second backup connection electrode.

[0012] The first power supply line comprises a main body portion and a branch portion, the branch portion of the first power supply line comprises the second backup connection electrode, the main body portion of the first power supply line is arranged between the second sub-pixel and the third sub-pixel, and the second backup connection electrode is located in the second sub-pixel and / or the third sub-pixel.

[0013] The main body portion of the first power supply line extends along a second direction, the second backup connection electrode in the second sub-pixel extends in the opposite direction of the first direction, and the second backup connection electrode in the third sub-pixel extends along the first direction.

[0014] In an exemplary embodiment, in a plane in which the display substrate is located, the plurality of sub-pixels comprises a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in sequence along a first direction; the plurality of first signal lines comprises a compensation signal line, and the backup connection electrode comprises a third backup connection electrode.

[0015] The compensation signal line is arranged in the first sub-pixel and the fourth sub-pixel respectively, and the compensation signal line comprises a main body portion and a branch portion, the branch portion of the compensation signal line comprises the third backup connection electrode, and the main body portion of the compensation signal line extends along a second direction; in the first sub-pixel, the third backup connection electrode extends along the first direction; and in the fourth sub-pixel, the third backup connection electrode extends in the opposite direction of the first direction.

[0016] In an exemplary embodiment, the backup signal line is located in at least two pixel units.

[0017] In an exemplary embodiment, in at least one of the sub-pixels, the driving circuit further comprises a first transistor, a second transistor and a third transistor; the active layer of the first transistor, the second transistor and the third transistor is located on the semiconductor layer, the gate electrode of the first transistor, the second transistor and the third transistor is located on the second conductive layer, and the first electrode and the second electrode of the first transistor, the second transistor and the third transistor are located on the third conductive layer.

[0018] In an exemplary embodiment, in at least one of the sub-pixels, the driving circuit further comprises a shielding layer, the shielding layer is located on the first conductive layer, and the active layer of the second transistor on the substrate has a projection within the projection of the shielding layer on the substrate.

[0019] In an exemplary embodiment, in the plane of the display substrate, the plurality of sub-pixels comprises a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in sequence along a first direction; the shielding layer is multiplexed as a first plate of a capacitor; the semiconductor layer comprises a second plate formed in each sub-pixel;

[0020] The projection of the second plate on the substrate is within the projection of the first plate on the substrate; the area of the second plate in the first sub-pixel and the third sub-pixel is greater than the area of the second plate in the second sub-pixel and the fourth sub-pixel.

[0021] In an exemplary embodiment, the second conductive layer further comprises a first scan signal line, a second scan signal line and a second gate electrode; the first scan signal line, the second scan signal line and the standby signal line are arranged along a second direction;

[0022] The first scan signal line comprises a main body portion and a branch portion, the main body portion is a strip structure extending along the first direction, and is located on the side of the second plate away from the second scan signal line in the second direction, the branch portion extends along the second direction, the branch portion comprises a first gate electrode corresponding to each sub-pixel, the first gate electrode serves as the gate electrode of the first transistor, and the projection of the first gate electrode on the substrate overlaps with the projection of the active layer of the first transistor on the substrate;

[0023] The second scan signal line is a strip structure extending along the first direction, and is located on the side of the second plate away from the first scan signal line in the second direction, the projection of the second scan signal line on the substrate overlaps with the projection of the active layer of the third transistor in each sub-pixel on the substrate, and the second scan signal line in the overlapping area serves as the gate electrode of the third transistor;

[0024] The second gate electrode is a gate electrode of a second transistor, a normal projection of the second gate electrode on the substrate and a normal projection of an active layer of the second transistor on the substrate have a second overlapping area, and a normal projection of the second gate electrode, a second electrode of the first transistor, and the active layer of the first transistor on the substrate have a third overlapping area.

[0025] In an exemplary embodiment, the first signal lines include data signal lines, the data signal lines are respectively arranged in each sub-pixel, the data signal lines include a main body part and a second branch part, the main body part of the data signal lines extends along the second direction; the second branch part in the first sub-pixel and the third sub-pixel extends in the opposite direction of the first direction, and the second branch part in the second sub-pixel and the fourth sub-pixel extends along the first direction; the second branch part is the first electrode of the first transistor.

[0026] The display substrate provided by the embodiment of the present disclosure further includes a preparation method of the display substrate, the display substrate includes a plurality of pixel units arranged in an array, each pixel unit includes a plurality of sub-pixels, and at least one sub-pixel includes a driving circuit layer arranged on a substrate; the preparation method includes:

[0027] The driving circuit layer includes a spare signal line and a plurality of first signal lines which are insulated and cross the spare signal line; the first signal lines include a spare connection electrode, and a normal projection of the spare connection electrode on the substrate and a normal projection of the spare signal line on the substrate have a first overlapping area.

[0028] The display substrate provided by the embodiment of the present disclosure further includes a repair method of the display substrate, the display substrate includes a plurality of pixel units arranged in an array, each pixel unit includes a plurality of sub-pixels, and at least one sub-pixel includes a driving circuit layer arranged on a substrate; the driving circuit layer includes a spare signal line and a plurality of first signal lines which are insulated and cross the spare signal line; the first signal lines include a spare connection electrode, and a normal projection of the spare connection electrode on the substrate and a normal projection of the spare signal line on the substrate have a first overlapping area; the repair method includes:

[0029] When any one of the first signal lines has a disconnection, the spare signal line is communicated with the spare connection electrode on the first signal line having the disconnection, and the spare signal line is communicated with the spare connection electrode on a first signal line which does not have the disconnection, and the first signal line which does not have the disconnection and the first signal line having the disconnection provide the same signal.

[0030] The display device provided by the embodiment of the present disclosure further includes the display substrate.

[0031] The display substrate provided by the embodiment of the present disclosure, the preparation method and the repairing method thereof, and the display device, the driving circuit layer in the display substrate is provided with a spare signal line and a plurality of first signal lines insulated and crossed with the spare signal line, the first signal line includes a spare connection electrode, and the orthographic projection of the spare connection electrode on a substrate and the orthographic projection of the spare signal line on the substrate have a first overlapping area. When a break occurs in any one of the first signal lines, the spare signal line is connected with the spare connection electrode on the first signal line where the break occurs to realize electrical connection, and the spare signal line is connected with the spare connection electrode of the first signal line where no break occurs to realize electrical connection, and the signal on the first signal line where no break occurs is provided to the first signal line where the break occurs, thereby overcoming the problem of low repair success rate of the existing display substrate.

[0032] Of course, practicing any of the products or methods of the present disclosure does not necessarily achieve all the advantages mentioned above. Other features and advantages of the present disclosure will be set forth in the description that follows, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present disclosure. The purposes and other advantages of the embodiments of the present disclosure can be realized and obtained by the structures particularly pointed out in the specification, claims and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0034] Figure 1 A structural schematic diagram of a display device is shown;

[0035] Figure 2 A planar structural schematic diagram of a display substrate is shown;

[0036] Figure 3 A cross-sectional structural schematic diagram of a display substrate is shown;

[0037] Figure 4 An equivalent circuit schematic diagram of a pixel driving circuit is shown;

[0038] Figure 5a A structural schematic diagram of a signal line with a break is shown;

[0039] Figure 5b A repairing method is shown Figure 5a A cross-sectional structural schematic diagram of a signal line break position is shown;

[0040] Figure 5c A repairing method is shown Figure 5aAnother cross-sectional structure schematic diagram of the signal line break position shown;

[0041] Figure 6a A plane structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown;

[0042] Figure 6b A plane structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown; Figure 6a A cross-sectional structure schematic diagram of the L-L position is shown;

[0043] Figure 7 A plane structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown; Figure 6a An equivalent circuit schematic diagram of the pixel driving circuit in the four sub-pixels is shown;

[0044] Figure 8 A schematic diagram after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure is shown;

[0045] Figure 9a A schematic diagram after forming a semiconductor layer pattern according to an exemplary embodiment of the present disclosure is shown;

[0046] Figure 9b A plane structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown; Figure 9a A plane structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown;

[0047] Figure 9c Another plane structure schematic diagram of a semiconductor layer according to an exemplary embodiment of the present disclosure is shown;

[0048] Figure 10a A schematic diagram after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure is shown;

[0049] Figure 10b A plane structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown; Figure 10a A plane structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown;

[0050] Figure 11a A schematic diagram after forming a third insulating layer pattern according to an exemplary embodiment of the present disclosure is shown;

[0051] Figure 11b A plane structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown; Figure 11a A cross-sectional structure schematic diagram of the H-H position is shown;

[0052] Figure 12a A schematic diagram after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure is shown;

[0053] Figure 12b A plane structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown; Figure 12a A plane structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown;

[0054] Figure 12c Another schematic diagram after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure is shown;

[0055] Figure 12d A plane structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown; Figure 12cA plan view of a third conductive layer;

[0056] Figure 13 A plan view of a display substrate according to an exemplary embodiment of the present disclosure is shown;

[0057] Figure 14a A plan view of a display substrate according to an exemplary embodiment of the present disclosure is shown; Figure 12c A plan view of a display substrate according to an exemplary embodiment of the present disclosure is shown; Figure 13 A cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure is shown;

[0058] Figure 14b A plan view of a display substrate according to an exemplary embodiment of the present disclosure is shown; Figure 12c A cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure is shown;

[0059] Figures 15a to 15c A plan view of a display substrate according to an exemplary embodiment of the present disclosure is shown;

[0060] Figure 15d A plan view of a display substrate according to an exemplary embodiment of the present disclosure is shown; Figure 15c A cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0061] The embodiments in the present disclosure can be implemented in a variety of different forms. It is to be understood that specific details that have been set forth in the following description of implementations merely set forth preferred implementations of the present disclosure and are not intended to limit the scope of the present disclosure. Those skilled in the relevant art will be able to conceive of alterations, modifications, and / or improvements within the scope of the present disclosure, which are intended to be within the scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the content described in the following implementations. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined so long as there is no conflict.

[0062] In the drawings, the size of the constituent elements, the thickness of the layers, or the region may, at times, be exaggerated for the sake of clarity. Thus, any one of the implementations of the present disclosure is not necessarily limited to the sizes as shown in the drawings, and the shapes of the components in the drawings do not reflect real proportions. Furthermore, the drawings schematically show ideal examples, and any one of the implementations of the present disclosure is not limited to the shapes or numerical values shown in the drawings.

[0063] The ordinal numbers "first", "second", "third", and the like used in the present disclosure are used to avoid confusion between constituents, and are not intended to limit the number thereof.

[0064] In the present disclosure, the words of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or locational relationship are used to refer to the positional relationship of the components with reference to the drawings for the purpose of facilitating the description of the embodiments and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components can be appropriately changed according to the direction of the components described. Therefore, it is not limited to the words described in the text, and can be appropriately replaced according to the situation.

[0065] In the present disclosure, unless explicitly specified and limited otherwise, the terms "mount", "connect", and "connect" should be broadly understood. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the meaning of the above terms in the present disclosure can be understood according to the situation.

[0066] In the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (or drain electrode terminal, drain connection region, or drain electrode) and the source electrode (or source electrode terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to the region through which current mainly flows.

[0067] In the present disclosure, the first pole can be a drain electrode, and the second pole can be a source electrode, or the first pole can be a source electrode, and the second pole can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation, the functions of "source electrode" and "drain electrode" can sometimes be exchanged with each other. Therefore, in the present disclosure, "source electrode" and "drain electrode" can be exchanged with each other.

[0068] In the present disclosure, "electrically connected" includes the case where the components are connected together by an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can perform the transmission of electrical signals between the connected components. The "element having a certain electrical effect" may, for example, be an electrode or a wiring, or a switching element such as a transistor, or another functional element such as a resistor, an inductor, or a capacitor, and the like.

[0069] In the present disclosure, "parallel" refers to a state in which two straight lines form an angle of -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0070] In the present disclosure, "film" and "layer" can be exchanged with each other. For example, "conductive layer" can be sometimes exchanged with "conductive film". Similarly, "insulating film" can be sometimes exchanged with "insulating layer".

[0071] In the present disclosure, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly defined, and can be an approximate triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. There can be some small deformation due to a tolerance, there can be a rounded corner, an arc edge, and a deformation, etc.

[0072] In the present disclosure, "about" refers to not strictly defined limits, and allows values within a range of process and measurement errors.

[0073] Figure 1 A structure diagram of a display device. As shown in FIG. 1, the display device includes a display panel 100, a driver circuit 200, and a backlight unit 300. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is connected to both the data driver and the scan driver. The data driver is connected to multiple data signal lines (D1 to D), and the scan driver is connected to multiple scan signal lines (S1 to Sm). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, and may provide clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., D. For example, the data driver may sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to D on a pixel-row basis, where n can be a natural number. A scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from a timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 through Sm. For example, the scan driver can be constructed as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number.

[0074] Figure 2 This is a schematic diagram of a planar structure of a display substrate. Figure 2 As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a fourth color light. Each of the four sub-pixels may include a circuit unit and a light-emitting device. The circuit unit may include a scan signal line, a data signal line, and a pixel driving circuit. The pixel driving circuit is connected to the scan signal line and the data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0075] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a white sub-pixel (W) that emits white light, the third sub-pixel P3 may be a blue sub-pixel (B) that emits blue light, and the fourth sub-pixel P4 may be a green sub-pixel (G) that emits green light.

[0076] In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal. In one exemplary embodiment, four sub-pixels can be arranged horizontally side-by-side to form an RWBG pixel arrangement. In another exemplary embodiment, the four sub-pixels can be arranged in a square, diamond, or vertically side-by-side arrangement, etc., which is not limited herein.

[0077] In an exemplary embodiment, multiple sub-pixels arranged sequentially in the horizontal direction are called pixel rows, and multiple sub-pixels arranged sequentially in the vertical direction are called pixel columns. Multiple pixel rows and multiple pixel columns constitute a pixel array arranged in an array.

[0078] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of four sub-pixels. For example... Figure 3 As shown, on a plane perpendicular to the display substrate, each sub-pixel in the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate.

[0079] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 of each sub-pixel may include a light-emitting device composed of multiple film layers. The multiple film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the pixel driving circuit, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of a corresponding color under the driving of the anode 301 and the cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting structure layer 103.

[0080] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), hole transport layer (HTL), electron blocking layer (EBL), light-emitting layer (EML), hole blocking layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In an exemplary embodiment, the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the light-emitting layers of all sub-pixels may be a common layer connected together, or they may be isolated from each other, with a small amount of overlap between the light-emitting layers of adjacent sub-pixels. In some possible implementations, the display substrate may include other film layers, which are not limited herein.

[0081] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 4 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. (Example) Figure 4 As shown, the pixel driving circuit is a 3T1C structure, which may include 3 transistors (first transistor T1, second transistor T2 and third transistor T3), 1 storage capacitor C and 6 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, compensation signal line S, first power supply line VDD and second power supply line VSS).

[0082] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor. The first terminal of the storage capacitor C is coupled to the control terminal of the second transistor T2, and the second terminal of the storage capacitor C is coupled to the second terminal of the second transistor T2. The storage capacitor C is used to store the potential of the control terminal of the second transistor T2. The control terminal of the first transistor T1 is coupled to the first scan signal line S1, the first terminal of the first transistor T1 is coupled to the data signal line D, and the second terminal of the first transistor T1 is coupled to the control terminal of the second transistor T2. The first transistor T1, under the control of the first scan signal line S1, receives the data signal transmitted through the data signal line D, causing the control terminal of the second transistor T2 to receive the data signal. The control terminal of the second transistor T2 is coupled to the second terminal of the first transistor T1, the first terminal of the second transistor T2 is coupled to the first power supply line VDD, and the second terminal of the second transistor T2 is coupled to the first terminal of the light-emitting device. The second transistor T2, under the control of the data signal received at its control terminal, generates a corresponding current at its second terminal. The control electrode of the third transistor T3 is coupled to the second scan signal line S2, the first electrode of the third transistor T3 is coupled to the compensation signal line S, and the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2. The third transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing, so as to compensate the threshold voltage Vth.

[0083] In an exemplary embodiment, the light-emitting device may be an OLED, which includes a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. The first electrode of the OLED is coupled to the second electrode of the second transistor T2, and the second electrode of the OLED is coupled to the second power line VSS. The OLED is used to emit light of corresponding brightness in response to the current of the second electrode of the second transistor T2.

[0084] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, while the second power line VSS provides a low-level signal. The first transistor T1 to the third transistor T3 can be either P-type or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the manufacturing process, reduces the manufacturing difficulty of the display panel, and improves product yield.

[0085] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. In an exemplary embodiment, the LTPS and oxide thin-film transistors can be integrated onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate. This leverages the advantages of both, enabling high resolution (Pixels Per Inch, PPI), low-frequency driving, reduced power consumption, and improved display quality. In an exemplary embodiment, the light-emitting device can be an organic light-emitting diode (OLED), comprising a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0086] In an exemplary embodiment, taking all three transistors as N-type transistors as an example, Figure 4 The operation of the example pixel driving circuit may include:

[0087] In the first stage A1, the signals on the first scan signal line S1 and the second scan signal line S2 are at high level. The data signal line D outputs the data voltage, the compensation signal line S outputs the compensation voltage, the first power supply line VDD is at high level, and the second power supply line VSS is at low level. The high level signal on the first scan signal line S1 turns on the first transistor T1. The data voltage output from the data signal line D is written to the first node N1, pulling up the potential of the first node N1 and charging the storage capacitor C. At this time, the potential of the first node N1 is V1 = V... data The signal on the second scan signal line S2 is high, turning on the third transistor T3. The compensation voltage output from the compensation signal line S is written to the second node N2, at which point the potential of the second node N2 is V2 = V. s Because the potential difference between the first node N1 and the second node N2 is greater than the threshold voltage V of the second transistor T2. th When the second transistor T2 is turned on, the power supply voltage output from the first power line VDD provides a driving voltage to the first electrode of the OLED through the turned-on second transistor T2, driving the OLED to emit light.

[0088] In the second stage A2, the signals on the first scan signal line S1 and the second scan signal line S2 are at a low level, turning off the first transistor T1 and the third transistor T3. The voltage in the storage capacitor C still keeps the second transistor T2 on. The power supply voltage output from the first power supply line VDD continuously pulls up the potential of the second node N2, and the OLED continues to emit light. When the potential of the second node N2 equals V... data -V th When the second transistor T2 is turned off, the OLED stops emitting light.

[0089] In an exemplary embodiment, in order to drive the OLED to emit light normally, both the OLED and the second transistor T2 are forward biased. In the first stage, the power supply voltage output by the first power supply line VDD is greater than the data voltage output by the data signal line D, the data voltage output by the data signal line D is greater than the compensation voltage output by the compensation signal line S, and the compensation voltage output by the compensation signal line S is greater than the power supply voltage output by the second power supply line VSS.

[0090] As display device size increases and PPI improves, signal lines in display devices (such as display panels) become increasingly dense. Due to the large size of display panels, the voltage is lower at locations farther from the power supply compared to locations closer to it; this phenomenon is called resistive voltage drop (IR Drop). To mitigate the IR Drop in large-size display panels, the film layer used for signal lines is typically thickened. However, when defects such as broken signal lines occur during the display panel manufacturing process (e.g.,...),... Figure 5a When the SD signal line breaks at position 01, repairs typically involve depositing metal powder at the break point. However, due to the thick film layer of the signal line, the deposited metal powder (such as tungsten powder) often fails to properly overlap, resulting in a low repair success rate. There are two main reasons why the deposited metal powder may fail to overlap at the break point: one such reason is... Figure 5b As shown, this is for repair. Figure 5a A cross-sectional view of a broken signal line at position 01 in the NN region. When connecting the signal line SD at the break point 01 using a deposited tungsten powder layer 02, the relatively thick thickness of the signal line SD (large dimension in the third direction Z) and the relatively thin thickness of the tungsten powder layer 02 often lead to ramp fractures on the sidewall of the tungsten powder layer 02 at the break point 01 (c1 in the figure is the ramp fracture location), resulting in repair failure. Another situation is... Figure 5c As shown, this is for repair. Figure 5a Another cross-sectional structure diagram of the broken line at position 01 at position NN. After depositing tungsten powder layer 02, the thickness of tungsten powder layer 02 is too thin, resulting in greater resistance. It often occurs that the tungsten powder layer 02 burns out due to excessive resistance. c2 is the position where the tungsten powder layer 02 burns out due to excessive resistance.

[0091] To address the low repair success rate of existing display substrates, this disclosure provides a display substrate. The display substrate may include multiple pixel units arranged in an array, each pixel unit including multiple sub-pixels, and at least one sub-pixel including a driving circuit layer disposed on a substrate. The driving circuit layer includes spare signal lines and multiple first signal lines that are insulated from and intersect with the spare signal lines.

[0092] The first signal line includes a spare connection electrode, and the orthographic projection of the spare connection electrode on the substrate and the orthographic projection of the spare signal line on the substrate have a first overlap region.

[0093] In the display substrate provided in this embodiment, the driving circuit layer is provided with a spare signal line and a plurality of first signal lines that are insulated from and cross each other. Each first signal line includes a spare connection electrode, and the orthographic projection of the spare connection electrode on the substrate and the orthographic projection of the spare signal line on the substrate have a first overlap area. When any one of the first signal lines is open-circuited, the spare signal line is electrically connected to the spare connection electrode on the open-circuited first signal line, and the spare signal line is also electrically connected to the spare connection electrode on the unopened first signal line. This provides the signal from the unopened first signal line to the open-circuited first signal line, overcoming the problem of low repair success rate in existing display substrates.

[0094] Figure 6a This is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 6b As shown Figure 6a A schematic diagram of the cross-sectional structure at position LL. (See diagram below.) Figure 6a and Figure 6b As shown, Figure 6a The diagram shows a planar structure of the display substrate. Figure 6b As shown Figure 6a A cross-sectional structural diagram of the LL position shows that the display substrate may include multiple pixel units arranged in an array, each pixel unit includes multiple sub-pixels, and at least one sub-pixel includes a driving circuit layer disposed on the substrate. The driving circuit layer includes a spare signal line 53 and multiple first signal lines (61, 62, 63) that are insulated from and cross the spare signal line 53.

[0095] The first signal line includes spare connection electrodes (61-3, 62-2, 63-1), and the orthographic projection of the spare connection electrodes (61-3, 62-2, 63-1) on the substrate 101 has a first overlapping area with the orthographic projection of the spare signal line 53 on the substrate 101.

[0096] In this embodiment of the disclosure, when the first signal line is broken, the backup connection electrode and the backup signal line can be connected in the first overlapping area by laser melting.

[0097] Figure 7 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of the driving circuit layer in the four sub-pixels (one pixel unit) of a bottom-emitting display substrate.

[0098] Figure 7 for Figure 6a The diagram shows the equivalent circuit diagram of the pixel driving circuit in the four sub-pixels shown. Figure 7 and Figure 7 As shown, in a direction parallel to the display substrate, at least one pixel unit may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged sequentially along a first direction X. Each sub-pixel includes a pixel driving circuit and a storage capacitor. In the following description, sub-pixels refer to the area where the pixel driving circuit is disposed. In an exemplary embodiment, at least one pixel unit may further include a first scan signal line 51, a second scan signal line 52, two compensation signal source lines 63, four data signal lines 62, a first power supply line 61, and four pixel driving circuits.

[0099] In an exemplary embodiment, the driving circuit layer of at least one sub-pixel includes a first conductive layer, a first insulating layer 20, a semiconductor layer, a second insulating layer 40, a second conductive layer, a third insulating layer 60, and a third conductive layer sequentially disposed on a substrate 101. A spare signal line 53 is located in the second conductive layer, and a plurality of first signal lines are located in the third conductive layer.

[0100] In an exemplary embodiment, the third insulating layer 60 is provided with a spare half-via Vm, which is filled with spare connection electrodes (62-2, 63-1, 61-3). The orthogonal projection of the spare half-via Vm on the substrate 101 is located within the range of the first overlapping region.

[0101] In this embodiment, a spare half-via Vm is provided on the third insulating layer between the spare connection electrode and the spare signal line, which allows more material of the spare connection electrode to be accommodated in the spare half-via Vm. When the first signal line with an open circuit is repaired by laser melting, the spare connection electrode can be well electrically connected to the spare signal line in the laser melting state.

[0102] In an exemplary embodiment, within the plane of the display substrate, a plurality of sub-pixels include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged sequentially along a first direction; a plurality of first signal lines include a data signal line 62, and a spare connection electrode includes a first spare connection electrode 62-2.

[0103] Data signal lines 62 are respectively disposed in each sub-pixel. Each data signal line 62 includes a main body and a first branch. The first branch includes a first spare connection electrode 62-2. The main body of the data signal line 62 extends along the second direction Y. The first spare connection electrode 62-2 in the first sub-pixel P1 and the third sub-pixel P3 extends in the opposite direction of the first direction X. The first spare connection electrode 62-2 in the second sub-pixel P2 and the fourth sub-pixel P4 extends along the first direction X.

[0104] In an exemplary embodiment, within the plane of the display substrate, a plurality of sub-pixels include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged sequentially along a first direction X; a plurality of first signal lines include a first power line 61, and a spare connection electrode includes a second spare connection electrode 61-3.

[0105] The first power line 61 includes a main body and a branch. The branch of the first power line 61 includes a second spare connection electrode 61-3. The main body of the first power line 61 is disposed between the second sub-pixel P2 and the third sub-pixel P3. The second spare connection electrode 61-3 is located between the second sub-pixel P2 and / or the third sub-pixel P3.

[0106] The main body of the first power line 61 extends along the second direction Y, the second spare connection electrode 61-3 in the second sub-pixel P2 extends in the opposite direction of the first direction X, and the second spare connection electrode 61-3 in the third sub-pixel P3 extends along the first direction X.

[0107] In an exemplary embodiment, within the plane of the display substrate, a plurality of sub-pixels include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged sequentially along a first direction X; a plurality of first signal lines include a compensation signal line 63, and a spare connection electrode includes a third spare connection electrode 63-1.

[0108] Compensation signal lines 63 are respectively disposed in the first sub-pixel P1 and the fourth sub-pixel P4. The compensation signal line 63 includes a main body and a branch body. The branch body of the compensation signal line 63 includes a third spare connection electrode 63-1. The main body of the compensation signal line 63 extends along the second direction Y. In the first sub-pixel P1, the third spare connection electrode 63-1 extends along the first direction X. In the fourth sub-pixel P4, the third spare connection electrode 63-1 extends in the opposite direction of the first direction X.

[0109] In an exemplary embodiment, the spare signal line 53 is located in at least two pixel units.

[0110] In an exemplary embodiment, in at least one sub-pixel, the driving circuit further includes a first transistor T1, a second transistor T2, and a third transistor T3; the active layers of the first transistor T1, the second transistor T2, and the third transistor T3 are located in the semiconductor layer, the gate electrodes of the first transistor T1, the second transistor T2, and the third transistor T3 are located in the second conductive layer, and the first and second electrodes of the first transistor T1, the second transistor T2, and the third transistor T3 are located in the third conductive layer.

[0111] In an exemplary embodiment, in at least one sub-pixel, the driving circuit further includes a masking layer located on the first conductive layer, and the orthographic projection of the active layer of the second transistor T2 onto the substrate 101 is within the range of the orthographic projection of the masking layer onto the substrate.

[0112] In an exemplary embodiment, within the plane of the display substrate, a plurality of sub-pixels include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged sequentially along a first direction X; the shielding layer can be reused as the first electrode plate of a capacitor; the semiconductor layer may include a second electrode plate formed in each sub-pixel;

[0113] The orthographic projection of the second electrode plate onto the substrate is within the range of the orthographic projection of the first electrode plate onto the substrate; the area of ​​the second electrode plate in the first sub-pixel P1 and the third sub-pixel P3 is greater than the area of ​​the second electrode plate in the second sub-pixel P2 and the fourth sub-pixel P4.

[0114] In an exemplary embodiment, the second conductive layer may further include a first scan signal line 51, a second scan signal line 52, and a second gate electrode 54; the first scan signal line 51, the second scan signal line 52, and the spare signal line 53 may be arranged along the second direction Y;

[0115] The first scan signal line 51 may include a main body and a branch. The main body of the first scan signal line 51 may be a strip structure extending along the first direction X, located on the side of the second electrode plate away from the second scan signal line 52 in the second direction Y. The branch of the first scan signal line 51 extends along the second direction Y. The branch of the first scan signal line 51 may include a first gate electrode 51-1 corresponding to each sub-pixel. The first gate electrode 51-1 may serve as the gate electrode of the first transistor T1. The orthographic projection of the first gate electrode 51-1 on the substrate 101 overlaps with the orthographic projection of the active layer of the first transistor T1 on the substrate 101.

[0116] The second scan signal line 52 is a strip structure extending along the first direction X, located on the side of the second electrode plate 34 away from the first scan signal line 51 in the second direction Y. The orthographic projection of the second scan signal line 52 on the substrate 101 overlaps with the orthographic projection of the active layer of the third transistor T3 in each sub-pixel on the substrate 101. The second scan signal line 52 in the overlapping area serves as the gate electrode of the third transistor T3.

[0117] The second gate 54 serves as the gate electrode of the second transistor T2. The orthographic projection of the second gate electrode 54 onto the substrate 101 overlaps with the orthographic projection of the active layer of the second transistor T2 onto the substrate 101 in a second overlapping region. The second gate electrode 54, the second electrode of the first transistor T1, and the orthographic projection of the active layer of the first transistor T1 onto the substrate 101 in a third overlapping region. The second and third overlapping regions do not overlap.

[0118] In an exemplary embodiment, the first signal line may include a data signal line 62, which is respectively disposed in each sub-pixel. The data signal line 62 may include a main body portion and a second branch portion. The main body portion of the data signal line 62 extends along the second direction Y. The second branch portion of the data signal line 62 in the first sub-pixel P1 and the third sub-pixel P3 extends in the opposite direction to the first direction Y. The second branch portion of the data signal line 62 in the second sub-pixel P2 and the fourth sub-pixel P4 extends along the first direction. The second branch portion of the data signal line 62 may serve as the first electrode of the first transistor T1.

[0119] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0120] In an exemplary embodiment, taking four sub-pixels (first sub-pixel P1, second sub-pixel P2, third sub-pixel P3 and fourth sub-pixel P4) as an example, the fabrication process of the driving circuit layer may include the following operations.

[0121] (1) Forming the first conductive layer pattern.

[0122] In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive layer thin film on a substrate 101, and patterning the first conductive film using a patterning process to form a first conductive layer 11 pattern disposed on the substrate 101, such as... Figure 8 The figure shown is a planar schematic diagram of the first conductive layer.

[0123] In an exemplary embodiment, patterning the first conductive film by a patterning process may include: coating a layer of photoresist on the first conductive film, forming a photoresist pattern by masking, exposure and development, forming an unexposed area in the patterned area of ​​the first conductive layer while retaining the photoresist, forming an exposed area without photoresist in the area outside the patterned area of ​​the first conductive layer, etching the first conductive film in the exposed area using an etching process, and finally peeling off the remaining photoresist to form the first conductive layer pattern.

[0124] In an exemplary embodiment, the first conductive layer pattern includes at least two power connection lines 11, two compensation connection lines 12, and a first electrode 13 and an interlayer connection electrode 14 of a capacitor formed in each sub-pixel. In an exemplary embodiment, the first conductive layer may be referred to as a shielding metal (SHL) layer.

[0125] In an exemplary embodiment, the two power connection lines 11 can be strip knots extending along the first direction X and arranged sequentially along the second direction Y.

[0126] In an exemplary embodiment, the two power connection lines 11 are respectively located on both sides of the first electrode plate 13 along the second direction Y, and the two power connection lines 11 can be reused by adjacent pixel units along the second direction Y. For example, the power connection line 11 located on one side of the first electrode plate 13 along the second direction Y can be reused as a power connection line by a pixel unit located on one side of the first electrode plate 13 along the second direction Y; the power connection line 11 located on the opposite side of the first electrode plate 13 along the second direction Y can be reused as a power connection line by a pixel unit located on the opposite side of the first electrode plate 13 along the second direction Y.

[0127] In an exemplary embodiment, two power connection lines 11 are arranged across the first sub-pixel P1 to the fourth sub-pixel P4.

[0128] In an exemplary embodiment, the two power connection lines 11 are configured to be connected to the subsequently formed first power line, and to provide power voltages to the second transistors T2 of the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4, respectively.

[0129] In an exemplary embodiment, the two compensation connection lines 12 can be strip structures extending along the first direction X, and are arranged sequentially along the first direction X. The two compensation lines 12 are located on one side of the first electrode plate 13 along the second direction Y, and are located between the first electrode plate 13 and the power connection line 11 in the second direction Y. One compensation connection line 12 is disposed across the first sub-pixel P1 and the second sub-pixel P2, and provides compensation voltage to the third transistor T3 of the first sub-pixel P1 and the second sub-pixel P2, respectively; the other compensation connection line 12 is disposed across the third sub-pixel P3 and the fourth sub-pixel P4, and provides compensation voltage to the third transistor T3 of the third sub-pixel P3 and the fourth sub-pixel P3, respectively.

[0130] In an exemplary embodiment, the interlayer connection electrode 14 can be a strip structure extending along the second direction Y. In an exemplary embodiment, the interlayer connection electrode 14 and the first electrode plate 13 are integrally formed.

[0131] In an exemplary embodiment, the first electrode plate 13 can be reused as a shielding layer.

[0132] In an exemplary embodiment, the first conductive layer film can be formed using a sputtering process. In an exemplary embodiment, the material of the first conductive layer can be molybdenum oxide (MoOx). Molybdenum oxide is black in color, has stable properties, and is readily available. The material of the light-shielding film can also be replaced with other materials, as long as the light-shielding film is opaque.

[0133] In an exemplary embodiment, the first electrode 13 can block light incident from the side of the substrate 101 away from the shielding layer from affecting the thin-film transistors in the display substrate, preventing changes in the electrical characteristics of the thin-film transistors due to external light exposure, thereby improving the stability of the thin-film transistors. For example, the semiconductor material used in the active layer of the thin-film transistor has a photoconductive effect, and its electrical characteristics such as on-state current and off-state current change significantly in the presence and absence of light. That is, drift and other problems are prone to occur in the presence of light, resulting in unstable electrical characteristics.

[0134] (2) Forming a semiconductor layer pattern.

[0135] In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate 101 on which the aforementioned pattern is formed; patterning the semiconductor film using a patterning process to form a first insulating layer 20 covering a first conductive layer and a semiconductor layer pattern disposed on the first insulating layer 20; the semiconductor layer pattern includes at least a first active layer 31, a second active layer 32, a third active layer 33, and a second electrode 34 of a capacitor formed in each sub-pixel, such as... Figure 9a and Figure 9b As shown, Figure 9b for Figure 9a A planar schematic diagram of the semiconductor layer.

[0136] In an exemplary embodiment, the first active layer 31 may be located on the side opposite to the second direction Y of the second electrode plate 34. The first active layer 31 may include a first region 31-1 and a second region 31-2 that are interconnected. In an exemplary embodiment, the second region 31-2 of the first active layer 31 may be connected to the second electrode plate 34, and the first active layer 31 and the second electrode plate 34 may be an integral structure that is interconnected.

[0137] In an exemplary implementation, such as Figure 9bAs shown, the first region 31-1 of the first active layer 31 may include a first part a1 and a second part a2 connected to each other. In the first sub-pixel P1 and the third sub-pixel P3, the first part a1 may be a strip-shaped structure extending along a first direction X, and the second part a2 may be a strip-shaped structure extending along a second direction Y, with the first part a1 located on one side of the second part a2 in the first direction X. In the second sub-pixel P2 and the fourth sub-pixel P4, the first part a1 may be a strip-shaped structure extending along the first direction X, and the second part a2 may be a strip-shaped structure extending at an angle of 30° to 80° to the opposite direction of the first direction X, with the first part a1 located on the opposite side of the second part a2 in the first direction X.

[0138] In an exemplary implementation, such as Figure 9c As shown, Figure 9a Another planar schematic diagram of the semiconductor layer shows that the first part a1 of the second sub-pixel P2 and the fourth sub-pixel P4 can be a strip structure extending along the first direction X, and the second part a2 can be a strip structure extending along the second direction Y, and the first part a1 is located on the side opposite to the first direction X of the second part a2.

[0139] In an exemplary embodiment, the second region 31-2 of the first active layer 31 can be a strip structure extending along the second direction, and the orthographic projection of the second region 31-2 of the first active layer 31 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 13 on the substrate.

[0140] In an exemplary embodiment, the second active layer 32 can be a strip-shaped structure extending along the second direction Y. The second active layer 32 can be located on the side opposite to the second direction Y of the second electrode plate 34. In the first sub-pixel P1 and the third sub-pixel P3, the second active layer 32 is located on the side opposite to the first direction X of the second region 31-2 of the first active layer 31; in the second sub-pixel P2 and the fourth sub-pixel P4, the second active layer 32 is located on the side of the first direction X of the second region 31-2 of the first active layer 31. The orthographic projection of the second active layer 32 on the substrate 101 is within the range of the orthographic projection of the first electrode plate 13 on the substrate 101. The second active layer 32 can include a first region 32-1 and a second region 32-2 symmetrically arranged along the centerline of the first direction X. The first electrode plate 13 can shield the channel region of the second active layer 32 to prevent light from affecting the channel, reduce leakage current, and thus prevent the influence of light on the transistor characteristics.

[0141] In an exemplary embodiment, the third active layer 33 may be a strip-shaped structure extending along the second direction Y, and the third active layer 33 is located on one side of the second electrode plate 34 in the second direction Y. The third active layer 33 may include a first region 33-1 and a second region 33-2 symmetrically arranged along the centerline of the first direction X.

[0142] In an exemplary embodiment, in each sub-pixel, the shape of the second electrode plate 34 can be similar to the shape of the first electrode plate 13 in the same sub-pixel, and the orthographic projection of the second electrode plate 34 onto the substrate is within the range of the orthographic projection of the first electrode plate 13 onto the substrate. In an exemplary embodiment, the area of ​​the second electrode plate 34 in the first sub-pixel P1 and the third sub-pixel P3 is larger than the area of ​​the second electrode plate 34 in the second sub-pixel P2 and the fourth sub-pixel P4.

[0143] In an exemplary embodiment, the semiconductor layer may be a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0144] (3) Forming a second conductive layer pattern.

[0145] In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate 101 on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a second insulating layer 40 covering the semiconductor layer; and a second conductive layer pattern disposed on the second insulating layer 40. The second conductive layer pattern includes at least a first scan signal line 51, a second scan signal line 52, a spare signal line 53, a second gate electrode 54, an auxiliary compensation line 55, an auxiliary data line 56, and an auxiliary power supply line 57. Figure 10a and Figure 10b As shown, Figure 10b for Figure 10a A schematic planar view of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as a gate metal (GATE) layer.

[0146] In an exemplary embodiment, the first scan signal line 51 is a strip structure extending along the first direction X, located on one side of the second electrode plate 34 in the second direction Y. The first scan signal line 51 spans from the first sub-pixel P1 to the fourth sub-pixel P4. A first gate electrode 51-1 is disposed on the first scan signal line 51 corresponding to each sub-pixel. The first gate electrode 51-1 serves as the gate electrode of the first transistor T1. The orthographic projection of the first gate electrode 51-1 on the substrate overlaps with the orthographic projection of the first active layer 31 on the substrate. In an exemplary embodiment, the first gate electrode 51-1 extends along the second direction Y, and the orthographic projection of the first gate electrode 51-1 on the substrate 101 overlaps with the orthographic projection of the first portion a1 of the first active layer 31 on the substrate.

[0147] In an exemplary embodiment, the first scan signal line 51 can be configured with a uniform width, the width of which is the dimension of the first scan signal line 51 in the second direction Y. Multiple second through holes 59 can be provided on the first scan signal line 51. The orthographic projection of the multiple second through holes 59 on the substrate overlaps with the orthographic projection of the subsequently formed first power line, data signal line, and compensation signal line on the substrate 101. The multiple second through holes 59 are configured to reduce the parasitic capacitance between the first scan signal line 51 and the first power line, data signal line, and compensation signal line. If one of the two first connecting lines b1 located on both sides of the second through hole 59 in the second direction Y is short-circuited with the subsequently formed first power line, data signal line, and compensation signal line, the short-circuited first connecting line b1 can be cut off, and the other first connecting line b1 can transmit the electrical signal. This allows for repair of the portion of the subsequently formed first power line, data signal line, and compensation signal line that is short-circuited with the first scan signal line 51, while ensuring normal signal transmission of the first scan signal line 51.

[0148] In an exemplary embodiment, the second scan signal line 52 is a strip structure extending along the first direction X and located on one side of the second electrode plate 34 in the second direction Y. The second scan signal line 52 spans from the first sub-pixel P1 to the fourth sub-pixel P4. The orthographic projection of the second scan signal line 52 on the substrate 101 overlaps with the orthographic projection of the third active layer 33 in each sub-pixel on the substrate. The second scan signal line 52 in the overlapping region serves as the gate electrode of the third transistor T3.

[0149] In an exemplary embodiment, the second scan signal line 52 can be configured with a uniform width, the width of which is the dimension of the second scan signal line 52 in the second direction Y. Multiple second through holes 59 can be provided on the second scan signal line 52. The orthographic projection of the multiple second through holes 59 on the substrate 101 overlaps with the orthographic projection of the subsequently formed first power line, data signal line, and compensation signal line on the substrate 101. The multiple second through holes 59 are configured to reduce the parasitic capacitance between the second scan signal line 52 and the first power line, data signal line, and compensation signal line. If one of the two second connecting lines b2 located on both sides of the second through hole 59 in the second direction Y is short-circuited with the subsequently formed first power line, data signal line, and compensation signal line, the short-circuited second connecting line b2 can be cut off, and the other second connecting line b2 can transmit the electrical signal. This allows for repair of the short-circuited portion of the subsequently formed first power line, data signal line, and compensation signal line with the second scan signal line 52 while ensuring normal signal transmission of the second scan signal line 52.

[0150] In an exemplary embodiment, the first scan signal line 51 and the second scan signal line 52 can be arranged in parallel.

[0151] In an exemplary embodiment, the spare signal line 53 may be a strip-shaped structure extending along the first direction X, located on one side of the second scan signal line 52 in the second direction Y. The second scan signal line 52 spans from the first sub-pixel P1 to the fourth sub-pixel P4. The spare signal line 53 may be of uniform width, the width of which is the dimension of the spare signal line 53 in the second direction Y.

[0152] In an exemplary embodiment, a second gate electrode 54 is formed within each sub-pixel as the gate electrode of the second transistor T2. Within each sub-pixel, on the one hand, the orthographic projection of the second gate electrode 54 on the substrate 101 overlaps with the orthographic projection of the second active layer 32 on the substrate, and on the other hand, the orthographic projection of the second gate electrode 53 on the substrate overlaps with the second region 31-2 of the first active layer 31.

[0153] In an exemplary embodiment, the auxiliary compensation line 55 is formed within the first sub-pixel P1 and the fourth sub-pixel P4, and is a strip structure extending along the second direction Y. Within the first sub-pixel P1, the auxiliary compensation line 55 is located on the side opposite to the first direction X of the second electrode plate 34. Within the fourth sub-pixel P4, the auxiliary compensation line 55 is located on one side of the second electrode plate 34 in the first direction X. The auxiliary compensation line 55 is configured to connect with subsequently formed compensation signal lines, forming a double-layer trace to ensure the reliability of compensation signal transmission and reduce the resistance of the compensation signal lines.

[0154] In an exemplary embodiment, auxiliary data lines 56 are formed within each sub-pixel as strip structures extending along the second direction Y. In the first sub-pixel P1 and the third sub-pixel P3, auxiliary data lines 45 are located on one side of the second electrode plate 34 in the first direction X. In the second sub-pixel P2 and the fourth sub-pixel P4, auxiliary data lines 56 are located on the opposite side of the second electrode plate 34 in the first direction X. The auxiliary data lines 56 are configured to connect with subsequently formed data signal lines, forming a double-layer trace to ensure the reliability of data signal transmission and reduce the resistance of the data signal lines.

[0155] In an exemplary embodiment, an auxiliary power line 57 is formed between the second sub-pixel P2 and the third sub-pixel P3, and is a strip structure extending along the second direction Y. The auxiliary power line 57 is configured to connect to the subsequently formed first power line, forming a double-layer trace to ensure the reliability of power signal transmission and reduce the resistance of the first power line.

[0156] In an exemplary embodiment, the second gate electrode 54 in the first sub-pixel P1 and the fourth sub-pixel P4 can be mirror-symmetrically arranged with respect to the vertical axis (auxiliary power line 57), the second gate electrode 43 in the second sub-pixel P2 and the third sub-pixel P3 can be mirror-symmetrically arranged with respect to the vertical axis (auxiliary power line 57), the auxiliary compensation line 55 in the first sub-pixel P1 and the fourth sub-pixel P4 can be mirror-symmetrically arranged with respect to the vertical axis (auxiliary power line 57), the first scan signal line 51 can be mirror-symmetrically arranged with respect to the vertical axis, the second scan signal line 52 can be mirror-symmetrically arranged with respect to the vertical axis, and the spare signal line 53 can be mirror-symmetrically arranged with respect to the vertical axis.

[0157] In an exemplary embodiment, the main bodies of the auxiliary power line 55, the auxiliary data line 56, and the auxiliary compensation line 57 can be arranged in parallel.

[0158] In an exemplary embodiment, the process further includes a conductor-enhancing process. The conductor-enhancing process involves performing plasma treatment using the second conductive layer as a shield after the second conductive layer pattern is formed. The semiconductor layer in the region shielded by the first gate electrode, the second gate electrode, and the third gate electrode serves as the channel region of the transistor, while the semiconductor layer in the region not shielded by the second conductive layer is processed into a conductor-enhanced layer, forming a conductor-enhanced second electrode 34 and conductor-enhanced source / drain regions.

[0159] (4) Form the third insulating layer pattern.

[0160] In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate 101 on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer 60 covering the second conductive layer. The third insulating layer has a plurality of vias, which include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, and an eleventh via V11, and a spare half-via Vm, such as... Figure 11a and Figure 11b As shown, Figure 11a A schematic diagram showing the setup of multiple vias. Figure 11b As shown Figure 11a A schematic diagram of the cross-sectional structure at the HH position.

[0161] In an exemplary embodiment, a first via V1 may be disposed in each sub-pixel. The orthographic projection of the first via V1 onto the substrate 101 lies within the range of the orthographic projection of the first region 31-1 of the first active layer 31 onto the substrate. The third and second insulating layers within the first via V1 are etched away, exposing the surface of the first region 31-1 (first part a1) of the first active layer 31. In an exemplary embodiment, the first via V1 is configured to connect subsequently formed data signal lines to the first active layer 31 via the via.

[0162] In an exemplary embodiment, a second via V2 can be disposed in each sub-pixel. The orthographic projection of the second via V2 onto the substrate 101 is within the range of the orthographic projection of the second region 31-2 of the first active layer 31 onto the substrate, and the orthographic projection of the second via V2 onto the substrate 101 at least partially overlaps with the orthographic projection of the second gate electrode 54 onto the substrate 101. The third insulating layer and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region 31-2 of the first active layer 31 and the surface of the second gate electrode 54. The second via V2 can be a transition via or a via structure, wherein the transition via consists of two half-holes, one half-hole formed on the second region 31-2 of the first active layer 31 and the other half-hole formed on the second gate electrode 54, such that the transition via composed of the two half-holes simultaneously exposes the surface of the second region 31-2 of the first active layer 31 and the surface of the second gate electrode 54. In an exemplary embodiment, the second via V2 is configured to allow the second electrode of the subsequently formed first transistor T1 to be simultaneously connected to the second gate electrode 54 and the first active layer 31 through the via.

[0163] In an exemplary embodiment, a third via V3 may be disposed in each sub-pixel. The orthographic projection of the third via V3 onto the substrate 101 lies within the range of the orthographic projection of the first region 32-1 of the second active layer 32 onto the substrate 101. The third insulating layer and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region 32-1 of the second active layer 32. In an exemplary embodiment, the third via V3 is configured to allow a subsequently formed first power line or a fifth connection electrode to be connected to the second active layer 32 through the via.

[0164] In an exemplary embodiment, a fourth via V4 may be disposed in each sub-pixel. The orthographic projection of the fourth via V4 onto the substrate 101 at least partially overlaps with the orthographic projection of the second region 32-2 of the second active layer 32 onto the substrate, and at least partially overlaps with the orthographic projection of the first electrode plate 13 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the fourth via V4 are etched away, thereby exposing the surface of the second region 32-2 of the second active layer 32 and the surface of the first electrode plate 13. In an exemplary embodiment, the fourth via V4 is configured to allow the second electrode of the subsequently formed second transistor T2 to be connected to both the first electrode plate 13 and the second active layer 32 through the via.

[0165] In an exemplary embodiment, a fifth via V5 may be disposed in each sub-pixel. The orthographic projection of the fifth via V5 onto the substrate at least partially overlaps with the orthographic projection of the first region 33-1 of the third active layer 33 onto the substrate, and at least partially overlaps with the orthographic projection of the compensation connection line 12 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the fifth via V5 are etched away, thereby exposing the surface of the first region 33-1 of the third active layer 33 and the surface of the compensation connection line 12. In an exemplary embodiment, the fifth via V5 is configured to allow the first electrode of the subsequently formed third transistor T3 to be connected to both the compensation connection line 12 and the third active layer 33 through the via.

[0166] In an exemplary embodiment, a sixth via V6 can be disposed in each sub-pixel. The orthographic projection of the sixth via V6 onto the substrate 101 at least partially overlaps with the orthographic projection of the second region 33-2 of the third active layer 33 onto the substrate, and at least partially overlaps with the orthographic projection of the interlayer connection electrode 14 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the sixth via V6 are etched away, exposing the surface of the second region 33-2 of the third active layer 33 and the surface of the interlayer connection electrode 14. In an exemplary embodiment, the sixth via V6 is configured to allow the second electrode of the subsequently formed third transistor T3 to be connected to both the interlayer connection electrode 14 and the third active layer 33 through the via. The third transistor T3 is connected to the first plate 13 of the capacitor through the connection of the interlayer connection electrode 14.

[0167] In an exemplary embodiment, a seventh via V7 may be disposed between the second sub-pixel p2 and the third sub-pixel p3. The orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection range of the middle portion of the power connection line 11 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the seventh via V7 are etched away, exposing the surface of the middle portion of the power connection line 11. In an exemplary embodiment, the seventh via V7 is configured to allow a subsequently formed first power line to be connected to the power connection line 11 through this via.

[0168] In an exemplary embodiment, an eighth via V8 may be disposed between the first sub-pixel P1 and the fourth sub-pixel P4. The orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection range of both ends of the power connection line 11 on the side of the first electrode plate 13 opposite to the second direction Y. The third insulating layer, the second insulating layer, and the first insulating layer within the eighth via V8 are etched away, exposing the surfaces of both ends of the power connection line 11. In an exemplary embodiment, the eighth via V8 is configured to allow the first electrode of the second transistor T2 subsequently formed in the third sub-pixel P3 and the fourth sub-pixel P4 to be connected to the end of the power connection line 11 through the via.

[0169] In an exemplary embodiment, a ninth via V9 may be disposed between the second sub-pixel P2 and the third sub-pixel P3. The orthographic projection of the ninth via V9 onto the substrate lies within the range of the orthographic projection of the auxiliary power line 57 onto the substrate. The third insulating layer within the ninth via V9 is etched away, exposing the surface of the auxiliary power line 57. In an exemplary embodiment, the ninth via V9 is configured to allow a subsequently formed first power line to connect to the auxiliary power line 57 through the via. In an exemplary embodiment, multiple ninth vias V9 may be included, and these multiple ninth vias V9 may be arranged sequentially along the second direction Y to increase the connection reliability between the first power line and the auxiliary power line 57.

[0170] In an exemplary embodiment, a tenth via V10 may be disposed in each sub-pixel. The orthographic projection of the tenth via V10 onto the substrate lies within the range of the orthographic projection of the auxiliary data line 56 onto the substrate. The third insulating layer within the tenth via V10 is etched away, exposing the surface of the auxiliary data line 56. In an exemplary embodiment, the tenth via V10 is configured to allow subsequently formed data signal lines to connect to the auxiliary data line 56 through the via. In an exemplary embodiment, multiple tenth vias V10 may be included, and the multiple tenth vias V10 may be arranged sequentially along the second direction Y to increase the connection reliability between the data signal lines and the auxiliary data line 56.

[0171] In an exemplary embodiment, an eleventh via V11 may be disposed between the first sub-pixel P1 and the fourth sub-pixel P4. The orthographic projection of the eleventh via V11 onto the substrate lies within the range of the orthographic projection of the auxiliary compensation line 55 onto the substrate. The third insulating layer within the eleventh via V11 is etched away, exposing the surface of the auxiliary compensation line 55. In an exemplary embodiment, the eleventh via V11 is configured to allow subsequently formed compensation signal lines to connect to the auxiliary compensation line 55 through the via. In an exemplary embodiment, multiple eleventh vias V11 may be included, and these multiple eleventh vias V11 may be arranged sequentially along the second direction Y to increase the connection reliability between the compensation signal lines and the auxiliary compensation line 55.

[0172] In an exemplary embodiment, a spare via Vm can be disposed between the first sub-pixel P1 and the fourth sub-pixel P4. The orthographic projection of the spare via Vm onto the substrate lies within the range of the orthographic projection of the spare signal line 53 onto the substrate. A portion of the third insulating layer within the spare via Vm is etched away, and the surface of the spare signal line 53 is not exposed. In an exemplary embodiment, the spare via Vm is configured such that at least one of the subsequently formed first power line 61, data signal line 62, and compensation signal line 63 is connected to the spare signal line 53 after the spare via is opened.

[0173] (5) Form the pattern of the third conductive layer.

[0174] In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the third conductive thin film using a patterning process, and forming a third conductive layer disposed on a third insulating layer. The third conductive layer includes at least: a first power line 61, a data signal line 62, a compensation signal line 63, a first connection electrode 64, a second connection electrode 65, a third connection electrode 66, a fourth connection electrode 67, and a fifth connection electrode 68, such as... Figure 12a and Figure 12b As shown, Figure 12b for Figure 12a A schematic planar view of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the source / drain metal (SD) layer.

[0175] In an exemplary embodiment, a first power line 61 is disposed between a second sub-pixel P2 and a third sub-pixel P3, and the main body of the first power line 61 extends along a second direction Y. The first power line 61 is connected to an auxiliary power line 57 through a plurality of ninth vias V9, such that the first power line 61 and the auxiliary power line 57 form a double-layer trace.

[0176] In an exemplary embodiment, a first protrusion 61-1 and a second protrusion 61-2 are provided on the first power line 61. The first end of the first protrusion 61-1 is connected to the first power line 61, and the second end of the first protrusion 61-1 extends along the opposite direction of the first direction X to the second sub-pixel P2, and is connected to the first region 32-1 of the second active layer 32 through the third via V3 of the sub-pixel, thus writing a power signal into the second transistor T2 of the second sub-pixel P2. The first end of the second protrusion 61-2 is connected to the first power line 61, and the second end of the second protrusion 61-2 extends along the first direction X to the third sub-pixel P3, and is connected to the first region 32-1 of the second active layer 32 through the third via V3 of the sub-pixel, thus writing a power signal into the second transistor T2 of the third sub-pixel P3.

[0177] In an exemplary embodiment, data signal lines 62 are respectively disposed in each sub-pixel, and the main body of the data signal lines 62 extends along the second direction Y. On one hand, the data signal lines 62 are connected to the first region 31-1 of the first active layer 31 through the first via V1 to realize the writing of data signals to the first transistor T1. On the other hand, the data signal lines 62 are connected to the auxiliary data lines 56 through a plurality of tenth vias V10, so that the data signal lines 62 and the auxiliary data lines 56 form a double-layer trace.

[0178] In an exemplary embodiment, the data signal line 62 is provided with a signal line connection portion 62-1 (i.e., the second branch portion of the data signal line 62) and a first spare connection electrode 62-2. In the first sub-pixel P1 and the third sub-pixel P3, the signal line connection portion 62-1 and the first spare connection electrode 62-2 extend along the opposite side of the main body portion of the data signal line 62 in the first direction X. The signal line connection portion 62-1 is connected to the first region 31-1 of the first active layer 31 through the first via V1, thereby realizing the writing of data signals to the first transistor T1. In the second sub-pixel P2 and the fourth sub-pixel P4, the signal line connection portion 62-1 and the first spare connection electrode 62-2 extend along the first direction X of the main body portion of the data signal line 62. The signal line connection portion 62-1 is connected to the first region 31-1 of the first active layer 31 through the first via V1, thereby realizing the writing of data signals to the first transistor T1. The orthogonal projection of the spare half-via Vm on the substrate is located within the range of the orthogonal projection of the first spare connection electrode 62-2 on the substrate. Opening the spare half-via Vm can realize the electrical connection between the first spare connection electrode 62-2 and the spare signal line 53. In an exemplary embodiment, the first spare connection electrode 62-2 and the data signal line 62 can be an integrally formed structure.

[0179] In an exemplary embodiment, compensation signal lines 63 are respectively disposed in the first sub-pixel P1 and the fourth sub-pixel P4, and the main body of the compensation signal lines 63 extends along the second direction Y. On one hand, the compensation signal lines 63 are connected to the first region 33-1 of the third active layer 33 and the compensation connection line 12 through the fourth connection electrode 67 and the fifth via V5, thereby realizing the writing of the compensation signal to the third transistor T3. On the other hand, the compensation signal lines 63 are connected to the auxiliary compensation lines 55 through multiple eleventh vias V11, so that the compensation signal lines 63 and the auxiliary compensation lines form a double-layer trace.

[0180] In an exemplary embodiment, the first connection electrode 64 is disposed in each sub-pixel and may be rectangular. The first connection electrode 64 in each sub-pixel is simultaneously connected to the second region 31-2 and the second gate electrode 54 of the first active layer 31 via the second via V2. In an exemplary embodiment, the first connection electrode 64 serves as the second electrode of the first transistor T1. Since the second region 31-2 of the first active layer 31 is connected to the second electrode plate 34, the first connection electrode 64 ensures that the second electrode of the first transistor T1, the second gate electrode 54, and the second electrode plate 34 have the same potential, i.e., the potential of the first node N1.

[0181] In an exemplary embodiment, the second connection electrode 65 is disposed in each sub-pixel and may be rectangular. The second connection electrode 65 in each sub-pixel is simultaneously connected to the second region 32-2 of the second active layer 32 and the first electrode plate 13 through a fourth via V4. In an exemplary embodiment, the second connection electrode 65 serves as the second electrode of the second transistor T2. Because the second connection electrode 65 is connected to the first electrode plate 13, the second connection electrode 65 ensures that the second electrode of the second transistor T2 and the first electrode plate 13 have the same potential, i.e., the potential of the first node N2.

[0182] In an exemplary embodiment, the third connection electrode 66 is disposed in each sub-pixel and may be rectangular. The third connection electrode 66 in each sub-pixel is simultaneously connected to the second region 33-2 of the third active layer 33 and the interlayer connection electrode 14 through the sixth via V6. In an exemplary embodiment, the third connection electrode 66 serves as the second electrode of the third transistor T3. Since the interlayer connection electrode 14 is connected to the first electrode plate 13, the third connection electrode 66 ensures that the second electrode of the third transistor T3 and the first electrode plate 13 have the same potential.

[0183] Since the second connecting electrode 65 makes the first electrode plate 13 and the second electrode of the second transistor T2 have the same potential, and the third connecting electrode 66 makes the first electrode plate 13 and the second electrode of the third transistor T3 have the same potential, the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode plate 11 have the same potential, that is, the potential of the second node N2.

[0184] In an exemplary embodiment, the fourth connection electrode 67 is respectively disposed in the first sub-pixel P1 and the fourth sub-pixel P4, and can be a strip structure extending along the first direction X. The fourth connection electrode 67 disposed in the first sub-pixel P1 and the compensation signal line 63 can be integrally formed. The fourth connection electrode 67 is located on one side of the compensation signal line 63 in the first direction X. The fourth connection electrode 67 in the first sub-pixel P1 is simultaneously connected to the first region 33-1 of the third active layer 33 and the compensation connection line 12 through the fifth via V5 of the sub-pixel. In an exemplary embodiment, the fourth connection electrode 67 serves as the first electrode of the third transistor T3. Since the compensation connection line 12 is connected to the compensation signal line 63, the fourth connection electrode 67 can write the compensation signal into the third transistor T3 of the first sub-pixel P1. The fourth connection electrode 67 disposed in the fourth sub-pixel P4 and the compensation signal line 63 can be integrally formed. The fourth connection electrode 67 is located on the side opposite to the first direction X of the compensation signal line 63. The fourth connection electrode 67 in the fourth sub-pixel P4 is connected to both the first region 33-1 of the third active layer 33 and the compensation connection line 12 through the fifth via V5 of the sub-pixel. In an exemplary embodiment, the fourth connection electrode 67 serves as the first electrode of the third transistor T3. Since the compensation connection line 12 is connected to the compensation signal line 63, the fourth connection electrode 67 can write the compensation signal into the third transistor T3 of the fourth sub-pixel P4.

[0185] In an exemplary embodiment, the fifth connection electrode 68 is respectively disposed in the first sub-pixel P1 and the fourth sub-pixel P4, and can be a strip structure extending along the second direction Y. The first end of the fifth connection electrode 68 is connected to the power connection line 11 through the eighth via V8, and the second end of the fifth connection electrode 68 is connected to the first region 32-1 of the second active layer 32 through the third via V3 of the sub-pixel. In an exemplary embodiment, the fifth connection electrode 68 serves as the first electrode of the second transistor T2. Since the power connection line 11 is connected to the first power line 61, the fifth connection electrode 68 can write power signals into the second transistor T2 of the first sub-pixel P1 and the fourth sub-pixel P4.

[0186] An exemplary embodiment of this disclosure enables the writing of power signals to the second transistor T2 of four sub-pixels by providing a first power line 61 extending along the second direction Y and a power connection line 11 extending along the first direction X. Specifically, in the second sub-pixel P2 and the third sub-pixel P3, the first power line 61 is directly connected to the second transistor T2 through vias. In the first sub-pixel P1 and the fourth sub-pixel P4, the first power line 61 is connected to the second transistor T2 through a fifth connection electrode 68.

[0187] In an exemplary implementation, such as Figure 12c and Figure 12d As shown, Figure 12dfor Figure 12c A planar schematic diagram of the third conductive layer. At least one side of the main body of the first power line 61, on one side of the first direction X and the opposite side of the first direction X, can be provided with a second spare connection electrode 61-3. The second spare connection electrode 61-3 is located in the second sub-pixel P2 and / or the third sub-pixel P3. In the second sub-pixel P2, the first end of the second spare connection electrode 61-3 is connected to the first power line 61, and the second end of the second spare connection electrode 61-3 extends in the opposite direction of the first direction X. In the third sub-pixel P3, the first end of the second spare connection electrode 61-3 is connected to the first power line 61, and the second end of the second spare connection electrode 61-3 extends in the first direction X. The orthographic projection of the spare half-via Vm on the substrate is located within the range of the orthographic projection of the second spare connection electrode 61-3 on the substrate. Opening the spare half-via Vm enables an electrical connection between the second spare connection electrode 61-3 and the spare signal line 53. In an exemplary embodiment, the second spare connection electrode 61-3 and the first power line 61 can be an integrally formed structure.

[0188] In an exemplary embodiment, a third spare connection electrode 63-1 may be provided on one side of the compensation signal line 63 in the first direction X and / or the opposite direction of the first direction X. The third spare connection electrode 63-1 is located in the first sub-pixel P1 and the fourth sub-pixel P4. In the first sub-pixel P1, the first end of the third spare connection electrode 63-1 is connected to the compensation signal line 63, and the second end of the third spare connection electrode 63-1 extends along the first direction X. Similarly, in the fourth sub-pixel P4, the first end of the third spare connection electrode 63-1 is connected to the compensation signal line 63, and the second end of the third spare connection electrode 63-1 extends along the opposite direction of the first direction X. The orthogonal projection of the spare half-via Vm onto the substrate is within the range of the orthogonal projection of the third spare connection electrode 63-1 onto the substrate. Opening the spare half-via Vm enables an electrical connection between the third spare connection electrode 63-1 and the spare signal line 53. In an exemplary embodiment, the third spare connection electrode 63-1 and the compensation signal line 63 can be an integrally formed structure. In an exemplary embodiment, as... Figure 13 As shown, two adjacent pixel units can share a compensation signal line 53. A third spare connection electrode 63-1 and a fourth connection electrode 67 are provided on both sides of the compensation signal line 53 in the two adjacent pixel units.

[0189] In an exemplary embodiment, Figure 13In the structure shown, each pixel unit includes four sub-pixels P1 to P4. The first sub-pixel P1 can be a green sub-pixel (G) emitting green light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, the third sub-pixel P3 can be a red sub-pixel (R) emitting red light, and the fourth sub-pixel P4 can be a white sub-pixel (W) emitting white light. For example... Figure 13 As shown, the area of ​​the capacitor plates (first plate 13 and second plate 34) in the plane of the display substrate in the first sub-pixel P1 and the third sub-pixel P3 is larger than the area of ​​the capacitor plates (first plate 13 and second plate 34) in the plane of the display substrate in the second sub-pixel P2 and the fourth sub-pixel P4. This allows the capacitors in the first sub-pixel P1 and the third sub-pixel P3 to store more electrical energy, thus meeting the larger driving current required to drive the light-emitting diodes corresponding to the red sub-pixel (i.e., the third sub-pixel P3) and the green sub-pixel (i.e., the first sub-pixel P1).

[0190] This exemplary embodiment of the present disclosure achieves the writing of compensation signals to the third transistor T3 of four sub-pixels by providing two compensation signal lines 63 extending along the second direction Y and two compensation connection lines 12 extending along the first direction X. Specifically, in the first sub-pixel P1 and the fourth sub-pixel P4, the compensation signal lines 63 are directly connected to the third transistor T3 through vias. In the second sub-pixel P2 and the third sub-pixel P3, the compensation signal lines 63 are connected to the third transistor T3 through the compensation connection lines 12. By providing compensation signals to the four sub-pixels through two compensation signal lines, this disclosure ensures that the RC delay of the compensation signals is substantially the same before being written to the transistor, thus guaranteeing display uniformity.

[0191] An exemplary embodiment of this disclosure achieves the writing of data signals into the first transistors T1 of the four sub-pixels by providing a data signal line 62 extending along the second direction Y in each sub-pixel, with the data signal line 62 connected to the first transistor T1 of the sub-pixel through a via.

[0192] In an exemplary embodiment, the first power line 61, the data signal line 62, and the compensation signal line 63 can be straight lines or broken lines of equal width, or straight lines or broken lines of non-equal width.

[0193] like Figure 14a As shown, Figure 12c and Figure 13 A schematic diagram of the cross-sectional structure at position LL. Figure 14b As shown Figure 12c A cross-sectional structural diagram at the WW position.

[0194] like Figure 15aThe diagram illustrates how a broken data signal line 62 can be repaired using a spare signal line 53. For example, if the data signal D13 of the third sub-pixel P3 in the first pixel unit M1 is transmitted in the data signal line 62 in the opposite direction of the second direction Y, and the data signal line 62 of the third sub-pixel P3 in the first pixel unit M1 is broken at position A1, the third sub-pixel P3 located on the opposite side of the second direction Y at the break position A1 cannot acquire the data signal D13. The data signal line 62 on the opposite side of the second direction Y at the break position A1 is intersected with the spare signal line 53 on the opposite side of the second direction Y at the break position A1 (i.e., the position of the first spare connection electrode 62-2). Figure 15a Laser drilling is performed at position B1 to melt the first spare connection electrode 62-2 and the spare signal line 53, thereby electrically connecting the spare signal line 53 to the data signal line 62 that has broken. Laser drilling is also performed at position C1 to melt the first spare connection electrode 62-2 and the spare signal line 53 at position C1, thereby electrically connecting the spare signal line 53 to the data signal line 62 at position C1. Since the data signal line 62 at both positions B1 and C1 is electrically connected to the spare signal line 53, the signal provided by the data signal line 62 of the third sub-pixel P3 in the second pixel unit M2 can be transmitted from the spare signal line 53 to the data signal line 62 of the third sub-pixel unit P3 in the first pixel unit M1, thus enabling the repair of the broken data signal line 62.

[0195] like Figure 15b The diagram illustrates how a broken first power line 61 can be repaired using a spare signal line 53. For example, if the first power line 61 in the first pixel unit M1 is broken at position A2, the pixel unit located on the opposite side of the second direction Y at position A2 cannot receive the first power signal. The first power line 61 on the opposite side of the second direction Y at position A2 is intersected with the spare signal line 53 on the opposite side of the second direction Y at position A2 (i.e., the position of the second spare connection electrode 61-3). Figure 15bLaser drilling is performed at position B2 to melt the second spare connection electrode 61-3 and the spare signal line 53, thereby electrically connecting the spare signal line 53 to the first power line 61 that has broken. Laser drilling is also performed at position C2 on the first power line 61 in the second pixel unit M2 to melt the second spare connection electrode 61-3 and the spare signal line 53 at position C2, thereby electrically connecting the spare signal line 53 to the first power line 61 at position C2. Since the first power line 61 at both positions B2 and C2 is electrically connected to the spare signal line 53, the signal provided by the first power line 61 in the second pixel unit M2 can be transmitted from the spare signal line 53 to the first power line 61 in the first pixel unit M1, thus enabling the repair of the first power line 61 that has broken.

[0196] like Figure 15c The diagram illustrates how a broken compensation signal line 63 can be repaired using a spare signal line 53. For example, if the compensation signal line 63 between the first pixel unit M1 and the second pixel unit M2 is broken at position A3, the pixel unit located on the opposite side of the second direction Y at position A3 cannot receive a compensation signal. The compensation signal line 63 on the opposite side of the second direction Y at position A3 is intersected with the spare signal line 53 on the opposite side of the second direction Y at position A3 (i.e., the position of the third spare connection electrode 63-1). Figure 15c Laser drilling is performed at position B3 to melt the third spare connection electrode 63-1 and the spare signal line 53, thereby electrically connecting the spare signal line 53 with the compensation signal line 63 that has broken. Laser drilling is also performed at position C3 on the compensation signal line 63 on the Y side of the second pixel unit M2, so that the third spare connection electrode 63-1 at position C3 melts the spare signal line 53, thereby electrically connecting the spare signal line 53 with the compensation signal line 63 at position C3. Since the compensation signal line 63 at both positions B3 and C3 is electrically connected to the spare signal line 53, the signal provided by the compensation signal line 63 on the X side of the second pixel unit M2 can be transmitted from the spare signal line 53 to the compensation signal line 63 of the first pixel unit M1, thereby enabling the repair of the compensation signal line 63 that has broken.

[0197] In an exemplary embodiment, Figure 15c In the process, the third spare connection electrode 63-1 at position B4 and the spare signal line 53 can be laser-drilled to achieve electrical connection between the spare signal line 53 and the compensation signal line 63 in the first pixel unit M1 where a break occurs; the third spare connection electrode 63-1 at position C4 and the spare signal line 53 can be laser-drilled to achieve electrical connection between the spare signal line 53 and the compensation signal line 63 in the second pixel unit M2.

[0198] Figure 15d As shown Figure 15cA cross-sectional structural diagram of the UU position in the middle, where Q is the position where the third backup connecting electrode 63-1 is electrically connected to the backup signal line 53 after melting following laser drilling.

[0199] In the embodiments of this disclosure, the first active layer can be the active layer of the first transistor, the second active layer can be the active layer of the second transistor, and the third active layer can be the active layer of the third transistor.

[0200] This disclosure also provides a method for fabricating a display substrate. The display substrate may include multiple pixel units arranged in an array, each pixel unit including multiple sub-pixels, and at least one sub-pixel including a driving circuit layer disposed on the substrate; the fabrication method includes:

[0201] A spare signal line is formed in the driving circuit layer, and a plurality of first signal lines are formed that are insulated from and cross each other with the spare signal line; the first signal line includes a spare connection electrode, and the orthographic projection of the spare connection electrode on the substrate and the orthographic projection of the spare signal line on the substrate have a first overlap area.

[0202] This disclosure also provides a method for repairing a display substrate. The display substrate includes multiple pixel units arranged in an array. Each pixel unit includes multiple sub-pixels. At least one sub-pixel includes a driving circuit layer disposed on a substrate. The driving circuit layer includes a spare signal line and multiple first signal lines that are insulated from and intersect with the spare signal line. The first signal line includes a spare connection electrode. The orthographic projection of the spare connection electrode on the substrate and the orthographic projection of the spare signal line on the substrate have a first overlap region. The repair method includes:

[0203] When any of the first signal lines is open-circuited, the spare signal line is connected to the spare connection electrode on the open-circuited first signal line, and the spare signal line is connected to the spare connection electrode on a first signal line that is not open-circuited. The first signal line that is not open-circuited and the first signal line that is open-circuited provide the same signal.

[0204] In an exemplary embodiment, the pixel unit containing the first signal line that is open-circuited and the pixel unit containing the first signal line that is not open-circuited contain the same spare signal line.

[0205] In an exemplary embodiment, the first signal line may include a data signal line, a first power supply line, and a compensation signal line, and the spare connection electrode may include a first spare connection electrode on the data signal line, a second spare connection electrode on the first power supply line, and a third spare connection electrode on the compensation signal line.

[0206] In an exemplary embodiment, the first power signal lines in different pixel units all provide power signals, which can be considered as the same type of signal. Similarly, the compensation signal lines in different pixel units all provide compensation signals, which can also be considered as the same type of signal. When a pixel unit includes four sub-pixels—a first sub-pixel p1, a second sub-pixel p2, a third sub-pixel p3, and a fourth sub-pixel p4—the four data signal lines providing data signals to the four sub-pixels p1 to p4 do not provide the same type of signal. In two pixel units, the two data signal lines providing data signals to the first sub-pixel p1 are considered the same type of signal. For example, the data signal line providing data signals to the first sub-pixel p1 in the first pixel unit and the data signal line providing data signals to the first sub-pixel p1 in the second pixel unit provide the same type of signal. In other words, data signal lines providing data signals to sub-pixels of different types provide different types of signals.

[0207] In an exemplary embodiment, when the first signal line that is open-circuited is a data signal line, for example, when the data signal line of the first sub-pixel p1 in the first pixel unit M1 is open-circuited, the first spare connection electrode on the data signal line that is open-circuited in the first pixel unit M1 is connected to the spare signal line, and the first spare connection electrode on the data signal line of the first sub-pixel p1 in the second pixel unit M2 is connected to the spare signal line, thereby enabling the data signal line of the first sub-pixel p1 in the second pixel unit M2 to provide the corresponding data signal to the first sub-pixel p1 in the first pixel unit M1.

[0208] In an exemplary embodiment, when the first signal line that is open-circuited is the first power line, for example, when the first power line in the first pixel unit M1 is open-circuited, the second spare connection electrode on the first power line in the first pixel unit M1 that is open-circuited is connected to the spare signal line, and the second spare connection electrode on the first power line in the second pixel unit M2 is connected to the spare signal line, thereby enabling the first power line in the second pixel unit M2 to provide a power signal to the sub-pixel in the first pixel unit M1.

[0209] In an exemplary embodiment, when the first signal line experiencing an open circuit is a compensation signal line, for example, when the compensation signal line in the first pixel unit M1 experiences an open circuit, the third spare connection electrode on the compensation signal line in the first pixel unit M1 that experienced an open circuit is connected to the spare signal line, and the third spare connection electrode on the compensation signal line in the second pixel unit M2 is also connected to the spare signal line, thereby enabling the compensation signal line in the second pixel unit M2 to provide a compensation signal to the corresponding sub-pixel in the first pixel unit M1. In another embodiment, when the first pixel unit M1 includes two compensation signal lines, and one of the compensation signal lines experiences an open circuit, the third spare connection electrode on the compensation signal line in the first pixel unit M1 that experienced an open circuit is connected to the compensation signal line, and the third spare connection electrode on the compensation signal line in the first pixel unit M1 that did not experience an open circuit is also connected to the compensation signal line, thereby enabling the compensation signal line that did not experience an open circuit to provide a compensation signal to the sub-pixel corresponding to the open circuit.

[0210] This disclosure also provides a display device, including the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0211] The display substrate, its fabrication method, repair method, and display device provided in this disclosure include a driving circuit layer in the display substrate with spare signal lines and multiple first signal lines that are insulated from and intersect with the spare signal lines. Each first signal line includes a spare connection electrode, and the orthographic projection of the spare connection electrode onto the substrate overlaps with the orthographic projection of the spare signal line onto the substrate in a first overlapping area. When any one of the first signal lines is open-circuited, the spare signal line is electrically connected to the spare connection electrode on the open-circuited first signal line, and the spare signal line is also electrically connected to the spare connection electrode on the unopened first signal line. This allows the signal from the unopened first signal line to be supplied to the open-circuited first signal line, overcoming the problem of low repair success rate in existing display substrates.

[0212] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, It includes multiple pixel units arranged in an array, each pixel unit includes multiple sub-pixels, at least one sub-pixel includes a driving circuit layer disposed on a substrate, the driving circuit layer includes a spare signal line and multiple first signal lines that are insulated from and cross the spare signal line; The first signal line includes a spare connection electrode, and the orthographic projection of the spare connection electrode on the substrate and the orthographic projection of the spare signal line on the substrate have a first overlap region; When any of the first signal lines is open-circuited, the spare signal line is connected to the spare connection electrode on the open-circuited first signal line to achieve electrical connection, and the spare signal line is connected to the spare connection electrode on the first signal line that is not open-circuited to achieve electrical connection, and the signal on the first signal line that is not open-circuited is provided to the first signal line that is open-circuited. A spare half-via is provided on the third insulating layer between the spare connection electrode and the spare signal line. The spare half-via is filled with the spare connection electrode. The orthogonal projection of the spare half-via on the substrate is located within the range of the first overlapping area. The spare half-via can accommodate more material of the spare connection electrode. When the first signal line with an open circuit is repaired by laser melting, the spare connection electrode can be well electrically connected to the spare signal line in the laser melting state.

2. The display substrate according to claim 1, characterized in that, The driving circuit layer of at least one sub-pixel includes a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer sequentially disposed on the substrate, wherein the spare signal line is located in the second conductive layer, and the plurality of first signal lines are located in the third conductive layer.

3. The display substrate according to any one of claims 1 to 2, characterized in that, Within the plane of the display substrate, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially along a first direction; the plurality of first signal lines include data signal lines; and the spare connection electrode includes a first spare connection electrode. The data signal lines are respectively disposed in each sub-pixel. The data signal line includes a main body portion and a first branch portion. The first branch portion includes a first spare connection electrode. The main body portion of the data signal line extends along a second direction. The first spare connection electrode in the first sub-pixel and the third sub-pixel extends in the opposite direction to the first direction. The first spare connection electrode in the second sub-pixel and the fourth sub-pixel extends along the first direction.

4. The display substrate according to any one of claims 1 to 2, characterized in that, Within the plane of the display substrate, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially along a first direction; the plurality of first signal lines include a first power line, and the spare connection electrode includes a second spare connection electrode; The first power line includes a main body and a branch portion. The branch portion of the first power line includes a second spare connection electrode. The main body of the first power line is disposed between the second sub-pixel and the third sub-pixel. The second spare connection electrode is located in the second sub-pixel and / or the third sub-pixel. The main body of the first power line extends along the second direction, the second spare connection electrode in the second sub-pixel extends in the opposite direction to the first direction, and the second spare connection electrode in the third sub-pixel extends along the first direction.

5. The display substrate according to any one of claims 1 to 2, characterized in that, Within the plane of the display substrate, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially along a first direction; the plurality of first signal lines include compensation signal lines, and the spare connection electrode includes a third spare connection electrode; The compensation signal lines are respectively disposed in the first sub-pixel and the fourth sub-pixel. The compensation signal line includes a main body portion and a branch portion. The branch portion of the compensation signal line includes the third spare connection electrode. The main body portion of the compensation signal line extends along a second direction. In the first sub-pixel, the third spare connection electrode extends along a first direction. In the fourth sub-pixel, the third spare connection electrode extends in the opposite direction to the first direction.

6. The display substrate according to any one of claims 1 to 2, characterized in that, The spare signal line is located in at least two pixel units.

7. The display substrate according to claim 2, characterized in that, In at least one sub-pixel, the driving circuit further includes a first transistor, a second transistor, and a third transistor; the active layers of the first transistor, the second transistor, and the third transistor are located in the semiconductor layer, the gate electrodes of the first transistor, the second transistor, and the third transistor are located in the second conductive layer, and the first and second electrodes of the first transistor, the second transistor, and the third transistor are located in the third conductive layer.

8. The display substrate according to claim 7, characterized in that, In at least one sub-pixel, the driving circuit further includes a masking layer located on the first conductive layer, wherein the orthographic projection of the active layer of the second transistor onto the substrate is within the range of the orthographic projection of the masking layer onto the substrate.

9. The display substrate according to claim 8, characterized in that, Within the plane of the display substrate, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially along a first direction; the shielding layer is multiplexed as a first electrode plate of a capacitor; the semiconductor layer includes a second electrode plate formed in each sub-pixel; The orthographic projection of the second electrode plate onto the substrate is within the range of the orthographic projection of the first electrode plate onto the substrate; the area of ​​the second electrode plate in the first sub-pixel and the third sub-pixel is larger than the area of ​​the second electrode plate in the second sub-pixel and the fourth sub-pixel.

10. The display substrate according to claim 9, characterized in that, The second conductive layer further includes a first scan signal line, a second scan signal line, and a second gate electrode; the first scan signal line, the second scan signal line, and the spare signal line are arranged along a second direction; The first scan signal line includes a main body and a branch. The main body is a strip structure extending along a first direction and located on the side of the second electrode plate away from the second scan signal line in a second direction. The branch extends along the second direction and includes a first gate electrode corresponding to each sub-pixel. The first gate electrode serves as the gate electrode of the first transistor. The orthographic projection of the first gate electrode on the substrate overlaps with the orthographic projection of the active layer of the first transistor on the substrate. The second scan signal line is a strip structure extending along the first direction. It is located on the side of the second electrode plate away from the first scan signal line in the second direction. The orthographic projection of the second scan signal line on the substrate overlaps with the orthographic projection of the active layer of the third transistor in each sub-pixel on the substrate. The second scan signal line in the overlapping area serves as the gate electrode of the third transistor. The second gate electrode serves as the gate electrode of the second transistor. The orthographic projection of the second gate electrode on the substrate and the orthographic projection of the active layer of the second transistor on the substrate have a second overlapping region. The second gate electrode, the second electrode of the first transistor, and the orthographic projection of the active layer of the first transistor on the substrate have a third overlapping region.

11. The display substrate according to claim 7, characterized in that, The first signal line includes a data signal line, which is respectively disposed in each sub-pixel. The data signal line includes a main body portion and a second branch portion. The main body portion of the data signal line extends along a second direction. The second branch portion in the first sub-pixel and the third sub-pixel extends in the opposite direction to the first direction, and the second branch portion in the second sub-pixel and the fourth sub-pixel extends along the first direction. The second branch portion is the first electrode of the first transistor.

12. A method for preparing a display substrate, characterized in that, The display substrate includes multiple pixel units arranged in an array, each pixel unit including multiple sub-pixels, and at least one sub-pixel including a driving circuit layer disposed on the substrate; the fabrication method includes: A backup signal line and a plurality of first signal lines that are insulated from and intersect with the backup signal line are formed in the driving circuit layer. The first signal line includes a backup connection electrode, and the orthographic projection of the backup connection electrode on the substrate and the orthographic projection of the backup signal line on the substrate have a first overlap area. When any first signal line is broken, the backup signal line is electrically connected to the backup connection electrode on the broken first signal line, and the backup signal line is electrically connected to the backup connection electrode of the unbroken first signal line, so that the signal on the unbroken first signal line is provided to the broken first signal line. A backup half-via is provided on the third insulating layer between the backup connection electrode and the backup signal line. The backup half-via is filled with the backup connection electrode, and the orthographic projection of the backup half-via on the substrate is located within the first overlap area. The backup half-via can accommodate more material of the backup connection electrode. When the broken first signal line is repaired by laser melting, the backup connection electrode can be well electrically connected to the backup signal line in the laser melting state.

13. A method for repairing a display substrate, characterized in that, The display substrate includes a plurality of pixel units arranged in an array, each pixel unit including a plurality of sub-pixels, at least one sub-pixel including a driving circuit layer disposed on the substrate, the driving circuit layer including a spare signal line and a plurality of first signal lines that are insulated from and intersect the spare signal line; the first signal line includes a spare connection electrode, the orthographic projection of the spare connection electrode on the substrate and the orthographic projection of the spare signal line on the substrate having a first overlap region, a spare half via is provided on a third insulating layer between the spare connection electrode and the spare signal line, the spare half via is filled with the spare connection electrode, and the orthographic projection of the spare half via on the substrate is located within the first overlap region; The repair method includes: When any of the first signal lines is open-circuited, the backup signal line is connected to the backup connection electrode on the open-circuited first signal line by laser melting, and the backup signal line is also connected to the backup connection electrode on a first signal line that is not open-circuited by laser melting. The first signal line that is not open-circuited and the first signal line that is open-circuited provide the same signal. The backup half-via can accommodate more material of the backup connection electrode. The open-circuited first signal line is repaired by laser melting. In the laser melting state, the backup connection electrode can be well electrically connected to the backup signal line.

14. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 11.

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