Level conversion circuit and chip

Abstract

The present disclosure relates to a level conversion circuit and a chip. The level conversion circuit comprises a voltage domain detection circuit, a first logic circuit and a second logic circuit. The voltage domain detection circuit detects whether a first domain voltage provided by a first domain voltage terminal is a zero domain voltage. If yes, a first control signal is output. If no, a second control signal is output. The first logic circuit is turned off in response to the first control signal. In response to the second control signal, a first level is received from a level input terminal and a first logic level is output in response to the first domain voltage. The second logic circuit outputs a second logic level in response to the first control signal according to a second domain voltage provided by a second domain voltage terminal. In response to the second control signal, the first logic level is received and a third logic level is output in response to the second domain voltage. The level conversion circuit not only avoids circuit damage caused by level mismatch, but also reduces the power consumption of the integrated circuit.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and in particular to a level conversion circuit and chip. Background Technology

[0002] In the field of integrated circuits, with the introduction of low-voltage logic, input / output logic level mismatches frequently occur in systems. These mismatches can easily lead to communication failures between different voltage domains, and even damage to the chip. To solve this problem, level conversion circuits are needed. As the demand for different voltage domains in integrated circuits increases, the necessity for research on logic level conversion circuits becomes even more prominent.

[0003] However, in practical applications of integrated circuits, when the input voltage domain drops to zero volts, the output voltage domain is not turned off, which leads to increased power consumption of the integrated circuit, hinders the development of low-power circuits, and results in a waste of resources.

[0004] Therefore, how to improve level conversion circuits to reduce the power consumption of integrated circuits is an urgent problem to be solved. Summary of the Invention

[0005] Therefore, it is necessary to provide a level conversion circuit and chip to effectively reduce the power consumption of integrated circuits.

[0006] This application provides a level conversion circuit, including: a voltage domain detection circuit, a first logic circuit, and a second logic circuit; wherein, the voltage domain detection circuit is connected to a first domain voltage terminal and is configured to: detect whether the first domain voltage provided by the first domain voltage terminal is a zero domain voltage; if yes, output a first control signal; if no, output a second control signal; the first logic circuit is connected to a level input terminal, the first domain voltage terminal, and the voltage domain detection circuit respectively, and is configured to: turn off in response to the first control signal; and, in response to the second control signal, receive a first level provided by the level input terminal and output a first logic level in response to the first domain voltage; the second logic circuit is connected to a second domain voltage terminal, the first logic circuit, and the voltage domain detection circuit respectively, and is configured to: output a second logic level in response to the first control signal based on the second domain voltage provided by the second domain voltage terminal; and, in response to the second control signal, receive the first logic level and output a third logic level in response to the second domain voltage.

[0007] In the aforementioned level conversion circuit, the voltage domain detection circuit is connected to the first domain voltage terminal, which can detect whether the first domain voltage provided by the first domain voltage terminal is zero. When the first domain voltage provided by the first domain voltage terminal is zero, the voltage domain detection circuit can control the first logic circuit to turn off and control the second logic circuit to output a second logic level according to the second domain voltage provided by the second domain voltage terminal, thereby reducing power consumption. Simultaneously, by detecting the first domain voltage provided by the first domain voltage terminal through the voltage domain detection circuit, the level conversion circuit ensures that the second logic circuit can respond to the second domain voltage terminal and output the corresponding logic level regardless of whether the first domain voltage value is zero, thus ensuring the normal operation of the second logic circuit. This not only avoids circuit damage caused by level mismatch within the chip but also effectively reduces chip power consumption.

[0008] Optionally, the first logic level is the inverted level of the first logic level; the third logic level is the inverted level of the first logic level.

[0009] Optionally, the level conversion circuit further includes a latching circuit; the latching circuit is connected to the first logic circuit, the second logic circuit, and the voltage domain detection circuit respectively, and is configured to: latch the first level and the first logic level; and, in response to the first control signal, turn off; and in response to the second control signal, output the first logic level to the second logic circuit.

[0010] In the aforementioned level conversion circuit, when the voltage value of the first domain provided by the first domain voltage terminal is zero, the first control signal output by the voltage domain detection circuit can also control the latch circuit to shut down without affecting the operation of the second logic circuit, so as to further reduce the power consumption of the chip.

[0011] Optionally, the latch circuit is also connected to the second domain voltage terminal and is configured to latch the first logic level in response to the second domain voltage.

[0012] In the above level conversion circuit, the latch circuit is connected to the first logic circuit, the second logic circuit, and the voltage domain detection circuit respectively, and latches the first logic level in response to the second domain voltage. It can convert the level difference between the first logic circuit and the second logic circuit while latching and transmitting the first logic level, thereby ensuring the stability and reliability of the output result of the second logic circuit.

[0013] Optionally, the first logic circuit includes: a first transistor, a second transistor, and a third transistor; each of the first transistor, the second transistor, and the third transistor includes a gate, a source, and a drain; the gate of the first transistor is connected to the gate of the second transistor and a latching circuit; the source of the first transistor is connected to a first domain voltage terminal and a voltage domain detection circuit; the drain of the first transistor is connected to the drain of the third transistor and a latching circuit; the drain of the second transistor is connected to the source of the third transistor; the source of the second transistor is connected to a ground voltage terminal; and the gate of the third transistor is connected to the voltage domain detection circuit.

[0014] Optionally, the voltage domain detection circuit includes: a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, each of which includes a gate, a source, and a drain; the gate and drain of the fourth transistor are connected to the first logic circuit, the gate and drain of the fifth transistor, the gate of the sixth transistor, and the gate of the seventh transistor; the source of the fourth transistor is connected to both the first domain voltage terminal and the first logic circuit; the source of the fifth transistor is connected to the ground voltage terminal; the source of the sixth transistor is connected to the latch circuit; the drain of the sixth transistor is connected to both the drain of the seventh transistor and the second logic circuit; the gate of the sixth transistor is connected to the second domain voltage terminal; and the source of the seventh transistor is connected to the ground voltage terminal.

[0015] Optionally, the latching circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor, each of which includes a gate, a source, and a drain; the gate of the eighth transistor is connected to the drain of the tenth transistor, the second logic circuit, and the drain of the eleventh transistor; the source of the eighth transistor and the source of the tenth transistor are both connected to the second domain voltage terminal; the drain of the eighth transistor is connected to the gate of the tenth transistor and the drain of the ninth transistor; the gate of the ninth transistor is connected to the drain of the first transistor and the drain of the third transistor; the source of the ninth transistor is connected to the ground voltage terminal; the gate of the eleventh transistor is connected to the gate of the first transistor and the gate of the second transistor; and the source of the eleventh transistor is connected to the ground voltage terminal.

[0016] Optionally, the second logic circuit includes: a twelfth transistor, a thirteenth transistor, and a fourteenth transistor, each of which includes a gate, a source, and a drain; the gate of the twelfth transistor is connected to a voltage domain detection circuit, and the drain of the twelfth transistor is connected to the gate of the eighth transistor, the drain of the eleventh transistor, the gate of the thirteenth transistor, and the gate of the fourteenth transistor; the source of the twelfth transistor is connected to a ground voltage terminal; the source of the thirteenth transistor is connected to a second domain voltage terminal, and the drain of the thirteenth transistor is connected to the drain of the fourteenth transistor; the source of the fourteenth transistor is connected to a ground voltage terminal.

[0017] Optionally, the first transistor, the fourth transistor, the sixth transistor, the eighth transistor, the tenth transistor, and the thirteenth transistor are all PMOS transistors; the second transistor, the fifth transistor, the seventh transistor, the ninth transistor, the eleventh transistor, the twelfth transistor, and the fourteenth transistor are all NMOS transistors.

[0018] Based on the same inventive concept, this application also provides a chip. The chip includes a level conversion circuit employing any of the foregoing solutions.

[0019] The chip in this embodiment employs a level conversion circuit with a zero-volt voltage domain detection circuit, which can prevent circuit damage caused by level mismatch within the chip. Furthermore, the voltage domain detection circuit can control the first logic circuit and latch circuit to shut down when the first domain voltage value is zero, thereby reducing the chip's power consumption and effectively improving its performance. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a block diagram of a level conversion circuit provided in one embodiment;

[0022] Figure 2 This is a block diagram of another level conversion circuit provided in one embodiment;

[0023] Figure 3 This is a circuit diagram of a level conversion circuit provided in one embodiment.

[0024] Explanation of reference numerals in the attached figures:

[0025] 10 - First logic circuit; 20 - Voltage domain detection circuit; 30 - Second logic circuit; 40 - Latch circuit;

[0026] IN - Level input terminal; OUT - Level input terminal / Third logic level; VDDA - First domain voltage terminal;

[0027] VDDB - Second domain voltage terminal; VSS - Grounding voltage terminal;

[0028] M1 - First transistor; M2 - Second transistor; M3 - Third transistor; M4 - Fourth transistor;

[0029] M5 - Fifth transistor; M6 - Sixth transistor; M7 - Seventh transistor; M8 - Eighth transistor;

[0030] M9 - Ninth transistor; M10 - Tenth transistor; M11 - Eleventh transistor;

[0031] M12 - Twelfth transistor; M13 - Thirteenth transistor; M14 - Fourteenth transistor. Detailed Implementation

[0032] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0034] The term "embodiment" in this document means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0035] It is understood that the terms "first," "second," "third," "fourth," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first transistor may be referred to as a second transistor, and similarly, a second transistor may be referred to as a first transistor. Both the first transistor and the second transistor are transistors, but they are not the same transistor.

[0036] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0037] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0038] In the field of integrated circuits, with the introduction of low-voltage logic, input / output logic level mismatches frequently occur in systems. These mismatches can easily lead to communication failures between different voltage domains, and even damage the chip. To solve this problem, level conversion circuits are needed. As the demand for different voltage domains in integrated circuits increases, the necessity for research on logic level conversion circuits becomes even more prominent.

[0039] However, in practical applications of integrated circuits, when the input voltage domain drops to zero volts, the output voltage domain is not turned off, which leads to increased power consumption of the integrated circuit, hinders the development of low-power circuits, and results in a waste of resources.

[0040] Therefore, how to improve level conversion circuits to reduce the power consumption of integrated circuits is an urgent problem to be solved.

[0041] In view of the shortcomings of the prior art, the purpose of this application is to provide a level conversion circuit and chip to effectively reduce the power consumption of integrated circuits.

[0042] Please see Figure 1This application provides a level conversion circuit, including: a voltage domain detection circuit 10, a first logic circuit 20, and a second logic circuit 30; wherein, the voltage domain detection circuit 10 is connected to the first domain voltage terminal VDDA and is configured to: detect whether the first domain voltage provided by the first domain voltage terminal VDDA is a zero domain voltage; if yes, output a first control signal; if no, output a second control signal; the first logic circuit 20 is connected to the level input terminal IN, the first domain voltage terminal VDDA, and the voltage domain detection circuit 10 respectively, and is configured to: turn off in response to the first control signal; and, in response to the second control signal, receive a first level provided by the level input terminal IN and output a first logic level in response to the first domain voltage; the second logic circuit 30 is connected to the second domain voltage terminal VDDB, the first logic circuit 20, and the voltage domain detection circuit 10 respectively, and is configured to: output a second logic level in response to the first control signal according to the second domain voltage provided by the second domain voltage terminal VDDB; and, in response to the second control signal, receive the first logic level and output a third logic level in response to the second domain voltage.

[0043] In the aforementioned level conversion circuit, the voltage domain detection circuit 10 is connected to the first domain voltage terminal VDDA, and can detect whether the first domain voltage provided by the first domain voltage terminal VDDA is zero. Thus, when the first domain voltage provided by the first domain voltage terminal VDDA is zero, the voltage domain detection circuit 10 can control the first logic circuit 20 to turn off and control the second logic circuit 30 to output a second logic level according to the second domain voltage provided by the second domain voltage terminal VDDB, thereby reducing power consumption. Simultaneously, by detecting the first domain voltage provided by the first domain voltage terminal VDDA through the voltage domain detection circuit 10, the level conversion circuit ensures that the second logic circuit 30 can respond to the second domain voltage terminal VDDB and output the corresponding logic level regardless of whether the first domain voltage value is zero, thus ensuring that the second logic circuit 30 can operate normally. This not only avoids circuit damage caused by level mismatch within the chip but also effectively reduces chip power consumption.

[0044] In some examples, the first logic level is the inverted level of the first logic level; the third logic level is the inverted level of the first logic level. For example, if the first logic level is high (logic 1), then the first logic level is low (logic 0), and the third logic level is high (logic 1).

[0045] Please see Figure 2 In some examples, the level conversion circuit further includes a latch circuit 40; the latch circuit 40 is connected to the first logic circuit 20, the second logic circuit 30 and the voltage domain detection circuit 10 respectively, and is configured to: latch a first level and a first logic level; and, in response to a first control signal, turn off; and in response to a second control signal, output the first logic level to the second logic circuit.

[0046] In the above-mentioned level conversion circuit, when the first domain voltage value provided by the first domain voltage terminal VDDA is zero, the first control signal output by the voltage domain detection circuit 10 can also control the latch circuit 40 to be turned off without affecting the operation of the second logic circuit 30, so as to further reduce the power consumption of the chip.

[0047] For example, latch circuit 40 can latch the first logic level (logic 1) provided by the level input terminal IN and the first logic level (logic 0) output by the first logic circuit 20. When the first domain voltage provided by the first domain voltage terminal VDDA is zero, voltage domain detection circuit 10 outputs a first control signal, and latch circuit 40 can turn off in response to the first control signal, thereby reducing power consumption. When the first domain voltage provided by the first domain voltage terminal VDDA is not zero, voltage domain detection circuit 10 outputs a second control signal, and latch circuit 40 responds to the second control signal by outputting the first logic level (logic 0) to the second logic circuit 30. The first logic level (logic 0) is then output as an inverse third logic level (logic 1) by the second logic circuit 30.

[0048] In some examples, latch circuit 40 is also connected to the second domain voltage terminal VDDB and is configured to latch the first logic level in response to the second domain voltage.

[0049] In the above level conversion circuit, the latch circuit 40 is connected to the first logic circuit 20, the second logic circuit 30 and the voltage domain detection circuit 10 respectively, and latches the first logic level in response to the second domain voltage. It can convert the level difference between the first logic circuit 20 and the second logic circuit 30 while latching and transmitting the first logic level, thereby ensuring the stability and reliability of the output result of the second logic circuit 30.

[0050] In some of the above embodiments, the first logic circuit 20, the voltage domain detection circuit 10, the second logic circuit 30, and the latch circuit 40 can be designed differently to match their respective functions. This disclosure provides some possible implementation methods exemplarily.

[0051] Please see Figure 3In some examples, the first logic circuit 20 includes: a first transistor M1, a second transistor M2, and a third transistor M3; each of the first transistor M1, the second transistor M2, and the third transistor M3 includes a gate, a source, and a drain; the gate of the first transistor M1 is connected to the gate of the second transistor M2 and a latching circuit; the source of the first transistor M1 is connected to the first domain voltage terminal VDDA and the voltage domain detection circuit 10; the drain of the first transistor M1 is connected to the drain of the third transistor M3 and a latching circuit; the drain of the second transistor M2 is connected to the source of the third transistor M3; the source of the second transistor M2 is connected to the ground voltage terminal; and the gate of the third transistor M3 is connected to the voltage domain detection circuit.

[0052] In some examples, the voltage domain detection circuit includes: a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. Each of the fourth transistor M4, fifth transistor M5, sixth transistor M6, and seventh transistor M7 includes a gate, a source, and a drain. The gate and drain of the fourth transistor M4 are connected to the first logic circuit 20, the gate and drain of the fifth transistor M5, the gate of the sixth transistor M6, and the gate of the seventh transistor M7. The source of the fourth transistor M4 is connected to the first domain voltage terminal VDDA and the first logic circuit 20. The source of the fifth transistor M5 is connected to the ground voltage terminal. The source of the sixth transistor M6 is connected to the latch circuit. The drain of the sixth transistor M6 is connected to the drain of the seventh transistor M7 and the second logic circuit. The gate of the sixth transistor M6 is connected to the second domain voltage terminal VDDB. The source of the seventh transistor M7 is connected to the ground voltage terminal.

[0053] In one optional embodiment, the gate and drain of the fourth transistor M4 are both connected to the first logic circuit 20, the gate and drain of the fifth transistor M5, the gate of the sixth transistor M6 and the gate of the seventh transistor M7, including: the gate and drain of the fourth transistor M4 are both connected to the gate of the third transistor M3, the gate and drain of the fifth transistor M5, the gate of the sixth transistor M6 and the gate of the seventh transistor M7.

[0054] In one optional embodiment, the source of the fourth transistor M4 is connected to both the first domain voltage terminal VDDA and the first logic circuit 20, including: the source of the fourth transistor M4 is connected to both the first domain voltage terminal VDDA and the drain of the second transistor M2.

[0055] In some examples, the latching circuit includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11. Each of the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 includes a gate, a source, and a drain. The gate of the eighth transistor M8 is connected to the drain of the tenth transistor M10, the second logic circuit, and the drain of the eleventh transistor M11. The sources of the eighth transistor M8 and the tenth transistor M10 are both connected to the second domain voltage terminal VDDB. The drain of the eighth transistor M8 is connected to the gate of the tenth transistor M10 and the drain of the ninth transistor M9. The gates of the ninth transistor M9 and the eleventh transistor M11 are respectively connected to the first logic circuit 20. The sources of the ninth transistor M9 and the eleventh transistor M11 are both connected to the ground voltage terminal.

[0056] In one optional embodiment, the source of the eighth transistor M8 and the source of the tenth transistor M10 are both connected to the second domain voltage terminal VDDB, including: the source of the eighth transistor M8 is connected to the source of the sixth transistor M6 and the source of the tenth transistor M10 are both connected to the second domain voltage terminal VDDB.

[0057] In one optional embodiment, the gate of the ninth transistor M9 and the gate of the eleventh transistor M11 are respectively connected to the first logic circuit 20, including: the gate of the ninth transistor M9 is connected to the drain of the first transistor M1 and the drain of the third transistor M3.

[0058] In some examples, the second logic circuit includes: a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14, each of which includes a gate, a source, and a drain; the gate of the twelfth transistor M12 is connected to the voltage domain detection circuit 10, and the drain of the twelfth transistor M12 is connected to the gate of the eighth transistor M8, the drain of the eleventh transistor M11, the gate of the thirteenth transistor M13, and the gate of the fourteenth transistor M14; the source of the twelfth transistor M12 is connected to the ground voltage terminal; the source of the thirteenth transistor M13 is connected to the second domain voltage terminal VDDB, and the drain of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14; the source of the fourteenth transistor M14 is connected to the ground voltage terminal.

[0059] In one alternative embodiment, the gate of the twelfth transistor M12 is connected to the voltage domain detection circuit 10, including: the gate of the twelfth transistor M12 is connected to the drain of the sixth transistor M6 and the drain of the seventh transistor M7.

[0060] In one optional embodiment, the drain of the twelfth transistor M12 is connected to the gate of the eighth transistor M8 and the drain of the latch circuit 40, the drain of the eleventh transistor M11, the gate of the thirteenth transistor M13, and the gate of the fourteenth transistor M14, including: the drain of the twelfth transistor M12 and the gate of the eighth transistor M8 are connected to the drain of the tenth transistor M10, the drain of the eleventh transistor M11, the gate of the thirteenth transistor M13, and the gate of the fourteenth transistor M14.

[0061] In one optional embodiment, the source of the thirteenth transistor M13 is connected to the second domain voltage terminal VDDB, including: the source of the thirteenth transistor M13 is connected to the source of the tenth transistor M10, the source of the eighth transistor M8, and the source of the sixth transistor M6.

[0062] Specifically, when the first domain voltage provided by the first domain voltage terminal VDDA is a non-zero volt voltage, the voltage domain detection circuit 10 outputs a second control signal. The first logic circuit 20 responds to the second control signal, with the third transistor M3 entering the deep linear region and the twelfth transistor M12 entering the cutoff region. This causes the first level (logic 1) input at the level input terminal IN to be processed by the first logic circuit 20 to output a first logic level (logic 0). Its maximum voltage is the first domain voltage provided by the first domain voltage terminal VDDA, and its minimum voltage is the ground voltage provided by the ground voltage terminal VSS. The latch circuit 40 latches the first level (logic 1) provided by the level input terminal IN and the first logic level (logic 0) output by the first logic circuit 20, and outputs the first logic level (logic 0) to the second logic circuit 30. The second logic circuit 30 receives the first logic level (logic 0) and responds to the second domain voltage to output a third logic level (logic 1). Its maximum voltage is the second domain voltage provided by the second domain voltage terminal VDDB, and its minimum voltage is the ground voltage provided by the ground voltage terminal VSS. This completes the level conversion from the first domain voltage provided by the first domain voltage terminal VDDA to the second domain voltage provided by the second domain voltage terminal VDDB.

[0063] When the voltage provided by the first domain voltage terminal VDDA is zero volts, the voltage domain detection circuit 10 outputs a first control signal. The first logic circuit 20 responds to the first control signal by turning off, and the third transistor M3 enters the cutoff region. The latch circuit 40 responds to the first control signal by turning off, and both the first logic circuit 20 and the latch circuit 40 stop working to reduce power consumption. The second logic circuit 40 responds to the first control signal, and the twelfth transistor M12 turns on, entering the deep linear region. The second logic circuit 40 outputs a second logic level (logic 1) based on the second domain voltage provided by the second domain voltage terminal VDDB. The second logic level (logic 1) is a fixed level.

[0064] Optionally, the first transistor M1, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the tenth transistor M10 and the thirteenth transistor M13 are all PMOS transistors; the second transistor M2, the fifth transistor M5, the seventh transistor M7, the ninth transistor M9, the eleventh transistor M11, the twelfth transistor M12 and the fourteenth transistor M14 are all NMOS transistors.

[0065] Based on the same inventive concept, this application also provides a chip. The chip includes a level conversion circuit employing any of the foregoing solutions.

[0066] The chip in this embodiment employs a level conversion circuit with a zero-volt voltage domain detection circuit 10, which can prevent circuit damage caused by level mismatch within the chip. Furthermore, the voltage domain detection circuit 10 can also control the first logic circuit 20 and the latch circuit 40 to shut down when the first domain voltage value is zero, thereby reducing the chip's power consumption and effectively improving its performance.

[0067] In the description of this specification, the technical features of the above-described embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0068] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A level conversion circuit, characterized in that, include: Voltage domain detection circuit, first logic circuit, and second logic circuit; wherein, The voltage domain detection circuit is connected to the first domain voltage terminal and is configured to: detect whether the first domain voltage provided by the first domain voltage terminal is a zero domain voltage; if yes, output a first control signal; if no, output a second control signal. The first logic circuit is connected to the level input terminal, the first domain voltage terminal, and the voltage domain detection circuit respectively, and is configured to: turn off in response to the first control signal; and, in response to the second control signal, receive the first level provided by the level input terminal, and output the first logic level in response to the first domain voltage. The second logic circuit is connected to the second domain voltage terminal and the voltage domain detection circuit respectively, and is configured to: output a second logic level according to the second domain voltage provided by the second domain voltage terminal in response to the first control signal; and receive the first logic level and output a third logic level in response to the second domain voltage in response to the second control signal. The level conversion circuit also includes a latch circuit; The latching circuit is connected to the first logic circuit, the second logic circuit, and the voltage domain detection circuit respectively, and is configured to: latch the first level and the first logic level; and, in response to the first control signal, turn off; and in response to the second control signal, output the first logic level to the second logic circuit. The voltage domain detection circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, each of which includes a gate, a source, and a drain. The gate and drain of the fourth transistor are connected to the first logic circuit, the gate and drain of the fifth transistor, the gate of the sixth transistor and the gate of the seventh transistor, and the source of the fourth transistor is connected to the first domain voltage terminal and the first logic circuit. The source of the fifth transistor is connected to the ground voltage terminal; The source of the sixth transistor is connected to the latch circuit, and the drain of the sixth transistor is connected to the drain of the seventh transistor and the second logic circuit; the gate of the sixth transistor is connected to the second domain voltage terminal. The source of the seventh transistor is connected to the ground voltage terminal.

2. The level conversion circuit as described in claim 1, characterized in that, The first logic level is the inverted level of the first level; The third logic level is the inverted level of the first logic level.

3. The level conversion circuit as described in claim 1, characterized in that, The latching circuit is also connected to the second domain voltage terminal and is configured to latch the first logic level in response to the second domain voltage.

4. The level conversion circuit as described in claim 1, characterized in that, The first logic circuit includes: a first transistor, a second transistor, and a third transistor; the first transistor, the second transistor, and the third transistor each include a gate, a source, and a drain. The gate of the first transistor is connected to the gate of the second transistor and the level input terminal. The source of the first transistor is connected to the first domain voltage terminal and the voltage domain detection circuit. The drain of the first transistor is connected to the drain of the third transistor and the latch circuit. The drain of the second transistor is connected to the source of the third transistor, and the source of the second transistor is connected to the ground voltage terminal. The gate of the third transistor is connected to the voltage domain detection circuit.

5. The level conversion circuit as described in claim 1, characterized in that, The latching circuit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor, wherein each of the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor includes a gate, a source, and a drain. The gate of the eighth transistor is connected to the drain of the tenth transistor, the second logic circuit, and the drain of the eleventh transistor. The source of the eighth transistor and the source of the tenth transistor are both connected to the second domain voltage terminal. The drain of the eighth transistor is connected to the gate of the tenth transistor and the drain of the ninth transistor. The gates of the ninth transistor and the eleventh transistor are respectively connected to the first logic circuit, and the sources of the ninth transistor and the eleventh transistor are both connected to the ground voltage terminal.

6. The level conversion circuit as described in claim 5, characterized in that, The second logic circuit includes: a twelfth transistor, a thirteenth transistor, and a fourteenth transistor, each of which includes a gate, a source, and a drain; The gate of the twelfth transistor is connected to the voltage domain detection circuit, the drain of the twelfth transistor is connected to the latch circuit, the drain of the eleventh transistor, the gate of the thirteenth transistor and the gate of the fourteenth transistor, and the source of the twelfth transistor is connected to the ground voltage terminal. The source of the thirteenth transistor is connected to the second domain voltage terminal, and the drain of the thirteenth transistor is connected to the drain of the fourteenth transistor. The source of the fourteenth transistor is connected to the ground voltage terminal.

7. The level conversion circuit as described in claim 4, characterized in that, The first transistor, the fourth transistor, and the sixth transistor are PMOS transistors; the second transistor, the fifth transistor, and the seventh transistor are all NMOS transistors.

8. The level conversion circuit as described in claim 5, characterized in that, The eighth and tenth transistors are both PMOS transistors; the ninth and eleventh transistors are both NMOS transistors.

9. The level conversion circuit as described in claim 6, characterized in that, The thirteenth transistor is a PMOS transistor; the twelfth and fourteenth transistors are both NMOS transistors.

10. A chip, characterized in that, Includes the level conversion circuit as described in any one of claims 1 to 9.

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