A dedicated sequential data selector, implementation method, electronic device and medium

Abstract

The present invention relates to the technical field of data selectors, and discloses a dedicated sequential data selector, including: an m-stage circuit, which is composed of a trigger conversion circuit and a merging circuit connected in series in sequence. There is one trigger conversion circuit, and (m - 1) merging circuits, and the (m - 1) merging circuits are connected in series. The trigger conversion circuit includes one trigger signal channel and n data channels, where n = 2<supgt;m - 1< / supgt>, and m is a positive integer not less than 2; the present invention also discloses a method for implementing the above dedicated sequential data selector, and the present invention also discloses an electronic device and a storage medium. In the digital IC technical fields such as FPGA, CPLD, semi-custom, and full-custom ASIC, in certain dedicated scenarios (the number of channels is known, each channel is only selected once, and the selection is made in sequence), the performance of the selector can be greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data selectors, and particularly relates to a dedicated sequential data selector, an implementation method, an electronic device, and a medium. Background Art

[0002] A data selector refers to a circuit that selects a specified one from a group of input signals according to the requirements of an address signal and delivers it to the output terminal through a transmission channel.

[0003] Traditional data selectors are implemented through a large number of combinational circuits. As shown in Figure 1 which is a schematic diagram of a traditional data selector, there are multiple-channel data input interfaces (i_data(1), i_data(2), i_data(3) …… i_data(n)), a channel selection input interface (i_sel), and a channel output interface (o_data). All input data channels are connected to the output channel through a selection switch, and the selection switch is controlled by i_sel. The output channel outputs the channel signal selected by the current selection switch. The implementation method is a pure combinational logic circuit. Common selector models include: four-to-one data selector (74ls153), eight-to-one data selector (74151). Currently, the scheme for implementing a multi-channel data selector is usually constructed by multiple low-channel data selectors. For example, two four-channel selectors are used to construct a sixteen-channel selector, and two eight-channel selectors are used to construct a sixty-four-channel selector, etc. Although a multi-channel data selector can be constructed by multiple low-channel data selectors, after all, low-channel data selectors are implemented through combinational circuits. The larger the scale of the combinational circuit, the higher the complexity, and the worse the final implementation effect will be. Therefore, the traditional combinational circuit implementation method is not suitable for high-speed, multi-channel data selectors. If the speed is too fast, the internal combinational circuit cannot respond in time, resulting in data errors; if the number of data channels is too large, it will greatly increase the complexity of the internal circuit, further increasing the complexity of the internal combinational circuit, thereby increasing the wiring difficulty inside, ultimately resulting in an increase in wiring delay and further reducing the processing speed. Selectors in special cases need to meet the following conditions: ① continuous data output; ② the number of data channels is known and is n, where n = 2 m-1 to the power of m (m is a positive integer not less than 2); ③ each channel is only selected once and is output sequentially in the order of the channels. Summary of the Invention

[0004] The present invention provides a dedicated sequential data selector, an implementation method, an electronic device, and a medium, which improve the performance of selectors in special cases, thereby solving the data selection problem in the case of large amounts of data (multiple channels) for selectors in special cases.

[0005] The present invention is achieved through the following technical solutions:

[0006] A dedicated sequential data selector, comprising:

[0007] An m-stage circuit, where the m-stage circuit consists of a trigger conversion circuit and a merging circuit connected in series in sequence. There is one trigger conversion circuit and (m - 1) merging circuits, and the (m - 1) merging circuits are connected in series. The trigger conversion circuit includes one trigger signal channel and n data channels, where n = 2 m-1 , and m is a positive integer not less than 2; the trigger signal channel includes one trigger signal input interface, the n data channels include n data input interfaces, and the trigger signal channel and the n data channels together have n data output interfaces and n valid identification output interfaces. The merging circuit is used to combine the data signals transmitted from the previous-stage circuit in pairs into a new data signal and use this new data signal as the data signal transmitted to the merging circuit of the next stage. At the same time, the merging circuit is also used to combine the valid identification signals transmitted from the previous-stage circuit in pairs into a new valid identification signal and use this new valid identification signal as the valid identification signal transmitted to the merging circuit of the next stage.

[0008] As an optimization, the trigger signal channel includes a first register, a second register, a NOT gate circuit, an AND gate circuit, and n third registers. There are n third registers. The first register is the trigger signal input interface. The output end of the first register is connected through the series connection of the second register and the NOT gate circuit. The output end of the first register is also connected to one input end of the AND gate circuit. The output end of the NOT gate circuit is connected to the other input end of the AND gate circuit. The output end of the AND gate circuit is connected to the input end of the first of the n third registers. The n third registers are connected in series, and the signals output by the n third registers are respectively used as the valid identification signals output by the corresponding n valid identification output channels;

[0009] Each of the n data channels respectively includes a fourth register, and each of the fourth registers is respectively connected to a D flip-flop. The fourth register is a data input interface. The data input terminal of the D flip-flop connected to the first fourth register receives the data signal output by the corresponding fourth register. The enable terminal of the D flip-flop connected to the first fourth register receives the output data of the AND gate circuit. The data input terminal of the D flip-flop connected to the (n′-i)-th fourth register receives the data signal output by the corresponding fourth register. The enable terminal of the D flip-flop connected to the (n′-i)-th fourth register receives the valid identification signal output by the (n′-i-1)-th third register, where i ∈ [0, n′-2], n′ is a power of 2 not less than 4. The signals output by the n D flip-flops respectively serve as the data signals output by the corresponding n data output channels.

[0010] As an optimization, the merging circuit includes several groups of screening circuits composed of OR gate circuits and multiplexers. The number of the screening circuits is one-half of the valid output signals transmitted from the previous-stage circuit, or is the valid identification signal transmitted from the previous-stage circuit. The two input terminals of the OR gate circuit respectively receive two adjacent valid identification signals transmitted from the previous-stage circuit, and the output terminal of the OR gate circuit outputs one of the received valid identification signals. The two input terminals of the multiplexer respectively receive two adjacent data signals transmitted from the previous-stage circuit. The selection terminal of the multiplexer receives one of the input signals of the OR gate circuit. The output terminal of the multiplexer selects the corresponding data signal for output according to the signal received by the selection terminal.

[0011] As an optimization, the NOT gate circuit is effective when the input is low level and effective when the output is high level.

[0012] As an optimization, the multiplexer is a signal selector, and the model of the signal selector is YR9033A.

[0013] The present invention also discloses an implementation method of a dedicated sequential data selector as described above, including the following steps:

[0014] S1. The trigger conversion circuit receives a trigger signal and n data signals, and converts them into n valid identification signals and n data signals according to the trigger signal and the n data signals.

[0015] S2. The merging circuit receives the valid identification signals and data signals transmitted from the previous-stage circuit, and respectively combines the transmitted valid identification signals and data signals in pairs into a new valid identification signal and data signal, and uses the new valid identification signal and data signal as the valid identification signal and data signal transmitted to the merging circuit of the next stage until finally one valid identification signal and data signal are output.

[0016] As an optimization, the specific implementation steps of S1 are as follows:

[0017] S1.1. Connect each data input interface of the trigger conversion circuit to the data interface of a D flip-flop with an enable terminal respectively;

[0018] S1.2. Perform a rising-edge detection on the input trigger signal, and use an AND gate circuit to output the detection result as the enable signal of the D flip-flop connected to the first data input interface to this D flip-flop, and also output it to the third register in the first position;

[0019] S1.3. According to the rising edge of the clock signal, transfer the data in the previous-level third register to the next-level third register;

[0020] S1.4. Take the output data of the A-th (1 ≤ A ≤ n - 1) third register as the enable signal of the D flip-flop connected to the (A + 1)-th data input interface. At the same time, take the output data of the A-th (1 ≤ A ≤ n - 1) third register as the valid identification signal of the corresponding A-th data interface for output. And take the output signal of the D flip-flop connected to the n-th data input interface as the data signal of the n-th data channel for output.

[0021] As an optimization, the specific steps of S2 are as follows:

[0022] S2.1. Connect the two input terminals of several OR gate circuits to two adjacent valid identification output interfaces of the previous-level circuit respectively, and output a valid identification signal;

[0023] S2.2. Connect the two input terminals of several multiplexers to two adjacent data output interfaces of the previous-level circuit respectively, and output a data signal, and connect one of the input terminals of the OR gate circuit to the control terminal of the corresponding multiplexer;

[0024] S2.3. Repeat S2.1 and S2.2 until finally only one valid identification signal and one data signal are output.

[0025] The present invention also discloses an electronic device, including at least one processor, and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute an implementation method of a dedicated sequential data selector as described above.

[0026] The present invention also discloses a storage medium storing a computer program, and when the computer program is executed by a processor, it implements an implementation method of a dedicated sequential data selector as described above.

[0027] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0028] In the digital IC technology fields such as FPGA, CPLD, semi-custom, and full-custom ASIC, in certain specific scenarios (the number of channels is known, each channel is selected only once, and the selection is made in sequence), the performance of the selector can be greatly improved. Since the use of combinational logic circuits is reduced, the selector has high-speed processing capabilities. At the same time, the internal of the selector is implemented in a pipelined manner, which also greatly facilitates layout and wiring. Compared with traditional selectors, the performance and advantages of this selector are more obvious when the speed is higher and the data volume is larger. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0030] Figure 1 Schematic diagram of a traditional data selector;

[0031] Figure 2 Schematic diagram of the structure of a dedicated sequential data selector of the present invention;

[0032] Figure 3 Schematic diagram of the implementation principle of a trigger conversion circuit;

[0033] Figure 4 Timing diagram of the trigger conversion circuit (primary circuit) of the present invention;

[0034] Figure 5 Schematic diagram of the implementation principle of a secondary circuit;

[0035] Figure 6 Timing diagram of the secondary circuit of the present invention;

[0036] Figure 7 Schematic diagram of the implementation principle of the last-stage circuit of the present invention;

[0037] Figure 8 Timing diagram of the last-stage circuit of the present invention.

[0038] Marks in the drawings and corresponding component names:

[0039] 1a - First register, 1b - Second register, 1c - Third register, 1d - Fourth register, 2 - NOT gate circuit, 3 - AND gate circuit, 4 - D flip - flop, 5 - OR gate circuit, 6 - 2 - to - 1 multiplexer. Detailed implementation mode

[0040] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to embodiments and the accompanying drawings. The illustrative embodiments and descriptions thereof of the present invention are only used to explain the present invention and do not limit the present invention.

[0041] Embodiment 1

[0042] As Figure 2 shown, a special sequential data selector of the present invention includes:

[0043] An m - stage circuit, where the m - stage circuit is composed of a trigger conversion circuit and a merging circuit connected in series in sequence. There is one trigger conversion circuit, (m - 1) merging circuits, and the (m - 1) merging circuits are connected in series.

[0044] As Figure 2 shown, the trigger conversion circuit is a first - stage circuit in Figure 2 , and the (m - 1) merging circuits are the subsequent second - stage circuit to the m - stage circuit.

[0045] The trigger conversion circuit includes a trigger signal channel and n data channels, where n = 2 m-1 , m is a positive integer not less than 2; the trigger signal channel includes a trigger signal input interface, the n data channels include n data input interfaces, and the trigger signal channel and the n data channels jointly have n data output interfaces and n valid identification output interfaces. The merging circuit is used to combine the data signals transmitted from the previous - stage circuit in pairs into a new data signal and use the new data signal as the data signal transmitted to the merging circuit of the next stage. At the same time, the merging circuit is also used to combine the valid identification signals transmitted from the previous - stage circuit in pairs into a new valid identification signal and use the new valid identification signal as the valid identification signal transmitted to the merging circuit of the next stage.

[0046] As Figure 3 shown, it is the implementation schematic diagram of the trigger conversion circuit.

[0047] In this embodiment, the trigger signal channel includes a first register 1a, a second register 1b, a NOT gate circuit 2, an AND gate circuit 3, and a third register 1c. There are n third registers 1c. The first register 1a is a trigger signal input interface. The output end of the first register 1a is connected by connecting the second register 1b and the NOT gate circuit 2 in series. The output end of the first register 1a is also connected to one input end of the AND gate circuit 3. The output end of the NOT gate circuit 2 is connected to the other input end of the AND gate circuit 3. The output end of the AND gate circuit 3 is connected to the input end of the first of the n third registers 1c. The n third registers 1c are connected in series. The signals output by the n third registers 1c are respectively used as the valid identification signals output by the corresponding n valid identification output channels; the output end of the third register 1c is the valid identification output interface, that is Figure 3 in (o_valid(1), o_valid(2)... o_valid(n)) in Figure 3 .

[0048] Each of the n data channels includes a fourth register 1d, and each fourth register 1d is respectively connected to a D flip-flop 4. In the D flip-flop 4, D is the data input end, EN is the enable end, and Q is the output end. When EN is at a high level, the Q end outputs the data at the D end; otherwise, the data at the Q end remains unchanged. Figure 4 is the timing diagram of the trigger conversion circuit (primary circuit) of the present invention.

[0049] The fourth register 1d is a data input interface, that is Figure 2 in (i_data(1), i_data(2)... i_data(n)) in Figure 2 . The data input end of the D flip-flop 4 connected to the first fourth register 1d receives the data signal output by the corresponding fourth register 1d. The enable end of the D flip-flop 4 connected to the first fourth register 1d receives the output data of the AND gate circuit 3. The data input end of the D flip-flop 4 connected to the (n′-i)th fourth register 1d receives the data signal output by the corresponding fourth register 1d. The enable end of the D flip-flop 4 connected to the (n′-i)th fourth register 1d receives the valid identification signal output by the (n′-i-1)th third register 1c, where i ∈ [0, n′-2], and n′ is a power of 2 not less than 4, that is, n′ ∈ 2 b , b ≥ 2. The signals output by the n D flip-flops 4 are respectively used as the data signals output by the corresponding n data output channels. That is, the output end of the D flip-flop 4 is the data output interface, that is also Figure 3 in (o_data(1), o_data(2)... o_data(n)) in Figure 3 .

[0050] In this embodiment, the merging circuit includes several groups of screening circuits each composed of an OR gate circuit 5 and a multiplexer 6. The number of screening circuits is one-half of the effective output signals transmitted from the previous-stage circuit or the effective identification signals transmitted from the previous-stage circuit. Two input terminals of the OR gate circuit 5 respectively receive two adjacent effective identification signals transmitted from the previous-stage circuit, and an output terminal of the OR gate circuit 5 outputs one of the received effective identification signals. Two input terminals of the multiplexer 6 respectively receive two adjacent data signals transmitted from the previous-stage circuit, a selection terminal of the multiplexer 6 receives one of the input signals of the OR gate circuit 5, and an output terminal of the multiplexer 6 selects and outputs the corresponding data signal according to the signal received by the selection terminal.

[0051] As Figure 5 shown, it is the implementation schematic diagram of the secondary circuit (i.e., the merging circuit in the first position). Its input interface is the output interface of the primary circuit (i.e., the trigger conversion circuit), and finally n / 2 data output interfaces (o1_data(1), o1_data(2) …… o1_data(n / 2)) and n / 2 effective identification output interfaces (o1_valid(1), o1_valid(2) …… o1_valid(n / 2)) are obtained, and the effective duration is two clock cycles. In Figure 5 , when the signal received by the selection port (control terminal) is high, the multiplexer 6 outputs the value of channel 1 (i.e., outputs the value of o_data(1)), otherwise it outputs the value of channel 2 (i.e., outputs the value of o_data(2)). Figure 6 is the timing diagram of the secondary circuit of the present invention.

[0052] Figure 7 And Figure 8 respectively give the implementation schematic diagram and timing diagram of the last-stage circuit of the present invention. One data valid identification signal and one data channel are output. The length of the valid identification signal is n clock cycles. During these n valid clock cycles, there are n data in the data channel, and these n data are exactly the data of the original n channels.

[0053] Figure 7 In, ox_valid and ox_data respectively correspond to Figure 1 o(m - 1)_valid and o(m - 1)_data in.

[0054] Embodiment 2

[0055] The present invention also discloses an implementation method of a dedicated sequential data selector as described above, including the following steps:

[0056] S1. The trigger conversion circuit receives a trigger signal and n data signals, and converts them into n valid identification signals and n data signals according to the trigger signal and the n data signals;

[0057] S2. The merging circuit receives the valid identification signals and data signals transmitted from the previous-stage circuit, combines the transmitted valid identification signals and data signals in pairs into a new valid identification signal and a new data signal respectively, and uses the new valid identification signal and data signal as the valid identification signal and data signal transmitted to the next-stage merging circuit until finally outputs one valid identification signal and one data signal.

[0058] First, assign a valid identification signal to each of the n data signals, and the width of each valid signal is 1 clock cycle. Then, perform pairwise synthesis on the n data signals, and synthesize every two data signals into one data signal. At this time, n / 2 signals and n / 2 valid signals can be obtained, and the width of each valid identification signal is twice that of the previous one (2 clock cycles). Then, perform pairwise synthesis on the n / 2 data signals again to obtain n / 4 data signals and n / 4 valid identification signals, and the width of each valid identification signal is twice that of the previous one (4 clock cycles). Repeat this pairwise synthesis process until finally obtain 1 data signal and 1 valid identification signal. At this time, the width of the valid identification signal is n clock cycles, and each clock cycle corresponds to the data signal of one channel.

[0059] In this embodiment, the specific implementation steps of S1 are as follows:

[0060] S1.1. Connect each data input interface of the trigger conversion circuit to the data interface of a D flip-flop 4 with an enable terminal respectively;

[0061] S1.2. Perform rising-edge detection on the input trigger signal (i_trig), and use the AND gate circuit 3 to output the detection result as the enable signal of the D flip-flop 4 connected to the first data input interface to this D flip-flop 4, and also output it to the third register 1c in the first position;

[0062] S1.3. According to the rising edge of the clock signal, transmit the data in the previous-stage third register 1c to the next-stage third register 1c; that is, perform continuous pipelining processing on the detection result for a total of n pipeline stages;

[0063] S1.4. Use the output data of the A-th (1 ≤ A ≤ n - 1) third register 1c as the enable signal of the D flip-flop 4 connected to the (A + 1)-th data input interface. At the same time, use the output data of the A-th (1 ≤ A ≤ n - 1) third register 1c as the valid identification signal of the corresponding A-th data interface for output. And, use the output signal of the D flip-flop 4 connected to the n-th data input interface as the data signal of the n-th data channel for output, and the valid duration is one clock cycle.

[0064] That is, use the A-th (1 ≤ A ≤ n - 1) beat result with rising edge edge detection as the enable signal of the D flip-flop 4 connected to the (A + 1)-th data input interface, and use the n-th beat result as the valid identification signal of the n-th data interface for output. At the same time, use the output signal of the D flip-flop 4 connected to the n-th data input interface as the data signal of the n-th data channel for output.

[0065] From Figure 4 it is not difficult to see that the input, output data, and number of channels of the trigger data conversion circuit are the same. It's just that at the output end, each data channel corresponds to one more valid identification output channel to output the valid signal identification, and the length of the valid signal identification is 1 clock cycle.

[0066] In this embodiment, the specific steps of S2 are as follows:

[0067] S2.1. Connect the two input terminals of several OR gate circuits 5 to two adjacent valid identification output interfaces of the previous-stage circuit respectively, and output a path of valid identification signal.

[0068] S2.2. Connect the two input terminals of several two-to-one selectors 6 to two adjacent data output interfaces of the previous-stage circuit respectively, and output a path of data signal. And connect one of the input terminals of the OR gate circuit 5 to the control terminal of the corresponding two-to-one selector 6.

[0069] S2.3. Repeat S2.1 and S2.2 until finally only one path of valid identification signal and data signal are output.

[0070] The input interface of the secondary circuit (the merging circuit at the first position) is the first-stage output interface. The screening circuit includes the OR gate circuit 5 and the two-to-one selector 6. The first screening circuit performs the following operations:

[0071] Take the OR operation of the valid identification signals output by the first and second valid identification output channels as the valid identification output of the first channel. Connect the data signals output by the first and second data signal output channels to a two-to-one selector 6. The valid identification of the first valid identification output channel is used as the selection input signal of this two-to-one selector 6, and the output of this two-to-one selector 6 is used as the output of the first data output channel.

[0072] The other screening circuits of the merging circuit are respectively processed by pairwise merging according to the merging method of the first screening circuit, and finally n / 2 data channel output interfaces (o1_data(1), o1_data(2) …… o1_data(n / 2)) and n / 2 data valid output interfaces (o1_valid(1), o1_valid(2) …… o1_valid(n / 2)) are obtained, and the valid duration is two clock cycles.

[0073] Figure 6 The timing diagram of the secondary circuit of the present invention is given. It can be seen from Figure 6 that within the two clock cycles of the output valid flag, there are two data in the data channel, each occupying one clock cycle.

[0074] Through the processing of the secondary circuit, the number of selectable channels is halved, and the amount of data per channel is doubled. Connect the output of the secondary circuit to the input of the tertiary circuit (the implementation method is the same as that of the secondary circuit), the number of output channels is halved again, and the amount of data per channel is doubled again. By repeating this cascading method (log 2 n) times, finally only one data valid flag signal and one data channel are output. The length of the valid flag signal is n clock cycles. Within these n valid clock cycles, there are n data in the data channel, and these n data are exactly the data of the original n channels. Figure 7 and Figure 8 respectively give the implementation schematic diagram and timing diagram of the last-stage dedicated sequential data selector.

[0075] The data selector implementation solution of the present invention adopts a multi-stage pipelining processing method, which greatly reduces the use of combinational circuits and can meet the requirements of high speed and large data volume (multi-channel selection).

[0076] Embodiment 3

[0077] The present invention also discloses an electronic device, including at least one processor and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute an implementation method of a dedicated sequential data selector as described above.

[0078] Embodiment 4

[0079] The present invention also discloses a storage medium storing a computer program, and when the computer program is executed by a processor, it implements an implementation method of a dedicated sequential data selector as described above.

[0080] The specific embodiments described above further elaborate on the object, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only for the specific embodiments of the present invention and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A dedicated sequential data selector, characterized in that, it includes: The m-level circuit is composed of a trigger conversion circuit and a merging circuit connected in series in sequence. There is one trigger conversion circuit, and there are (m - 1) merging circuits. The (m - 1) merging circuits are connected in series. The trigger conversion circuit includes one trigger signal channel and n data channels, where n = 2 m-1 , and m is a positive integer not less than 2. The trigger signal channel includes one trigger signal input interface. The n data channels include n data input interfaces. Moreover, the trigger signal channel and the n data channels jointly have n data output interfaces and n valid identification output interfaces. The merging circuit is used to combine the data signals transmitted from the previous-level circuit in pairs into a new data signal and use the new data signal as the data signal transmitted to the next-level merging circuit. At the same time, the merging circuit is also used to combine the valid identification signals transmitted from the previous-level circuit in pairs into a new valid identification signal and use the new valid identification signal as the valid identification signal transmitted to the next-level merging circuit.

2. The dedicated sequential data selector according to claim 1, characterized in that, the trigger signal channel includes a first register, a second register, a NOT gate circuit, an AND gate circuit and a third register. There are n third registers. The first register is the trigger signal input interface. The output end of the first register is connected in series through the second register and the NOT gate circuit. The output end of the first register is also connected to one input end of the AND gate circuit. The output end of the NOT gate circuit is connected to the other input end of the AND gate circuit. The output end of the AND gate circuit is connected to the input end of the third register located at the first position. The n third registers are arranged in series. The signals output by the n third registers are respectively used as the valid identification signals output by the corresponding n valid identification output channels; each of the n data channels includes a fourth register, and each of the fourth registers is respectively connected to a D flip-flop. The fourth register is the data input interface. The data input end of the D flip-flop connected to the first fourth register receives the data signal output by the corresponding fourth register. The enable end of the D flip-flop connected to the first fourth register receives the output data of the AND gate circuit. The data input end of the D flip-flop connected to the (n'-i)th fourth register receives the data signal output by the corresponding fourth register. The enable end of the D flip-flop connected to the (n'-i)th fourth register receives the valid identification signal output by the (n'-i-1)th third register, where i ∈ [0, n'-2], n' is a power of 2 not less than 4. The signals output by the n D flip-flops are respectively used as the data signals output by the corresponding n data output channels.

3. The dedicated sequential data selector according to claim 2, characterized in that, the merging circuit includes several groups of screening circuits composed of OR gate circuits and two-way selectors. The number of screening circuits is one-half of the valid output signals transmitted from the previous-stage circuit or the valid identification signals transmitted from the previous-stage circuit. The two input ends of the OR gate circuit respectively receive two adjacent valid identification signals transmitted from the previous-stage circuit. The output end of the OR gate circuit outputs one of the received valid identification signals. The two input ends of the two-way selector respectively receive two adjacent data signals transmitted from the previous-stage circuit. The selection end of the two-way selector receives one of the input signals of the OR gate circuit. The output end of the two-way selector selects the corresponding data signal for output according to the signal received by the selection end.

4. The dedicated sequential data selector according to claim 2, characterized in that, the NOT gate circuit is effective for input low level and effective for output high level.

5. The dedicated sequential data selector according to claim 3, characterized in that, the two-way selector is a signal selector, and the model of the signal selector is YR9033A.

6. A method for implementing a dedicated sequential data selector as described in any one of claims 1-5, characterized in that, it includes the following steps: S1. The trigger conversion circuit receives a trigger signal and n data signals, and converts them into n valid identification signals and n data signals according to the trigger signal and the n data signals; S2. The merging circuit receives the valid identification signals and data signals transmitted from the previous-stage circuit, and respectively combines the transmitted valid identification signals and data signals in pairs into a new valid identification signal and a new data signal, and uses the new valid identification signal and data signal as the valid identification signal and data signal transmitted to the merging circuit of the next stage until finally one valid identification signal and one data signal are output.

7. A method for implementing a dedicated sequential data selector according to claim 6, characterized in that, the specific implementation steps of S1 are: S1.

1. Connect each data input interface of the trigger conversion circuit to the data interface of a D flip-flop with an enable terminal respectively; S1.

2. Perform a rising-edge detection on the input trigger signal, and use an AND gate circuit to output the detection result as the enable signal of the D flip-flop connected to the first data input interface to this D flip-flop and to the third register in the first position; S1.

3. According to the rising edge of the clock signal, transmit the data in the previous-stage third register to the next-stage third register; S1.

4. Use the output data of the A-th third register as the enable signal of the D flip-flop connected to the (A + 1)-th data input interface, where 1 ≤ A ≤ n - 1. At the same time, use the output data of the A-th third register as the valid identification signal of the corresponding A-th data interface for output, and use the output signal of the D flip-flop connected to the n-th data input interface as the data signal of the n-th data channel for output.

8. A method for implementing a dedicated sequential data selector according to claim 7, characterized in that, the specific steps of S2 are: S2.

1. Connect the two input terminals of several OR gate circuits to two adjacent valid identification output interfaces of the previous-stage circuit respectively, and output one valid identification signal; S2.

2. Connect the two input terminals of several two-way selectors to two adjacent data output interfaces of the previous-stage circuit respectively, and output one data signal, and connect one of the input terminals of the OR gate circuit to the control terminal of the corresponding two-way selector; S2.

3. Repeat S2.1 and S2.2 until finally only one valid identification signal and one data signal are output.

9. An electronic device, characterized in that, it includes at least one processor and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a method for implementing a dedicated sequential data selector as described in any one of claims 6 to 8.

10. A storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements a method for implementing a dedicated sequential data selector according to any one of claims 6 to 8.

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