Superconducting pulse counter

Abstract

A 1-bit superconducting pulse counter is provided, comprising a superconducting XOR gate including a first input terminal for receiving a superconducting pulse signal and a clock terminal, an output terminal for outputting data, and a second input terminal for receiving data of the output terminal of the superconducting XOR gate; a DFFC flip-flop including an input terminal for receiving data of the output terminal of the superconducting XOR gate, a clock terminal for receiving the superconducting pulse signal, and a first output terminal and a second output terminal for outputting data; and a Q_D converter including a first input terminal for receiving data of the first output terminal of the DFFC flip-flop, a second input terminal for receiving data of the second output terminal of the DFFC flip-flop, and an output terminal for outputting a level signal. An N-bit superconducting pulse counter is also provided, comprising N 1-bit superconducting pulse counters, the Nth 1-bit superconducting pulse counter for receiving a carry signal of the N-1th superconducting pulse counter, outputting an Nth level signal, and outputting a carry signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of superconducting electronic circuits, and in particular to a superconducting pulse counter. BACKGROUND

[0002] The superconducting circuit of rapid single flux quantum (RSFQ) has the characteristics of low energy consumption and fast running frequency, and is a potential development direction of digital circuit research in the post-moore era. At present, there are not many related circuit logic designs. In digital circuits, counters are a commonly used component for recording the number of incoming signals, and can be used as a digital circuit address generator or a clock divider. There is no efficient counter suitable for RSFQ circuits at present. SUMMARY

[0003] The present application provides a 1-bit superconducting pulse counter, which comprises:

[0004] a superconducting XOR gate, comprising a first input end for receiving a superconducting pulse signal, a clock end for receiving the superconducting pulse signal, an output end for outputting data, and a second input end for receiving data of the output end of the superconducting XOR gate;

[0005] a DFFC flip-flop, comprising an input end for receiving data of the output end of the superconducting XOR gate, a clock end for receiving the superconducting pulse signal, and a first output end and a second output end for outputting data; and

[0006] a Q_D converter, comprising a first input end for receiving data of the first output end of the DFFC flip-flop, a second input end for receiving data of the second output end of the DFFC flip-flop, and an output end for outputting a level signal.

[0007] Preferably, the time when the superconducting pulse signal arrives at the clock end of the superconducting XOR gate is later than the time when the superconducting pulse signal arrives at the first input end of the superconducting XOR gate; and the time when the superconducting pulse signal arrives at the clock end of the superconducting XOR gate is substantially the same as the time when the superconducting pulse signal arrives at the clock end of the DFFC flip-flop.

[0008] Preferably, it further comprises a first SPL, which comprises an input end for receiving data of the second output end of the DFFC flip-flop, a first output end for outputting data to the second input end of the Q_D converter, and a second output end for outputting a carry signal.

[0009] Preferably, the DFFC flip-flop further comprises a reset end for receiving a reset signal, which is connected to the first input end, the second input end, the clock end of the superconducting XOR gate, and the clock end of the DFFC flip-flop, respectively.

[0010] The present application also provides an N-bit superconducting pulse counter, comprising N one-bit superconducting pulse counters as described above, wherein N is an integer greater than 1,

[0011] The first one-bit superconducting pulse counter is configured to receive a superconducting pulse signal, output a first bit level signal, and output a carry signal;

[0012] The Nth one-bit superconducting pulse counter is configured to receive a carry signal from the (N-1)th one-bit superconducting pulse counter, output an Nth bit level signal, and output a carry signal.

[0013] Preferably, the DFFC flip-flop in each one-bit superconducting pulse counter further comprises a reset terminal configured to receive a reset signal, which is respectively connected to the first input terminal, the second input terminal, the clock terminal of the superconducting XOR gate, and the clock terminal of the DFFC flip-flop in each one-bit superconducting pulse counter.

[0014] Preferably, the N-bit superconducting pulse counter further comprises an overflow counter, comprising:

[0015] a superconducting XOR gate comprising a first input terminal configured to receive a carry signal from the Nth one-bit superconducting pulse counter and a clock terminal, an output terminal configured to output data, and a second input terminal configured to receive data from the output terminal of the superconducting XOR gate;

[0016] a DFFC flip-flop comprising an input terminal configured to receive data from the output terminal of the superconducting XOR gate, a clock terminal configured to receive a carry signal from the Nth one-bit superconducting pulse counter, and a first output terminal and a second output terminal configured to output data; and

[0017] a Q_D converter comprising a first input terminal configured to receive data from the first output terminal of the DFFC flip-flop, a second input terminal configured to receive data from the second output terminal of the DFFC flip-flop, and an output terminal configured to output a level signal.

[0018] Preferably, the DFFC flip-flop further comprises a reset terminal configured to receive a reset signal, which is respectively connected to the first input terminal, the second input terminal, the clock terminal of the superconducting XOR gate, and the clock terminal of the DFFC flip-flop.

[0019] Preferably, the N-bit superconducting pulse counter further comprises an overflow counter, comprising:

[0020] a superconducting XOR gate comprising a first input terminal configured to receive a carry signal from the Nth one-bit superconducting pulse counter and a clock terminal, an output terminal configured to output data, and a second input terminal configured to receive data from the output terminal of the superconducting XOR gate;

[0021] A DFF flip-flop includes an input terminal for receiving data of an output terminal of a superconducting XOR gate, a clock terminal for receiving a carry signal from an Nth 1-bit superconducting pulse counter, and an output terminal for outputting an overflow signal.

[0022] Preferably, the DFF flip-flop further includes a reset terminal for receiving a reset signal, which is connected to the first input terminal, the second input terminal, the clock terminal of the superconducting XOR gate, and the clock terminal of the DFF flip-flop, respectively.

[0023] The present application implements a superconducting pulse counter by using an existing RSFQ superconducting circuit process. After m superconducting pulses are input at an input terminal of the counter, a binary count representation of m can be output at an output terminal of the counter. The superconducting pulse counter of the present application can be used in scenarios such as PC address generation and clock division in a superconducting processor. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1A A schematic diagram of a prior art SPL device.

[0025] Figure 1B A schematic diagram of a prior art CB device.

[0026] Figure 1C A schematic diagram of a prior art NOT device.

[0027] Figure 1D A schematic diagram of a prior art XOR device.

[0028] Figure 1E A schematic diagram of a prior art DFF flip-flop.

[0029] Figure 1F A schematic diagram of a prior art RDFF flip-flop.

[0030] Figure 2A A schematic diagram of a prior art DFFC flip-flop.

[0031] Figure 2B A circuit schematic diagram of a prior art DFFC flip-flop.

[0032] Figure 2C A schematic diagram of a prior art RDFFC flip-flop.

[0033] Figure 2D A circuit schematic diagram of a prior art RDFFC flip-flop.

[0034] Figure 3 A schematic diagram of a prior art Q_D converter.

[0035] Figure 4A circuit schematic diagram of a 1-bit superconducting pulse counter according to one embodiment of the present application is shown.

[0036] Figure 5 A circuit schematic diagram of a 1-bit superconducting pulse counter with carry according to one embodiment of the present application is shown.

[0037] Figure 6 A simplified representation of a 1-bit superconducting pulse counter in Figure 5

[0038] Figure 7 A schematic diagram of an N-bit superconducting pulse counter according to one embodiment of the present application is shown.

[0039] Figure 8 A circuit schematic diagram of an overflow counter according to another embodiment of the present application is shown.

[0040] Figure 9A A circuit schematic diagram of a 1-bit superconducting pulse counter according to one embodiment of the present application is shown.

[0041] Figure 9B A circuit schematic diagram of a 1-bit superconducting pulse counter with carry according to one embodiment of the present application is shown.

[0042] Figure 10 A simplified representation of a 1-bit superconducting pulse counter in Figure 9B

[0043] Figure 11 A schematic diagram of an N-bit superconducting pulse counter according to one embodiment of the present application is shown.

[0044] Figure 12 A circuit schematic diagram of an overflow counter according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0045] In order to make the objects, technical solutions and advantages of the present application clearer, further specific embodiments will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments given by the present application are only for illustration and do not limit the protection scope of the present application.

[0046] The present application relates to a superconducting RSFQ circuit, in which, instead of a direct current voltage in a conventional digital circuit, a binary information is represented by selecting whether there is a superconducting pulse between two adjacent clock pulses in a superconducting RSFQ digital circuit, 0 representing a state without a superconducting pulse input and 1 representing a state with a superconducting pulse input.

[0047] ​​The superconducting pulse counter in this invention relates to existing superconducting devices such as splitters (SPL), confluence buffers (CB), NOT gates, XOR gates, DFF flip-flops, RDFF flip-flops, DFFC flip-flops, RDFFC flip-flops, and Q-D converters. The above-mentioned superconducting devices are described in detail below with reference to the accompanying drawings.

[0048] Figure 1A This is a schematic diagram of a prior art SPL device, which does not require a clock input. For example... Figure 1A As shown, the SPL device includes an input terminal (in) for receiving input data and a first output terminal (out1) and a second output terminal (out2) for outputting data. When the SPL device receives a superconducting pulse input, it will directly output two identical superconducting pulses. The SPL device may also include three output terminals, and when a superconducting pulse input is received, it will directly output three identical superconducting pulses (not shown in the figure). In the following text, both SPL devices capable of generating two output pulses and SPL devices capable of generating three output pulses will be referred to as SPL devices.

[0049] Figure 1B This is a schematic diagram of a prior art superconducting pulse (CB) device, which includes a first input terminal in1 and a second input terminal in2 for receiving input data, and an output terminal out for outputting data. Its function is to output the superconducting pulses from the two input terminals in1 and in2 from the same output terminal out. When a superconducting pulse is input to either the first input terminal in1 or the second input terminal in2, the output terminal out will output the input superconducting pulse.

[0050] Figure 1C This is a schematic diagram of a prior art NOT gate device, which includes an input terminal (in) for receiving input data, a clock terminal (clk) for receiving a clock signal, and an output terminal (out) for outputting data. The NOT gate inverts the state of the data input to the input terminal. Specifically, within one clock cycle, if the input signal is 0 (i.e., no superconducting pulse signal is input), then a superconducting pulse signal will be output after the clock signal arrives, i.e., the output signal is 1. Conversely, if the input signal is 1 (i.e., a superconducting pulse signal is input), then no superconducting pulse signal will be output after the clock signal arrives, i.e., the output signal is 0.

[0051] Figure 1DFig. 1 is a schematic diagram of a prior art XOR device, which includes a first input terminal in1 and a second input terminal in2 for receiving input data, a clock terminal clk for receiving a clock signal, and an output terminal out for outputting data. Before the clock signal arrives, if a superconducting pulse signal arrives at the first input terminal in1 or the second input terminal in2, it is considered as an input of 1, and if no superconducting pulse signal arrives at the first input terminal in1 or the second input terminal in2 during the arrival of two clock signals, it is considered as an input of 0. The XOR device is driven by the clock signal, and after the clock signal arrives, the input data of the first input terminal in1 and the second input terminal in2 are subjected to an exclusive-OR calculation, and the operation result is output via the output terminal out. Table 1 shows a logical truth table of the XOR device of the present application. As can be seen from Table 1, when the input data of the first input terminal in1 and the second input terminal in2 are the same, the output of the output terminal out is 0; when the input data of the first input terminal in1 and the second input terminal in2 are different, the output of the output terminal out is 1.

[0052] In1 In2 out 0 0 0 0 1 1 1 0 1 1 1 0

[0053] Table 1: Logical truth table of XOR device

[0054] Figure 1E Fig. 2 is a schematic diagram of a prior art DFF flip-flop, which includes an input terminal in for receiving input data, a clock terminal clk for receiving a clock signal, and an output terminal out for outputting data. When the clock signal t1 arrives, the previous clock signal is t0, if there is a pulse signal input at the input terminal in between t0 and t1, then after the clock signal t1 arrives, the output terminal out outputs a pulse signal. If there is no pulse signal input at the input terminal in between t0 and t1, then after the clock signal t1 arrives, the output terminal out does not output a pulse signal.

[0055] Figure 1F Fig. 3 is a schematic diagram of a prior art RDFF flip-flop, which includes an input terminal in for receiving input data, a clock terminal clk for receiving a clock signal, an output terminal out for outputting data, and a reset terminal reset for receiving a reset signal. The RDFF flip-flop is a DFF flip-flop with a reset terminal reset, and its working mode is basically the same as that of the DFF flip-flop, except that when the reset terminal reset has a pulse signal input, the RDFF flip-flop will clear the internal state, and after the subsequent clock signal arrives, the output terminal out does not output a pulse signal.

[0056] Figure 2AThis is a schematic diagram of a prior art DFFC flip-flop, which includes an input terminal in for receiving input data, a clock terminal clk for receiving a clock signal, and a first output terminal out1 and a second output terminal out2 for outputting data. The DFFC flip-flop is a DFF flip-flop with inverted outputs; the output data of the first output terminal out1 and the second output terminal out2 are inverted. The operating mode of the DFFC flip-flop is as follows: When clock signal t1 arrives, the previous clock signal is t0. If there is a pulse signal input at input terminal in between clock signals t0 and t1, then after clock signal t1 arrives, the first output terminal out1 will output a pulse signal, and the second output terminal out2 will not output a pulse signal. If there is no pulse signal input at input terminal in between clock signals t0 and t1, then after clock signal t1 arrives, the first output terminal out1 will not output a pulse signal, and the second output terminal out2 will output a pulse signal. The DFFC flip-flop is essentially a DFF flip-flop with inverted outputs. In practical applications, a standalone DFFC flip-flop can be used, or it can be implemented using a combination of DFF flip-flops, SPL, and NOT gates, such as... Figure 2B As shown, its working mode is similar to Figure 2A The DFFC trigger shown is the same, so it will not be described again here.

[0057] Figure 2C This is a schematic diagram of a prior art RDFFC flip-flop, which includes an input terminal (in) for receiving input data, a clock terminal (clk) for receiving a clock signal, a reset terminal (reset) for receiving a reset signal, and a first output terminal (out1) and a second output terminal (out2) for outputting data. The RDFFC flip-flop is a DFFC flip-flop with a reset terminal (reset). Its operating mode is basically the same as a traditional DFFC flip-flop, except that when a pulse signal is input to the reset terminal (reset), the RDFFC flip-flop clears its internal state. After a subsequent clock signal arrives, the first output terminal (out1) does not output a pulse, while the second output terminal (out2) outputs a pulse. In practical applications, a standalone DFFC flip-flop can be used, or a combination of an RDFFC flip-flop, an SPL gate, and a NOT gate can be used, such as... Figure 2D As shown, its working mode is similar to Figure 2C The RDFFC trigger shown is the same, so it will not be described again here.

[0058] Figure 3This is a schematic diagram of a prior art Q-D converter. A Q-D converter is a device that converts a superconducting pulse signal into a level signal. It includes a first input terminal in1 and a second input terminal in2 for receiving input data, and an output terminal out for outputting a level signal. When a superconducting pulse is input to the first input terminal in1, the output terminal out outputs a high-level signal; when a superconducting pulse is input to the second input terminal in2, the output terminal out outputs a low-level signal. After receiving a superconducting pulse that changes the output level, the Q-D converter maintains its output level unchanged until the next superconducting pulse changes the output level of the Q-D converter.

[0059] Figure 4 A circuit diagram of a 1-bit superconducting pulse counter according to an embodiment of the present invention is shown. Figure 4 As shown, the 1-bit superconducting pulse counter 400 includes an SPL 401, an XOR 402, an SPL 403, a DFFC flip-flop 404, and a Q-D converter 405. The SPL 401 includes an input terminal *in* for receiving superconducting pulse signals, and first output terminals *out1*, second output terminals *out2*, and third output terminals *out3* for outputting the superconducting pulse signals. The XOR 402 includes a first input terminal *in1* for receiving data from the third output terminal *out3* of the SPL 401, a second input terminal *in2* for receiving data from the second output terminal *out2* of the SPL 403, a clock terminal *clk* for receiving data from the second output terminal *out2* of the SPL 401, and an output terminal *out* for outputting data. The SPL 403 includes an input terminal *in* for receiving data from the output terminal *out* of the XOR 402, and first output terminals *out1* and second output terminals *out2* for outputting data. The DFFC flip-flop 404 includes an input terminal in for receiving data from the first output terminal out1 of SPL 403, a clock terminal clk for receiving data from the first output terminal out1 of SPL 401, and a first output terminal out1 and a second output terminal out2 for outputting data. The Q-D converter 405 includes a first input terminal in1 for receiving data from the first output terminal out1 of the DFFC flip-flop 404, a second input terminal in2 for receiving data from the second output terminal out2 of the DFFC flip-flop 404, and an output terminal out for outputting a level signal.

[0060] For the convenience of explaining the working mode of the superconducting pulse counter, the time when the superconducting pulse reaches the input end in of the SPL 401 is defined as time t, the time when the superconducting pulse reaches the clock end clk of the XOR 402 is defined as time a, the time when the superconducting pulse reaches the first input end in1 of the XOR 402 is defined as time b, the time when the superconducting pulse reaches the clock end clk of the DFFC flip-flop 404 is defined as time c, the time when the superconducting pulse reaches the input end in of the DFFC flip-flop 404 is defined as time d, and the time when the superconducting pulse reaches the second input end in2 of the XOR 402 is defined as time e. Among them, the time a when the superconducting pulse reaches the clock end clk of the XOR 402 is later than the time b when the superconducting pulse reaches the first input end in1 of the XOR 402; the time a when the superconducting pulse reaches the clock end clk of the XOR 402 is approximately the same as the time c when the superconducting pulse reaches the clock end clk of the DFFC flip-flop 404.

[0061] The first superconducting pulse reaches the input end in of the SPL 401, which is at time t. After the first superconducting pulse branches through the SPL 401, it reaches the clock end clk of the XOR 402 at time a and the first input end in1 of the XOR 402 at time b. The present application controls the arrival time of the superconducting pulse through the JTL transmission line, so that time b is earlier than time a. Therefore, when the clock end clk of the XOR 402 has data input, the first input end in1 of the XOR 402 has pulse signal input, and the second input end in2 has no pulse signal input, so that the output end out of the XOR 402 outputs a pulse signal. Since time a and time c are approximately the same, when the clock end clk of the DFFC flip-flop 404 has data input, the input end in of the DFFC flip-flop 404 has no signal input, so that the first output end out1 of the DFFC flip-flop 404 has no pulse signal output, and the second output end out2 has pulse signal output. The first input end in1 of the Q_D converter 405 has no pulse signal input, and the second input end out2 has pulse signal input, so that the output end out of the Q_D converter 405 outputs a low-level signal 0.

[0062] In the present application, the output level signal is represented by low level as 0 and high level as 1. However, the representation method of high level as 0 and low level as 1 can also be used, which only needs to reverse the output end of the DFFC flip-flop 404 and the input end of the Q_D converter 405, which is within the protection scope of the present application.

[0063] The second superconducting pulse arrives, at this time, the second input in2 of the XOR 402 has a pulse signal input, and the input in of the DFFC flip-flop 404 also has a pulse signal input. When the second superconducting pulse arrives at the clock end clk of the XOR 402, the first input in1 and the second input in2 of the XOR 402 both have a pulse signal input, so that the output end out of the XOR 402 does not output a pulse signal. When the second superconducting pulse arrives at the clock end clk of the DFFC flip-flop 404, the input in of the DFFC flip-flop 404 has a signal input, so that the first output end out1 of the DFFC flip-flop 404 has a pulse signal output, and the second output end out2 has no pulse signal output. The first input in1 of the Q_D converter 405 has a pulse signal input, and the second input out2 has no pulse signal input, so that the output end out of the Q_D converter 405 outputs a high-level signal 1.

[0064] The third superconducting pulse arrives, at this time, the second input in2 of the XOR 402 has no pulse signal input, and the input in of the DFFC flip-flop 404 also has no pulse signal input. When the third superconducting pulse arrives at the clock end clk of the XOR 402, the first input in1 of the XOR 402 has a pulse signal input, and the second input in2 has no pulse signal input, so that the output end out of the XOR 402 outputs a pulse signal. When the third superconducting pulse arrives at the clock end clk of the DFFC flip-flop 404, the input in of the DFFC flip-flop 404 has no signal input, so that the first output end out1 of the DFFC flip-flop 404 has no pulse signal output, and the second output end out2 has a pulse signal output. The first input in1 of the Q_D converter 405 has no pulse signal input, and the second input out2 has a pulse signal input, so that the output end out of the Q_D converter 405 outputs a low-level signal 0.

[0065] Table 2 shows the 3 superconducting pulse inputs and output level signals. As can be seen from Table 2, the 1-bit superconducting pulse counter alternately outputs 0 / 1 with the input of the counting pulse.

[0066] Number of pulse inputs Output level signal 1 0 2 1 3 0

[0067] Table 2: 3 superconducting pulse inputs and output level signals

[0068] Figure 5 A circuit schematic diagram of a 1-bit superconducting pulse counter with carry according to an embodiment of the present application is shown. It is similar to the circuit schematic diagram of the 1-bit superconducting pulse counter without carry shown in FIG. 2, and the difference is that the DFFC flip-flop 404 is replaced by a DFFC flip-flop 404 with carry. Figure 4The 1-bit superconducting pulse counter 400 is basically the same as the one-bit superconducting pulse counter 500 with carry, except that the 1-bit superconducting pulse counter 500 with carry also includes SPL 506, which includes an input terminal in for receiving data from the second output terminal out2 of the DFFC flip-flop 504, a first output terminal out1 for outputting data to the second input terminal in2 of the Q_D converter 505, and a second output terminal out2 for outputting the carry signal.

[0069] Figure 6 It shows Figure 5 This is a simplified representation of a 1-bit superconducting pulse counter with carry. The 1-bit superconducting pulse counter 600 includes an input terminal in for receiving superconducting pulse signals, a level output terminal out1 for outputting level signals, and a carry output terminal out2 for outputting carry signals.

[0070] Figure 7 A schematic diagram of an N-bit superconducting pulse counter according to an embodiment of the present invention is shown. The N-bit superconducting pulse counter 700 includes N 1-bit counters with carry, including a first counter 7011, a second counter 7012, ..., an Nth counter 701... N Where N is an integer greater than 1. The first counter 7011 includes an input terminal in for receiving a superconducting pulse signal, a level output terminal out1 for outputting the first bit level signal, and a carry output terminal out2 for outputting a carry signal; the second counter 7012 includes an input terminal in for receiving the carry signal from the carry output terminal out2 of the first counter 7011, a level output terminal out1 for outputting the second bit level signal, and a carry output terminal out2 for outputting a carry signal; and so on, the Nth counter 701... N Includes a counter 701 for receiving the (N-1)th counter. N-1 The carry output terminal out2 is the input terminal in of the carry signal, the level output terminal out1 is used to output the level signal of the Nth bit, and the carry output terminal out2 is used to output the carry signal. By reading the level output terminal of the N-bit counter, the binary count of the number of input superconducting pulses can be obtained.

[0071] The N-bit superconducting pulse counter 700 may also include an overflow counter 702 for recording whether the superconducting pulse counter 700 overflows, accumulating 2 inputs. N After +1 superconducting pulse signal, overflow counter 702 generates an overflow signal. Overflow counter 702 includes a function for receiving the Nth counter 701. N The carry output terminal out2 has the carry signal input terminal in, and the overflow output terminal out is used to output the overflow signal. The overflow counter 702 can be as follows: Figure 4 The example shown is a 1-bit counter without carry; in this case, the overflow signal is a level signal.

[0072] The working process of the superconducting pulse counter is described below by taking a 3-bit superconducting pulse counter as an example. The 3-bit superconducting pulse counter includes a first counter, a second counter, a third counter, and an overflow counter. The overflow counter is a 1-bit counter without carry as shown in Table 3. Figure 4 Table 3 shows an output example of the 3-bit superconducting pulse counter. When no superconducting pulse is input, the level signals and the carry signals output by the first counter, the second counter, and the third counter are all 0, and the level output of the 3-bit superconducting pulse counter is 000, and the level signal output by the overflow counter is 0. When the first superconducting pulse is input, the level signal of the first counter is 0, and the carry signal is 1; the level signal of the second counter is 0, and the carry signal is 1; the level signal of the third counter is 0, and the carry signal is 1; at this time, the level output of the 3-bit superconducting pulse counter is 000, and the level signal output by the overflow counter is 0. In this way, when the eighth superconducting pulse is input, the level signal of the first counter is 1, and the carry signal is 0; the level signal of the second counter is 1, and the carry signal is 0; the level signal of the third counter is 1, and the carry signal is 0; at this time, the level output of the 3-bit superconducting pulse counter is 111, and the level signal output by the overflow counter is 0. When the ninth superconducting pulse is input, the output is basically the same as when the first superconducting pulse is input, except that the level signal output by the overflow counter is 1 at this time.

[0073]

[0074] Table 3: Output example of 3-bit superconducting pulse counter

[0075] In the above embodiment, the Q_D converter maintains the output level unchanged after receiving the pulse signal changes the output level until the next input pulse signal arrives. Each 1-bit counter generates a carry pulse output after receiving two count pulse inputs. Therefore, for the pth counter, the output level state changes once after receiving 1 carry signal from the upper level, and a carry signal is generated after receiving two carry signals from the upper level. For the p+1th counter, the pth counter changes the output level state once after receiving 1 carry signal from the pth counter, and the p+1th counter generates a carry signal after receiving two carry signals from the pth counter.

[0076] And so on. With each input of a counting pulse from the superconducting pulse counter, the first-stage counter changes its output level once for every one counting pulse received, maintaining the 0-1 state transition; the second-stage counter changes its output level once for every two counting pulses received; the third-stage counter changes its output level once for every four counting pulses received; and so on... N-1 For each counting pulse, the Nth stage counter changes its output level once. The overflow counter changes its output level once at the second input pulse. N An overflow signal is generated when +1 counting pulse is reached. Therefore, reading the level output of the N-bit counter yields the binary count of the input pulses. Reading the overflow signal output of the N-bit counter indicates whether the input pulse count has overflowed.

[0077] As shown in Table 3, when the first counting pulse is input to the counter, the counter output is 000, the same as the output when no pulse is input. Preferably, the superconducting pulse counter can be initialized before counting the input pulses; that is, the first pulse in Table 3 is the initialization pulse, and counting begins from the second pulse. At this time, the overflow counter will overflow when the second pulse is input. N An overflow signal is generated when the counting pulse reaches the specified value. For clarity, this invention will be described as an example without inputting an initialization pulse, i.e., counting starts from the first pulse. However, those skilled in the art can perform initialization operations on the superconducting pulse counter as needed.

[0078] Figure 8 A circuit diagram of an overflow counter according to another embodiment of the present invention is shown, wherein the overflow counter 800 can output a superconducting overflow signal. Figure 8As shown, the superconducting overflow counter 800 comprises a SPL 801, an XOR 802, a SPL 803 and a DFF flip-flop 804. The SPL 801 comprises an input end in for receiving a superconducting pulse signal, and a first output end out1, a second output end out2 and a third output end out3 for outputting the superconducting pulse signal. The XOR 802 comprises a first input end in1 for receiving data of the third output end out3 of the SPL 801, a second input end in2 for receiving data of the second output end out2 of the SPL 803, a clock end clk for receiving data of the second output end out2 of the SPL 801, and an output end out for outputting data. The SPL 803 comprises an input end in for receiving data of the output end out of the XOR 802, and a first output end out1 and a second output end out2 for outputting data. The DFF flip-flop 804 comprises an input end in for receiving data of the first output end out1 of the SPL 803, a clock end clk for receiving data of the first output end out1 of the SPL 401, and an output end out for outputting an overflow signal.

[0079] The working timing of the superconducting pulse counter 400 is shown in FIG. 4B. Figure 4 As shown, the 1-bit superconducting pulse counter 400 is similar to the 1-bit superconducting pulse counter 300, except that the DFFC flip-flop in the 1-bit superconducting pulse counter 300 is replaced by a RDFFC flip-flop, which comprises a reset end reset for receiving a reset signal.

[0080] The superconducting pulse counter in the above embodiments can start counting from 0 (or from 1) and return to 0 after accumulation of overflow, but does not have a reset-to-zero function. Figure 9A As shown, the 1-bit superconducting pulse counter 900 has a reset-to-zero function according to an embodiment of the present application. The 1-bit superconducting pulse counter 900 is similar to the 1-bit superconducting pulse counter 400, except that the DFFC flip-flop in the 1-bit superconducting pulse counter 400 is replaced by a RDFFC flip-flop, which comprises a reset end reset for receiving a reset signal. Figure 4 As shown, the superconducting pulse counter 400 is similar to the superconducting pulse counter 300, except that the DFFC flip-flop in the superconducting pulse counter 300 is replaced by a RDFFC flip-flop, which comprises a reset end reset for receiving a reset signal. Figure 4 As shown, the superconducting pulse counter 400 is similar to the superconducting pulse counter 300, except that the DFFC flip-flop in the superconducting pulse counter 300 is replaced by a RDFFC flip-flop, which comprises a reset end reset for receiving a reset signal. Figure 9AThe 1-bit superconducting pulse counter 900 shown in FIG. 9 further includes CB 907, SPL 908, CB 909, and SPL 910, where CB 907 includes a first input in1 for receiving the superconducting pulse signal, a second input in2 for receiving the reset signal from the first output out1 of SPL 908, and an output out for outputting data to the input in of SPL 901. SPL 908 includes an input in for receiving the reset signal from the first output out1 of SPL 910, and a first output out1 and a second output out2 for outputting data. CB 909 includes a first input in1 for receiving the reset signal from the second output out2 of SPL 908, a second input in2 for receiving the data from the second output out2 of SPL 903, and an output out for outputting the data to the second input in2 of XOR 902. SPL 910 includes an input in for receiving the reset signal, a first output out1 for outputting the reset signal to the input in of SPL 908, and a second output out2 for outputting the reset signal to the reset end reset of RDFFC flip-flop 904. The same parts are not described again here, Figure 4

[0081] The operation timing of the 1-bit superconducting pulse counter 900 is the same as that of the 1-bit superconducting pulse counter 800 shown in FIG. 8, Figure 4 ​The same parts are not repeated here. The difference is that the 1-bit superconducting pulse counter 900 has a clear function. Specifically, the reset signal reaches the input end in of the SPL 910, and is output to the reset end reset of the RDFFC flip-flop 904 via the second output end out2 of the SPL 910, and is output to the input end in of the SPL 908 via the first output end out1 of the SPL 910; the SPL 908 receives the reset signal, and is output to the first input end in1 of the CB 909 via the second output end out2 of the SPL 908, and is output to the second input end in2 of the CB 907 via the first output end out1 of the SPL 908; the CB 909 receives the reset signal, and outputs the reset signal to the second input end in2 of the XOR 902 via the output end out of the CB 909; the CB 907 receives the reset signal, and outputs the reset signal to the input end in of the SPL 901 via the output end out of the CB 907; the SPL 901 receives the reset signal, and outputs the reset signal to the clock end clk of the RDFFC flip-flop 904 via the first output end out1 of the SPL 901, outputs the reset signal to the clock end clk of the XOR 902 via the second output end out2 of the SPL 901, and outputs the reset signal to the first input end in1 of the XOR 902 via the third output end out3 of the SPL 901.

[0082] When the reset signal is input, the first input end in1 and the second input end in2 of the XOR 902 have pulse signals input, then the clock end clk of the XOR 902 receives the reset signal, so that the output end out of the XOR 902 has no pulse signal output, realizing the data clear of the XOR 902. The reset end reset of the RDFFC flip-flop 904 receives the reset signal, so that the content of the RDFFC flip-flop 904 is cleared, then the clock end clk of the RDFFC flip-flop 904 receives the reset signal, so that the first output end out1 of the RDFFC flip-flop 904 has no pulse signal output, and the second output end out2 has a pulse signal output, and then the output of the Q_D converter is 0. Therefore, the content of the entire superconducting pulse counter is all zero.

[0083] Figure 9B The circuit schematic diagram of the 1-bit superconducting pulse counter with carry according to one embodiment of the present application is shown. It is basically the same as the 1-bit superconducting pulse counter in Figure 9A The difference is that: Figure 9BThe 1-bit superconducting pulse counter with carry also includes an SPL 906, which includes an input terminal in for receiving data from the second output terminal out2 of the RDFFC flip-flop 904, a first output terminal out1 for outputting data to the second input terminal in2 of the Q_D converter 905, and a second output terminal out2 for outputting a carry signal.

[0084] Figure 10 It shows Figure 9B A simplified representation of a 1-bit superconducting pulse counter. The 1-bit superconducting pulse counter 1000 includes an input terminal in for receiving superconducting pulse signals, a reset terminal reset for receiving reset signals, a level output terminal out1 for outputting level signals, and a carry output terminal out2 for outputting carry signals.

[0085] Figure 11 A circuit diagram of an N-bit superconducting pulse counter according to an embodiment of the present invention is shown. The N-bit superconducting pulse counter 1100 includes N 1-bit counters with carry, including a first counter 11011, a second counter 11012, ..., an Nth counter 1101 N SPL1, SPL2, ..., SPLN, where N is an integer greater than 1. SPL1 includes an input terminal for receiving a reset signal, and a first output terminal out1 and a second output terminal out2 for outputting the reset signal; SPL2 includes an input terminal in for receiving the reset signal from the second output terminal out2 of SPL1, and a first output terminal out1 and a second output terminal out2 for outputting the reset signal; ... and so on, SPLN includes an input terminal in for receiving the reset signal from the second output terminal out2 of SPLN-1, and a first output terminal out1 and a second output terminal out2 for outputting the reset signal. The first counter 11011 includes an input terminal in for receiving a superconducting pulse signal, a reset terminal reset for receiving the reset signal from the first output terminal in1 of SPL1, a level output terminal out1 for outputting the first bit level signal, and a carry output terminal out2 for outputting the carry signal; and so on, the Nth counter 1101... N Includes a counter 1101 for receiving the (N-1)th counter. N-1 The superconducting pulse counter has several terminals: the carry output terminal out2 (in), the carry signal input terminal in, the reset terminal reset (reset terminal), the level output terminal out1 (out), and the carry output terminal out2 (out), all for outputting the carry signal. Reading the level output ports of the N-bit counter yields the binary count of the input pulses. When a reset signal is input, the entire superconducting pulse counter is cleared.

[0086] The N-bit superconducting pulse counter 1100 can further comprise an overflow counter 1102 for recording whether the superconducting pulse counter 1100 overflows after counting the input 2 N superconducting pulse signals, the overflow counter 1102 generates an overflow signal. The overflow counter 1102 comprises an input in for receiving a carry signal from the carry output out2 of the Nth counter 1101 N , a reset end reset for receiving a reset signal from the second output in2 of the SPL N, and an output out for outputting the overflow signal. The overflow counter 1102 can be a 1-bit counter without carry as shown in Figure 9A , in which case the overflow signal is a level signal.

[0087] Figure 12 A circuit schematic of an overflow counter according to another embodiment of the present application is shown, in which the overflow counter 1200 can output a superconducting signal and has a clear function. It is similar to the overflow counter shown in Figure 8 , except that the RDFF flip-flop has a reset end reset for receiving a reset signal. The overflow counter 1200 further comprises a CB 1207, a SPL 1208, a CB 1209, and a SPL 1210, wherein the CB 1207 comprises a first input in1 for receiving a superconducting pulse signal, a second input in2 for receiving a reset signal from the first output out1 of the SPL 1208, and an output out for outputting data to the input in of the SPL 1201. The SPL 1208 comprises an input in for receiving a reset signal from the first output out1 of the SPL 1210, and a first output out1 and a second output out2 for outputting data. The CB 1209 comprises a first input in1 for receiving a reset signal from the second output out2 of the SPL 1208, a second input in2 for receiving data from the second output out2 of the SPL 1203, and an output out for outputting data to the second input in2 of the XOR 1202. The SPL 1210 comprises an input in for receiving a reset signal, a first output out1 for outputting the reset signal to the input in of the SPL 1208, and a second output out2 for outputting the reset signal to the reset end reset of the RDFF flip-flop 1204. The same parts as in Figure 8 are not repeated here.

[0088] The working timing of the overflow counter 1200 with the clear function is similar to Figure 8The overflow counter 1200 is similar to the overflow counter in the above-mentioned embodiment, and the same parts are not described again here. The difference is that the overflow counter 1200 has a clear function. Specifically, the reset signal reaches the input end in of the SPL 1210, and is output to the reset end reset of the RDFF flip-flop 1204 via the second output end out2 of the SPL 1210 and the input end in of the SPL 1208 via the first output end out1 of the SPL 1210; the SPL 1208 receives the reset signal and outputs the reset signal to the first input end in1 of the CB 1209 via the second output end out2 of the SPL 1208 and the second input end in2 of the CB 1207 via the first output end out1 of the SPL 1208; the CB 1209 receives the reset signal and outputs the reset signal to the second input end in2 of the XOR 1202 via the output end out of the CB 1209; the CB 1207 receives the reset signal and outputs the reset signal to the input end in of the SPL 1201 via the output end out of the CB 1207; the SPL 1201 receives the reset signal and outputs the reset signal to the clock end clk of the RDFF flip-flop 1204 via the first output end out1 of the SPL 1201, to the clock end clk of the XOR 1202 via the second output end out2 of the SPL 1201, and to the first input end in1 of the XOR 1202 via the third output end out3 of the SPL 1201.

[0089] When the reset signal is input, the first input end in1 and the second input end in2 of the XOR 1202 both have pulse signals input, then the clock end clk of the XOR 1202 receives the reset signal, so that the output end out of the XOR 1202 has no pulse signal output, realizing the data clear of the XOR 1202. The reset end reset of the RDFF flip-flop 1204 receives the reset signal, so that the content of the RDFF flip-flop 1204 is cleared, then the clock end clk of the RDFF flip-flop 1204 receives the reset signal, so that the output end out of the RDFF flip-flop 1204 has no pulse signal output. Therefore, the content of the entire overflow counter is all zero.

[0090] It should be noted that the term "connection" used in the present application includes direct connection and indirect connection, which can be, for example, connection via a SPL or CB device.

[0091] The input signal of the superconducting pulse counter is a fast single-flux-quantum pulse signal, the overflow signal can be a fast single-flux-quantum pulse signal or a level signal, and the N-bit count value output signal is a level signal. After a single-flux-quantum pulse signal is input to the signal input end of the superconducting pulse counter, the counter outputs a binary count value represented by the high and low levels of the output end of the superconducting pulse counter after a time delay. When a single-flux-quantum pulse signal is input again to the superconducting signal input end, the binary value output by the output end of the superconducting pulse counter is incremented by one. When the N-bit output count reaches the maximum value of all 1s, the input of the superconducting pulse signal is continued, the overflow counter outputs an overflow signal or changes the level output value to represent that the count value is full overflow, and the counter output value is reset to zero.

[0092] The application realizes a superconducting pulse counter by using the existing RSFQ superconducting circuit process. After m superconducting pulses are input to the input end of the counter, the binary count of m can be output at the output end of the counter. The counter can be used in the PC address generation and clock frequency division of a superconducting processor.

[0093] Although the application has been described by preferred embodiments, the application is not limited to the embodiments described herein, and various changes and variations can be made without departing from the scope of the application.

Claims

1. A 1-bit superconducting pulse counter, comprising: A superconducting XOR gate includes a first input terminal for receiving a superconducting pulse signal, a clock terminal for receiving the superconducting pulse signal, an output terminal for outputting data, and a second input terminal for receiving data from the output terminal of the superconducting XOR gate. The DFFC flip-flop includes an input terminal for receiving data from the output terminal of the superconducting XOR gate, a clock terminal for receiving the superconducting pulse signal, and a first output terminal and a second output terminal for outputting data; and, The Q-D converter includes a first input terminal for receiving data from a first output terminal of the DFFC flip-flop, a second input terminal for receiving data from a second output terminal of the DFFC flip-flop, and an output terminal for outputting a level signal. Wherein, the time when the superconducting pulse signal arrives at the clock terminal of the superconducting XOR gate is later than the time when the superconducting pulse signal arrives at the first input terminal of the superconducting XOR gate; and the time when the superconducting pulse signal arrives at the clock terminal of the superconducting XOR gate is substantially the same as the time when the superconducting pulse signal arrives at the clock terminal of the DFFC flip-flop.

2. The 1-bit superconducting pulse counter according to claim 1 further includes a first SPL, which includes an input terminal for receiving data from the second output terminal of the DFFC flip-flop, a first output terminal for outputting data to the second input terminal of the Q_D converter, and a second output terminal for outputting a carry signal.

3. The 1-bit superconducting pulse counter according to claim 1 or 2, wherein, The DFFC trigger also includes a reset terminal for receiving a reset signal.

4. An N-bit superconducting pulse counter, comprising N 1-bit superconducting pulse counters as described in claim 2, wherein N is an integer greater than 1; The first 1-bit superconducting pulse counter is used to receive superconducting pulse signals, output the first bit level signal, and output the carry signal; The Nth 1-bit superconducting pulse counter is used to receive the carry signal from the (N-1)th superconducting pulse counter, output the Nth bit level signal, and output the carry signal. in, In superconducting pulse technology, the time when the superconducting pulse signal arrives at the clock terminal of the superconducting XOR gate is later than the time when the superconducting pulse signal arrives at the first input terminal of the superconducting XOR gate; The time when the superconducting pulse signal arrives at the clock terminal of the superconducting XOR gate is substantially the same as the time when the superconducting pulse signal arrives at the clock terminal of the DFFC flip-flop.

5. The N-bit superconducting pulse counter according to claim 4, wherein, Each DFFC flip-flop in a 1-bit superconducting pulse counter also includes a reset terminal for receiving a reset signal.

6. The N-bit superconducting pulse counter according to claim 4, wherein, The N-bit superconducting pulse counter further includes an overflow counter, which comprises: A superconducting XOR gate includes a first input terminal and a clock terminal for receiving a carry signal from the Nth 1-bit superconducting pulse counter, an output terminal for outputting data, and a second input terminal for receiving data from the output terminal of the superconducting XOR gate. The DFFC flip-flop includes an input terminal for receiving data from the output terminal of the superconducting XOR gate, a clock terminal for receiving the carry signal from the Nth 1-bit superconducting pulse counter, and a first output terminal and a second output terminal for outputting data; and, The Q-D converter includes a first input terminal for receiving data from a first output terminal of the DFFC flip-flop, a second input terminal for receiving data from a second output terminal of the DFFC flip-flop, and an output terminal for outputting a level signal.

7. The N-bit superconducting pulse counter according to claim 6, wherein, The DFFC trigger also includes a reset terminal for receiving a reset signal.

8. The N-bit superconducting pulse counter according to claim 4, wherein, The N-bit superconducting pulse counter also includes an overflow counter, comprising: A superconducting XOR gate includes a first input terminal and a clock terminal for receiving a carry signal from the Nth 1-bit superconducting pulse counter, an output terminal for outputting data, and a second input terminal for receiving data from the output terminal of the superconducting XOR gate. The DFF flip-flop includes an input for receiving data from the output of a superconducting XOR gate, a clock input for receiving a carry signal from the Nth 1-bit superconducting pulse counter, and an output for outputting an overflow signal.

9. The N-bit superconducting pulse counter according to claim 8, wherein, The DFF trigger also includes a reset terminal for receiving a reset signal.

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