Ramp signal correction method and correction device, processing device, and image sensor

Abstract

The present invention provides a ramp signal correction method and correction device, processing device, and image sensor. The ramp signal correction method includes: an initialization phase and a correction phase; the initialization phase includes: obtaining the count value of the counter corresponding to the reference ramp signal corresponding to the reference pixel signal in the VR phase; and obtaining the count value of the counter corresponding to the ramp signals with different slopes in the VS phase; calculating the difference between the count values ​​of the ramp signals corresponding to the VR phase and the VS phase; the initialization phase is completed and the correction phase is entered; the correction phase includes: obtaining the actual count value of the counter corresponding to the actual ramp signal corresponding to the actual pixel signal in the VS phase; comparing the magnitude relationship between the actual count value and the above count value, and outputting according to the comparison result. The ramp signal correction method proposed by the present invention can correct the different offset errors of the SS‑ADC caused by the ramp signals with different slopes, and further ensure the linearity of the CIS.

Description

Technical Field

[0001] The present invention is mainly applied to the field of integrated circuit design, and specifically relates to a ramp signal correction method and correction device, a processing device, and an image sensor applied to a CMOS image sensor (CIS). Background Art

[0002] CMOS image sensors (CIS) have been widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and home appliances. The mainstream readout circuit structure of CIS is a readout circuit based on a column-level single-slope analog-to-digital converter (SS-ADC) to ensure that CIS has sufficient conversion accuracy and speed under reasonable power consumption. The main disadvantage of this structure is that the counting cycle required for conversion is long, and its counting cycle increases exponentially with the ADC resolution. For example, a 12-bit SS-ADC requires 4095 counting cycles. In applications where the resolution and frame rate of CIS are high, the readout circuit structure based on the traditional SS-ADC can no longer meet such requirements. For this reason, some designs use a slope-segmented SS-ADC structure, which greatly shortens the time of the integral signal conversion stage and improves the frame rate of CIS. However, due to the different slopes of the ramp signal, the signal offset difference obtained by the SS-ADC conversion is different, which greatly increases the nonlinear error of the SS-ADC.

[0003] Therefore, the present invention proposes a ramp signal correction method and correction device, a processing device, and an image sensor to correct different offset errors of SS-ADC caused by ramp signals with different slopes. Summary of the invention

[0004] The embodiments of the present invention provide a ramp signal correction method and correction device, a processing device, and an image sensor to correct different offset errors of SS-ADC caused by ramp signals with different slopes.

[0005] In a first aspect, the present invention provides a ramp signal correction method, comprising: an initialization phase and a correction phase;

[0006] The initialization phase includes:

[0007] Acquire a reference ramp signal in a first ramp stage corresponding to a reference pixel signal output by a column of pixel units, obtain a reference count value of a counter according to the reference ramp signal, and reset the counter; acquire a first ramp signal in a second ramp stage, obtain a first count value of the counter according to the first ramp signal, and reset the counter; acquire a second ramp signal in a second ramp stage, obtain a second count value of the counter according to the second ramp signal, and reset the counter; acquire a third ramp signal in a second ramp stage, obtain a third count value of the counter according to the third ramp signal, and reset the counter;

[0008] The slope of the first ramp signal is equal to the slope of the reference ramp signal, the slope of the second ramp signal is M times the slope of the first ramp signal, the slope of the third ramp signal is N times the slope of the second ramp signal, and both M and N are greater than 1;

[0009] Calculating a first difference value, where the first difference value is a difference between the reference count value and the second count value; calculating a second difference value, where the second difference value is a difference between the reference count value and the third count value;

[0010] The correction phase includes:

[0011] Acquire an actual ramp signal in the second ramp stage corresponding to an actual pixel signal output by a pixel unit of a corresponding column in the pixel array, and obtain an actual count value of a counter according to the actual ramp signal;

[0012] When the actual count value is less than or equal to the first count value, the actual count value is output; when the actual count value is greater than the first count value and less than or equal to the second count value, a first true value is output, and the first true value is the difference between the actual count value and the first difference value; when the actual count value is greater than the second count value and less than or equal to the third count value, a second true value is output, and the second true value is the difference between the actual count value and the second difference value.

[0013] The beneficial effect is that the ramp signal correction method proposed in the present invention can correct different offset errors of the SS-ADC caused by ramp signals with different slopes, thereby further ensuring the linearity of the CIS.

[0014] Optionally, the M is less than or equal to 3, and the N is less than or equal to 3.

[0015] In a second aspect, the present invention provides a ramp signal correction device, configured to perform the ramp signal correction method described in any one of the first aspects, including: an initialization module and a correction module;

[0016] The initialization module includes an acquisition module and a calculation module. The acquisition module includes a reference value acquisition unit, a first value acquisition unit, a second value acquisition unit and a third value acquisition unit. The calculation module includes a first calculation unit and a second calculation unit.

[0017] The reference value acquisition unit is used to acquire a reference ramp signal corresponding to a reference pixel signal output by a column of pixel units in a first ramp stage, and obtain a reference count value of the counter according to the reference ramp signal; the first value acquisition unit is used to acquire a first ramp signal in a second ramp stage, and obtain a first count value of the counter according to the first ramp signal; the second value acquisition unit is used to acquire a second ramp signal in a second ramp stage, and obtain a second count value of the counter according to the second ramp signal; the third value acquisition unit is used to acquire a third ramp signal in a second ramp stage, and obtain a third count value of the counter according to the third ramp signal;

[0018] The slope of the first ramp signal is equal to the slope of the reference ramp signal, the slope of the second ramp signal is M times the slope of the first ramp signal, the slope of the third ramp signal is N times the slope of the second ramp signal, and both M and N are greater than 1;

[0019] The first calculation unit is used to calculate a first difference value, where the first difference value is the difference between the reference count value and the second count value; the second calculation unit is used to calculate a second difference value, where the second difference value is the difference between the reference count value and the third count value;

[0020] The correction module includes an actual value acquisition unit, a judgment unit, and an output unit;

[0021] The actual value acquisition unit is used to acquire the actual ramp signal corresponding to the actual pixel signal output by the pixel unit of the corresponding column in the pixel array in the second ramp stage, and obtain the actual count value of the counter according to the actual ramp signal;

[0022] The judging unit is used to judge the relationship between the actual count value and the first count value, the second count value and the third count value;

[0023] When the actual count value is less than or equal to the first count value, the output unit is used to output the actual count value; when the actual count value is greater than the first count value and less than or equal to the second count value, the output unit is used to output a first true value, and the first true value is the difference between the actual count value and the first difference value; when the actual count value is greater than the second count value and less than or equal to the third count value, the output unit is used to output a second true value, and the second true value is the difference between the actual count value and the second difference value.

[0024] Optionally, the M is less than or equal to 3, and the N is less than or equal to 3.

[0025] Further optionally, the ramp signal correction device further includes a reset control module;

[0026] The reset control module is used to control the resetting of the counter when the reference value acquisition unit obtains the reference count value of the counter; it is also used to control the resetting of the counter when the first value acquisition unit obtains the first count value of the counter; it is also used to control the resetting of the counter when the second value acquisition unit obtains the second count value of the counter; it is also used to control the resetting of the counter when the third value acquisition unit obtains the third count value of the counter.

[0027] In a third aspect, the present invention provides a ramp signal processing device, comprising: a ramp wave generator and a ramp wave signal correction device as described in any one of the second aspects.

[0028] The fourth invention provides an image sensor, comprising: a pixel array composed of pixel units, an ADC module, the ramp signal processing device as described in the third aspect, a timing control module, a row selection decoding driving module, and an output signal processing module;

[0029] The row selection decoding driving module is used to control the pixel array to output pixel signals;

[0030] The ramp wave generator is used to output a ramp wave signal;

[0031] The ADC module includes a comparator and a counter, wherein the comparator is used to compare the pixel signal with the ramp signal, and the counter is used to output a current count value when the comparator is deflected;

[0032] The ramp signal correction device is used to correct the current count value of the counter and send the corrected value to the output signal processing device;

[0033] The timing control module is used to control the working state of the image sensor.

[0034] For the beneficial effects of the second to fourth aspects, reference may be made to the description of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a CIS standard four-pixel unit circuit structure;

[0036] Figure 2 It is the working timing of a standard four-pixel unit;

[0037] Figure 3 A schematic diagram of the structure of a CIS readout circuit;

[0038] Figure 4 A working timing of a CIS readout circuit;

[0039] Figure 5 A flowchart of the initialization phase of a ramp signal correction method provided by the present invention;

[0040] Figure 6 A flow chart of the correction phase of a ramp signal correction method adopted by the present invention;

[0041] Figure 7 A schematic diagram of the working principle of a ramp signal correction method provided by the present invention;

[0042] Figure 8 A schematic diagram of a ramp signal correction device provided by the present invention. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present application. As used in the specification and the appended claims of the present application, the singular expressions "a kind", "the", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in a kind of "or" relationship.

[0044] References to "one embodiment" or "some embodiments" etc. described in this specification mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. The term "connection" includes direct connection and indirect connection, unless otherwise specified. "First" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0045] In the embodiments of the present application, the words "exemplarily" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.

[0046] Figure 1It is a CIS standard four-tube pixel unit circuit structure, which is widely used in CIS with row exposure mode. It consists of a photodiode PD, a transfer transistor Mtg, a reset transistor Mrst, a source follower transistor Msf, and a row selection transistor Msel. The photodiode PD is grounded at one end and connected to the drain of the transfer transistor Mtg at the other end; the gate of the transfer transistor Mtg is used to access the TX signal, the source of the transfer transistor Mtg is connected to the drain of the reset transistor Mrst, and connected to the gate of the source follower transistor Msf; the source of the reset transistor Mrst is connected to the power supply, and the gate of the reset transistor Mrst is connected to the RX signal; the source of the source follower transistor Msf is connected to the power supply, the drain of the source follower transistor Msf is connected to the source of the row selection transistor Msel, the gate of the row selection transistor Msel is connected to the SEL signal, and the drain of the row selection transistor Msel is connected to the row output line of the pixel array. When the photodiode PD is exposed to light, it generates photoelectrons proportional to the light intensity. The function of the transfer transistor Mtg is to transfer the photoelectrons in the photodiode PD. When the TX signal is at a high potential, the transfer transistor Mtg is turned on, and the photoelectrons in the photodiode PD are transferred to the floating node FD. The function of the reset transistor Mrst is to reset the potential of the floating point FD when the RX signal is at a high potential. The source follower transistor Msf is an amplifier. When SEL is at a high potential, the row selection transistor Msel is turned on, and the source follower transistor Msf, the row selection transistor Msel and the current source to the ground form a path. At this time, the source follower transistor Msf follows the change of the floating point FD potential and is finally output by the output bus PIX_OUT.

[0047] Figure 2 for Figure 1The working sequence of the four-tube pixel unit shown is divided into reset (Rst), exposure (Exp), and signal reading (Read). In the Rst stage, the TX signal and the RX signal are at a "high" potential, the transfer transistor Mtg and the reset transistor Mrst are both turned on, the floating point FD is reset and its potential is pulled up to the power supply voltage VDD. After that, the RX signal and the TX signal become "low" potentials, and the Exp stage is entered, and the floating point PD is sensitive to light and accumulates electrons. Then, the Read stage is entered, SEL is at a "high" potential, the RX signal is first at a "high" potential, and after resetting the potential of the floating point FD, the RX signal is pulled to a "low" potential again, and the TX signal remains at a "low" potential. At this time, the source follower transistor Msf is controlled by the floating point FD potential and outputs the reset potential VRST through the output bus PIX_OUT. After that, the TX signal is pulled to a "high" potential, and the electrons on the photodiode PD are transferred to the floating point FD. At this time, the source follower transistor Msf is controlled by the potential of the floating point FD and outputs the integration potential VSIG through the output bus PIX_OUT. The difference between VRST and VSIG is the analog voltage corresponding to the photoelectrons on the photodiode PD. The VRST and VSIG potentials are converted into digital quantities by the analog-to-digital converter (ADC) circuit and subtracted to obtain the actual digital quantity corresponding to the photoelectrons on the photodiode PD. If the ADC is 12 bits and the ADC reference voltage range is VREF, the final output is DOUT = (VRST-VSIG) × 2 12 / VREF.

[0048] Figure 3 The structure diagram of the CIS readout circuit includes: a pixel array, an ADC module, a ramp generator, a timing control module, a row selection decoding drive module, and an output signal processing module. Figure 1 The pixel unit P shown is composed of the pixel unit P shown. The pixel array is read out row by row, and the specific order is ROW(0), ROW(1), ... ROW(k-1), ROW(k). The k is a positive integer. Each column in the pixel array is connected to an output bus, and these output buses are PIX_OUT(0), PIX_OUT(1), ... PIX_OUT(n-1), PIX_OUT(n). The output ends of these output buses are connected to the ADC module. The ADC module is composed of a comparator and a counter. The comparator compares the output pixel signal with the ramp signal RAMP, and the comparison result determines the size of the counter count value. The ADC module will also judge the above-mentioned VRST and VSIG potentials respectively, and convert the VRST-VSIG difference into a digital output.

[0049] Figure 4 for Figure 3 The working timing of the CIS readout circuit shown is Figure 2 The Read phase of the timing. Entering the Read phase, SEL is pulled to a "high" potential, RX is a "high" potential, and the pixel unit is reset. RST_CM is the comparator reset control signal, and RST_CM is also pulled to a "high" potential to reset the comparators in all ADC modules. Then RX and RST_CM change from a "high" potential to a "low" potential, and the ADC module enters a normal working state. The working process of the ADC module consists of two processes: comparison and counting. First, when the ramp RAMP potential begins to decrease, the counter CNT starts counting until the comparator signal flips from a "low" potential to a "high" potential. The counter CNT stops counting and stores the current count value. To complete the analog-to-digital conversion of the pixel signal, the ADC module needs to perform the above operation twice, that is, as the benchmark of the ADC module, two ramps will be generated. The first ramp stage (that is, Figure 4 The ADC module will determine and store the reset potential VRST, and the counter CNT will count and store the count value CN1 corresponding to the t1 period during the t1 period; the second ramp stage (i.e. Figure 4 In the "VS phase" of the ADC, the ADC module will determine and store the reset potential VSIG, and the counter CNT will count and store the count value CN2 corresponding to the t2 time period within the t2 time period. Finally, the counter CNT will output the count difference ΔCN=CN2-CN1, which corresponds to the difference of VSIG-VRST. The above timing is the traditional SS-ADC conversion process. It can be seen that the main time required for the traditional SS-ADC conversion is the "VS phase". A 12-bit SS-ADC needs to consume at least 4095 counting cycles in its "VS phase". In order to shorten the time of the "VS phase", the prior art proposes a slope-segmented SS-ADC, which is to divide the ramp signal of the "VS phase" into several ramp signal phases with different slopes, such as Figure 4 As shown by the dotted line of the "VS stage", the "VS stage" is divided into three stages: "VS1, VS2, and VS3" (corresponding to the three amplitudes of "small", "medium", and "large" in the pixel signal, respectively). After these three stages are completed, the same signal amplitude range as the traditional SS-ADC can still be achieved.

[0050] Since the main noise of CIS comes from readout noise under low light conditions, the slope of the ramp signal in the "VS1 stage" remains consistent with that in the "VR stage", and the conversion accuracy in the "VS1 stage" is higher. The least significant bit LSB of the ADC module is 1 / 2 12V (assuming the effective signal range of the ADC module is 1V), which can ensure the integrity of the image details under low light conditions of the CIS; as the light intensity increases, the shot noise of the photoelectrons will become the dominant factor of the CIS noise. At this time, the quantization noise of the analog-to-digital converter is very small compared to the shot noise, and the accuracy of the ADC module can be appropriately reduced. Therefore, the slope of the ramp signal in the "VS2 stage" is doubled compared to the slope of the ramp signal in the "VS1 stage", making one LSB 1 / 2 6 V; Similarly, when the light intensity is greater, the ADC accuracy can be further reduced. The slope of the ramp signal in the "VS3 stage" is doubled compared to the slope of the ramp signal in the "VS2 stage", making one LSB 1 / 2 3 V. As the slope increases, the time for the comparator to deflect will be shortened, that is, the time for the counter to count will be shortened, and the counting time of the "VS2 stage" is shorter than that of the original SS-ADC. Similarly, the counting time of the "VS3 stage" will also be shorter than that of the original SS-ADC. It can be seen that this SS-ADC based on the use of slope segmentation in the "VS stage" can effectively improve the SS-ADC conversion speed. However, since the slope of the ramp wave in the "VS2 stage" and "VS3 stage" is different from that in the "VR stage", the flip delay of the comparator must be different. In this way, there will be different delay times for the conversion of the ADC signal in the three stages of "VS1, VS2, and VS3", which will cause different offset errors in the signals of the three amplitudes of the pixel signal "small", "medium", and "large", affecting the linearity of the final CIS image.

[0051] In order to solve the influence of the above-mentioned misalignment error on the CIS image, the present invention provides a ramp signal correction method, including: an initialization stage and a correction stage.

[0052] The specific process of the initialization phase is as follows Figure 5 As shown, including:

[0053] S501: obtaining a reference ramp signal corresponding to a reference pixel signal output by a column of pixel units in a first ramp stage (VR stage), obtaining a reference count value of a counter according to the reference ramp signal, and resetting the counter;

[0054] S502: Acquire a first ramp signal in a second ramp stage (VS stage), obtain a first count value of a counter according to the first ramp signal, and reset the counter;

[0055] S503: Acquire a second ramp signal in the VS phase, obtain a second count value of a counter according to the second ramp signal, and reset the counter;

[0056] S504: Acquire a third ramp signal in the VS phase, obtain a third count value of a counter according to the third ramp signal, and reset the counter; wherein the slope of the first ramp signal is equal to the slope of the reference ramp signal, the slope of the second ramp signal is M times the slope of the first ramp signal, the slope of the third ramp signal is N times the slope of the second ramp signal, and both M and N are greater than 1;

[0057] S505: Calculate a first difference value, where the first difference value is a difference between the reference count value and the second count value;

[0058] S506: Calculate a second difference value, where the second difference value is a difference between the reference count value and the third count value.

[0059] The process of the calibration phase is as follows Figure 6 As shown, including:

[0060] S601: Acquire an actual ramp signal corresponding to an actual pixel signal output by a pixel unit of a corresponding column in a pixel array in a VS phase, and obtain an actual count value of a counter according to the actual ramp signal;

[0061] S602: Determine the magnitude relationship between the actual count value and the first count value, the second count value, and the third count value, and output a numerical value according to the determination result.

[0062] S602 is specifically as follows: when the actual count value is less than or equal to the first count value, output the actual count value; when the actual count value is greater than the first count value and less than or equal to the second count value, output a first true value, the first true value being the difference between the actual count value and the first difference value; when the actual count value is greater than the second count value and less than or equal to the third count value, output a second true value, the second true value being the difference between the actual count value and the second difference value.

[0063] Optionally, the M is less than or equal to 3, and the N is less than or equal to 3.

[0064] For example, in the CIS conversion process, the first frame is generally an initialization frame, in which various CIS parameters such as gain, exposure time, frequency, etc. are determined. In the initialization frame, the input terminal of the ADC is first grounded ( Figure 3 In the figure, "SW" is at a high potential to turn on switches S(0), S(1), ...S(n)). Then it enters the initialization phase, which has two detection processes. One is the detection process of the counting delay difference caused by the ramp signal of the "VS2 phase" and the ramp signal of the "VR phase" that causes the comparator to deflect, and the other is the detection process of the delay difference between the ramp signal of the "VS3 phase" and the "VR phase". Figure 7 As shown, the first process: obtaining the reference pixel signal output by a column of pixel units corresponding to the reference ramp signal RAMP_R in the "VR stage", and obtaining the reference count value CN_R of the counter according to the reference ramp signal RAMP_R, and resetting the counter; obtaining the first ramp signal RAMP_S1 of the "VS stage", and obtaining the first count value CN_S1 of the counter according to the first ramp signal RAMP_S1, and resetting the counter, the slope of the first ramp signal RAMP_S1 is equal to the slope of the reference ramp signal RAMP_R, so CN_S1 is equal to CN_R.

[0065] Next, the second ramp signal RAMP_S2 of the "VS stage" is obtained, and the second count value CN_S2 of the counter is obtained according to the second ramp signal RAMP_S2, and the counter is reset. The slope of the second ramp signal RAMP_S2 is twice the slope of the first ramp signal RAMP_S1, and the first difference ΔCN_VS2 is calculated, that is, the difference between the reference count value CN_R and the second count value CN_S2, ΔCN_VS2 = CN_S2-CN_R. ΔCN_VS2 is temporarily stored. The reference count value CN_R contains the flip delay information D_R of the comparator when the ramp signal has a normal slope. CN_S2 contains the flip delay information D_S2 of the comparator when the ramp signal has a slope twice as large, so the first difference ΔCN_VS2 is the digital value corresponding to the flip delay difference between the signal in the VS2 stage and the comparator in the "VR" stage.

[0066] Finally, the third ramp signal RAMP_S3 of the "VS stage" is obtained, and according to the third ramp signal RAMP_S3, the third count value CN_S3 of the counter is obtained, and the counter is reset. The slope of the third ramp signal RAMP_S3 is twice the slope of the second ramp signal RAMP_S2. The second difference ΔCN_VS3 is calculated, that is, the difference between the reference count value CN_R and the third count value CN_S3 is calculated, ΔCN_VS3 = CN_S3-CN_R. ΔCN_VS3 is the delay difference of the slope of the "VS3 stage", and this value is also temporarily stored. After the initialization stage is completed, other parameters such as gain, exposure time, etc. will continue to be configured in the initial frame CIS.

[0067] Next is the correction stage. Entering the normal frame, the actual ramp signal corresponding to the actual pixel signal output by the pixel unit of the corresponding column in the pixel array in the "VS stage" is obtained, and the actual count value CN_T of the counter is obtained according to the actual ramp signal; when the actual count value CN_T is less than or equal to the first count value CN_S1, the actual count value CN_T is output; when the actual count value CN_T is greater than the first count value CN_S1, and less than or equal to the second count value CN_S2, the first true value CN_T1 is output, and the first true value CN_T1 is the difference between the actual count value CN_T and the first difference ΔCN_VS2; when the actual count value CN_T is greater than the second count value CN_S2, and less than or equal to the third count value CN_S3, the second true value CN_T2 is output, and the second true value CN_T2 is the difference between the actual count value CN_T and the second difference ΔCN_VS3.

[0068] The ramp signal correction method proposed in the present invention can correct different offset errors of the SS-ADC caused by ramp signals with different slopes, thereby further ensuring the linearity of the CIS.

[0069] The present invention also provides a ramp signal correction device, such as Figure 8 As shown, the method for correcting the ramp signal as described in any one of the above embodiments includes: an initialization module 801 and a correction module 802.

[0070] The initialization module 801 includes an acquisition module 8011 and a calculation module 8012. The acquisition module 8011 includes a reference value acquisition unit 80111, a first value acquisition unit 80112, a second value acquisition unit 80113 and a third value acquisition unit 80114; the calculation module 8012 includes a first calculation unit 80121 and a second calculation unit 80122.

[0071] The reference value acquisition unit 80111 is used to acquire the reference ramp signal corresponding to the reference pixel signal output by a column of pixel units in the "VR stage", and obtain the reference count value of the counter based on the reference ramp signal; the first value acquisition unit 80112 is used to acquire the first ramp signal of the "VS stage", and obtain the first count value of the counter based on the first ramp signal; the second value acquisition unit 80113 is used to acquire the second ramp signal of the "VS stage", and obtain the second count value of the counter based on the second ramp signal; the third value acquisition unit 80114 is used to acquire the third ramp signal of the "VS stage", and obtain the third count value of the counter based on the third ramp signal. Among them, the slope of the first ramp signal is equal to the slope of the reference ramp signal, the slope of the second ramp signal is M times the slope of the first ramp signal, the slope of the third ramp signal is N times the slope of the second ramp signal, and both M and N are greater than 1; the first calculation unit 80121 is used to calculate a first difference, and the first difference is the difference between the reference count value and the second count value; the second calculation unit 80122 is used to calculate a second difference, and the second difference is the difference between the reference count value and the third count value.

[0072] The correction module 802 includes an actual value acquisition unit 8021, a judgment unit 8022, and an output unit 8023; the actual value acquisition unit 8021 is used to obtain the actual ramp signal corresponding to the actual pixel signal output by the pixel unit of the corresponding column in the pixel array in the "VS stage", and obtain the actual count value of the counter according to the actual ramp signal; the judgment unit 8022 is used to judge the relationship between the actual count value and the first count value, the second count value and the third count value; when the actual count value is less than or equal to the first count value, the output unit 8023 is used to output the actual count value; when the actual count value is greater than the first count value and less than or equal to the second count value, the output unit 8023 is used to output a first true value, and the first true value is the difference between the actual count value and the first difference value; when the actual count value is greater than the second count value and less than or equal to the third count value, the output unit 8023 is used to output a second true value, and the second true value is the difference between the actual count value and the second difference value.

[0073] Optionally, the M is less than or equal to 3, and the N is less than or equal to 3.

[0074] Further optionally, the ramp signal correction device also includes a reset control module; the reset control module is used to control the resetting of the counter when the reference value acquisition unit obtains the reference count value of the counter; it is also used to control the resetting of the counter when the first value acquisition unit obtains the first count value of the counter; it is also used to control the resetting of the counter when the second value acquisition unit obtains the second count value of the counter; it is also used to control the resetting of the counter when the third value acquisition unit obtains the third count value of the counter.

[0075] Based on the ramp signal correction device described in any one of the above embodiments, the present invention provides a ramp signal processing device, including: a ramp wave generator and the ramp signal correction device described in any one of the above embodiments.

[0076] Based on the ramp signal processing device provided by the present invention, the present invention further provides an image sensor, comprising: a pixel array composed of pixel units, an ADC module, the ramp signal processing device as described in the above embodiment, a timing control module, a row selection decoding driving module, and an output signal processing module; the row selection decoding driving module is used to control the pixel array to output a pixel signal; the ramp generator is used to output a ramp signal; the ADC module includes a comparator and a counter, the comparator is used to compare the pixel signal with the ramp signal, and the counter is used to output a current count value when the comparator is deflected; the ramp signal correction device is used to correct the current count value of the counter and send the corrected value to the output signal processing device; the timing control module is used to control the working state of the image sensor.

[0077] The above is only a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed in the embodiment of the present application should be included in the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiment of the present application should be based on the protection scope of the claims.

Claims

1. A ramp signal correction method, characterized in that: include: Initialization phase and calibration phase; The initialization phase includes: Acquire a reference ramp signal in a first ramp stage corresponding to a reference pixel signal output by a column of pixel units, obtain a reference count value of a counter according to the reference ramp signal, and reset the counter; acquire a first ramp signal in a second ramp stage, obtain a first count value of the counter according to the first ramp signal, and reset the counter; acquire a second ramp signal in a second ramp stage, obtain a second count value of the counter according to the second ramp signal, and reset the counter; acquire a third ramp signal in a second ramp stage, obtain a third count value of the counter according to the third ramp signal, and reset the counter; The slope of the first ramp signal is equal to the slope of the reference ramp signal, the slope of the second ramp signal is M times the slope of the first ramp signal, the slope of the third ramp signal is N times the slope of the second ramp signal, and both M and N are greater than 1; Calculating a first difference value, where the first difference value is a difference between the reference count value and the second count value; calculating a second difference value, where the second difference value is a difference between the reference count value and the third count value; The correction phase includes: Acquire an actual ramp signal corresponding to an actual pixel signal output by a pixel unit of a corresponding column in a pixel array in a VS phase, and obtain an actual count value of a counter according to the actual ramp signal; When the actual count value is less than or equal to the first count value, the actual count value is output; when the actual count value is greater than the first count value and less than or equal to the second count value, a first true value is output, and the first true value is the difference between the actual count value and the first difference value; when the actual count value is greater than the second count value and less than or equal to the third count value, a second true value is output, and the second true value is the difference between the actual count value and the second difference value.

2. The ramp signal correction method according to claim 1, characterized in that: The M is less than or equal to 3, and the N is less than or equal to 3.

3. A ramp signal correction device, characterized in that: The device is configured to perform the ramp signal correction method according to any one of claims 1 to 2, comprising: an initialization module and a correction module; The initialization module includes an acquisition module and a calculation module. The acquisition module includes a reference value acquisition unit, a first value acquisition unit, a second value acquisition unit and a third value acquisition unit. The calculation module includes a first calculation unit and a second calculation unit. The reference value acquisition unit is used to acquire a reference ramp signal corresponding to a reference pixel signal output by a column of pixel units in a first ramp stage, and obtain a reference count value of the counter according to the reference ramp signal; the first value acquisition unit is used to acquire a first ramp signal in a second ramp stage, and obtain a first count value of the counter according to the first ramp signal; the second value acquisition unit is used to acquire a second ramp signal in a second ramp stage, and obtain a second count value of the counter according to the second ramp signal; the third value acquisition unit is used to acquire a third ramp signal in a second ramp stage, and obtain a third count value of the counter according to the third ramp signal; The slope of the first ramp signal is equal to the slope of the reference ramp signal, the slope of the second ramp signal is M times the slope of the first ramp signal, the slope of the third ramp signal is N times the slope of the second ramp signal, and both M and N are greater than 1; The first calculation unit is used to calculate a first difference value, where the first difference value is the difference between the reference count value and the second count value; the second calculation unit is used to calculate a second difference value, where the second difference value is the difference between the reference count value and the third count value; The correction module includes an actual value acquisition unit, a judgment unit, and an output unit; The actual value acquisition unit is used to acquire the actual ramp signal corresponding to the actual pixel signal output by the pixel unit of the corresponding column in the pixel array in the second ramp stage, and obtain the actual count value of the counter according to the actual ramp signal; The judging unit is used to judge the relationship between the actual count value and the first count value, the second count value and the third count value; When the actual count value is less than or equal to the first count value, the output unit is used to output the actual count value; when the actual count value is greater than the first count value and less than or equal to the second count value, the output unit is used to output a first true value, and the first true value is the difference between the actual count value and the first difference value; when the actual count value is greater than the second count value and less than or equal to the third count value, the output unit is used to output a second true value, and the second true value is the difference between the actual count value and the second difference value.

4. The ramp signal correction device according to claim 3, characterized in that: The M is less than or equal to 3, and the N is less than or equal to 3.

5. The ramp signal correction device according to claim 3, characterized in that: Also includes a reset control module; The reset control module is used for controlling the counter to reset when the reference value acquisition unit obtains the reference count value of the counter; is also used for controlling the counter to reset when the first value acquiring unit obtains the first count value of the counter; is also used for controlling the counter to reset when the second value obtaining unit obtains the second count value of the counter; It is also used to control the counter to reset when the third value acquisition unit obtains the third count value of the counter.

6. A ramp signal processing device, characterized in that: include: A ramp wave generator and a ramp wave signal correction device as claimed in any one of claims 3 to 5.

7. An image sensor, characterized in that: include: A pixel array composed of pixel units, an ADC module, a ramp signal processing device as claimed in claim 6, a timing control module, a row selection decoding drive module, and an output signal processing module; The row selection decoding driving module is used to control the pixel array to output pixel signals; The ramp wave generator is used to output a ramp wave signal; The ADC module includes a comparator and a counter, wherein the comparator is used to compare the pixel signal with the ramp signal, and the counter is used to output a current count value when the comparator is deflected; The ramp signal correction device is used to correct the current count value of the counter and send the corrected value to the output signal processing module; The timing control module is used to control the working state of the image sensor.

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