Digital-to-analog converter circuit system for a stimulator device with nonlinear amplitude adjustment

Abstract

A digital-to-analog converter (DAC) circuit system that can be used in a stimulator device is disclosed. The DAC circuit system produces an output current whose amplitude varies as a function of the amplitude value provided by a digital amplitude bus. The relationship between the output current and the amplitude (Iout(A)) can be linear or non-linear, depending on the current-voltage characteristics of the circuit in the DAC selected for use. For example, if a resistor is selected, the output current will vary linearly with the amplitude; if a p-n diode is selected, the output current will vary exponentially with the amplitude. The shape of Iout(A) affects the resolution of the output current, and depending on the circuit selected, the resolution can be made constant, or at least more constant, over the dynamic range of the DAC circuit system. The DAC circuit system is further beneficial in its ability to be programmed with minimum and maximum output currents.

Description

Technical Field

[0001] The present application relates to implantable stimulator devices, and in particular to current source circuitry for providing therapeutic current at electrodes of the device. Background Art

[0002] Implantable neurostimulator devices are devices that generate electrical stimulation and deliver it to nerves and tissues for the treatment of various biological diseases, such as pacemakers for treating cardiac arrhythmias, defibrillators for treating cardiac fibrillation, cochlear stimulators for treating deafness, retinal stimulators for treating blindness, muscle stimulators for producing coordinated limb movements, spinal cord stimulators for treating chronic pain, cortical and deep brain stimulators for treating movement and psychological disorders, and other neurostimulators for treating urinary incontinence, sleep apnea, shoulder subluxation, etc. The following description generally focuses on the use of the present invention in a spinal cord stimulation (SCS) system or a deep brain stimulation (DBS) system. However, the present invention can be applied to any implantable neurostimulator device system.

[0003] An SCS or DBS system typically includes an implantable pulse generator (IPG) 10 shown in FIG1 . The IPG 10 includes a biocompatible device housing 12 that houses circuitry and a battery 14 for providing power for the IPG to function. The IPG 10 is coupled to tissue stimulation electrodes 16 via one or more electrode leads forming an electrode array 17. For example, one or more percutaneous leads 15 having ring or open ring electrodes 16 carried on a flexible body 18 may be used. In another example, a paddle-shaped lead 19 provides an electrode 16 positioned on one of its generally flat surfaces. A guidewire 20 within the lead is coupled to the electrode 16 and to a proximal contact 21 that can be inserted into a lead connector 22 that is secured in a header 23 on the IPG 10 that can include, for example, epoxy. Once inserted, the proximal contacts 21 connect to header contacts 24 within the lead connector 22 , which in turn are coupled to stimulation circuitry 28 within the housing 12 through feedthrough pins 25 and through housing feedthroughs 26 .

[0004] In the IPG 10 shown, there are 32 electrodes (E1 to E32) divided between four percutaneous leads 15 or contained on a single paddle-shaped lead 19, and therefore the head 23 may include a 2×2 array of 8-electrode lead connectors 22. However, the type and number of leads, lead connectors, and electrodes in an IPG are application specific and therefore may vary. The conductive housing 12 may also include electrodes (Ec). In SCS applications, the electrode lead(s) are typically implanted in the patient's spinal cord in the spine near the dura mater, while the IPG is typically implanted under the skin in the gluteal area. In DBS applications, the electrode leads are typically implanted in specific areas of the brain, while the IPG is typically implanted under the skin under the clavicle or collarbone. In other examples of IPGs designed for direct implantation at the site where stimulation is desired, the IPG may be leadless, with the electrodes 16 instead present on the body of the IPG 10 for contacting the patient's tissue. In other solutions, the IPG lead(s) may be integrated with and permanently connected to the IPG 10. The goal of neurostimulation therapy is to provide electrical stimulation from the electrodes 16 to alleviate a patient's symptoms, such as chronic back pain in SCS applications, or tremors in DBS applications.

[0005] The IPG 10 may include an antenna 27a, allowing it to communicate bidirectionally with multiple external devices used to program or monitor the IPG (such as a handheld patient remote control or clinician programmer). For example, see U.S. Patent Application Publications 2015 / 0360038 and 2015 / 0231402. The antenna 27a shown includes a conductive coil within the housing 12, although the coil antenna 27a may also be present in the head 23. When the antenna 27a is configured as a coil, communication with the external device preferably occurs using near-field magnetic induction. The IPG 10 may also include a radio-frequency (RF) antenna 27b. In FIG1 , the RF antenna 27b is shown within the head 23, but it may also be within the housing 12. The RF antenna 27b may include a patch, a slot, or a wire and may operate as a monopole or a dipole. The RF antenna 27b preferably communicates using far-field electromagnetic waves and may operate according to any number of known RF communication standards, such as Bluetooth, Zigbee, MICS, etc. If the battery 14 is rechargeable, the IPG 10 may further include a charging coil (not shown) to wirelessly receive energy from an external charging device.

[0006] Stimulation in the IPG 10 is typically provided by pulses, and each pulse can include multiple phases, as shown in the example of FIG2A . The stimulation parameters of the pulses typically include amplitude (current I, although voltage amplitude V can also be used); frequency (F); pulse width (PW) of the pulse or its various phases; the electrodes 16 selected to provide the stimulation; and the polarity of these selected electrodes, i.e., whether they act as anodes supplying current to the tissue or cathodes sinking current from the tissue. These stimulation parameters, along with other stimulation parameters that may be employed, comprise a stimulation program that the stimulation circuitry 28 in the IPG 10 can execute to provide therapeutic stimulation to the patient.

[0007] In the example of FIG2A , electrode E4 has been selected as the anode (during its first phase 30 a) and thus provides a pulse of positive current supplying an amplitude of +I to the tissue. Electrode E5 has been selected as the cathode (again during the first phase 30 a) and thus provides a pulse of a corresponding negative current absorbing an amplitude of −I from the tissue. This is an example of bipolar stimulation, in which only two lead-based electrodes are used to provide stimulation to the tissue (one anode, one cathode). However, more than one electrode may be selected to act as an anode at a given time, and more than one electrode may be selected to act as a cathode at a given time. In the case of a so-called monopolar scenario, the housing electrode Ec (12) may also be selected to act as an electrode or current loop.

[0008] As mentioned above, the IPG 10 includes stimulation circuitry 28 to generate prescribed stimulation at the patient's tissue. FIG3A illustrates an example of stimulation circuitry 28, which includes a digital-to-analog converter (DAC) that provides analog current at the electrodes according to a prescribed amplitude, as further explained below. The depicted stimulation circuitry 28 includes multiple current sourcing circuits (PDACs) and multiple current sinking circuits (NDACs), so named based on the positive (supplied, anodic) and negative (sinked, cathodic) currents they source, respectively. In the illustrated example, the NDACi / PDACi pairs are dedicated to (hardwired to) specific electrode nodes ei. For reasons explained below, each of the electrode nodes ei is connected to one of the electrodes Ei 16 via a DC blocking capacitor Ci 38. The stimulation circuitry 28 in this example also supports the selection of the conductive housing 12 as the electrode (Ec 12), which is typically selected for monopolar stimulation. Although the PDACs and NDACs are assumed in this disclosure to comprise current sources capable of providing a prescribed constant current, they may also comprise voltage sources capable of providing a prescribed constant voltage.

[0009] Power for the stimulation circuitry 28 is provided by a compliance voltage VH. As described in further detail in U.S. Patent Application Publication 2013 / 0289665, compliance voltage VH can be generated by a compliance voltage generator 29, which can include circuitry for boosting the voltage (Vbat) of the battery 14 to a voltage VH sufficient to drive a prescribed current I through the tissue R. Compliance voltage generator 29 can include an inductor-based boost converter or a capacitor-based charge pump, as explained, for example, in U.S. Patent Application Publication 2018 / 0071512. Because the resistance of the tissue is variable, VH can also be variable and, in one example, can be as high as 18 volts. Although not shown, U.S. Patent Application Publication 2018 / 0071520 explains that the PDAC and NDAC can be powered by different power domains. For example, the PDAC can be powered using a first power domain that includes VH as a high power supply and VH-Vcc as a low power supply (both of which can vary because VH can vary). The NDAC may be powered using a second power domain including Vcc as a high power supply and ground (GND) as a low power supply.

[0010] Appropriate control of the stimulation circuitry 28 allows any of the electrodes 16 to act as an anode or cathode to generate a current through the patient's tissue R, hopefully with a therapeutic effect. The amplitude of the current provided by each NDACi is determined via a digital amplitude bus <ani>The PDACi is controlled to allow its associated electrode Ei to act as a cathode to sink a current of a specified magnitude from the tissue. Similarly, the magnitude of the current provided by each PDACi is controlled via the digital amplitude bus <api>Controlled, thereby allowing its associated electrode Ei to act as an anode to supply a current of a prescribed magnitude to the tissue.

[0011] Digital Amplitude Bus <ani>and <api>Other digital control signals for the DAC can be issued by digital control circuitry 40 in IPG 10. Digital control circuitry 40 can include a microcontroller, such as part number MSP430 manufactured by Texas Instruments, as described in the datasheet at http: / / www.ti.com / lsds / ti / microcontroller / 16-bit_msp430 / overview.page?DCMP=MCU_other&HQS=msp430. Control circuitry 40 can more generally include a microprocessor, a field programmable grid array, a programmable logic device, a digital signal processor, or the like, and can include a central processing unit capable of executing instructions stored in volatile or non-volatile memory within or associated with the control circuitry. Digital control circuitry 40 can be separate from stimulation circuitry 28; for example, each can be formed in its own integrated circuit. Alternatively, digital control circuitry 40 and stimulation circuitry 28 can be integrated on the same integrated circuit, such as an application-specific integrated circuit (ASIC). Various examples of digital control circuitry 40 and stimulation circuitry 28 and how they may be connected or integrated are provided in U.S. patent application publications 2008 / 0319497, 2012 / 0095529, 2018 / 0071513, 2018 / 0071520, or 2019 / 0083796.

[0012] FIG3A shows the programming of the stimulation circuitry 28 necessary to create the first stage 30a of FIG2A, wherein electrodes E4 and E5 are selected as the anode and cathode, respectively, to create a current of amplitude I through the tissue. In this example, the digital amplitude bus serving PDAC4 <ap4>is set to have an amplitude value X corresponding to the desired current amplitude I, serving the bus of NDAC5 <an5>These buses will be asserted at specific times to produce the desired current I with the correct timing (e.g., according to the specified frequency F and pulse width PWa). During the second phase 30b (PWb), PDAC5 and NDAC4 will be asserted via the digital amplitude bus <ap5>and <an4>is similarly programmed to reverse the polarity of the current, which is useful during the generation of biphasic pulses discussed further below. Other digital amplitude buses used to program the PDACs and NDACs associated with other inactive electrodes (e.g., associated with PDAC1 and NDAC1 at electrode E1) <ap1>and <an1>) will be set to zero, or these PDACs or NDACs can be deactivated by other means. By appropriate control of the DACs, more than one anode and more than one cathode can be selected at a time, and thus current can flow through tissue R between two or more of the electrodes 16.

[0013] 3A also shows a DC blocking capacitor Ci 38 placed in series in the electrode current path between each of the electrode nodes ei 39 and the electrode Ei 16 (including the housing electrode Ec 12). The DC blocking capacitor 38 acts as a safety measure to prevent DC current from being injected into the patient, which could occur, for example, if there is a circuit fault in the stimulation circuitry 28.

[0014] Although not shown, the circuitry in the IPG 10 including the stimulation circuitry 28 may also be included in an external test stimulator (ETS) device for simulating the operation of the IPG during a test period and before implantation of the IPG 10. The ETS is typically used after the electrode array 17 has been implanted in the patient. The proximal ends of the leads in the electrode array 17 pass through an incision in the patient and are connected to an externally worn ETS, allowing the ETS to provide stimulation to the patient during the test period. Similar to the IPG 10, the ETS may include various antennas for communicating with external devices. Additional details about the ETS device are described in USP9,259,574 and U.S. Patent Application Publication 2019 / 0175915.

[0015] Referring again to FIG. 2A , the stimulation pulses shown are biphasic, with each pulse at each electrode comprising a first phase 30a followed by a second phase 30b of opposite polarity. Biphasic pulses are useful for actively recovering any charge that may be stored in capacitive elements (such as DC blocking capacitors 38) in the electrode current path, at the electrode / tissue interface, or within the tissue itself. In order to recover all charge at the end of the second pulse phase 30b of each pulse (Vc4=Vc5=0V), the first and second phases 30a and 30b are preferably charge balanced at each electrode, wherein the phases comprise equal amounts of charge but have opposite polarity. In the example shown, this charge balance is achieved by using the same pulse width (PWa=PWb) and the same amplitude (|+I|=|-I|) for each of the pulse phases 30a and 30b. However, as is known, the pulse phases 30a and 30b can also be charge balanced if the product of the amplitude and pulse width of the two phases 30a and 30b is equal.

[0016] FIG. 3A shows that the stimulation circuit system 28 may include a passive recycling switch 41 i , which is further described in U.S. Patent Application Publication Nos. 2018 / 0071527 and 2018 / 0140831. Passive Recycling Switch 41 i 39 and is used to passively recycle any residual charge, such as that which may remain on the DC blocking capacitor Ci 38 after the second pulse phase 30b is delivered. Passive charge recycling occurs without actively driving current using the DAC circuitry and may be prudent because non-idealities in the stimulation circuitry 28 may result in active charge recycling that is not completely charge balanced. By closing the passive recycling switch 41 connected at one end to the electrode node 39 i , passive charge recovery typically occurs during phase 30c ( FIG. 2A ), which may include a portion of the quiet period between pulses. Switch 41 i The other end of is connected to a common reference voltage, which in this example comprises the voltage Vbat of the battery 14, although another reference voltage may be used. As explained in the reference cited above, by placing a capacitor in parallel between the reference voltage (Vbat) and the patient's tissue, passive charge recovery tends to balance the charge on the DC blocking capacitor 38 and other capacitive elements in the output current path. Note that in FIG2A , during 30c, passive charge recovery is illustrated as a small exponential decay curve that can be positive or negative, depending on whether the pulse phase 30a or 30b imparts a charge advantage at a given electrode. Although not shown, control of the passive recovery switch can be performed via a signal output by the digital control circuit system 40.

[0017] Other designs of stimulation circuitry 28 may be used in IPG 10, and FIG. 3A is only one example. Figure 3B In another example shown in FIG, the PDAC and NDAC may not be dedicated to working with a specific electrode. Instead, a switch matrix (SM Pi) may be between each PDACi and electrode node ei 39, and a switch matrix (SM Ni) may be between each NDACi and electrode node ei 39. Each switch matrix may be controlled by a digital switch bus (e.g., <sp1> 、 <sn1>etc.) to control the electrode node to which the output of its associated DAC should be connected (e.g., PDAC1, NDAC1, etc.). Depends on the design and is related to Figure 3B Unlike what is shown in FIG, the stimulation circuit system 28 may include only one PDAC (and one switch matrix SMP) and one NDAC (and one switch matrix SMN). However, more than one PDAC and more than one NDAC may be provided (e.g., Figure 3B Each is an "x" (shown in FIG. 1 ), allowing for the formation of more complex stimuli, such as those requiring simultaneous control of current at more than one anode or cathode, or stimuli formed in different time channels. Figure 3B In the example of FIG. 5 , the digital control circuitry 40 issues a digital amplitude bus (eg, <ap1> 、 <an1>etc.) and a digital switch bus for each switch matrix (e.g., <sp1> 、 <sn1>Other variations of the stimulation circuit system 28 are possible, and different options are disclosed in USP 6,181,969, 8,606,362, 8,620,436, and US Patent Application Publications 2018 / 0071520 and 2019 / 0083796.

[0018] FIG4 shows an example circuit system for a given NDAC and PDAC (such as those used in FIG3A and 3B), although as explained in the reference just cited, the PDAC and NDAC may also be constructed differently. As previously described, the amplitude of the current output by the NDAC is determined by the digital amplitude bus<An[8:1]> Control, in this example, the bus includes eight digital control signals An[8] to An[1] capable of representing 256 different amplitude values. Each of these digital control signals is input to a select transistor 56n, each of which is connected in series with a different number of transistors 54n connected in parallel. Reference current Iref is generated by generator 50n and provided to transistor 52n, which mirrors its current to each of transistors 54n. (As is well known, this current mirroring occurs because the gates of transistors 52n and 54n are connected to the drain of transistor 52n).

[0019] The number of parallel transistors 54n varies in a binary fashion such that An[1] controls the connection of one transistor 54n to provide Iref; An[2] controls the connection of two transistors 54n that together provide 2*Iref; An[3] controls the connection of four transistors 54n that together provide 4*Iref, and so on, while [8] controls the connection of 128 transistors 54n that together provide 128*Iref. Because the select transistors 56n are N-channel transistors in this example, the digital control signals An[i] are preferably active high. Thus, for example, if the digital amplitude bus<An[8:1]> ='00110101', i.e., the number 53 in binary form, then control signals An[6], An[5], An[3], and An[1] are asserted to close their associated select transistors 56n. These control signals cause 32*Iref, 16*Iref, 4*Iref, and Iref, respectively, to be sunk into the NDAC (e.g., from its associated electrode nodes ( FIG. 3A ) or into its associated switch matrix ( FIG. 4A ). Figure 3B )), a total of 53*Iref. If we assume Iref = 0.1mA, the current Iout absorbed will be equal to 5.3mA. In short, by asserting the digital amplitude bus<An[8:1]> By using various digital control signals in the NDAC, the output current Iout can be sunk to the NDAC in increments of Iref=0.1mA over a dynamic range from Iref=0.0mA ('00000000') to 255*Iref=25.5mA ('1111111'). Iref can of course include amplitudes other than 0.1mA, and the amplitude An can include a number of increments other than 256.

[0020] The PDAC is largely similar in construction to the NDAC, although it operates to supply current. Again, the select transistor 56p is driven by the digital amplitude bus.<Ap[8:1]> control, where each transistor 56p controls the current from a different number of parallel transistors 54p. The Iref generated by generator 50p is mirrored to transistor 54p by transistor 52p. Because select transistor 56p is a P-channel transistor, the digital control signal Ap[i] is preferably active low. Thus, for example, if the digital amplitude bus<Ap[8:1]> ='11001010', i.e., 53's complement in binary form, then control signals Ap[6], Ap[5], Ap[3], and An[1] are asserted to close their associated select transistors 56p, which results in 32*Iref, 16*Iref, 4*Iref, and Iref being supplied, respectively, for a total of 53*Iref. Assuming again that Iref=0.1 mA, the supplied current Iout (e.g., supplied to an electrode node of the PDAC ( FIG. 3A ) or a switch matrix ( Figure 3B )) will equal 5.3mA (note that Iref can be fine-tuned at the generators 50p and 50n to ensure proper balance of the currents produced by the PDAC and NDAC). Similarly, by asserting the digital amplitude bus<Ap[8:1]> By using various digital control signals in , an output current lout in a dynamic range from Iref=0.0mA ('11111111') to 255*Iref=25.5mA ('0000000') can be supplied from the PDAC in 256 increments of Iref=0.1mA. Summary of the Invention

[0021] A stimulator device is disclosed that may include: a plurality of electrode nodes, each electrode node configured to couple to a corresponding electrode configured to contact tissue of a patient; and a digital-to-analog converter (DAC) circuit system that is controllable by a digital amplitude bus configured to specify a plurality of amplitude values, wherein the DAC circuit system is configured to set the amplitude of an output current at at least one of the electrode nodes based on the amplitude value carried by the digital amplitude bus, wherein the amplitude of the output current increases non-linearly as the amplitude value increases through the plurality of amplitude values.

[0022] In one example, the amplitude of the output current varies parabolically as the amplitude value increases through the plurality of amplitude values. In one example, the DAC circuitry includes at least one MOS diode having a parabolic current-voltage characteristic. In one example, the amplitude of the output current varies exponentially as the amplitude value increases through the plurality of amplitude values. In one example, the DAC circuitry includes at least one pn diode having an exponential current-voltage characteristic. In one example, the resolution of the output current is constant as the amplitude value increases through the plurality of amplitude values. In one example, the resolution comprises a percentage change in the amplitude of the output current as the amplitude value increases. In one example, the DAC circuitry is further controlled by at least one function select signal, wherein the at least one function select signal sets a relationship that specifies how the amplitude of the output increases as the amplitude value increases through the plurality of amplitude values. In one example, the at least one function select signal causes the amplitude of the output to either (i) increase parabolically as the amplitude value increases through the plurality of amplitude values, or (ii) increase exponentially as the amplitude value increases through the plurality of amplitude values. In one example, a DAC circuit system includes an input stage configured to receive a digital amplitude bus and generate a third voltage; and an output stage configured to receive the third voltage and generate an output current. In one example, the third voltage varies linearly with the amplitude value. In one example, the third voltage is applied to a third circuit in the output stage having a nonlinear current-voltage characteristic, wherein the output current is formed by the third circuit based on the nonlinear current-voltage characteristic. In one example, the third circuit is selectable. In one example, the input stage includes a first bias stage configured to generate a first voltage that varies with a first current. In one example, the first current is programmable to set a maximum amplitude of the output current. In one example, the first bias stage includes a first circuit configured to receive the first current, wherein the first voltage is generated based on the nonlinear current-voltage characteristic of the first circuit. In one example, the first circuit is selectable. In one example, the nonlinear current-voltage characteristic of the first circuit is the same as the nonlinear current-voltage characteristic of the third circuit. In one example, the third voltage is generated as a function of the first voltage. In one example, the input stage includes a first bias stage configured to generate a first voltage that varies with the first current, and a second bias stage configured to generate a second voltage that varies with a second current. In one example, the first current is programmable to set a maximum amplitude of the output current, and the second current is programmable to set a minimum amplitude of the output current. In one example, the first bias stage includes a first circuit configured to receive the first current, wherein a first voltage is generated according to a nonlinear current-voltage characteristic of the first circuit, and the second bias stage includes a second circuit configured to receive the second current, wherein a second voltage is generated according to a nonlinear current-voltage characteristic of the second circuit. In one example, the first and second circuits are selectable.In one example, the nonlinear current-voltage characteristics of the first, second, and third circuits are the same. In one example, the third voltage is generated as a function of the first and second voltages. In one example, the third voltage is equal to or between the first and second voltages.

[0023] A stimulator device is disclosed that may include: a plurality of electrode nodes, each electrode node being configured to couple to a corresponding electrode configured to contact tissue of a patient; and a digital-to-analog converter (DAC) circuit system that is controllable by a digital amplitude bus configured to specify a plurality of amplitude values, wherein the DAC circuit system is configured to set the amplitude of an output current at at least one of the electrode nodes based on the amplitude value carried by the digital amplitude bus, wherein the DAC circuit system is further controlled by at least one function selection signal, wherein the at least one function selection signal is configured to set a relationship that specifies how the amplitude of the output current changes as the amplitude value increases through the plurality of amplitude values.

[0024] In one example, at least one function selection signal is configured to set the amplitude of the output current to vary parabolically as the amplitude value increases through a plurality of amplitude values. In one example, at least one function selection signal is configured to select the use of at least one MOS diode having a parabolic current-voltage characteristic. In one example, at least one function selection signal is configured to set the amplitude of the output current to vary exponentially as the amplitude value increases through a plurality of amplitude values. In one example, at least one function selection signal is configured to select the use of at least one pn diode having an exponential current-voltage characteristic. In one example, at least one function selection signal is configured to set the amplitude of the output current to vary linearly as the amplitude value increases through a plurality of amplitude values. In one example, at least one function selection signal is configured to select the use of at least one resistor having a linear current-voltage characteristic. In one example, at least one function selection signal is configured to set the amplitude of the output to increase (i) linearly, (ii) parabolically, or (iii) exponentially as the amplitude value increases through a plurality of amplitude values. In one example, a DAC circuit system includes an input stage configured to receive a digital amplitude bus and generate a third voltage; and an output stage configured to receive the third voltage and generate an output current. In one example, the third voltage varies linearly with the amplitude value. In one example, the third voltage is applied to a selected one of a plurality of third circuits in the output stage based on at least one function selection signal, wherein each of the third circuits has a different current-voltage characteristic. In one example, the output current is formed by the selected third circuit based on the current-voltage characteristic of the selected third circuit. In one example, the input stage includes a first bias stage configured to generate a first voltage that varies with a first current, wherein the third voltage varies with the first voltage. In one example, the first current is programmable to set a maximum amplitude of the output current. In one example, the first bias stage includes a plurality of first circuits, each having a different current-voltage characteristic. In one example, the first voltage is generated in the selected one of the first circuits based on the at least one function selection signal. In one example, the first voltage is generated based on the current-voltage characteristic of the selected first circuit. In one example, the input stage includes a first bias stage configured to generate a first voltage that varies with a first current, and a second bias stage configured to generate a second voltage that varies with a second current, wherein the third voltage varies with the first voltage. In one example, the first current is programmable to set a maximum amplitude of the output current, and wherein the second current is programmable to set a minimum amplitude of the output current. In one example, the first bias stage includes a plurality of first circuits each having a different current-voltage characteristic, and wherein the second bias stage includes a plurality of second circuits each having a different current-voltage characteristic.In one example, a first voltage is generated at a selected one of the first circuits based on at least one function selection signal, and a second voltage is generated at a selected one of the second circuits based on at least one function selection signal. In one example, the first voltage is generated based on a current-voltage characteristic of the selected first circuit, and the second voltage is generated based on a current-voltage characteristic of the selected second circuit. In one example, a third voltage is generated as a function of the first and second voltages. In one example, the third voltage is equal to or between the first and second voltages.

[0025] A stimulator device is disclosed that may include: a plurality of electrode nodes, each electrode node being configured to couple to a corresponding electrode configured to contact tissue of a patient; and a digital-to-analog converter (DAC) circuit system that is controllable by a digital amplitude bus configured to specify a plurality of amplitude values, wherein the DAC circuit system is configured to set the amplitude of an output current that affects an electrode current at at least one of the electrode nodes, wherein the output current is equal to a maximum amplitude and a minimum amplitude or ranges between a maximum amplitude and a minimum amplitude based on the amplitude value carried by the digital amplitude bus, wherein the DAC circuit system is further programmable to set the maximum amplitude and the minimum amplitude.

[0026] In one example, a DAC circuit system is configured to provide an output current as an electrode current at at least one of the electrode nodes. In one example, the DAC circuit system includes an amplifier stage configured to amplify the output current into the electrode current. In one example, the DAC circuit system is programmable via a first bus to set a maximum amplitude of the output current, and the DAC circuit system is programmable via a second bus to set a minimum amplitude of the output current. In one example, the DAC circuit system includes: an input stage configured to receive a digital amplitude bus and generate a third voltage, and an output stage configured to receive the third voltage and generate an output current. In one example, the third voltage varies linearly with the amplitude value. In one example, the third voltage is applied to a third circuit in the output stage, wherein the third circuit includes a current-voltage characteristic. In one example, the output current is formed by the third circuit based on the current-voltage characteristic of the third circuit. In one example, the third circuit is selectable. In one example, the input stage includes a first bias stage configured to generate a first current based on a set maximum amplitude, and a second bias stage configured to generate a second current based on a set minimum amplitude. In one example, the first bias stage is configured to generate a first voltage that varies with a first current, and the second bias stage is configured to generate a second voltage that varies with a second current. In one example, the first bias stage includes a first circuit configured to receive the first current, wherein the first voltage is generated based on a current-voltage characteristic of the first circuit, and the second bias stage includes a second circuit configured to receive the second current, wherein the second voltage is generated based on a current-voltage characteristic of the second circuit. In one example, the first and second circuits are selectable. In one example, a third voltage is generated as a function of the first and second voltages. In one example, the third voltage is equal to or between the first and second voltages. In one example, the third voltage varies linearly with amplitude.

[0027] A stimulator device is disclosed, which may include: a plurality of electrode nodes, each electrode node being configured to couple to a corresponding electrode configured to contact patient tissue; and a digital-to-analog converter (DAC) circuit system, which is configured to provide stimulation to at least one of the plurality of electrode nodes, including: a first bias stage, which is configured to generate a first voltage that varies with a first current; a resistor block, which is configured to receive the first voltage and the second voltage, wherein the resistor block can be controlled by a digital amplitude bus to generate a third voltage equal to or between the first and second voltages based on the amplitude value carried by the digital amplitude bus; and an output stage, which is configured to receive the third voltage and generate an output current that varies with the third voltage.

[0028] In one example, the first current is programmable. In one example, the second voltage is ground. In one example, the amplitude value sets the amplitude of the output current equal to zero and the first current, or ranging between zero and the first current. In one example, the output current varies linearly with the amplitude value. In one example, the output current varies parabolically with the amplitude value. In one example, the output current varies exponentially with the amplitude value. In one example, the first bias stage includes a first circuit configured to receive the first current, wherein a first voltage is generated based on a current-voltage characteristic of the first circuit. In one example, the output stage includes a third circuit having the same current-voltage characteristic as the first circuit, wherein the third circuit receives a third voltage to generate an output current based on its current-voltage characteristic. In one example, the first bias stage includes a plurality of first circuits selectable to receive the first current and generate the first voltage, wherein the current-voltage characteristics of the plurality of first circuits differ from one another, wherein the first voltage is generated based on the current-voltage characteristic of a selected first circuit. In one example, the output stage includes a plurality of selectable third circuits, wherein the current-voltage characteristics of the plurality of third circuits differ from one another, wherein a selected third circuit receives the third voltage to generate an output current based on its current-voltage characteristic. In one example, the DAC circuit further includes a second bias stage configured to generate a second voltage, wherein the second voltage varies with a second current. In one example, the first and second currents are programmable. In one example, the amplitude value is set to an output current amplitude equal to the second current and the first current, or a range between the second current and the first current. In one example, the output current varies linearly with the amplitude value. In one example, the output current varies parabolically with the amplitude value. In one example, the output current varies exponentially with the amplitude value. In one example, the first bias stage includes a first circuit configured to receive the first current, wherein the first voltage is generated based on a current-voltage characteristic of the first circuit, and the second bias stage includes a second circuit configured to receive the second current, wherein the second voltage is generated based on a current-voltage characteristic of the second circuit. In one example, the output stage includes a third circuit having the same current-voltage characteristic as the first and second circuits, wherein the third circuit receives a third voltage to generate an output current based on its current-voltage characteristic. In one example, the first bias stage includes a plurality of first circuits selectable to receive a first current and generate a first voltage, wherein current-voltage characteristics of the plurality of first circuits are different from one another, wherein the first voltage is generated according to the current-voltage characteristics of the selected first circuits, and wherein the second bias stage includes a plurality of second circuits selectable to receive a second current and generate a second voltage, wherein the current-voltage characteristics of the plurality of second circuits are different from one another, wherein the second voltage is generated according to the current-voltage characteristics of the selected second circuits.In one example, the output stage includes a plurality of selectable third circuits, wherein the current-voltage characteristics of the plurality of third circuits differ from one another, wherein the selected third circuit receives a third voltage to generate an output current according to its current-voltage characteristic. In one example, the third voltage varies linearly with an amplitude between the first and second voltages. In one example, the output current is provided to at least one of the electrode nodes. In one example, the output current is amplified before being presented to the at least one of the electrode nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 shows an implantable pulse generator (IPG) according to the prior art.

[0030] 2A and 2B illustrate examples of stimulation pulses that may be generated by an IPG according to the prior art.

[0031] Figure 3A and Figure 3B Different examples of stimulation circuitry including PDACs and NDACs that can be used in an IPG according to the prior art are shown.

[0032] FIG. 4 shows a method for using FIG. 3A and FIG. Figure 3B Circuit details of the PDAC and NDAC in the stimulation circuit system.

[0033] Figures 5A to 5C An improved design of an NDAC is shown that is capable of selecting how the output current will vary between maximum and minimum currents according to the amplitude value specified on the digital amplitude bus through circuits with different IV characteristics.

[0034] Figures 6A to 6B It shows how the output current from the NDAC varies as a function of amplitude value when different circuits are selected. Figure 6C and Figure 6D The resulting current increment and resolution are shown as a function of the amplitude value when different circuits are selected, respectively.

[0035] Figure 7A and Figure 7B An improved design of a PDAC is shown that is similar in construction and functionality to an NDAC.

[0036] Figure 8 A modification is shown in which the outputs of the improved NDAC and PDAC are amplified.

[0037] Figure 9 A modification is shown in which the improved NDAC and PDAC lack a minimum current bias stage.

[0038] Figure 10 A modification is shown in which an improved NDAC and PDAC use a single, non-selectable circuit to determine how the output current will vary depending on the amplitude value.

[0039] Figures 11A to 11C The use of the improved NDAC and PDAC to provide output currents between maximum and minimum currents is shown.

[0040] Figure 12A and Figure 12B Examples of stimulation circuitry in an IPG using either of the previously described improved NDACs and PDACs are shown.

[0041] Figure 13 A graphical user interface is shown that can be reproduced on an external device capable of programming the IPG, where the GUI includes options for programming the improved NDAC and PDAC circuitry. DETAILED DESCRIPTION

[0042] The stimulation circuit system as described above is beneficial because it is programmable to provide a current of a specified amplitude and polarity at the electrodes. However, the inventors have discovered certain shortcomings in their digital-to-analog (DAC) circuit system (e.g., FIG. 4 ). As described above, the amplitude of the current provided by the DAC, Iout, can be incremented by a constant unit Iref (e.g., 0.1 mA) such that the amplitude (digital amplitude bus) is <ap>or <an>) increases or decreases by 1, the output current increases or decreases by Iref. In other words, the output current varies linearly with the amplitude value: Iout(An) = Iref * An and Iout(Ap) = Iref * Ap. However, this increase is more significant at the low end of the DAC's current dynamic range and less significant at the high end of the range.

[0043] This may not be ideal when one considers that the magnitude of the optimal current to provide effective treatment may vary. Sometimes a lower current (e.g., 1 mA) is needed. For example, an SCS patient whose electrode array 17 is relatively close to the spinal cord may require a lower current. A lower current may also be warranted for different types of stimulation therapies. For example, DBS applications generally require a lower current than SCS applications. Other times, a higher current (e.g., 10 mA) is needed. For example, an SCS patient whose electrode array 17 is relatively far from the spinal cord may require a higher current.

[0044] In these various situations, the need for the DAC circuitry to provide the appropriate current amplitude complicates its design. For patients or therapies requiring lower currents, a constant current increment of 0.1 mA may be too coarse for adjusting the current. This increment operates with a 10% resolution (0.1 mA / 1 mA) for a lower current amplitude of 1 mA, so that increasing the amplitude (i.e., incrementing the digital amplitude bus) will increase the current to 1.1 mA, and decreasing the amplitude will decrease the current to 0.9 mA. This may include too large a change when a lower current is required. If the patient requires a lower current, such as 1 mA, smaller current adjustments may result in meaningful changes to the treatment. Therefore, it may be desirable to adjust the current with a lower resolution of, for example, 3% (0.03 mA increments), so that increasing the amplitude will increase the current to 1.03 mA, while decreasing the amplitude will decrease the current to 0.97 mA. Providing better resolution at lower currents will allow the clinician (via the clinician programmer) or the patient (via the patient remote control) to more flexibly adjust the current to achieve the appropriate treatment.

[0045] For patients or therapies requiring higher currents, a constant current increment of 0.1 mA may be too fine to meaningfully adjust the current. Such increments can only work with a resolution of 1% (0.1 mA / 10 mA) for a higher current amplitude of 10 mA, such that increasing the amplitude will increase the current to 10.1 mA, and decreasing the amplitude will decrease the current to 9.9 mA. When a higher current is required, this may comprise too small a change, as such an increment may not meaningfully affect the therapy. In such a case, it may be desirable to adjust the current with a finer resolution (0.3 mA increments) of, say (again), 3%, such that increasing the amplitude will more significantly increase the current to 10.3 mA, and decreasing the amplitude will more significantly decrease the current to 9.7 mA.

[0046] Therefore, designing a DAC circuit system (such as the DAC circuit system shown in Figure 4) that can handle stimulation at lower and higher currents may involve undesirable trade-offs. If the DAC circuit system is designed to provide good resolution (e.g., 3%) for higher currents (e.g., 10mA), a current increment of 0.3mA is required. But this will provide inappropriately high resolution (e.g., 30%) at lower currents (1mA), as well as too coarse regulation. In contrast, if the DAC circuit system is designed to provide good resolution (e.g., 3%) for lower currents (e.g., 1mA), a current increment of 0.03mA is required. This will not only result in undesirably low resolution (0.3%) at higher currents (e.g., 10mA), but will also complicate the DAC circuit system design. For example, if it is assumed that the DAC circuit system should have a dynamic range of 25.5mA, a current increment of 0.03 will require the amplitude to be controllable in 850 increments (25.5mA / 0.03mA). Given the binary nature of the PDAC and NDAC (Figure 4), the digital amplitude bus now requires additional signals, for example 10 signals instead of 8, to correctly shape the current. (The ten signals provide the ability to specify the 2 10 = 1024 different amplitudes, enough to handle the required 850). This complicates the DAC design and may result in invalid amplitude bus values ​​(those from 851 to 1024).

[0047] Another drawback associated with DAC circuit systems having a constant current increment is that for a given application, it may not be necessary to use their entire dynamic range. For example, assume it is known that a given SCS patient requires a current on the order of 4 mA to provide effective treatment for their condition. It may never be guaranteed that the current amplitude for this patient is below 3 mA or above 5 mA, such that for this patient, the effective range of the DAC circuit system is from 3 mA to 5 mA. In this example, most of the dynamic range of the DAC circuit system (A < 3 mA; 5 < A < 25.5 mA) is effectively wasted on this patient. Further, because the current increment is constant across all amplitude values (e.g., 0.1 mA), the patient can only effectively adjust the current to 21 out of 256 possible amplitude values (e.g., from 3.0 mA to 5.0 mA), which is limiting. It may be desirable to allow the patient to more finely adjust the output current within the effective range they require.

[0048] In short, the previously described DAC circuit systems may be too inflexible. Instead, it is desirable to provide a DAC circuit system design that can increment and decrement current more meaningfully based on the amplitude of that current. For example, at lower amplitudes (e.g., 1 mA), the current increment should be lower (e.g., 0.03 mA), while at higher amplitudes (e.g., 10 mA), the current increment should be higher (e.g., 0.3 mA). In short, it is desirable to provide a design that offers a constant or at least more constant resolution across the dynamic range.

[0049] Further, it is desirable to provide a DAC circuit system design that allows the dynamic range to be set for a particular patient or application while still retaining the ability to finely increment the current across the entire amplitude value range within that range.

[0050] Finally, it is desirable to be able to select different circuits having different current-voltage (I-V) characteristics within the DAC circuit system to control the shape of the output current. This is because, as explained below, different I-V characteristics have different effects on the way the output current increments and thus on the resolution of the current regulation.

[0051] To support these goals, starting from Figure 5A a more flexible DAC circuit system design 100 is disclosed. More specifically, Figure 5A a new NDAC circuit system design is shown that can absorb the output current Iout from the cathode. Figure 7A And Figure 7B changes to the circuit system to form a PDAC 100 that can supply the output current Iout to the anode are described later. The new DAC circuit system design can exist as part of a stimulation circuit system in an IPG or similar device, such as the ETS device described previously.

[0052] As shown, the NDAC circuitry 100 receives the digital amplitude bus <an>and produces an analog output current, Iout, which is a function of the specified amplitude, An, carried by the bus. However, as further described below, and depending on how the NDAC 100 is programmed, the output current, Iout, may not necessarily be linearly proportional to the amplitude, An. That is, Iout(An) may not increase at a constant current increment (such as Iref) as An increases, and thus Iout may not necessarily be linearly proportional to A, as occurs in the DAC circuitry described in the introduction. Digital Amplitude Bus <an>It is shown as a parallel bus including a plurality of signal lines (eg, eight signal lines An[8] to An[1]), but may also include a serial bus including a single signal line.

[0053] like Figure 5A The NDAC 100 shown includes an input stage 101 and an output stage 104. The input stage in this example includes two bias stages 102a and 102b. These bias stages 102a / b can be similar in design and are used to set the maximum (Imax) and minimum (Imin) values ​​of the current to be generated at the output lout. Each bias stage 102a / b includes a current source 106a / b that can be programmable to generate Imax / Imin. In this regard, the control circuitry 40 of the IPG can issue a digital bus as needed. <imax>and <imin>To program the current sources 106a / b to generate Imax and Imin. Like other digital buses, these buses <imax>and <imin>A parallel or serial bus may be included. Note that current sources 106a / b may include any design of programmable current source. For example, current sources 106a / b may be constructed as previously shown in FIG. 4 , or may include other designs such as those disclosed in USP 6,181,969, 8,606,362, 8,620,436, and U.S. Patent Application Publications 2018 / 0071520 and 2019 / 0083796.

[0054] In this example, the maximum and minimum currents Imax and Imin are provided to current-voltage (IV) selection blocks 108a and 108b (generally 108i), which Figure 5B The IV selection block 108i allows selection of different circuits 109i to receive the Imax and Imin generated by the current sources 106a / b. Preferably, each of the different circuits 109i has a different current-voltage (IV) characteristic and is Figure 5B . In this example, the three illustrated circuits 109i comprise a single device, although this is for simplicity. In other examples, the circuits 109i may comprise one or more devices that together provide a desired IV characteristic, i.e., a network of devices.

[0055] The first circuit in circuit 109L includes a resistor whose current IL is linearly proportional to the voltage across it: IL ~ kV, where k is equal to the conductance of the resistor (1 / R). The second circuit in circuit 109S includes a MOS diode, which can be formed by connecting the drain of a MOS transistor to its gate as shown. As is well known, the current IS flowing through this MOS diode is proportional to the square of the voltage across it: IS ~ k(V-Vt) 2 , where k is a constant and Vt comprises the threshold voltage of the MOS transistor. The third circuit in circuit 109E comprises a pn diode, which in one example can be formed by connecting the collector of a bipolar junction transistor to its base. As is well known, the current IE flowing through this pn diode is exponentially proportional to the voltage V across it: IE ~ m*e n*V , where m and n are constants.

[0056] By closing switches 111L, 111S, and 111E connected in series, any one of these circuits 109L, 109S, and 109E can be selected for use within IV selection block 108i. These switches are controlled by control signals L (linear), S (squared), and E (exponential), respectively, which together constitute the function selection signals. These function selection signals are issued by control circuitry 40, and in the illustrated example, different function selection signals a, b, and c are used to control the selection of circuit 109i in IV selection block 108a, IV selection block 108b, and a third IV selection block 108c present in output stage 104, which will be discussed later. Preferably, but not necessarily, control circuitry 40 will select the same circuit 109i in each of IV selection blocks 108a, 108b, and 108c. In this regard, and although not shown, the control circuitry 40 may issue only one set of functional control signals (ie, one set of L, S, and E control signals) to be received by each of the IV selection blocks 108a, 108b, and 108c.

[0057] In bias stage 102a, Imax is provided to the selected circuit 109i within IV selection block 108a, which in turn produces a voltage Vmax governed by the IV characteristics of the selected circuit. For example, if resistor 109L is selected, Vmax will be equal to Imax*R. If MOS diode 109S is selected, Vmax will be proportional to SQRT(Imax). If pn diode 109E is selected, Vmax will be proportional to ln(Imax). Vmax is provided to voltage follower 110a to produce a buffered version of Vmax at its output. Bias stage 102b is similar, with Imin being provided to the selected circuit 109i within IV selection block 108b, which in turn produces a voltage Vmin governed by the IV characteristics of the selected circuit. Vmin is provided to voltage follower 110b to produce a buffered version of Vmin at its output.

[0058] The buffered Vmax and Vmin are provided to a resistor block 112 in the input stage 101, which is controlled by the digital amplitude bus An to generate a voltage V(An) that varies with the amplitude value An carried by the bus. An example of resistor block 112 is shown in FIG. Figure 5C , and includes a demultiplexer (demux) 120 and a resistor ladder 122. This example assumes a digital amplitude bus <an>It includes eight control signals An[8] to An[1], and thus can specify 256 different amplitude values. Figure 5C As shown in the table in , demux 120 asserts one of 256 possible X control signals depending on the value of An. For example, if An = 0 ( <an>='00000000'), then demux 120 asserts signal X0; if An=1( <an>='00000001'), then demux asserts signal X1, and so on, where when An=255 ( <an>='1111111'). Assert X255.

[0059] Except for the case where An = 0 (discussed further below), the asserted X control signal closes switch 124 in resistor ladder 122 to set V(An) to a value equal to or between Vmax and Vmin. In this example, resistor ladder 122 comprises a series connection of 254 resistors, preferably all having the same value r. Given the manner in which switches 124 are connected to the resistors, voltage V(An) = [(An-1) / 254]*[Vmax-Vmin]+Vmin. Thus, when An = 1, X1 is asserted, which sets V(An) = Vmin. When An = 255, X255 is asserted, which sets V(An) = Vmax. For other values ​​of An, V(An) scales linearly between Vmin and Vmax.

[0060] It may be desirable to retain the amplitude that specifies that the NDAC 100 should not provide an output, ie, Iout should be equal to zero (instead of Imin). <an>='00000000'), this situation remains. In this case, demux 120 asserts signal X0, which controls switch 126 that connects V(An) to ground. This sets V(An) to zero, which in turn sets Iout to zero, as explained later.

[0061] Reference again Figure 5A , V(An) is provided to the output stage 104 of the NDAC 100. Specifically, V(An) is provided to the non-inverting input of an operational amplifier (op amp) 114, the output of which is provided to the gate of an output transistor 116. The inverting input of the op amp 114 is connected to the top of the IV selection block 108c. Feedback will force the output transistor 116 to conduct to the extent necessary to equalize the voltage at the input of the op amp; therefore, V(An) will be dropped across the IV selection block 108c. Based on the circuit 109i ( Figure 5B ), this voltage drop V(An) induces a current Iout through the IV selection block 108c and the output transistor 116.

[0062] refer to Figure 5A and 6A to 6D The operation of the NDAC 100 and the relevance of selecting different circuits 109i are explained. In the example shown, it is assumed that Imax is set (via <imax>) is 25.5mA and Imin is set (via <imin>As previously mentioned, it is preferred that the circuit 109i selected in each of the IV selection blocks 108a-c is identical, and 6A to 6D An example is shown in which the resistor 109L, the MOS diode 109S, and the pn diode 109E are selected in each block via control signals L, S, and E, respectively.

[0063] Each of the selectable circuits 109i in the IV selection block 108i provides a different scaling of the current Iout as the amplitude value An changes. In other words, the selected circuit 109i changes the shape of Iout(An).

[0064] For example, the selection of resistor 109L provides a linear response to Iout as a function of the amplitude An. This is because the V(An) generated by the resistor block 112 will be equal to V(An) = [R(An-1) / 254]*[Imax-Imin]+R*Imin, where R is equal to the resistance of resistor 109L. When V(An) is applied across resistor R in the IV selection block 108c in the output stage 104, a current Iout = [(An-1) / 254]*[Imax-Imin]+Imin is generated. In other words, Iout is linearly proportional to the amplitude An, as shown in FIG. Figure 6A Note that Iout ranges from Imin=0.1 mA (An=1) to Imax=25.5 mA (An=255), except when An=0 (which results in V(A) being zero, which sets Iout to zero).

[0065] The selection of MOS diode 109S provides a square or parabolic response to Iout as a function of the amplitude An. This is because the V(An) generated by the resistor block 112 will be proportional to [(An-1) / 254]*[SQRT(Imax)-SQRT(Imin)]+SQRT(Imin), as specified by the IV characteristics of the MOS diode 109S. V(An) is applied across the MOS diode 109S in the IV selection block 108c in the output stage 104, which results in a voltage that is generally proportional to An. 2 The math here is more complex and may be further complicated by other secondary effects inherent in the IV characteristics of a MOS diode, such as considering its threshold voltage. Nevertheless, Iout is generally proportional to An 2 Proportional changes, such as Figure 6A and Figure 6B Likewise, Iout ranges from Imin=0.1 mA (An=1) to Imax=25.5 mA (An=255) (except when An=0, which sets Iout to zero).

[0066] The selection of pn diode 109E provides an exponential response to Iout as a function of amplitude An. This is because V(An) generated by resistor block 112 will be proportional to [(An-1) / 254]*[ln(Imax)-ln(Imin)]+ln(Imin), as dictated by the IV characteristic of pn diode 109S. V(An) is applied across pn diode 109E in IV selection block 108c in output stage 104, resulting in a current Iout proportional to Imin*(Imax / Imin)^((An-1) / 254). In other words, Iout scales exponentially with amplitude An. Figure 6B This is best shown in , which plots the logarithm of Iout versus An. Again, Iout ranges from Imin=0.1 mA (An=1) to Imax=25.5 mA (An=255) (except when An=0, which sets Iout to zero).

[0067] Figure 6C shows the amount by which the output current Iout increases when An is increased. Mathematically, this diagram effectively shows Figure 6A and Figure 6B The derivative of the curve provided in d(Iout) / dAn.

[0068] When resistor 109L is chosen, each increment of amplitude An provides a constant increment to the output current Iout, which in this example is equal to 0.1 mA. (Note that this makes sense from a calculus point of view: because Iout varies linearly with A when the resistor is used, d(Iout) / dAn should be constant). This response is similar to the stimulus circuit system described previously (Figure 4), which also provides a constant current increment (Iref) and therefore provides an output current that scales linearly with the amplitude (Iout = Iref*An). For a given implementation, this may be fine, but as mentioned earlier, having a DAC that only allows the output current to be adjusted in constant increments has a disadvantage: the increment may be too large to provide good resolution at lower amplitudes of Iout, and too small to provide good resolution at higher amplitudes. This resolution (increment / Iout) is in Figure 6D quantized in . It can be seen that when a constant increment is used (selection of resistor 109L), the resulting resolution is inversely proportional to A. For example, when An = 10 (corresponding to Iout = 1 mA), the resolution is 10% (0.1 mA / 1 mA) and is higher at lower values ​​of An. When An = 100 (corresponding to Iout = 10 mA), the resolution is 1% (0.1 mA / 10 mA), and is lower at much higher values ​​of An. As discussed previously, this resolution may be too high at lower currents, inhibiting the ability to make finer adjustments to the current that may be required for the patient's treatment. Likewise, at higher currents, the resolution may be too low, resulting in insignificant incremental changes to the current.

[0069] In this regard, it may be useful to select a nonlinear circuit 109i to shape the output current lout, as such a circuit provides smaller current increments at lower amplitudes of lout and larger increments at higher amplitudes. This provides a constant, or at least more constant, resolution within the dynamic range of the NDAC 100.

[0070] For example, Figure 6C It is shown that when MOS diode 109S is selected, the increment scales essentially linearly with An. (Note again that this makes sense: since Iout is generally proportional to An 2 (The current increment is less than 0.1 mA at lower current values ​​and is approximately 0.1 mA in the middle of the dynamic range of the NDAC 100 (at An-127). The increment increases at higher values ​​of An, ultimately reaching approximately 0.2 mA at Amax=255.) Figure 6D The resulting resolution using this non-constant increment is shown, typically between 1% and 8% across the full dynamic range of the NDAC 100. Note that due to secondary effects inherent in the IV characteristics of MOS diodes, the resolution may not follow a simple trend. However, when using MOS diodes 109S, and when compared to using resistors 109L, the resolution is more reasonable across the full dynamic range of the NDAC 100, with less resolution at lower currents and more resolution at higher currents.

[0071] When the pn diode 109E is selected, the increment changes exponentially with A, as shown in Figure 6C (Again, this makes sense: since Iout varies with e An So d(Iout) / dAn should also change with e An Since Iout also changes exponentially with An, the resulting resolution ( Figure 6D ) is constant, in this example about 2.2%. In other words, each incremental adjustment to the output current increases or decreases Iout by 2.2%. For example, when An=100, Iout=1mA ( Figure 6B ), then when An increases to 101, Iout will be equal to 1.022 mA. If Iout = 10 mA when An = 215, then when An increases to 216, Iout will be equal to 10.22 mA, and so on. Note that using nonlinear increments in this example solves the problem highlighted previously because the resolution is constant (e.g., 2.2%) across the entire dynamic range of the stimulus circuitry.

[0072] NDAC 100 is advantageous in its ability to account for potential variations and, therefore, perform predictably even in the presence of such variations. For example, there may be variations inherent in the manufacturing process used to manufacture NDAC 100 (e.g., on an ASIC), which may alter the IV characteristics of circuit 109i. Furthermore, and particularly with respect to the use of MOS diode 109s or pn diode 109e, the IV characteristics may be temperature-dependent. Such variations will ultimately affect the voltages Vmax and Vmin generated by IV selection blocks 108a and 108b. However, because these voltages Vmax and Vmin are subtracted in resistor block 112 when forming V(An), and because V(An) is applied to circuit 109i in IV selection block 108c, which is similarly affected by such variations, such variations are eliminated or mitigated, resulting in a predictable Iout value.

[0073] Although it is preferred to select the same circuit 109i in each of the IV selection blocks 108i, different circuits 109i may be selected. As will be appreciated by those skilled in the art, using different types of circuits will result in different shapes of Iout as a function of amplitude ( Figure 6A and Figure 6B ), thus providing different Iout current increments across the entire dynamic range of the DAC ( Figure 6C ) and resolution ( Figure 6D For example, bias stages 102a and 102b may be controlled to select the use of pn diode 109E, while output stage 104 may be controlled to select the use of resistor 109L, which may be beneficial in a given implementation.

[0074] Figure 7A and Figure 7B An example of a PDAC 100 capable of supplying current Iout from the anode is shown, and as will be appreciated by those skilled in the art, the circuitry is very similar to that of the NDAC 100 and functions similarly. <ap>, which forms a voltage V(Ap) that forms a supply current Iout that can vary linearly, quadratically, or exponentially with Ap depending on the circuit 109i selected. The devices used in the PDAC 100 can have different polarities. For example, P-channel or NPN transistors can be used instead of the N-channel or PNP transistors used in the NDAC 100. In addition, the digital control signal (e.g., <imax> 、 <imin> 、 <ap>, function select signals L, S, and E, etc.) may also be complementary (active low). Further, and as explained in U.S. Patent Application Publication 2018 / 0071520, the NDAC 100 and PDAC 100 may be powered by different power domains. For example, although Figure 5A and Figure 5B As shown in Figure 2, the power domain Vcc / GND can be used to power the NDAC, and as shown in Figure 2 Figure 7A and Figure 7B As shown, the power domain VH / VH-Vcc can be used to power the PDAC.

[0075] Many modifications to the disclosed DAC circuitry are possible, and Figures 8 to 10 Some different modification examples are shown in . Figure 8 An NDAC 100' and a PDAC 100' are shown, which include the NDAC 100 and PDAC 100 as described above, but which also include additional amplifier stages 110n and 110p. For example, the NDAC 100' includes the NDAC 100 which receives the amplitude An (via bus 100) as described above. <an>), maximum and minimum currents Imax and Imin (via bus <imin>and <imax>) and a function selection signal (L, S, E) that selects the circuit 109i having the desired IV characteristic. The NDAC 100 outputs a current Iout between Imin and Imax that varies (linearly, quadratically, or exponentially) as a function of An as previously described. This output current is then provided to the amplifier stage 110n, which (in this example) linearly amplifies Iout by a scalar Jn to produce an output current IJ=Jn*Iout at the cathode between Jn*Imin and Jn*Imax. In the example shown, the scalar Jn is a current that can be obtained via the amplifier bus. <jn>Although the amplification stage 110n is programmable (which may be provided by the control circuitry 40), it is also possible for the amplification stage 110n to provide a fixed amplification of Jn and is not programmable. The amplification stage 110n may employ a current mirror to provide the desired scalar Jn and may be constructed, for example, as previously shown in FIG4 . The PDAC 100′ is similarly constructed and operates similarly to supply a current IJ=Jp*Iout at the anode.

[0076] Figure 9 A modification of 102a shows the use of a DAC circuit system with only a single maximum current bias stage 102a in the input stage 101. This example is shown in the context of an NDAC 100, but a PDAC 100 ( Figure 7A ) can be similarly modified. Bias stage 102a is programmed as before to produce Imax, and in turn Vmax, which is provided to resistor block 112. When compared with Figure 5A By comparison, note that there is no minimum current bias stage 102b, and instead the other end of resistor block 112 is grounded. This is equivalent to setting Imin=Vmin=0 in bias stage 102b. In effect, this modification provides an output current Iout equal to zero and Imax or ranging between zero and Imax, which may be useful in applications where it is desirable to extend the dynamic range of current that can be produced by NDAC 100 down to zero. By Figure 5A The same effect can be achieved by setting Imax=0 in bias stage 102b in FIG. Note that in this example, the control circuit system 40 does not issue <imin>and function selection signals b(L, S, E) since these signals are irrelevant when bias stage 102b is absent.

[0077] Figure 10 It is shown that the DAC circuit system may not have different selectable circuits 109i with different IV characteristics. This example is again shown in the context of NDAC 100, but PDAC 100 ( Figure 7A ) can be modified similarly. Figure 10 In FIG. 1 , NDAC 100 includes a single, non-selectable circuit 109i having the IV characteristics necessary to provide the desired response of Iout as the amplitude varies. Specifically, Figure 10 The use of a pn diode 109E in the DAC is shown (i.e., in place of the IV select stage 108i), although other circuits (resistor 109L, MOS diode 109S) could also be shown. Using a single, non-selectable circuit 109i reduces the DAC's flexibility in choosing how Iout will vary with amplitude, but limiting this flexibility is still a reasonable design choice. For example, if an exponential relationship between Iout and amplitude is desired to produce constant resolution over the entire dynamic range of the DAC ( Figure 6D ), then the use of pn diode 109E is a reasonable choice. Further, although not shown, the non-selectable circuits can be different in stages 102a, 102b, and 104. Note that in this example, control circuitry 40 does not issue function selection signals because these signals are irrelevant.

[0078] The disclosed DAC circuitry is further advantageous in its ability to limit the dynamic range of the output current, lout, to between a minimum value, Imax, and a maximum value, Imin, which can be useful in a given application. Take, for example, the hypothetical, previously proposed SCS patient requiring a current on the order of 4 mA. As previously mentioned, it may never be possible to guarantee that the current amplitude for this patient will be below 3 mA or above 5 mA. In a DAC circuitry with fixed increments (e.g., 0.1 mA), the patient is effectively limited to a relatively small number of amplitude adjustments within this dynamic range, such as 21 of 256 possible values.

[0079] Current DAC designs do not have this limitation, and instead the amplitude can still be varied in 256 increments within the desired dynamic range, thus providing the patient with greater flexibility in adjusting the current within this range. Figures 11A to 11C In this example, Imin and Imax are programmed to 3mA and 5mA respectively (via bus <imin>and <imax>) to provide the desired effective dynamic range. A type of circuit 109i, namely resistor 109L, MOS diode 109S or pn diode 190E, is selected to provide the desired relationship between Iout and amplitude An, as explained above. Note that limiting the dynamic range of Iout can flatten the response, as Figure 11A As shown, although these responses are still linear (resistor 109L), squared (MOS diode 190S) and exponential (pn diode 190E), as previously described. Figure 11B and Figure 11C The resulting increment and resolution are shown as a function of the amplitude An, which shows the same basic response mentioned previously (although flattened again). Figure 11B As shown, when the resistor 109L is used, the current increment of Iout is constant (~0.0078mA); when the MOS diode 109S is used, it generally increases linearly; and when the pn diode 109E is used, it increases exponentially. Figure 11C As shown, the resolution decreases conversely when resistor 109L is used, and is constant (~0.2%) when pn junction diode 109E is used. (For simplicity, Figure 11C The resolution of the MOS diode 109S is not shown).

[0080] Figure 12A and Figure 12B The disclosed NDAC 100 and PDAC 100 are shown integrated into stimulation circuitry 128 for providing current to electrodes of an IPG. These stimulation circuitry 128 are similar to those previously described in FIG. Figure 3B The stimulation circuit system shown in FIG. 1 and FIG. 2 shows a stimulation circuit system in which a PDACi / NDACi pair is dedicated to a specific electrode node ei ( Figure 12A ) and wherein the PDAC and NDAC can control the current at different electrodes through the switch matrix SM Pi and SM Ni ( Figure 12B ). Also shown are the control signals received by the various components, which, as previously described, may be issued from the control circuitry 40 of the IPG. In the example shown, each PDACi and NDACi receives a digital amplitude bus <api>and <ani>Each PDACi and NDACi may also receive control signals specific to the disclosed DAC design, such as setting maximum and minimum current ( <imaxpi> 、 <iminpi> 、 <imaxni> 、 <iminni>) and function select signals (L, S, E(pi) and L, S, E(ni)) for shaping Iout. In one example, the maximum and minimum currents and function select signals may be the same for each of the PDAC and NDAC. In this regard, control circuitry 40 may only need to issue one set of such signals (i.e., <imax> 、 <imin>and L, S or E), and each PDACi and NDACi can receive a set of such signals. Figure 12B As before, the switch matrices SM Pi and SW Ni additionally receive switch matrix control signals <spi>and <sni>.

[0081] Figure 13 A graphical user interface (GUI 150) is shown that can be used to program and control the operation of the disclosed DAC circuit system. Those skilled in the art will appreciate that GUI 150 can be rendered on a display of an external device used to program or monitor the IPG, such as a handheld patient remote control or clinician programmer. Software for rendering GUI 150 and receiving input from a user can be stored in a non-transitory computer-readable medium, such as in a memory of an external device.

[0082] The GUI 150 may include a DAC circuitry control interface 152 that allows selection and programming of one or more of the PDAC and NDAC. Figure 13 In FIG. 1 , it is assumed that the IPG stimulation circuitry 128 includes four PDACs and four NDACs, although this number may vary depending on the design of the stimulation circuitry. DAC programming may include options for specifying the maximum and minimum currents (Imax and Imin) produced by the associated DAC(s), and for selecting the shape of Iout with respect to amplitude (such as linearly, squarely, or exponentially), which will respectively select the resistor 109L, MOS diode 109S, and pn diode 109E to be used in the stimulation circuitry 128. Such programming may be transferred from an external device to the IPG to allow the IPG's control circuitry 40 to form a bus for each or all of the DACs. <imax> 、 <imin>and function selection signals L, S, and E. (In other DAC designs, <imin>and function selection signals may be unrelated (see Figure 9 and Figure 10 ), in which case control of these variables may be omitted from the GUI 150).

[0083] Because the external device can be programmed with the relevant IV characteristics of the circuit 109i used in the DAC circuit system, the external device can calculate the current Iout corresponding to each amplitude value (Iout(A)) given Imin, Imax and the selected Iout shape. In fact, the external device can determine the current Iout that forms the previously Figure 6A , which shows Iout versus A. If necessary or useful, Iout(A) may be displayed in the GUI 150 as a table of values, or it may be as shown in FIG. Figure 6A Based on the Iout(A) data, the external device can further determine the range of increments and resolutions or both, as previously described. In fact, the external device can determine the range of increments and resolutions previously drawn in Figure 6C and Figure 6D The data required for the graph shown in FIG15 is obtained and such data can be plotted again. Displaying such information in GUI 150 is useful for reference and can help the user select an appropriate shape for lout given Imin and Imax. For example, the user can review the resolution provided within the dynamic range of selectable amplitudes to ensure that each amplitude increment will provide a significant adjustment to lout.

[0084] Establishing Iout(A) in the external device is essential to enable the external device to convert the desired current amplitude to be used by the digital amplitude bus ( <ap> ， <an>) may also be useful. In this regard, the GUI 150 may include an electrode programming interface 154 that allows a user (a patient or clinician) to specify the current I to be generated at each of the electrodes in the IPG electrode array 17. In an actual implementation, the electrode programming interface 154 may be significantly more complex and may include additional options for specifying the stimulation the patient will receive. For example, the frequency and pulse width of the pulses may also be specified, but for simplicity this is not shown.

[0085] In the example shown, the user selects electrodes E1 and E3 to act as anodes, where each anode supplies +2.0 mA to the patient's tissue. The user also selects electrode E2 to act as a cathode to sink -4.0 mA from the patient's tissue. Knowing how Iout scales with the amplitude of the selected Iout shape (Iout(A)), the external device can determine the amplitude value A required to establish the desired current I, and this can be done using the amplitude conversion module 130 stored in the external device in association with the software of the GUI 150. For example, assuming that Iout is used Figure 12A The stimulation circuit system 128 architecture of FIG (where each electrode Ei has a dedicated PDACi / NDACi pair), and the user has programmed the DAC to provide an exponential response to Iout. As described above, an external device can determine Iout(A) and provide it to the amplitude conversion module 130 so that an amplitude value A can be determined for each of the specified currents I. Figure 6C In the graph of Iout versus A, when the exponential shape is selected, we can see that the currents of 2mA and 4mA correspond to amplitude values ​​of 138 and 170 respectively. <ap1>(serving PDAC1 and electrode E1) is set to 138 ('01110101', 138 is low and valid), and the digital amplitude bus <an2>(serving NDAC2 and electrode E2) is set to 170 ('10101010', 170 high level is valid), and the digital amplitude bus <ap3>(serving PDAC3 and electrode E3) is set to 138 ('01110101', 138 is active low). These amplitude values ​​can then be transmitted from the external device to the IPG along with other relevant data to allow the control circuitry 40 in the IPG to form the control signals required by the stimulation circuitry 128 to form the desired stimulation.

[0086] Alternatively, an external device may transmit the desired current amplitude to the IPG 10, thereby allowing the IPG 10 to convert these currents into amplitude values. In this regard, the control circuit system 40 of the IPG may also include an amplitude conversion module 130, such as Figure 12A and Figure 12B Thus, control circuitry 40 in IPG 10 can determine Iout(A) given other user selections in GUI 150 (Imin, Imax, Iout shape, etc.), or Iout(A) can also be telemetered to the IPG. In either case, module 130 can determine the amplitude value A required to form the desired current I at each of the electrodes. < / an> < / ap> < / imin> < / imin> < / imax> < / sni> < / spi> < / imin> < / imax> < / iminni> < / imaxni> < / iminpi> < / imaxpi> < / ani> < / api> < / imax> < / imin> < / imin> < / jn> < / imax> < / imin> < / an> < / ap> < / imin> < / imax> < / ap> < / imin> < / imax> < / an> < / an> < / an> < / an> < / an> < / imin> < / imax> < / imin> < / imax> < / an> < / an> < / an> < / ap> < / sp1> < / ap1> < / sp1> < / api> < / ani> < / api> < / ani>

Claims

1. A stimulator device comprising: a plurality of electrode nodes, each electrode node configured to couple to a corresponding electrode configured to contact tissue of a patient; as well as a digital-to-analog converter circuitry controllable by a digital amplitude bus configured to specify a plurality of amplitude values, wherein the digital-to-analog converter circuitry is configured to set the amplitude of an output current at at least one of the electrode nodes in accordance with the amplitude value carried by the digital amplitude bus, The amplitude of the output current increases non-linearly as the amplitude value increases incrementally through a plurality of amplitude values.

2. A stimulator device according to claim 1, wherein the amplitude of the output current changes parabolically as the amplitude value increases through the multiple amplitude values.

3. A stimulator device according to claim 1, wherein the amplitude of the output current changes exponentially as the amplitude value increases through the multiple amplitude values.

4. A stimulator device according to claim 1, wherein as the amplitude value increases through the multiple amplitude values, the resolution of the output current is constant, wherein the resolution includes a percentage change in the amplitude of the output current as the amplitude value increases.

5. A stimulator device according to any one of claims 1 to 4, wherein the digital-to-analog converter circuit system is also controlled by at least one function selection signal, wherein the at least one function selection signal sets a relationship that specifies how the amplitude of the output current increases as the amplitude value increases through the multiple amplitude values.

6. A stimulator device according to claim 5, wherein the at least one function selection signal causes the amplitude of the output current to either (i) increase parabolically as the amplitude value increases through the multiple amplitude values, or (ii) increase exponentially as the amplitude value increases through the multiple amplitude values.

7. A stimulator device according to any one of claims 1 to 4 and 6, wherein the digital to analog converter circuitry comprises: an input stage configured to receive the digital amplitude bus and generate a third voltage, and An output stage is configured to receive the third voltage and generate the output current.

8. A stimulator device according to claim 7, wherein the third voltage is applied to a third circuit having a nonlinear current-voltage characteristic in the output stage, wherein the output current is formed by the third circuit according to the nonlinear current-voltage characteristic.

9. A stimulator device according to claim 8, wherein the third circuit is selectable.

10. A stimulator device according to claim 8 or claim 9, wherein the input stage comprises a first bias stage configured to generate a first voltage that varies with a first current, wherein the first current is programmable to set a maximum amplitude of the output current.

11. A stimulator device according to claim 10, wherein the first bias stage comprises a first circuit configured to receive the first current, wherein the first voltage is generated according to a non-linear current-voltage characteristic of the first circuit.

12. A stimulator device according to claim 11, wherein the first circuit is selectable.

13. A stimulator device according to claim 8, wherein the input stage includes a first bias stage configured to generate a first voltage that varies with a first current, and a second bias stage configured to generate a second voltage that varies with a second current.

14. A stimulator device according to claim 13, wherein the first bias stage includes a first circuit configured to receive the first current, wherein the first voltage is generated according to a nonlinear current-voltage characteristic of the first circuit, and wherein the second bias stage includes a second circuit configured to receive the second current, wherein the second voltage is generated according to a nonlinear current-voltage characteristic of the second circuit.

15. A stimulator device according to claim 13 or 14, wherein the third voltage is generated as a function of the first voltage and the second voltage, wherein the third voltage is equal to the first voltage and the second voltage or between the first voltage and the second voltage.

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