Feedback for power management of memory dies using dedicated pins

Abstract

This application is directed to feedback for power management of memory dies using a dedicated pin. A memory device can include a pin for communicating feedback about a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device can bias the pin to a first voltage indicating that the supply voltage is within a target range. The memory device can then determine that the supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device can select the second voltage based on whether the supply voltage is above or below the target range.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application is a national phase application of international patent application No. PCT / US2020 / 067261, filed by Choi et al. on December 29, 2020, entitled “FEEDBACK FOR POWER MANAGEMENT OF A MEMORY DIE USING A DEDICATED PIN,” which claims priority to U.S. provisional patent application No. 16 / 740,293, filed by Choi et al. on January 10, 2020, entitled “FEEDBACK FOR POWER MANAGEMENT OF A MEMORY DIE USING ADEDICATED PIN,” both of which are assigned to the present assignee and are expressly incorporated herein by reference in their entirety. Technical Field

[0003] The technical field relates to feedback of power management to a memory die using dedicated pins. Background Art

[0004] The following relates generally to one or more memory systems, and more specifically, to feedback for power management of a memory die using dedicated pins.

[0005] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, often represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states, either of which can be stored. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program a state into the memory device.

[0006] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selective memory, chalcogenide memory technologies, and others. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for extended periods of time, even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source. SUMMARY

[0007] An apparatus is described. The apparatus can include an array of memory cells; a pin to transmit a signal indicative of feedback regarding a supply voltage used during operation of the array of memory cells to a power management component; and a controller operable to cause the apparatus to determine that the supply voltage is outside of a target range associated with the supply voltage and transition a voltage at the pin from a first voltage to a second voltage indicative of the supply voltage being outside of the target range.

[0008] A system is described. The system can include a first memory device comprising a first pin; a second memory device comprising a second pin; a power management component coupled with the first pin and the second pin and operable to provide a supply voltage to the first memory device and the second memory device; wherein the first memory device is operable to determine that the supply voltage is outside of a voltage range and to bias the first pin to a first voltage based at least in part on determining that the supply voltage is outside of the voltage range; and wherein the second memory device is operable to determine that the supply voltage is outside of the voltage range and to bias the second pin to a second voltage based at least in part on determining that the supply voltage is outside of the voltage range.

[0009] A method is described. The method can include biasing a pin of a memory device to a first voltage indicative of a supply voltage associated with the memory device being within a target range; after biasing the pin of the memory device to the first voltage, determining that the supply voltage is outside of the target range; and based at least in part on determining that the supply voltage is outside of the target range, transitioning a voltage at the pin of the memory device from the first voltage to a second voltage indicative of the supply voltage being outside of the target range. BRIEF DESCRIPTION OF DRAWINGS

[0010] FIG. 1 An example of a system supporting feedback of power management of a memory die using dedicated pins according to examples disclosed herein is described.

[0011] FIG. 2 An example of a memory system supporting feedback of power management to a memory die using dedicated pins according to examples disclosed herein is shown.

[0012] FIG. 3 An example of a memory system supporting feedback of power management to a memory die using dedicated pins according to examples disclosed herein is shown.

[0013] FIG. 4A 、 4B 4 and 4C show examples of voltage signals that support feedback for power management of a memory die using dedicated pins according to examples disclosed herein.

[0014] FIG. 5 A block diagram illustrating a memory device supporting feedback of power management to a memory die using dedicated pins according to examples disclosed herein.

[0015] FIG. 6 and 7 A flow chart illustrating one or more methods of supporting feedback for power management of a memory die using dedicated pins according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0016] In some memory systems, a power management component, such as a power management integrated circuit (PMIC), can be used to manage the power supplied to one or more memory devices by controlling the voltage of a power rail. In some cases, the voltage on the power rail can decay at locations that are relatively far from the power management component due to, for example, parasitic capacitance along the rail or other factors. For memory devices that are relatively far from the power management component, the voltage on the power rail can decay sufficiently to fall below the minimum supply voltage, which can cause errors at the memory devices. However, the power management component may not have access to information about the voltages at various locations along the rail and may not be able to adjust the power supplied to the rail to compensate for these deviations from a target range of voltage levels.

[0017] In some examples, a memory device may include a dedicated pin (e.g., a pin not used for other purposes) that provides feedback to a power management component regarding the voltage level of a power rail at the memory device so that the power management component can appropriately adjust the voltage. For example, the dedicated pin may be coupled to the power management component using a conductive wire. The memory device may be operable to provide feedback to the power management component by biasing the pin to a voltage level that indicates the voltage level of the power rail at the memory device. For example, the memory device may set the voltage at the pin to a first voltage to indicate that the supply voltage is within a target range, and may set the voltage at the pin to a different voltage to indicate that the supply voltage is outside the target range. The target range may be, for example, a supply voltage range for which the memory device is designed to operate properly, such as a supply voltage range specified by a standards document associated with the memory device. The memory device may set the voltage at the pin to one of three or more voltages, each of which may be associated with a voltage level of a power rail. For example, the memory device may set the voltage at the pin to a first voltage to indicate that the supply voltage is within the target range, a second voltage to indicate that the supply voltage is below the target range, and a third voltage to indicate that the supply voltage is above the target range. In some cases, a memory device may be operable to change the voltage at a pin from one voltage to another voltage a certain number of times (for example), where the number of times is associated with the value of the supply voltage. In some cases, a memory system may include multiple memory devices, each of which may include a dedicated pin to provide feedback to the power management component as described above.

[0018] The power management component can then be operable to detect the voltage at a dedicated pin of the memory device, a change in the voltage at the pin, and / or the number of voltage transitions at the pin. In the case where the power management component is coupled to multiple memory devices, each including its own pin, the power management component can be operable to detect such feedback at each pin, or to detect combined feedback from all pins. The power management component can use such feedback information to determine whether and how to adjust the power (e.g., the supply voltage) supplied to the memory device via the power rail; that is, the power management component can adjust the voltage of the rail based on feedback received from one or more memory devices.

[0019] As shown in the following reference FIG. 1 Features of the present disclosure are further described in the context of the memory systems and dies described herein. FIG. 2 -4 describes the features of the present disclosure in the context of the system and voltage signals described. FIGS. 5-7These and other features of the present disclosure are further illustrated by and described with reference to the described device diagrams and flow diagrams relating to feedback for power management of memory dies using dedicated pins.

[0020] FIG. 1 An example of a system 100 utilizing one or more memory devices according to examples as disclosed herein is described. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include the one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0021] System 100 may include a portion of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop, a tablet, a smartphone, a cellular phone, a wearable device, a networked device, a vehicle controller, etc. Memory device 110 may be a component of the system that may be used to store data for one or more other components of system 100.

[0022] At least a portion of system 100 may be an example of a host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, or some other stationary or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0023] Memory device 110 may be a standalone device or component operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configurable to operate with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: a modulation scheme for modulating signals, various pin configurations for transmitting signals, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0024] Memory device 110 may be operable to store data for components of host device 105. In some examples, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0025] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using a bus 135.

[0026] The processor 125 may be operable to provide control or other functionality for at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, the processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a system on a chip (SoC), among other examples. In some examples, the external memory controller 120 may be implemented by or be part of the processor 125.

[0027] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run the various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and the various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0028] The memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) to support a desired or specified capacity for data storage. Each memory die 160 can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 can be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more sections) where each memory cell can be used to store at least one bit of data. A memory device 110 that includes two or more memory dies can be referred to as a multi-die memory or a multi-die package, or a multi-chip memory or a multi-chip package.

[0029] In some examples, the memory dies 160 can be coupled with a power management component that is operable to provide one or more supply voltages to the memory dies 160. For example, the power management component can supply a VDD voltage, a VSS voltage, a VDDQ voltage, etc. using power supply rails (e.g., conductive lines). The power management component is operable to maintain a substantially constant supply voltage on the rails to provide power to the memory device 110 or the memory dies 160 during operation. The power management component can include or be coupled with one or more voltage source components that are operable to generate the appropriate supply voltages. In some cases, the power management component can be referred to as a PMIC or a registered clock device (RCD).

[0030] In some cases, due to parasitic capacitance along the power supply rails, for example, the voltage along the power supply rails can decrease along the rails as the distance from the power management component increases. Thus, if multiple memory dies 160 are coupled with a power supply rail that provides a supply voltage to the memory dies 160, the memory dies 160 that are relatively farther from the power management component can receive a lower supply voltage than the memory dies 160 that are closer to the power management component. In some cases, if the supply voltage drops below a lower voltage threshold, the memory dies 160 can experience memory errors.

[0031] The memory dies 160 (or the memory device 110) can include dedicated pins for providing feedback to the power management component regarding the supply voltage on the power supply rail at the memory dies, in turn enabling the power management component to properly adjust the supply voltage.

[0032] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and may advantageously be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0033] A local memory controller 165 (e.g., local to the memory die 160) may be operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate with the device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some examples, the memory device 110 may not include a device memory controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0034] The local memory controller 165 of the memory die 160 is operable to determine whether the supply voltage is outside of a target range associated with the supply voltage. If the local memory controller 165 determines that the supply voltage is outside of the target range, the local memory controller 165 may transition (e.g., change) the voltage at the pin of the memory die 160 from a first voltage indicating that the supply voltage is within the range to a second voltage indicating that the supply voltage is outside of the range.

[0035] The external memory controller 120 may be used to enable one or more of information, data, or commands to be transferred between components of the system 100 or host device 105 (e.g., processor 125) and the memory device 110. The external memory controller 120 may convert or translate communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105, or the functionality described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or the functionality described herein may be implemented by one or more components of the memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0036] Components of host device 105 can exchange information with memory device 110 using one or more channels 115. Channels 115 can be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 can be an example of a transmission medium that carries information between host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path can be an example of a conductive path operable to carry a signal. For example, channel 115 can include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. A pin can be an example of a conductive input or output point of a device of system 100, and a pin can be operable to serve as part of a channel.

[0037] Channels 115 (and associated signal paths and terminals) can be dedicated to conveying one or more types of information. For example, channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, information may be communicated via channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on either a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both a rising and falling edge of a clock signal).

[0038] FIG. 2 An example of a memory system 200 that supports feedback for power management of a memory die using dedicated pins is described. The memory system 200 can include a power management component 205, a memory device 210 including a memory array 215, and a feedback path 230 and a supply path 225 between the power management component 205 and the memory device 210. In the example of the memory system 200, the feedback path 230 and / or the supply path 225 can be examples of conductive lines coupling the power management component 205 to the memory device 210. The memory device 210 can be a reference FIG. 1 The memory array 215 may be a reference to an example of a memory device 110. FIG. 1 An example of a memory array 170 is described.

[0039] The power management component 205 may include a supply interface 235, low dropout regulators (LDO) 240, 245, power supplies (SWA, SWB) 250, 255 (e.g., switching regulators), and a multi-time programmable memory (MTP) 260. The supply interface 235 is operable to receive power to activate the power management component 205 and to be distributed to other components of the memory system (e.g., the memory device 210) through the power management component 205.

[0040] Low-dropout (LDO) regulators 240 and 245 may be used to output power (e.g., DC power) to memory devices of the memory system, including memory device 210. In some cases, low-dropout (LDO) regulators 240 and 245 may be used to regulate an output voltage, such as a supply voltage. Power supplies 250 and 255 may be used to output power to memory devices of the memory system, including memory device 210. Power management component 205 may include any number of LDO regulators (e.g., one, two, three, four, five, six, seven, eight), or any number of power supplies (e.g., one, two, three, four, five, six, seven, eight), or both.

[0041] The multi-time programmable memory 260 can be any type of memory used by the power management component 205 to perform the functions described herein. In some cases, the multi-time programmable memory 260 can be an example of an electrically erasable programmable read-only memory (EEPROM) or other type of memory technology. The multi-time programmable memory 260 can be used to protect circuits, improve the reliability of power-up or power-down sequences, set output voltages, set output pull-down resistors, or other functions, or any combination thereof.

[0042] Memory device 210 can include a pin 220 for providing feedback to the power management component. A pin can be, for example, a conductive terminal of an integrated circuit package that allows the integrated circuit to connect with other components or circuitry. Pin 220 can also be referred to as, for example, a pad, socket, connector, contact, or ball (of a ball grid array package). In some cases, pin 220 can be a conductive point that is located within an integrated circuit package or outside of an integrated circuit package. In some cases, pin 220 can be associated with a predefined functionality (e.g., a predefined type or format of signal) that can be specified as part of, for example, a standardized interface that allows the integrated circuit to connect to other circuitry or components. In some cases, pin 220 can be a dedicated pin that is associated with a single function (e.g., for providing feedback) and can not be used for purposes other than the single function.

[0043] Feedback path 230 can couple pin 220 of memory device 210 with power management component 205. Feedback path 230 can include any set of one or more wires that establish a communication link between memory device 210 and power management component 205. Feedback path 230 can directly couple memory device 210 and power management component 205, meaning that feedback path 230 can establish a connection between the two components to allow signals to be routed between the components using conductive wires.

[0044] Supply path 225 can be (or can be coupled with) a power supply rail to, for example, enable power management component 205 to provide a supply voltage to memory device 210. The supply voltage can be used by memory device 210 during operation of memory device 210 and can include, for example, a VDD voltage, a VSS voltage, or another supply voltage.

[0045] Provided herein are techniques for using pin 220 to provide feedback to power management component 205 by transitioning a voltage at pin 220 from a first voltage to a second voltage based on determining that a supply voltage provided by power management component 205 is outside of a target range. The voltage at pin 220 or the voltage transition at pin 220 can be detected by power management component 205 (and / or by another device, such as a host device) and can be used by power management component 205 to adjust (e.g., maintain or adjust) a voltage supplied to memory device 210 (e.g., using supply path 225) or to adjust another operational aspect of memory device 210.

[0046] FIG. 3An example of a system 300 according to the examples disclosed herein is illustrated. The system 300 includes a host device 305 and a memory system 310. The host device 305 and the memory system 310 can be (e.g., electrically) coupled or connected to each other via a channel 315 (e.g., a public channel, a common channel). The host device 305 can refer to a device that uses the memory system 310 for data storage or otherwise coordinates the use of the memory system 310 for data storage.

[0047] The memory system 310 can include one or more memory devices 110 (e.g., memory devices 110-a, 110-b), which can be examples of the memory devices 110 described with reference to FIG. 1 An example of a memory device 110 described, such as a DRAM device. Each memory device 110 can include a pin 220 (e.g., pins 220-a, 220-b) for providing feedback to the power management component 205-a. In some cases, the pins 220-a, 220-b can be dedicated pins. The power management component 205-a can be an example of the power management component 205 described with reference to FIG. 2 An example of a power management component 205 described.

[0048] In some examples, the memory system 310 can refer to a set of components that are physically distinct from the host device 305, such as a memory module or a memory assembly. For example, the memory system 310 can refer to a single inline memory module (SIMM), a dual inline memory module (DIMM), or another type of module or assembly. In some cases, a SIMM or a DIMM can include a power management component (such as depicted in the memory system 310). In some cases, the power management component 205-a can be located outside of the SIMM or the DIMM.

[0049] In some cases, the memory system 310 can include a single DRAM integrated circuit (e.g., a single memory device 110). The memory system 310 can include a first number of pins (e.g., 72 pins or another number of pins), which can be used, for example, to couple the memory system 310 with a power management component, a host processor, or other electronic components. Each pin of the memory system 310 can support 32-bit data transfer.

[0050] In some cases, memory system 310 may include a series of DRAM integrated circuits, such as a series of memory devices 110. Memory system 310 may include a second number of pins (e.g., 100, 144, 168, 172, 184, 204, 214, 240, or another number of pins), which may be used, for example, to couple memory system 310 to a power management component, a host processor, or other electronic components. Each pin of memory system 310 may support 64-bit data transfer. In some cases, DRAMs in memory system 310 are coupled to one or more power rails, and DRAMs that are farther from the voltage source may receive a lower voltage on the power rail than DRAMs that are closer to the voltage source.

[0051] In some cases, the number of pins described above of memory system 310 may include dedicated pins for providing feedback to power management components as described herein. In some cases, additional pins may be added to memory system 310 to provide this functionality, and thus the number of pins may be increased by one relative to the number of pins described above of memory system 310.

[0052] In some cases, memory device 110 may bias (e.g., set, drive) the voltage at pin 220 to a first voltage that indicates the supply voltage is within a target range. For example, memory device 110 may determine that the supply voltage is within a target range and may bias the voltage at pin 220 to the first voltage based on determining that the supply voltage is within the target range.

[0053] In some cases, memory device 110 may determine whether a supply voltage used during operation of memory device 110 is outside a target range. If memory device 110 determines that the supply voltage is outside the target range, memory device 110 may transition the voltage at pin 220 from a first voltage to a second voltage indicating that the supply voltage is outside the target range. For example, the second voltage may indicate that the supply voltage is below a lower voltage threshold of the target range or that the supply voltage is above an upper voltage threshold of the target range.

[0054] In some cases, memory device 110 may use two levels of voltage feedback. For example, memory device 110 may determine whether the supply voltage is within a target range or below a lower voltage threshold of the target range. If memory device 110 determines that the supply voltage is within the target range, memory device 110 may bias pin 220 to a first voltage indicating that the supply voltage is within the target range. If memory device 210 determines that the supply voltage is below the lower voltage threshold of the target range, memory device 110 may transition the voltage at pin 220 to a second voltage indicating that the supply voltage is below the lower voltage threshold. In some cases, the second voltage may be lower than the first voltage. ReferenceFIG. 4A Two levels of voltage feedback are described.

[0055] In some cases, memory device 110 can use three levels of voltage feedback. For example, memory device 110 can determine whether the supply voltage is within a target range, below a lower voltage threshold of the target range, or above a higher voltage threshold of the target range. If memory device 110 determines that the supply voltage is within the target range, memory device 110 can bias pin 220 to a first voltage that indicates that the supply voltage is within the target range. If memory device 210 determines that the supply voltage is below the lower voltage threshold of the target range, memory device 110 can transition the voltage at pin 220 to a second voltage that is lower than the first voltage. If memory device 110 determines that the supply voltage is above the higher voltage threshold of the target range, memory device 110 can transition the voltage at pin 220 to a third voltage. In some cases, the third voltage can be between the first voltage and the second voltage, or can be lower than the second voltage, or can be higher than the first voltage.

[0056] In some cases, if memory device 110 determines that the supply voltage is outside of the target range, memory device 110 can select a voltage level (e.g., select the second voltage or the third voltage) based on whether the supply voltage is below the lower voltage threshold of the target range or above the higher voltage threshold of the target range, and transition the voltage at the pin from the first voltage to the selected voltage level (e.g., the second voltage or the third voltage). Referring to FIG. 4B Three levels of voltage feedback are described.

[0057] In some cases, memory device 110 can be operable to determine a value (e.g., a voltage value) of the supply voltage. Memory device 110 can indicate the value of the supply voltage by causing a certain number of voltage transitions at pin 220, such as voltage transitions between the first voltage and the second voltage, the second voltage and the third voltage, the first voltage and the third voltage, or transitions between other voltages.

[0058] In some cases, the number of voltage transitions can be based on the value of the supply voltage. For example, memory device can transition the voltage at the pin a first number of times (e.g., instances) based on determining a first value of the supply voltage, and can transition the voltage at the pin a second number of times based on determining a second value of the supply voltage.

[0059] In some cases, the voltage used for the voltage transitions can be based on the value of the supply voltage. For example, memory device 110 can transition the voltage at the pin from a first voltage to a second voltage based on determining a first value of the supply voltage, and can transition the voltage at the pin from a third voltage to a fourth voltage based on determining a second value of the supply voltage.

[0060] In some cases, memory device 110 may be operable to provide feedback to power management component 205 using an asynchronous protocol. The asynchronous protocol may include, for example, multi-bit signaling based on voltage level transitions at pin 220. That is, memory device 110 may generate a multi-bit signal (e.g., based on the value of the supply voltage) and transmit the multi-bit signal using pin 220. Such a multi-bit signal may include an indication of the value of the supply voltage, an identifier of memory device 110 (e.g., a DRAM identifier), an indication of whether the supply voltage is above an upper voltage threshold or below a lower voltage threshold, a difference between the value of the supply voltage and a target value, other information related to the supply voltage or memory device 110, or a combination of these.

[0061] In some cases, power management component 205-a may be operable to detect a voltage at pin 220 (e.g., via feedback path 230). For example, power management component 205-a may be operable to poll the voltage at pin 220 or on feedback path 230-a at periodic intervals, or based on other timing or conditions. In some cases, power management component 205-a may be operable to detect a number of voltage transitions at pin 220, such as a number of transitions initiated by memory device 110. In some cases, power management component 205-a may be operable to detect asynchronous multi-bit signaling by capturing the number of voltage transitions at pin 220.

[0062] In some cases, power management component 205-a may maintain or adjust the power supplied to memory device 110 based on a voltage detected at pin 220, a number of transitions at pin 220, asynchronous multi-bit signaling at pin 220, or a combination thereof. Power management component 205-a may, for example, use LDOs 240, 245, SAs 250, 255, MTP 260, or a combination of these components to maintain, increase, or decrease the voltage on the supply rail.

[0063] Memory device 110 may be operable to receive an adjusted supply voltage (eg, from power management component 205 - a ) based on shifting the voltage at pin 220 .

[0064] The power management component 205-a can be coupled to multiple memory devices 110-a, 110-b using a single feedback path 230-a. In this case, each memory device 110 can provide an indication of the supply voltage at the memory device 110, which can be different for memory device 110-a and memory device 110-b, for example. Thus, in some cases, the supply voltage at memory device 110-a can be outside of a target range, while the supply voltage at memory device 110-b can be within the target range (or vice versa). In this case, the feedback provided by memory device 110-a at pin 220-a can conflict with the feedback provided by memory device 110-b at pin 220-b, which can present challenges for the power management component 205-a in regulating the power supply to the memory devices 110.

[0065] To address such challenges, in some cases, each memory device 110 in the memory system 310 may be coupled with an in-line resistor 320 between the pin 220 of the memory device 110 and the power management component 205-a to weight the feedback from each memory device 110. For example, pin 220-a of memory device 110-a may be coupled with resistor 320-a to weight the feedback from memory device 110-a, and pin 220-b of memory device 110-b may be coupled with resistor 320-b to weight the feedback from memory device 110-b. The values ​​of resistor 320-a and resistor 320-b may be different and may be selected (e.g., during the design of memory devices 110) to provide different weightings for the feedback from memory devices 110-a and 110-b. For example, the value of resistor 320 may be selected based on the orientation of memory device 110 within memory system 310 or based on the proximity of memory device 110 to a power source. In this manner, resistors 320-a, 320-b may enable multiple memory devices 110 to be coupled to a single feedback path 230-a and provide a single combined feedback signal, with the contribution from each memory device 110 weighted by the value of the corresponding resistor 320.

[0066] In some cases, each memory device 110 may be coupled to the power management component 205-a using a separate point-to-point connection (e.g., a separate feedback path), and the power management component 205-a may internally weight or otherwise process feedback from each memory device 110 to determine how to adjust the supply voltage.

[0067] In some cases, each memory device 110 may apply a different drive strength at pin 220 to weight the feedback of each memory device 110. In some cases, the drive strength may be the amount of current that flows out (e.g., supplied) or flows into (e.g., received) at pin 220 while outputting or maintaining a given voltage at pin 220. For example, each memory device 110 may be preconfigured to apply a specific drive strength at pin 220 based on, for example, the orientation of the memory device 110 within the memory system 310 or the proximity (e.g., electrical proximity) of the memory device 110 to a power source.

[0068] FIG. 4A Depicted are examples of voltage signals supporting feedback for power management of a memory die using dedicated pins according to examples disclosed herein. FIG. 4A A memory device (eg, memory device 110 ) may be depicted outputting a voltage on a dedicated pin (eg, pin 220 ) to provide two levels of voltage feedback to a power management component (eg, power management component 205 ) or another device.

[0069] At or before time t0, the memory device may bias the pin to a first voltage 405 indicating that the supply voltage is within a target range. The first voltage 405 may be, for example, the VDD voltage or another voltage.

[0070] At time t0, the memory device may determine that the supply voltage is outside the target range. The memory device may, based on determining that the supply voltage is outside the target range, transition the voltage at the pin from the first voltage 405 to a second voltage 410 indicating that the supply voltage is outside the target range (e.g., during transition 415 occurring between time t0 and time t1). In some cases, transition 415 may be the last duration, e.g., from t0 to t1. In some cases, second voltage 410 may be lower than first voltage 405, e.g., FIG. 4A . For example, second voltage 410 may be ground, VDD / 2, or another voltage. In other cases, second voltage 410 may be higher than first voltage 405. In some cases, the memory device may maintain the voltage at the pin at the second voltage for a duration after transition 415. For example, the memory device may maintain the voltage at the second voltage for a predefined duration, or as long as the memory device continues to detect that the supply voltage is outside of a target range. In some cases, the memory device may maintain the voltage at the second voltage until the memory device determines that the supply voltage has returned to within the target range, or until the memory device determines that the supply voltage has changed in another manner.

[0071] FIG. 4BDepicted are two examples (435-a, 435-b) of voltage signals supporting feedback for power management of a memory die using dedicated pins according to examples disclosed herein. FIG. 4B A memory device (eg, memory device 110 ) may be depicted outputting a voltage on a dedicated pin (eg, pin 220 ) to provide three levels of voltage feedback to a power management component (eg, power management component 205 ) or another device.

[0072] Prior to time t0, the memory device may bias the pin to a first voltage 420 indicating that the supply voltage is within a target range. The first voltage 420 may be, for example, the VDD voltage or another voltage.

[0073] At or before time t0, the memory device may determine that the supply voltage is outside of a target range.

[0074] In the example of 435 - a , the memory device may determine that the supply voltage is outside of the target range by determining that the supply voltage is below a lower voltage threshold of the target range.

[0075] In this case, at t0, the memory device may, based on determining that the supply voltage is below the lower voltage threshold of the target range, cause the voltage at the pin to transition from the first voltage 420 to the second voltage 430 indicating that the supply voltage is below the lower threshold voltage (e.g., during the first transition 415-a occurring between time t0 and time t1), as depicted in example 435-a. In example 435-a, the second voltage 430 is lower than the first voltage 420. For example, the second voltage 430 may be ground or another voltage lower than the first voltage 420.

[0076] Alternatively, as depicted in example 435-b, the memory device can determine that the supply voltage is outside the target range by determining that the supply voltage is above a higher voltage threshold of the target range. The memory device can transition the voltage at the pin from the first voltage 420 to a third voltage 425 indicating that the supply voltage is above an upper threshold voltage (e.g., during first transition 415-a) based on determining that the supply voltage is above the higher voltage threshold of the target range. FIG. 4B In the example of , the third voltage 425 is between the first voltage 420 and the second voltage 430. For example, the third voltage 425 can be VDD / 2 or another voltage between the first voltage and the third voltage.

[0077] In some cases, memory device 110 may select the second voltage or the third voltage based on whether the supply voltage is below or above the target range, respectively, and may transition the voltage at pin 220 to the selected voltage level (eg, the second voltage or the third voltage).

[0078] In some cases, the power management component may detect the second voltage 430, the third voltage 425, the first transition 415-a, or a combination of these, and adjust the supply voltage so that the supply voltage at the memory device returns to within a target range.

[0079] At time t2, the memory device may determine that the supply voltage is again within the target range. The memory device may transition the voltage at the pin from the second voltage 430 to the first voltage 420 (e.g., 435-b) or from the third voltage 425 to the first voltage 420 (e.g., 435-a) during a second transition 415-b occurring between time t2 and time t3 based on determining that the supply voltage is within the target range.

[0080] FIG. 4C Depicted are examples of voltage signals supporting feedback for power management of a memory die using dedicated pins according to examples disclosed herein. FIG. 4C A memory device (eg, memory device 110 ) may be depicted outputting a voltage on a dedicated pin (eg, pin 220 ) to provide feedback to a power management component (eg, power management component 205 ) or another device using a multi-bit signal.

[0081] Prior to time t0, the memory device may bias the pin to a first voltage 440 indicating that the supply voltage is within a target range. The first voltage 440 may be, for example, the VDD voltage or another voltage.

[0082] At or before time t0, the memory device may determine that the supply voltage is outside of a target range, which may include determining a value of the supply voltage.

[0083] In some cases, the memory device may determine the transition amount based on the value of the supply voltage. The memory device may then transition the voltage at the pin by the transition amount. For example, FIG. 4C An example of includes at least three transitions 415 - c , 415 - d , 415 - e .

[0084] In some cases, the number of transitions may provide a multi-bit signal indicating, for example, that the supply voltage is outside a target range, the value of the supply voltage, an identifier of the memory device, or a combination thereof. In some cases, the multi-bit signal may be an asynchronous signal; that is, the multi-bit signal may be asynchronous (not synchronized) with a clock signal of memory device 110.

[0085] FIG. 5 A block diagram 500 illustrates a memory device 505 that supports feedback of power management to a memory die using dedicated pins according to examples disclosed herein. The memory device 505 may be a reference FIG. 1Examples of aspects of the memory device described in 4. The memory device 505 can include a bias component 510, a determination component 515, and a voltage transition component 520. Each of these modules can communicate, directly or indirectly (e.g., via one or more buses), with one another.

[0086] The bias component 510 can bias a pin of the memory device to a first voltage that indicates that a supply voltage associated with the memory device is within a target range. In some examples, the bias component 510 can bias the pin to a third voltage that is between the first voltage and a second voltage, where the third voltage indicates that the supply voltage is above a higher voltage threshold.

[0087] The determination component 515 can determine, after biasing the pin of the memory device to the first voltage, that the supply voltage is outside the target range.

[0088] In some examples, the determination component 515 can determine, at a first time, that the supply voltage is below a lower voltage threshold of the target range, where determining that the supply voltage is outside the target range is based on determining that the supply voltage is below the lower voltage threshold. In some examples, the determination component 515 can determine, at a second time, that the supply voltage is above a higher voltage threshold of the target range.

[0089] The voltage transition component 520 can transition the voltage at the pin of the memory device from the first voltage to a second voltage that indicates that the supply voltage is outside the target range based on determining that the supply voltage is outside the target range.

[0090] FIG. 6 A flow diagram illustrating one or more methods 600 that support feedback for power management of a memory die using a dedicated pin in accordance with examples as disclosed herein is shown. The operations of method 600 can be implemented by a memory device or its components as described with reference to FIG. 1 4. In some examples, operations of method 600 can be performed by a memory device as described with reference to FIG. 5 In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0091] At 605, the memory device can bias a pin of the memory device to a first voltage that indicates that a supply voltage associated with the memory device is within a target range. The operations of 605 can be performed according to the methods described with reference to FIG. 2 4. In some examples, aspects of the operations of 605 can be performed by a bias component as described with reference to FIG. 5 4. In some examples, aspects of the operations of 605 can be performed by a bias component as described with reference to

[0092] At 610, the memory device may determine that the supply voltage is outside of a target range after biasing a pin of the memory device to a first voltage. FIG. 2 -4 described method performs the operation of 610. In some examples, the reference FIG. 5 Aspects of the operations of the determination component 610 are described.

[0093] At 615, the memory device may transition a voltage at a pin of the memory device from a first voltage to a second voltage indicating that the supply voltage is outside the target range based on determining that the supply voltage is outside the target range. FIG. 2 -4 described method performs the operation of 615. In some examples, the reference FIG. 5 The described voltage conversion component performs aspects of the operation of 615 .

[0094] In some examples, an apparatus as described herein may perform one or more methods, such as method 600. The apparatus may include features, means, or instructions (e.g., instructions executable by a processor stored by a non-transitory computer-readable medium) for biasing a pin of a memory device to a first voltage indicating that a supply voltage associated with the memory device is within a target range.

[0095] Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for, after biasing the pin of the memory device to the first voltage, determining that the supply voltage is outside of the target range.

[0096] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for: based on determining that the supply voltage is outside the target range, transitioning the voltage at the pin of the memory device from the first voltage to a second voltage indicating that the supply voltage is outside the target range.

[0097] FIG. 7 A flowchart illustrating one or more methods 700 for supporting feedback of power management of a memory die using dedicated pins according to examples disclosed herein is shown. In some examples, the operations of the method 700 may be performed by reference to FIG. 1 4 to 4 described memory device or its components. In some examples, the operations of method 700 can be performed by reference FIG. 5 The memory device described herein performs the functions described herein. In some examples, the memory device may execute an instruction set to control functional elements of the memory device to perform the functions described herein. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the functions described herein.

[0098] At 705, the memory device may bias a pin of the memory device to a first voltage indicating that a supply voltage associated with the memory device is within a target range. FIG. 2 -4 described method performs the operation of 705. In some examples, the reference FIG. 5 The described biasing assembly performs aspects of the operation of 705 .

[0099] At 710, the memory device may determine that a supply voltage is outside a target range after biasing a pin of the memory device to a first voltage. FIG. 2 -4 described method performs the operation of 710. In some examples, the reference FIG. 5 Aspects of the operations of the determination component 710 are described.

[0100] At 715, the memory device may transition a voltage at a pin of the memory device from a first voltage to a second voltage indicating that the supply voltage is outside the target range based on determining that the supply voltage is outside the target range. FIG. 2 -4 described method performs the operation of 715. In some examples, the reference FIG. 5 The described voltage conversion component performs aspects of the operation of 715 .

[0101] At 720, the memory device may determine, at a first time, that the supply voltage is below a lower voltage threshold of a target range, wherein determining that the supply voltage is outside the target range is based at least in part on determining that the supply voltage is below the lower voltage threshold. FIG. 2 -4 described method performs the operation of 720. In some examples, the reference FIG. 5 The described voltage conversion component performs aspects of the operation of 720 .

[0102] At 725, the memory device may determine at a second time that the supply voltage is above a higher voltage threshold of the target range. FIG. 2 -4 described method performs the operation of 725. In some examples, the reference FIG. 5 The described voltage conversion component performs aspects of the operation of 725 .

[0103] At 730, the memory device may bias the pin to a third voltage between the first voltage and the second voltage, wherein the third voltage indicates that the supply voltage is above the upper voltage threshold. FIG. 2 -4 described method performs the operation of 730. In some examples, the reference FIG. 5 The described voltage conversion component performs aspects of the operation of 730 .

[0104] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, means, or instructions (e.g., instructions executable by a processor stored by a non-transitory computer-readable medium) for biasing a pin of a memory device to a first voltage indicating that a supply voltage associated with the memory device is within a target range.

[0105] Some examples of the method 700 and apparatus described herein may additionally include operations, features, means, or instructions for, after biasing the pin of the memory device to the first voltage, determining that the supply voltage is outside of the target range.

[0106] Some examples of the method 700 and apparatus described herein may further include operations, features, means, or instructions for: based on determining that the supply voltage is outside the target range, transitioning the voltage at the pin of the memory device from the first voltage to a second voltage indicating that the supply voltage is outside the target range.

[0107] Some examples of the method 700 and apparatus described herein may additionally include operations, features, means, or instructions for determining, at a first time, that a supply voltage is below a lower voltage threshold of a target range, wherein determining that the supply voltage is outside the target range is based at least in part on determining that the supply voltage is below the lower voltage threshold.

[0108] Some examples of the method 700 and apparatus described herein may additionally include operations, features, means, or instructions for: determining, at a second time, that the supply voltage is above an upper voltage threshold of the target range.

[0109] Some examples of method 700 and apparatus described herein may additionally include operations, features, means, or instructions for biasing the pin to a third voltage between the first and second voltages, wherein the third voltage indicates that the supply voltage is above an upper voltage threshold.

[0110] It should be noted that the methods described above describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and other embodiments are possible. Furthermore, parts from two or more of the methods may be combined.

[0111] An apparatus is described. The apparatus may include a memory cell array; a pin for transmitting a signal indicative of feedback regarding a supply voltage used during operation of the memory cell array to a power management component; and a controller operable to cause the apparatus to: determine that the supply voltage is outside a target range associated with the supply voltage; and transition a voltage at the pin from a first voltage to a second voltage indicating that the supply voltage is outside the target range.

[0112] Some examples may further include, at a first time, determining that the supply voltage may be below a lower voltage threshold of the target range, wherein determining that the supply voltage may be outside the target range may be based on determining that the supply voltage may be below the lower voltage threshold. Some examples may further include, before determining that the supply voltage may be below the lower voltage threshold, biasing the pin to the first voltage to indicate that the supply voltage may be within the target range, wherein modifying the voltage at the pin from the first voltage to the second voltage indicates that the supply voltage may be below the lower voltage threshold.

[0113] Some examples may further include determining, at a second time, that the supply voltage may be above an upper voltage threshold, wherein determining that the supply voltage may be outside the target range may be based on determining that the supply voltage may be above the upper voltage threshold. Some examples may further include biasing the pin to a third voltage indicating that the supply voltage may be above the upper voltage threshold. In some examples, the second voltage may be lower than the first voltage and the third voltage may be between the first and second voltages.

[0114] Some examples may further include selecting a voltage level for the second voltage based on determining that the supply voltage may be below a lower voltage threshold of the target range or above an upper voltage threshold of the target range, wherein a first voltage level indicates that the supply voltage may be below the lower voltage threshold and a second voltage level indicates that the supply voltage may be above the upper voltage threshold. Some examples may further include determining a value for the supply voltage, wherein determining that the supply voltage may be outside the target range may be based on determining the value for the supply voltage; and based on the value for the supply voltage, transitioning the voltage at the pin between two or more voltage levels a certain number of times, including the transitioning of the voltage from the first voltage to the second voltage. Some examples may further include determining the number of times based on the value for the supply voltage.

[0115] In some examples, transitioning the voltage at the pin between the two or more voltage levels the number of times may include operations, features, means, or instructions for: biasing the pin to a third voltage different from the second voltage after transitioning the pin from the first voltage to the second voltage. Some examples may further include generating a multi-bit signal based on the value of the supply voltage; and transmitting the multi-bit signal using the pin. In some examples, the multi-bit signal includes an indication of the value of the supply voltage, an identifier of the device, an indication of whether the supply voltage is above an upper voltage threshold or below a lower voltage threshold, or a combination thereof. In some examples, the pin may be dedicated to providing feedback to the power management component. Some examples may further include receiving an adjusted supply voltage based on transitioning the voltage at the pin. The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signaling as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a bus of signals, where the bus may have various bit widths.

[0116] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some instances, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0117] The term "coupling" refers to the condition of moving from an open-circuit relationship between components, in which signals are currently unable to communicate between the components via the conductive paths, to a closed-circuit relationship between the components, in which signals are able to communicate between the components via the conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via the conductive paths that previously did not permit signal flow.

[0118] The term "isolation" refers to a relationship between components where signals cannot flow between them. Components are isolated from one another if an open circuit exists between them. For example, components separated by a switch positioned between them are isolated from one another when the switch is open. When a controller separates two components, it implements a change that prevents signals from flowing between them using the conductive path that previously allowed signal flow.

[0119] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0120] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (e.g., most carriers are signals), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "switched on" or "activated." When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0121] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred" or "superior" to other examples. The detailed description includes specific details to provide an understanding of the described technology. However, these technologies can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0122] In the accompanying drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0123] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0124] The various illustrative blocks and modules described in connection with the present disclosure herein may be implemented or executed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0125] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located in various locations, including being distributed so that portions of the functions are implemented in different physical locations. Furthermore, as used herein, including in the claims, the term "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0126] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: memory cell array, a first pin for transmitting a signal to a power management component indicating a voltage level of a plurality of voltage levels of a supply voltage at a first memory device used during operation of the memory cell array, a second pin for transmitting a signal to the power management component indicative of a voltage level of the plurality of voltage levels of the supply voltage at a second memory device used during operation of the memory cell array, a first resistor coupled between the first pin and the power management component, wherein a value of the first resistor is based at least in part on a distance from the first resistor to the supply voltage, a second resistor coupled between the second pin and the power management component, wherein the first resistor and the second resistor have different resistance values, and A controller operable to cause the device to: determining that the supply voltage is outside of a target range associated with the supply voltage; and The voltage at the first pin is transitioned from a first voltage to a second voltage indicating that the supply voltage is outside of the target range.

2. The apparatus of claim 1 , wherein the controller is further operable to cause the apparatus to: At a first time, the supply voltage is determined to be below a lower voltage threshold of the target range, wherein determining that the supply voltage is outside the target range is based at least in part on determining that the supply voltage is below the lower voltage threshold.

3. The apparatus of claim 2, wherein the controller is further operable to cause the apparatus to: Prior to determining that the supply voltage is below the lower voltage threshold, biasing the first pin to the first voltage to indicate that the supply voltage is within a target range, wherein modifying the voltage at the first pin from the first voltage to the second voltage indicates that the supply voltage is below the lower voltage threshold.

4. The apparatus of claim 2, wherein the controller is further operable to cause the apparatus to: At a second time, the supply voltage is determined to be above an upper voltage threshold, wherein determining that the supply voltage is outside of the target range is based at least in part on determining that the supply voltage is above the upper voltage threshold.

5. The apparatus of claim 4, wherein the controller is further operable to cause the apparatus to: The first pin is biased to a third voltage indicating that the supply voltage is above the upper voltage threshold. 6 . The apparatus of claim 5 , wherein the second voltage is lower than the first voltage and the third voltage is between the first voltage and the second voltage.

7. The apparatus of claim 1 , wherein the controller is further operable to cause the apparatus to: A voltage level of the second voltage is selected based at least in part on determining that the supply voltage is below a lower voltage threshold of the target range or above an upper voltage threshold of the target range, wherein a first voltage level of the second voltage indicates that the supply voltage is below the lower voltage threshold and a second voltage level of the second voltage indicates that the supply voltage is above the upper voltage threshold.

8. The apparatus of claim 1 , wherein the controller is further operable to cause the apparatus to: determining a value of the supply voltage, wherein determining that the supply voltage is outside of the target range is based at least in part on determining the value of the supply voltage; and Based at least in part on the value of the supply voltage, the voltage at the first pin is transitioned between two or more voltage levels a number of times, including the transitioning of the voltage from the first voltage to the second voltage.

9. The apparatus of claim 8, wherein the controller is further operable to cause the apparatus to: The number is determined based at least in part on the value of the supply voltage.

10. The apparatus according to claim 9, wherein: Transitioning the voltage at the first pin between the two or more voltage levels the number of times includes biasing the first pin to a third voltage different than the second voltage after transitioning the first pin from the first voltage to the second voltage.

11. The apparatus of claim 8, wherein the controller is further operable to cause the apparatus to: generating a multi-bit signal based at least in part on the value of the supply voltage; and The multi-bit signal is transmitted using the first pin.

12. The apparatus of claim 11, wherein the multi-bit signal comprises an indication of the value of the supply voltage, an identifier of the apparatus, an indication of whether the supply voltage is above an upper voltage threshold or below a lower voltage threshold, or a combination thereof.

13. The device of claim 1, wherein the first pin is dedicated to providing feedback to the power management component.

14. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: Based at least in part on shifting the voltage at the first pin, a regulated supply voltage is received.

15. A system comprising: a first memory device comprising a first pin; a second memory device comprising a second pin; a power management component coupled to the first pin and the second pin and operable to provide a supply voltage to the first memory device and the second memory device; wherein the first memory device is operable to determine that the supply voltage is outside of a voltage range, and bias the first pin to a first voltage of a voltage level indicative of a plurality of voltage levels of the supply voltage at the first memory device based at least in part on determining that the supply voltage is outside of the voltage range; and wherein the second memory device is operable to determine that the supply voltage is outside of the voltage range, and bias the second pin to a second voltage based at least in part on determining that the supply voltage is outside of the voltage range; a first resistor coupled between the first pin and the power management component, wherein a value of the first resistor is based at least in part on a distance from the first resistor to the supply voltage; and A second resistor is coupled between the second pin and the power management component, wherein the first resistor and the second resistor have different resistance values. 16 . The system of claim 15 , wherein the power management component is configured to determine voltages at the first pin and the second pin and adjust the supply voltage based at least in part on the voltages at the first pin and the second pin.

17. The system of claim 15, wherein the power management component is configured to determine a first number of voltage transitions at the first pin and a second number of voltage transitions at the second pin and to adjust the supply voltage based at least in part on the first number of voltage transitions.

18. A method comprising: biasing a first pin of a memory device to a first voltage indicating that a supply voltage associated with the memory device is within a target range, wherein a power management component is coupled to the first pin and is operable to provide the supply voltage to the memory device, wherein a first resistor is coupled between the first pin and the power management component, wherein a value of the first resistor is based at least in part on a distance from the first resistor to the supply voltage, wherein a second resistor is coupled between a second pin of the memory device and the power management component, and wherein the first resistor and the second resistor have different resistance values; after biasing the first pin of the memory device to the first voltage, determining that the supply voltage is outside of the target range; and Based at least in part on determining that the supply voltage is outside the target range, a voltage at the first pin of the memory device is transitioned from the first voltage to a second voltage indicating that the supply voltage is outside the target range.

19. The method of claim 18, further comprising: At a first time, the supply voltage is determined to be below a lower voltage threshold of the target range, wherein determining that the supply voltage is outside the target range is based at least in part on determining that the supply voltage is below the lower voltage threshold.

20. The method of claim 19, further comprising: at a second time, determining that the supply voltage is above a higher voltage threshold of the target range; and The first pin is biased to a third voltage between the first voltage and the second voltage, wherein the third voltage indicates that the supply voltage is above the upper voltage threshold.

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