Array substrate and manufacturing method thereof, and display device

Abstract

An array substrate and a manufacturing method thereof, and a display device, wherein the array substrate comprises a P-type driving transistor (DT), an N-type first transistor (T1), a capacitor (C), a base substrate (1), a first conductive layer, a first dielectric layer (43), a first buffer layer (41), and a second conductive layer, wherein the first conductive layer is stacked on one side of the base substrate (1) and comprises a first conductive portion (13) configured as a gate of the driving transistor (DT) and a first electrode of the capacitor (C); the first dielectric layer (43) is stacked on the first conductive layer away from the first conductive layer. A first buffer layer (41) is stacked on a side of a first dielectric layer (43) away from the base substrate (1), and is provided with a groove (411); a second conductive layer is stacked on a side of the first buffer layer (41) away from the base substrate (1), and comprises a second conductive portion (55) and a third conductive portion (721), the second conductive portion (55) being configured as a gate of a first transistor (T1); and the third conductive portion (721) is located at the bottom of the groove (411) to form a second electrode of a capacitor (C). In the array substrate, the gate of the driving transistor (DT) has good noise interference resistance.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display device. Background Art

[0002] In the related art, the pixel driving circuit can be formed by using low temperature polycrystalline oxide (LTPO) technology. The low temperature polycrystalline oxide technology forms a pixel driving circuit by combining an N-type metal oxide transistor and a P-type low temperature polycrystalline silicon transistor.

[0003] In the related art, LTPO technology usually forms an electrode of a capacitor in a pixel driving circuit through a conductive part located in the source and drain layer. The conductive part is connected to the gate of the driving transistor through a via to achieve the connection between the capacitor and the gate of the driving transistor. However, in order to form a capacitor structure, the conductive part has a large area, which makes the gate of the driving transistor connected to the conductive part susceptible to noise.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

[0005] Public Content

[0006] According to one aspect of the present disclosure, an array substrate is provided, which includes a pixel driving circuit, wherein the pixel driving circuit includes a P-type driving transistor, an N-type first transistor, and a capacitor, wherein a first electrode of the first transistor is connected to a gate of the driving transistor, and a first electrode of the capacitor is connected to the gate of the driving transistor, wherein the array substrate also includes: a base substrate, a first conductive layer, a first dielectric layer, a first buffer layer, and a second conductive layer. A first conductive layer is stacked on one side of the base substrate, the first conductive layer includes a first conductive portion, and the first conductive portion is configured as the gate of the driving transistor and the first electrode of the capacitor; a first dielectric layer is stacked on the side of the first conductive layer away from the base substrate; a first buffer layer is stacked on the side of the first dielectric layer away from the base substrate, a groove is provided on the first buffer layer, and the orthographic projection of the groove on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate; a second conductive layer is stacked on the side of the first buffer layer away from the base substrate, the second conductive layer includes a second conductive portion and a third conductive portion, the second conductive portion is configured as the gate of the first transistor; the third conductive portion is located at the bottom of the groove, and the orthographic projection of the third conductive portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate to form the second electrode of the capacitor.

[0007] In an exemplary embodiment of the present disclosure, the groove extends to the surface of the first dielectric layer, and the third conductive portion is located on a side of the first dielectric layer facing away from the base substrate.

[0008] In an exemplary embodiment of the present disclosure, the array substrate also includes: a third conductive layer, which is stacked on a side of the second conductive layer away from the base substrate, and includes a fourth conductive portion, which is electrically connected to the first conductive portion through a first via hole penetrating the third conductive portion, and is insulated from the second conductive portion; wherein the orthographic projection of the fourth conductive portion on the base substrate is located on the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection area of ​​the fourth conductive portion on the base substrate is smaller than the orthographic projection area of ​​the first conductive portion on the base substrate.

[0009] In an exemplary embodiment of the present disclosure, a ratio of an orthographic projection area of ​​the fourth conductive portion on the base substrate to an orthographic projection area of ​​the first via hole on the base substrate is 1-1.5.

[0010] In an exemplary embodiment of the present disclosure, a ratio of an orthographic projection area of ​​the fourth conductive portion on the base substrate to an orthographic projection area of ​​the first conductive portion on the base substrate is 8%-15%.

[0011] In an exemplary embodiment of the present disclosure, a second via is formed on the third conductive portion, the second via penetrates the first dielectric layer and extends to the surface of the first conductive portion, the array substrate also includes a second dielectric layer, the second dielectric layer is stacked between the second conductive layer and the third conductive layer, the first via is formed on the second dielectric layer, the first via penetrates the third conductive portion and extends to the surface of the first conductive portion; and the orthographic projection of the first via on the base substrate is located within the orthographic projection of the second via on the base substrate.

[0012] In an exemplary embodiment of the present disclosure, the third conductive layer also includes a power line for providing a power supply voltage, and the array substrate also includes a fourth conductive layer, which is stacked on a side of the third conductive layer away from the base substrate, and the fourth conductive layer includes a fifth conductive part connected to the power line, and the orthographic projection of the fifth conductive part on the base substrate covers the orthographic projection of the first conductive part on the base substrate.

[0013] In an exemplary embodiment of the present disclosure, the second conductive layer further includes a sixth conductive portion connected to the third conductive portion, and the sixth conductive portion is connected to the power line through a via hole.

[0014] In an exemplary embodiment of the present disclosure, the first buffer layer includes a first buffer layer and a first gate insulating layer. The first buffer layer is stacked on a side of the first dielectric layer away from the substrate; the first gate insulating layer is stacked on a side of the first buffer layer away from the substrate.

[0015] In an exemplary embodiment of the present disclosure, the array substrate further comprises: a first active layer, a second active layer, a second gate insulating layer, a blocking layer, a second buffer layer, a second dielectric layer, a passivation layer, and a first gate insulating layer. The blocking layer is stacked on one side of the base substrate; the second buffer layer is stacked on the side of the blocking layer away from the base substrate; the first active layer is stacked on the side of the second buffer layer away from the base substrate, the first active layer comprises a first active portion, and the first active portion is configured as a channel region of the driving transistor; the second gate insulating layer is stacked on the side of the first active layer away from the base substrate, wherein the first conductive layer is stacked on the side of the second gate insulating layer away from the base substrate; the second active layer is stacked on the side of the first buffer layer away from the base substrate, and comprises a first active portion; The present invention relates to a transistor having two active parts, wherein the second active part is configured as a channel region of the first transistor; a first gate insulating layer is stacked on a side of the second active layer away from the substrate, wherein a second conductive layer is stacked on a side of the first gate insulating layer away from the substrate; a second dielectric layer is stacked on a side of the second active layer away from the substrate, and a second dielectric layer is stacked on a side of the second conductive layer away from the substrate, wherein a third conductive layer is stacked on a side of the second dielectric layer away from the substrate; and a passivation layer is stacked on a side of the third conductive layer away from the substrate.

[0016] In an exemplary embodiment of the present disclosure, the array substrate includes a non-display area, and a strip groove is formed on the array substrate in the non-display area, and the strip groove penetrates the passivation layer, the second dielectric layer, the first buffer layer, the first dielectric layer, the second buffer layer, and the barrier layer and extends to the surface of the base substrate; the array substrate also includes a first flat layer, which is stacked on a side of the passivation layer away from the base substrate and fills the strip groove; wherein the bendability of the material of the first flat layer is stronger than the bendability of the material of the passivation layer, the second dielectric layer, the first buffer layer, the first dielectric layer, the second buffer layer, and the barrier layer.

[0017] In an exemplary embodiment of the present disclosure, the thickness of the first dielectric layer in the stacking direction is 1200-1400 angstroms.

[0018] In an exemplary embodiment of the present disclosure, the array substrate further includes: an enable signal line, an initial signal line, an anode layer, a first reset signal line, a second reset signal line, a power line, a first gate line, a second gate line, and a data line. The second electrode of the first transistor is connected to the second electrode of the driving transistor, and the gate is connected to the second gate line. The pixel driving circuit further includes: a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first electrode of the second transistor is connected to the data line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the first gate line; the first electrode of the third transistor is connected to the gate of the driving transistor, the second electrode is connected to the initial signal line, and the gate is connected to the second reset signal line; the first electrode of the fourth transistor is connected to the power line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the enable signal line; the first electrode of the fifth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the anode layer, and the gate is connected to the enable signal line; the first electrode of the sixth transistor is connected to the second electrode of the fifth transistor, the second electrode is connected to the initial signal line, and the gate is connected to the first reset signal line.

[0019] In an exemplary embodiment of the present disclosure, the driving transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are P-type low-temperature polysilicon transistors; and the first transistor and the third transistor are N-type metal oxide transistors.

[0020] According to one aspect of the present disclosure, a method for manufacturing an array substrate is provided, wherein the array substrate includes a pixel driving circuit, wherein the pixel driving circuit includes a P-type driving transistor, an N-type first transistor, and a capacitor, wherein a first electrode of the first transistor is connected to a gate of the driving transistor, and a first electrode of the capacitor is connected to the gate of the driving transistor, and the array substrate manufacturing method includes:

[0021] forming a substrate base;

[0022] forming a first conductive layer on one side of the base substrate, wherein the first conductive layer includes a first conductive portion, and the first conductive portion is configured as a gate of the driving transistor and a first electrode of the capacitor;

[0023] forming a first dielectric layer on a side of the first conductive layer facing away from the substrate;

[0024] A first buffer layer is formed on a side of the first dielectric layer away from the base substrate, wherein a groove is provided on the first buffer layer, and an orthographic projection of the groove on the base substrate at least partially overlaps with an orthographic projection of the first conductive portion on the base substrate;

[0025] A second conductive layer is formed on a side of the first buffer layer away from the first conductive layer, wherein the second conductive layer comprises:

[0026] a second conductive portion, the second conductive portion being configured as a gate of the first transistor;

[0027] A third conductive portion is located at the bottom of the slot, and an orthographic projection of the third conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first conductive portion on the base substrate to form a second electrode of the capacitor.

[0028] A first buffer layer is formed on a side of the first dielectric layer facing away from the first conductive layer, comprising:

[0029] forming a first buffer material layer on a side of the first dielectric layer away from the substrate;

[0030] forming a first gate insulating material layer on a side of the first buffer material layer away from the base substrate;

[0031] Etching the first buffer material layer and the first gate insulating material layer to form the groove;

[0032] Wherein, the first buffer material layer after etching forms the first buffer layer.

[0033] In an exemplary embodiment of the present disclosure, the groove extends to the surface of the first dielectric layer, and the third conductive portion is located on a side of the first dielectric layer away from the substrate.

[0034] In an exemplary embodiment of the present disclosure, the substrate manufacturing method further includes:

[0035] forming a third conductive layer on a side of the second conductive layer away from the base substrate, wherein the third conductive layer comprises a fourth conductive portion, and the fourth conductive portion is electrically connected to the first conductive portion through a via hole penetrating the third conductive portion;

[0036] The orthographic projection of the fourth conductive part on the base substrate is located on the orthographic projection of the first conductive part on the base substrate, and the orthographic projection area of ​​the fourth conductive part on the base substrate is smaller than the orthographic projection area of ​​the first conductive part on the base substrate.

[0037] In an exemplary embodiment of the present disclosure, before forming a third conductive layer on a side of the second conductive layer away from the base substrate, the method further includes:

[0038] forming a second via hole on the third conductive portion, wherein the second via hole penetrates the first dielectric layer and extends to a surface of the first conductive portion;

[0039] forming a second dielectric layer on a side of the second conductive layer facing away from the substrate, wherein the second dielectric layer fills the second via hole;

[0040] forming a first via hole on the second dielectric layer, wherein the first via hole penetrates the third conductive portion and extends to the surface of the first conductive portion; and an orthographic projection of the first via hole on the base substrate is located within an orthographic projection of the second via hole on the base substrate;

[0041] Wherein, the fourth conductive part fills the first via hole.

[0042] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned array substrate.

[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0045] Figure 1 A schematic diagram of the circuit structure of a pixel driving circuit disclosed in the present invention;

[0046] Figure 2 It is a structural schematic diagram of an array substrate in the related art;

[0047] Figure 3 This is a schematic structural diagram of an exemplary embodiment of an array substrate disclosed in the present invention;

[0048] Figure 4a is a structural schematic diagram of another exemplary embodiment of the array substrate disclosed in the present invention;

[0049] Figure 4b for Figure 3 A partial top view of

[0050] Figure 4c A partial top view of another exemplary embodiment of the array substrate disclosed in the present invention;

[0051] Figure 4d A partial top view of another exemplary embodiment of the array substrate disclosed in the present invention;

[0052] Figure 5 is a structural schematic diagram of another exemplary embodiment of the array substrate disclosed in the present invention;

[0053] Figure 6 is a structural schematic diagram of another exemplary embodiment of the array substrate disclosed in the present invention;

[0054] Figure 7 is a structural schematic diagram of another exemplary embodiment of the array substrate disclosed in the present invention;

[0055] Figure 8-14 A process flow chart of an exemplary embodiment of a method for manufacturing an array substrate disclosed herein;

[0056] Fig.15 is the structural layout of the first active layer;

[0057] Fig.16 is a structural layout of a first conductive layer;

[0058] Fig.17 is the structural layout of the second active layer;

[0059] Fig.18 A combination layout of a first active layer, a first conductive layer, and a second active layer;

[0060] Fig.19 is a structural layout of a second conductive layer;

[0061] Fig. 20 A combination layout of a first active layer, a first conductive layer, a second active layer, and a second conductive layer;

[0062] Fig.21 is a structural layout of the third conductive layer;

[0063] Fig. 22 A combination layout of a first active layer, a first conductive layer, a second active layer, a second conductive layer, and a third conductive layer;

[0064] Fig.23 is a structural layout of a fourth conductive layer;

[0065] Fig.24 A combination layout of a first active layer, a first conductive layer, a second active layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;

[0066] Fig.25 is the structural layout of the anode layer;

[0067] Fig.26 A combination pattern of a first active layer, a first conductive layer, a second active layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and an anode layer;

[0068] Fig. 27 for Figure 1 A timing diagram of each node in a driving method of a pixel driving circuit;

[0069] Fig.28 for Fig. 9 A local layout structure of the first conductive layer;

[0070] Fig.29 for Fig.21 Partial layout structure of the third conductive layer;

[0071] Fig.30 for Fig. 22 Part of the layout structure in ;

[0072] Fig.31 for Fig.24 Part of the layout structure. DETAILED DESCRIPTION

[0073] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0074] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". Other relative terms, such as "high", "low", "top", "bottom", "left", "right", etc., also have similar meanings. When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0075] The terms "a", "an", and "the" are used to indicate the presence of one or more elements / component distinctions / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / component distinctions / etc. may exist in addition to the listed elements / component distinctions / etc.

[0076] like Figure 1FIG. 2 is a schematic diagram of a circuit structure of a pixel driving circuit disclosed in the present invention. The pixel driving circuit may include: a driving transistor DT, a second transistor T2, a first transistor T1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a capacitor C. Among them, the first electrode of the second transistor T2 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor DT, and the gate is connected to the first gate driving signal terminal G1; the first electrode of the fourth transistor T4 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor DT, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor DT is connected to the node N, and the second electrode is connected to the first electrode of the fifth transistor T5; the first electrode of the first transistor T1 is connected to the node N, the second electrode is connected to the second electrode of the driving transistor DT, and the gate is connected to the second gate driving signal terminal G2; the second electrode of the fifth transistor T5 is connected to the first electrode of the sixth transistor T6, the gate is connected to the enable signal terminal EM, the second electrode of the sixth transistor T6 is connected to the initial signal terminal Vinit, and the gate is connected to the first reset signal terminal Re1; the first electrode of the third transistor T3 is connected to the node N, the second electrode is connected to the initial signal terminal Vinit, and the gate is connected to the second reset signal terminal Re2, and the capacitor C is connected between the first power supply terminal VDD and the node N. The pixel driving circuit can be connected to a light-emitting unit OLED, which is used to drive the light-emitting unit OLED to emit light, and the light-emitting unit OLED is connected between the second electrode of the fifth transistor T5 and the second power supply terminal VSS. Among them, the first transistor T1 and the third transistor T3 can be N-type metal oxide transistors, which have a small leakage current, so that the node N can be prevented from leaking through the first transistor T1 and the third transistor T3 during the light-emitting stage. At the same time, the driving transistor DT, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be low-temperature polysilicon transistors, which have a high carrier mobility, so as to be conducive to realizing a display device with high resolution, high response speed, high pixel density, and high aperture ratio.

[0077] like Figure 2 FIG. 1 is a schematic diagram of a structure of an array substrate in the related art. The array substrate may include Figure 1The pixel driving circuit shown. The array substrate may include a substrate 01, a barrier layer 02 located on one side of the substrate 01, a second buffer layer 03 located on a side of the barrier layer away from the substrate 01, a first active layer (including a first active portion 04) located on a side of the second buffer layer 03 away from the substrate 01, a first gate insulating layer 05 located on a side of the first active layer away from the substrate, a first gate layer (including a first gate portion 06) located on a side of the first gate insulating layer away from the substrate, a first dielectric layer 07 located on a side of the first gate layer away from the substrate, a first buffer layer 08 located on a side of the first buffer layer 08 away from the substrate 01. The second active layer (including the second active portion 09), the second gate insulating layer (including the first insulating portion 0101 and the second insulating portion 0102) located on the side of the second active layer away from the substrate, the second gate layer (including the second gate portion 0112 and the third gate portion 0111) located on the side of the second gate insulating layer away from the substrate, the second dielectric layer 012 located on the side of the second gate layer away from the substrate, the first source and drain layer (including the first conductive portion 013) located on the side of the second dielectric layer 012 away from the substrate, the passivation layer 014 located on the side of the first source and drain layer away from the substrate, and the second source and drain layer (including the second conductive portion 015) located on the side of the passivation layer 014 away from the substrate. The first gate portion 06 can be configured as the gate of the driving transistor, and the second gate portion 0112 can be configured as the gate of the first transistor T1 or the third transistor T3. The first conductive portion 013 is connected to the first gate portion 06 through a via. In the related art, the distance between the first source-drain layer and the second source-drain layer is small, so that the second conductive part 015 can form the second electrode of the capacitor C, and at the same time, the second conductive part 015 can cover the first conductive part 013 to shield the noise influence of other signals on the first conductive part 013. However, since the first conductive part 013 needs to form the electrode of the capacitor, the first conductive part 013 needs to be designed to have a larger area, so that in a limited plane space, it is not easy for the second conductive part 015 to completely cover the first conductive part 013, which makes the first conductive part 013 susceptible to external noise interference. In addition, the first conductive part 013 with a larger area is also easy to form a larger parasitic capacitance with other structures. Under the parasitic capacitance coupling effect, the gate of the driving transistor is more susceptible to external noise interference.

[0078] Based on this, this exemplary embodiment provides an array substrate, wherein the array substrate includes a pixel driving circuit. The pixel driving circuit can be as follows: Figure 1 As shown. Figure 3FIG. 1 is a schematic diagram of the structure of an exemplary embodiment of an array substrate of the present disclosure. The array substrate may include: a base substrate 1, a first conductive layer, a first dielectric layer 43, a first buffer layer 41, and a second conductive layer. A first conductive layer is stacked on one side of the base substrate 1, and the first conductive layer may include a first conductive portion 13, and the first conductive portion 13 may be configured as the gate of the driving transistor and the first electrode of the capacitor C; a first dielectric layer 43 may be stacked on the side of the first conductive layer away from the base substrate 1; a first buffer layer 41 may be stacked on the side of the first dielectric layer 43 away from the base substrate 1, and a groove 411 is provided on the first buffer layer 41, and the orthographic projection of the groove 411 on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion 13 on the base substrate; a second conductive layer is stacked on the side of the first buffer layer 41 away from the base substrate 1, and the second conductive layer may include a second conductive portion 55 and a third conductive portion 721, and the second conductive portion 55 is configured as the gate of the first transistor; the third conductive portion 721 is located at the bottom of the groove 411, and the orthographic projection of the third conductive portion 721 on the base substrate 1 at least partially overlaps with the orthographic projection of the first conductive portion 13 on the base substrate, so as to form the second electrode of the capacitor. The second conductive portion 55 may be located outside the slot 411 , that is, the orthographic projection of the second conductive portion 55 on the base substrate does not intersect with the orthographic projection of the slot 411 on the base substrate.

[0079] It should be noted that, in this exemplary embodiment, different structural parts in the same structural film layer (for example, the first conductive layer, the second conductive layer) can be formed by a single patterning process. Regarding the description in the present disclosure: "Layer A (any structural film layer) is located on the side of layer B (any structural film layer) away from the base substrate", wherein, when layer B is a patterned structural film layer, layer A can include not only a portion located directly above layer B, but also a portion filled in the hollow area of ​​layer B, that is, layer A can include portion X located directly above layer B and other structural parts formed with portion X by a single patterning process or a single deposition process, and the orthographic projection of portion X on the base substrate coincides with the orthographic projection of layer B on the base substrate. For example, as Figure 3 As shown, the first dielectric layer 43 includes not only the portion located directly above the first conductive portion 13 but also other portions formed by the same deposition process; the second conductive layer may include not only the second conductive portion 55 located directly above the first buffer layer 41 but also the third conductive portion 721 formed with the second conductive portion 55 through a single patterning process.

[0080] The array substrate provided by this exemplary embodiment is provided with a groove 411 on the first buffer layer 41, and a third conductive portion 721 is provided at the bottom of the groove 411. The provision of the groove 411 reduces the distance between the third conductive portion 721 and the first conductive portion 13, so that the third conductive portion 721 and the first conductive portion 13 can form two electrodes of the capacitor C. On the one hand, this exemplary embodiment does not need to design the first conductive portion 013 with a large area as a capacitor electrode in the related art, thereby reducing the noise influence of the external signal on the gate of the driving transistor; on the other hand, the array substrate provided by this exemplary embodiment can be provided without the second source and drain layer in the related art, thereby simplifying the structure of the array substrate.

[0081] It should be understood that in other exemplary embodiments, the pixel driving circuit may also be of other structures, and the array substrate including the LTPO pixel driving circuit may adopt the above structure to form the capacitor of the corresponding pixel driving circuit.

[0082] In this exemplary embodiment, Figure 3 As shown, the groove 411 can extend to the surface of the first dielectric layer 43, that is, the bottom of the groove 411 can be formed by the first dielectric layer 43, and the third conductive portion 721 can be located on the side of the first dielectric layer 43 away from the substrate 1. The first dielectric layer 43 located between the first conductive portion 13 and the third conductive portion 721 can serve as a dielectric layer of a parallel plate capacitor structure. It should be understood that in other exemplary embodiments, the groove 411 can also extend to other positions, for example, Figure 4a , which is a schematic diagram of another exemplary embodiment of the array substrate of the present disclosure. The groove 411 may extend into the first buffer layer 41, that is, the bottom of the groove 411 is formed by a portion of the first buffer layer 41. Figure 4b As shown, Figure 3 In the partial top view of the substrate, the area of ​​the third conductive portion 721 projected on the substrate is smaller than the area of ​​the bottom of the slot 411 projected on the substrate, and the third conductive portion 721 is located at the bottom of the slot 411. It should be understood that in other exemplary embodiments, the area of ​​the third conductive portion 721 projected on the substrate may also be greater than or equal to the area of ​​the bottom of the slot 411 projected on the substrate. Figure 4c , which is a partial top view of another exemplary embodiment of the array substrate of the present disclosure, wherein the area of ​​the third conductive portion 721 projected on the substrate is larger than the area of ​​the bottom of the slot 411 projected on the substrate. Figure 4d , which is a partial top view of another exemplary embodiment of the array substrate of the present disclosure, wherein the area of ​​the orthographic projection of the third conductive portion 721 on the substrate is equal to the area of ​​the orthographic projection of the bottom of the slot 411 on the substrate.

[0083] In this exemplary embodiment, Figure 5 , which is a schematic diagram of the structure of another exemplary embodiment of the array substrate of the present disclosure. The array substrate may further include: a third conductive layer, which may be stacked on the side of the second conductive layer away from the base substrate 1, and the third conductive layer may include a fourth conductive portion 24, and the fourth conductive portion 24 may be electrically connected to the first conductive portion 13 through a first via 81 penetrating the third conductive portion 721, and is insulated from the third conductive portion 721. The orthographic projection of the fourth conductive portion 24 on the base substrate 1 may be located on the orthographic projection of the first conductive portion 13 on the base substrate 1, and the orthographic projection area of ​​the fourth conductive portion 24 on the base substrate 1 may be smaller than the orthographic projection area of ​​the first conductive portion 13 on the base substrate.

[0084] In this exemplary embodiment, the fourth conductive portion 24 is set to a smaller area. On the one hand, this setting can reduce the parasitic capacitance between the fourth conductive portion 24 and other conductive structures (such as data lines, anode layers, etc.), thereby reducing the noise impact of other structures on the gate of the driving transistor; on the other hand, this setting can facilitate shielding the fourth conductive portion 24 through a shielding layer to further reduce the noise impact of other structures on the gate of the driving transistor. Among them, the ratio of the orthogonal projection area of ​​the fourth conductive portion 24 on the substrate 1 to the orthogonal projection area of ​​the first conductive portion 13 on the substrate can be 4%-25%. For example, the ratio of the orthogonal projection area of ​​the fourth conductive portion 24 on the substrate 1 to the orthogonal projection area of ​​the first conductive portion 13 on the substrate can be any one of 4%, 8%, 10%, 12%, 15%, 20%, and 25%.

[0085] In this exemplary embodiment, the ratio of the orthographic projection area of ​​the fourth conductive portion 24 on the substrate 1 to the orthographic projection area of ​​the first via hole 81 on the substrate may be 1-2.5. For example, the ratio of the orthographic projection area of ​​the fourth conductive portion 24 on the substrate 1 to the orthographic projection area of ​​the first via hole 81 on the substrate may be 1, 1.2, 1.3, 1.5, 2.0, 2.3, 2.5, etc. It should be understood that in other exemplary embodiments, due to process errors and other reasons, the orthographic projection area of ​​the fourth conductive portion 24 on the substrate 1 may also be slightly smaller than the orthographic projection area of ​​the first via hole 81 on the substrate.

[0086] In this exemplary embodiment, Figure 5As shown, a second via hole 82 may be formed on the third conductive part 721, and the second via hole 82 may extend through the first dielectric layer 43 to the upper surface of the first conductive part 13. The array substrate may also include a second dielectric layer 42, and the second dielectric layer 42 may be stacked between the second conductive layer and the third conductive layer, and fill the second via hole 2. The first via hole 81 may be formed on the second dielectric layer 42, and the first via hole 81 may extend through the third conductive part 721 to the upper surface of the first conductive part 13, and the orthographic projection of the first via hole 81 on the substrate 1 is located within the orthographic projection of the second via hole 82 on the substrate. This arrangement can realize the electrical connection between the fourth conductive part 24 and the first conductive part 13, and at the same time, the fourth conductive part 24 can be insulated from the third conductive part 721. Among them, regarding the above description "the orthographic projection of the first via hole at 81 of the substrate substrate 1 is located within the orthographic projection of the second via hole 82 at the substrate substrate", it can be understood that the orthographic projection of the first via hole at 81 of the substrate substrate 1 is located on the orthographic projection of the second via hole 82 at the substrate substrate, and the edge of the orthographic projection of the first via hole at 81 of the substrate substrate 1 is spaced from the edge of the orthographic projection of the second via hole 82 at the substrate substrate.

[0087] In this exemplary embodiment, Figure 5 As shown, the third conductive layer may further include a power line 26 for providing a power supply voltage, and the array substrate may further include a passivation layer 49, a first flat layer 47, and a fourth conductive layer. The passivation layer 49 may be stacked on the side of the third conductive layer away from the base substrate 1, the first flat layer 47 may be stacked on the side of the passivation layer 49 away from the base substrate 1, the fourth conductive layer may be stacked on the side of the first flat layer 47 away from the base substrate 1, and the fourth conductive layer may include a fifth conductive portion 35 connected to the power line 26, and the orthographic projection of the fifth conductive portion 35 on the base substrate may cover the orthographic projection of the first conductive portion on the base substrate. Among them, the power line 26 may be used to provide Figure 1 As for the first power supply terminal VDD in the circuit, since the fifth conductive part 35 is connected to a stable voltage and the orthographic projection of the fifth conductive part 35 on the substrate can cover the orthographic projection of the first conductive part 13 on the substrate, the fifth conductive part 35 can serve as a shielding layer to shield the noise influence of other signals on the first conductive part 13.

[0088] In this exemplary embodiment, Figure 5 As shown, the second conductive layer may further include a sixth conductive portion 722 connected to the third conductive portion 721 , and the sixth conductive portion 722 may be connected to the power line 26 through a via hole, thereby connecting the second electrode of the capacitor to the first power terminal VDD.

[0089] It should be noted that the power line 26 can extend in one direction. Figure 5 The reason why the power line 26 appears in two different positions is that Figure 5 It is a cross-sectional view along a bending line on the array substrate layout structure. The position of the bending line will be specifically described below in relation to the array substrate layout structure.

[0090] In this exemplary embodiment, Figure 6 , which is a schematic diagram of the structure of another exemplary embodiment of the array substrate of the present disclosure. The array substrate may also include: a barrier layer 48, a second buffer layer 44, a first active layer, a second gate insulating layer 45, a second active layer, and a first gate insulating layer 18. Among them, the base substrate 1, the barrier layer 48, the second buffer layer 44, the first active layer, the second gate insulating layer 45, the first conductive layer, the first dielectric layer 43, the first buffer layer 41, the second active layer, the first gate insulating layer 18, the second conductive layer, the second dielectric layer 42, the third conductive layer, the passivation layer 49, the first flat layer 47, and the fourth conductive layer are stacked in sequence. Among them, the first active layer may include a first active portion 53, and the first active portion 53 may be configured as the channel region of the driving transistor DT. The second active layer may include a second active portion 62, and the second active portion 62 may be configured as the channel region of the first transistor T1.

[0091] In this exemplary embodiment, Figure 7 , which is a schematic diagram of the structure of another exemplary embodiment of the array substrate of the present disclosure. The array substrate may include a non-display area 403, and a strip groove 121 located in the non-display area 403 is formed on the array substrate, and the strip groove 121 may penetrate the passivation layer 49, the second dielectric layer 42, the first buffer layer 41, the first dielectric layer 43, the second gate insulating layer 45, the second buffer layer 44, and the barrier layer 48 to extend to the surface of the base substrate 1. The first flat layer 47 may fill the strip groove 121. The bendability of the material of the first flat layer 47 may be stronger than the bendability of the material of the passivation layer 49, the second dielectric layer 42, the first buffer layer 41, the first dielectric layer 43, the second gate insulating layer 45, the second buffer layer 44, and the barrier layer 48. For example, the first planar layer 47 may be made of organic materials, and the passivation layer 49, the second dielectric layer 42, the first buffer layer 41, the first dielectric layer 43, the second gate insulating layer 45, the second buffer layer 44, and the barrier layer 48 may be made of inorganic materials. The location of the strip groove 121 may be used as a bending area to bend the chip connected to the array substrate to the back of the array substrate. Figure 7 As shown, the fourth conductive layer may further include a signal line 38 , and the signal line 38 may be located in the non-display area 403 .

[0092] In this exemplary embodiment, Figure 7 As shown, the array substrate may further include a second flat layer 19, an anode layer 20, and a pixel defining layer 401. The second flat layer 19 may be stacked and arranged on the side of the fourth conductive layer away from the base substrate 1; the anode layer 20 may be stacked and arranged on the side of the second flat layer 19 away from the base substrate 1; and the pixel defining layer 401 may be stacked and arranged on the side of the anode layer away from the base substrate 1. The anode layer 20 may be configured as Figure 1 The pixel defining layer 401 may form a pixel opening for depositing the light emitting unit. In addition, a support column 402 may be provided on the side of the pixel defining layer 401 away from the substrate, and the support column 402 may be used to support the mask.

[0093] In this exemplary embodiment, the substrate substrate may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, a second polyimide (PI) layer, and a second silicon oxide layer stacked in sequence. The barrier layer 48 may be located on the side of the second silicon oxide layer away from the first polyimide (PI) layer. The thickness of the first polyimide (PI) layer and the second polyimide (PI) layer may be 90000-110000±5% angstroms, for example, 90000 angstroms, 95000 angstroms, 110000 angstroms; the thickness of the first silicon oxide layer may be 5000-7000 angstroms, for example, 5000 angstroms, 5500 angstroms, 7000 angstroms; the thickness of the amorphous silicon layer may be 40-60 angstroms, for example, 40 angstroms, 45 angstroms, 60 angstroms; the thickness of the second silicon oxide layer may be 4500-6500 angstroms, for example, 4500 angstroms, 5000 angstroms, 6500 angstroms.

[0094] In this exemplary embodiment, the second buffer layer 44 may include a first silicon nitride (SiN) layer and a third silicon oxide layer stacked in sequence, and the first silicon nitride layer may be located between the third silicon oxide layer and the substrate. The thickness of the first silicon nitride layer may be 900-1100 angstroms, for example, 900 angstroms, 950 angstroms, 1100 angstroms; the thickness of the third silicon oxide layer may be 2000-4000 angstroms, for example, 2000 angstroms, 2500 angstroms, 4000 angstroms. The first active layer may be a polycrystalline silicon layer, and the thickness of the first active layer may be 400-600 angstroms, for example, 400 angstroms, 500 angstroms, 600 angstroms. The second gate insulating layer 45 may be a silicon oxide layer, and the thickness of the second gate insulating layer 45 may be 500-2000 angstroms, for example, 500 angstroms, 1500 angstroms, 2000 angstroms. The first conductive layer and the second conductive layer may both be molybdenum layers, and the thickness of the first conductive layer and the second conductive layer may both be 1500-2500 angstroms, for example, 1500 angstroms, 2000 angstroms, and 2500 angstroms. The first dielectric layer 43 may be a silicon nitride layer, and the thickness of the first dielectric layer 43 may be 1200-1400 angstroms, for example, 1200 angstroms, 1250 angstroms, 1300 angstroms, 1350 angstroms, and 1400 angstroms. The first buffer layer 41 may be a silicon oxide layer, and the thickness of the first buffer layer 41 may be 3000-5000 angstroms, for example, 3000 angstroms, 3500 angstroms, and 5000 angstroms. The second active layer may be an indium gallium zinc oxide (IGZO) layer, and the thickness of the second active layer may be 300-500 angstroms, for example, 300 angstroms, 350 angstroms, and 500 angstroms. The second gate insulating layer 45 may be a silicon oxide layer, and the thickness of the second gate insulating layer 45 may be 1000-2000 angstroms, for example, 1000 angstroms, 1500 angstroms, 2000 angstroms. The third conductive layer may include a first titanium layer, an aluminum layer, and a second titanium layer stacked in sequence, and the thickness of the first titanium layer and the second titanium layer may be 300-700 angstroms, for example, 300 angstroms, 450 angstroms, 700 angstroms, and the thickness of the aluminum layer may be 4500-6500 angstroms, for example, 4500 angstroms, 5000 angstroms, 6500 angstroms. The second planar layer 19 may be a polyimide (PI) layer, and the thickness of the second planar layer 19 may be 10000-20000 angstroms, for example, 10000 angstroms, 16000 angstroms, 20000 angstroms. The pixel defining layer 401 may be a polyimide (PI) layer, and the thickness of the pixel defining layer 401 may be 10000-20000 angstroms, for example, 10000 angstroms, 16000 angstroms, 20000 angstroms. The support column 402 may be a polyimide (PI) layer, and the thickness of the support column 402 may be 10000-20000 angstroms, for example, 10000 angstroms, 16000 angstroms, 20000 angstroms.The anode layer 20 may include a first indium tin oxide layer, a silver layer, and a second indium tin oxide layer stacked in sequence. The thickness of the first indium tin oxide layer and the second indium tin oxide layer may be 50-100 angstroms, for example, 50 angstroms, 80 angstroms, and 100 angstroms. The thickness of the silver layer may be 500-1500 angstroms, for example, 500 angstroms, 800 angstroms, and 1500 angstroms.

[0095] It should be understood that the above-mentioned structural film layer can also be made of other materials and thicknesses. For example, the materials of the dielectric layer and the passivation layer can also be materials such as silicon nitride or transparent organic resin, and the material of the planar layer can also be transparent polyimide (CPI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), etc. The material of the conductive layer can also be metal materials such as copper and molybdenum.

[0096] An exemplary embodiment of the present disclosure further provides an array substrate manufacturing method, the array substrate may include a pixel driving circuit, the pixel driving circuit may include a P-type driving transistor, an N-type first transistor, and a capacitor, the first electrode of the first transistor is connected to the gate of the driving transistor, and the first electrode of the capacitor is connected to the gate of the driving transistor. The array substrate manufacturing method includes:

[0097] Step S1: forming a substrate;

[0098] Step S2: forming a first conductive layer on one side of the base substrate, wherein the first conductive layer includes a first conductive portion, and the first conductive portion is configured as a gate of the driving transistor and a first electrode of the capacitor;

[0099] Step S3: forming a first dielectric layer on a side of the first conductive layer away from the substrate;

[0100] A first buffer layer is formed on a side of the first dielectric layer away from the base substrate, wherein a groove is provided on the first buffer layer, and an orthographic projection of the groove on the base substrate at least partially overlaps with an orthographic projection of the first conductive portion on the base substrate;

[0101] Step S4: forming a second conductive layer on a side of the first buffer layer away from the first conductive layer, wherein the second conductive layer comprises:

[0102] a second conductive portion, the second conductive portion being configured as a gate of the first transistor;

[0103] A third conductive portion is located at the bottom of the slot, and an orthographic projection of the third conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first conductive portion on the base substrate to form a second electrode of the capacitor.

[0104] like Figure 8, which is a process flow chart of an exemplary embodiment of the array substrate manufacturing method disclosed in the present invention. The array substrate manufacturing method may also include: sequentially forming on the base substrate 1: a barrier layer 48, a second buffer layer 44, a first active layer, a second gate insulating layer 45, a first conductive layer, a first dielectric layer 43, a first buffer material layer 041, a second active layer, and a first gate insulating material layer 018. Among them, the first active layer may include a first active portion 53, the first conductive layer may include a first conductive portion 13 configured as a gate of a driving transistor, and the second active layer may include a second active portion 62.

[0105] like Fig. 9 , 10 As shown in FIG. 1 , it is a process flow chart of an exemplary embodiment of the array substrate manufacturing method disclosed in the present invention. Fig. 9 As shown, the array substrate manufacturing method may further include etching the first buffer material layer 041 and the first gate insulating material layer 018 through a patterning process to form the groove 411, and the etched first buffer material layer 041 forms a first buffer layer. The groove 411 may extend to the first surface of the first dielectric layer 43, and the third conductive portion may be located on the first surface of the first dielectric layer, and the first surface is the surface of the first dielectric layer facing the first buffer layer. Fig.10 As shown, the array substrate manufacturing method may further include forming a second conductive layer by a patterning process, and the second conductive layer may include a second conductive portion 55 configured as a first transistor gate and a third conductive portion 721, and the third conductive portion 721 may be located at the bottom of the groove 411. Wherein, when the second conductive layer is formed by the patterning process, the first gate insulating material layer 018 may also be patterned to form the first gate insulating layer 18. It should be understood that in other exemplary embodiments, the array substrate manufacturing method may also be etched by the patterning process only on any one of the first buffer material layer 041 and the first gate insulating material layer 018 to form the groove 411.

[0106] like Fig.11 , 12 , 13, and 14 are process flow charts of an exemplary embodiment of the array substrate manufacturing method disclosed in the present invention. Fig.11 As shown, the array substrate manufacturing method may further include: forming a second via hole 82 on the third conductive portion, wherein the second via hole 82 may penetrate the first dielectric layer 43 and extend to the surface of the first conductive portion 13. Fig.12 As shown, a second dielectric layer 42 is formed on the side of the second conductive layer away from the base substrate 1, and the second dielectric layer 42 fills the second via hole 82. Fig.13As shown, the first via hole 81 is formed on the second dielectric layer 42, and the first via hole 81 passes through the third conductive portion 721 and extends to the surface of the first conductive portion 13; and the orthographic projection of the first via hole 81 on the base substrate 1 is located within the orthographic projection of the second via hole 82 on the base substrate. Fig.14 As shown, the array substrate manufacturing method may further include: forming a third conductive layer on the side of the second dielectric layer 42 away from the base substrate 1, the third conductive layer may include a fourth conductive portion 24, and the fourth conductive portion 24 may be electrically connected to the first conductive portion 13 through a first via 81. The orthographic projection of the fourth conductive portion 24 on the base substrate 1 may be located on the orthographic projection of the first conductive portion 13 on the base substrate 1, and the orthographic projection area of ​​the fourth conductive portion 24 on the base substrate may be smaller than the orthographic projection area of ​​the first conductive portion 13 on the base substrate.

[0107] In this exemplary embodiment, the fourth conductive portion 24 is set to a smaller area. On the one hand, this setting reduces the parasitic capacitance between the fourth conductive portion 24 and other conductive structures (such as data lines, anode layers, etc.), thereby reducing the noise impact of other conductive structures on the gate of the driving transistor; on the other hand, this setting facilitates shielding the fourth conductive portion 24 through a shielding layer to further reduce the noise impact of other conductive structures on the gate of the driving transistor. Among them, the positive projection area of ​​the fourth conductive portion 24 on the substrate 1 can be 4%-25% of the positive projection area of ​​the first conductive portion 13 on the substrate. For example, the ratio of the positive projection area of ​​the fourth conductive portion 24 on the substrate 1 to the positive projection area of ​​the first conductive portion 13 on the substrate can be any one of 4%, 8%, 10%, 12%, 15%, 20%, and 25%.

[0108] In this exemplary embodiment, the ratio of the orthographic projection area of ​​the fourth conductive portion 24 on the substrate 1 to the orthographic projection area of ​​the first via 81 on the substrate may be 1-2.5. For example, the ratio of the orthographic projection area of ​​the fourth conductive portion 24 on the substrate 1 to the orthographic projection area of ​​the first via 81 on the substrate may be 1, 1.2, 1.3, 1.5, 2.0, 2.3, 2.5, etc.

[0109] In this exemplary embodiment, the array substrate manufacturing method may further include: forming a second dielectric layer, a third conductive layer, a passivation layer, a first flat layer, a fourth conductive layer, a second flat layer, an anode layer, and a pixel definition layer in sequence on the side of the third conductive layer away from the base substrate to form Figure 7 The array substrate structure shown.

[0110] The overall structure of the array substrate is described in detail below in this exemplary embodiment.

[0111] like Figure 15-26 As shown, Fig.15 is the structural layout of the first active layer; Fig.16 is a structural layout of a first conductive layer; Fig.17 is the structural layout of the second active layer; Fig.18 A combination layout of a first active layer, a first conductive layer, and a second active layer; Fig.19 is a structural layout of a second conductive layer; Fig. 20 A combination layout of a first active layer, a first conductive layer, a second active layer, and a second conductive layer; Fig.21 is a structural layout of the third conductive layer; Fig. 22 A combination layout of a first active layer, a first conductive layer, a second active layer, a second conductive layer, and a third conductive layer; Fig.23 is a structural layout of a fourth conductive layer; Fig.24 A combination layout of a first active layer, a first conductive layer, a second active layer, a second conductive layer, a third conductive layer, and a fourth conductive layer; Fig.25 is the structural layout of the anode layer; Fig.26 It is a combination layout of a first active layer, a first conductive layer, a second active layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and an anode layer.

[0112] like Fig.15 , 18 As shown, the first active layer may include the above-mentioned first active portion 53. In addition, the first active layer may further include: a third active portion 51 and a fourth active portion 52 extending along the first direction Y1, and the third active portion 51 and the fourth active portion 52 may be spaced apart along the second direction X. The first active portion 53 may be connected between the third active portion 51 and the fourth active portion 52. The third active portion 51 may include a first sub-active portion 511 and a second sub-active portion 514, and the fourth active portion 52 may include a third sub-active portion 525 and a fourth sub-active portion 526. The first active portion 53 may be configured as a channel region of the driving transistor DT; the first sub-active portion 511 may be configured as a channel region of the second transistor T2; the second sub-active portion 514 may be configured as a channel region of the fourth transistor T4; the third sub-active portion 525 may be configured as a channel region of the fifth transistor T5; and the fourth sub-active portion 526 may be configured as a channel region of the sixth transistor T6. In this exemplary embodiment, the first active layer may be a polysilicon material, and accordingly, the driving transistor DT, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be P-type low temperature polysilicon transistors. The orthographic projection of the third conductive portion 721 on the substrate substrate may not overlap with the orthographic projection of the fourth active portion 52 on the substrate substrate, thereby avoiding unnecessary parasitic capacitance between the third conductive portion 721 and the fourth active portion 52.

[0113] like Fig.18 , 16 As shown, the first conductive layer may include the above-mentioned first conductive part 13. In addition, the first conductive layer may also include a first gate line 11, a second gate line 12, a third gate line 14, a fifth gate line 15, and a sixth gate line 16. The first gate line 11 may be located on one side of the first conductive part 13; the second gate line 12 may be located on the side of the first gate line 11 away from the first conductive part 13; the third gate line 14 may be located on the side of the second gate line 12 away from the first conductive part 13; the fifth gate line 15 is located on the side of the first conductive part 13 away from the first gate line; and the sixth gate line 16 is located on the side of the fifth gate line 15 away from the first conductive part 13. The first gate line 11, the second gate line 12, the third gate line 14, the fifth gate line 15, and the sixth gate line 16 may all extend along the second direction X. The first gate line 11 may be used to provide Figure 1 The first gate driving signal terminal G1 in the embodiment of the present invention, the first gate line 11 may include a first gate portion 113; the second gate line 12 may be used to provide Figure 1 The second gate driving signal terminal G2 in the second gate line 12 may include a second gate portion 125; the third gate line 14 may be used as a second reset signal line for providing Figure 1 The third gate line 14 may include a third gate portion 143; the fifth gate line 15 may be used as an enable signal line for providing Figure 1 The enable signal terminal EM in the fifth gate line 15 may include a fourth gate portion 154 and a fifth gate portion 155; the sixth gate line 16 may be used as a first reset signal line for providing Figure 1 The first reset signal terminal Re1 in the sixth gate line 16 includes a sixth gate portion 166. Among them, the first gate portion 113 can be configured as the gate of the second transistor T2, the second gate portion 125 can be configured as the first gate of the first transistor T1; the third gate portion 143 can be configured as the first gate of the third transistor T3; the fourth gate portion 154 can be configured as the gate of the fourth transistor T4; the fifth gate portion 155 can be configured as the gate of the fifth transistor T5; and the sixth gate portion 166 can be configured as the gate of the sixth transistor T6.

[0114] like Fig.18 , 17 As shown, the second active layer may include a plurality of active portions 6 extending along the first direction Y1, the plurality of active portions 6 may be spaced apart along the second direction X, and the plurality of active portions 6 are disposed one-to-one with the plurality of pixel driving circuits. Fig.10 As shown, the active portion 6 may include the second active portion 62 and the fifth active portion 63 described above, wherein the second active portion 62 may form a channel region of the first transistor T1 , and the fifth active portion 63 may form a channel region of the third transistor T3 .

[0115] like Fig.19 , 20 As shown, the second conductive layer may include the above-mentioned second conductive portion 55, the third conductive portion 721, and the sixth conductive portion 722. The second conductive layer may also include: a fourth gate line 74, a fifth gate line 75, and a sixth gate line 76. The fourth gate line 74, the fifth gate line 75, and the sixth gate line 76 may all extend along the second direction X. The fourth gate line 74 may be connected to the second gate line 12 through a via in the routing area around the display area; the fifth gate line 75 may be connected to the third gate line 14 through a via in the routing area around the display area. The fourth gate line 74 may include the above-mentioned second conductive portion 55, and the second conductive portion 55 may be configured as the second gate end of the first transistor. The fifth gate line 75 may include a seventh gate portion 753, and the seventh gate portion 753 may form the second gate of the third transistor. The sixth gate line 76 may be used as an initial signal line for providing Figure 1 The initial signal terminal Vinit in the substrate. The orthographic projection of the third conductive part 721 on the substrate can cover the orthographic projection of the first conductive part 13 on the substrate. Among them, the sixth conductive part 722 can be connected to the power line in the third conductive layer through a via.

[0116] like Fig.21 , 22 As shown, the third conductive layer may include the above-mentioned power line 26 and the fourth conductive part 24. In addition, the third conductive layer may also include: a first conductive line 21, a seventh conductive part 23, a first connecting part 27, a second connecting part 28, a third connecting part 29, and a fourth connecting part 201. The first connecting part 27 may be connected to the fourth active part 52 through a via 202 to connect the second pole of the sixth transistor. The first connecting part 27 is also connected to the sixth gate line 76 through a via 203, so that the initial signal end can be provided to the second pole of the sixth transistor through the sixth gate line 76. In addition, the first connecting part 27 may also be connected to the active part 6 in the next row of pixel driving circuits through a via 204 to provide the initial signal end to the third transistor in the next row of pixel driving circuits through the sixth gate line 76. The second connecting part 28 may be connected to the fourth active part 52 through a via 205 to connect the second pole of the fifth transistor. The third connection portion 29 is connected to the active portion 6 through the via 206 to connect the second electrode of the first transistor. The third connection portion 29 can be connected to the fourth active portion 52 through the via 207 to connect the second electrode of the driving transistor, so that the second electrode of the first transistor is connected to the second electrode of the driving transistor. The fourth connection portion 201 can be connected to the third active portion 51 through the via 208 to connect the first electrode of the second transistor.

[0117] like Fig.23 , 24As shown, the fourth conductive layer may include the fifth conductive portion 35 described above. In addition, the fourth conductive layer may also include a data line 31 and a fifth connecting portion 32. The data line 31 may be connected to the fourth connecting portion 201 through a via 33 to connect to the first electrode of the second transistor T2. The fifth conductive portion 35 may be connected to the power line 26 through a via 34. The fifth connecting portion 32 may be connected to the second connecting portion 28 through a via 36 to connect to the second electrode of the fifth transistor. Fig.24 As shown, the following can be cut along the dotted line A in the figure: Figure 5 It should be noted that: Figure 5 Some structures are omitted.

[0118] like Fig.25 , 26 As shown, the anode layer may include a first anode portion 87, a second anode portion 88, and a third anode portion 83. The first anode portion 87 may be connected to the fifth connection portion 32 through a via hole 84 to be connected to the second electrode of the fifth transistor; the second anode portion 88 may be connected to the fifth connection portion 32 in another pixel driving circuit through a via hole 85; and the third anode portion 83 may be connected to the fifth connection portion 32 in another pixel driving circuit through a via hole 86. A G light emitting unit may be formed on the first anode portion 87; an R light emitting unit may be formed on the second anode portion 88; and a B light emitting unit may be formed on the third anode portion 83.

[0119] like Fig. 27 As shown, Figure 1A timing diagram of each node in a driving method of a pixel driving circuit. Among them, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, R represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, N represents the timing of the node N, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3. In the reset stage t1: the first reset signal terminal Re1 outputs a low-level signal, the second reset signal terminal Re2 outputs a high-level signal, the third transistor T3 and the sixth transistor T6 are turned on, and the initial signal terminal Vinit inputs an initialization signal to the node N and the second electrode of the fifth transistor T5. In the compensation stage t2: the first gate drive signal terminal G1 outputs a low-level signal, the second gate drive signal terminal G2 outputs a high-level signal, the second transistor T2 and the first transistor T1 are turned on, and at the same time the data signal terminal Da outputs a drive signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the drive signal and Vth is the threshold voltage of the drive transistor DT. Light-emitting stage t3: the enable signal terminal EM outputs a low-level signal, the fourth transistor T4 and the fifth transistor T5 are turned on, and the drive transistor DT emits light under the action of the voltage Vdata+Vth stored in the capacitor C. According to the output current formula of the drive transistor I=(μWCox / 2L)(Vgs-Vth) 2 , where μ is carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current of the driving transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0120] However, due to the parasitic capacitance between the gate and the first electrode of the first transistor T1, Figure 2As shown, after the compensation stage t2 ends, the second gate drive signal terminal G2 is reduced from a high level to a low level, that is, the gate of the first transistor T1 is reduced from a high level to a low level, and the voltage of the first electrode of the first transistor T1 will be reduced under the capacitive coupling effect, and the voltage of the node N connected to the first electrode of the first transistor T1 will also be reduced accordingly. According to the above-mentioned driving transistor output current formula, it can be known that the voltage drop of node N (that is, the gate of the driving transistor) will affect the output current of the driving transistor. In order to ensure that the driving transistor outputs the required driving current normally, the source driving circuit needs to provide a data signal with a higher voltage value to the data signal terminal through the data line. Through simulation, when the above-mentioned pixel driving circuit displays grayscale 0, the voltage provided by the source driving circuit to the data line needs to be greater than 6.3V, but the maximum voltage provided by the existing source driving circuit to the data line is 6V, which cannot meet the normal display requirements.

[0121] In this exemplary embodiment, Fig.16 As shown, the array substrate provided by this exemplary embodiment arranges the second gate line 12 on the side of the first gate line 11 away from the first conductive portion 13. On the one hand, this arrangement increases the distance between the second gate line 12 and the first conductive portion 13, reduces the lateral capacitance between the second gate line 12 and the first conductive portion 13, and thus reduces the pull-down effect of the first transistor gate on the driving transistor gate after the compensation stage ends; on the other hand, the first gate line 11 and the first conductive portion 13 can form a lateral capacitance, such as Figure 2 As shown, after the compensation stage t2 ends, the second transistor jumps from a low level to a high level, so that the gate of the second transistor can produce a pull-up effect on the gate of the driving transistor. The array substrate provided by this exemplary embodiment reduces the distance between the first gate line 11 and the first conductive portion 13, increases the lateral capacitance between the first gate line 11 and the first conductive portion 13, and thus can enhance the pull-up effect of the gate of the second transistor on the gate of the driving transistor; on the other hand, the first gate line 11 is located between the first conductive portion 13 and the second gate line 12, and the first gate line 11 can play a certain shielding role on the second gate line 12, thereby further reducing the pull-down effect of the gate of the first transistor on the gate of the driving transistor. In this exemplary embodiment, the pull-up effect of the first gate line 11 on the first conductive portion 13 is stronger than the pull-down effect of the second gate line 12 on the first conductive portion 13, so that the array substrate can offset the pull-down effect of the first transistor on the gate of the driving transistor to a certain extent.

[0122] like Fig.28 As shown, Fig. 9The local layout structure of the first conductive layer in the first gate line 11. The first gate line 11 may be located on one side of the first conductive part 13 in the first direction Y1, and extend along the second direction X, the first direction Y1 may intersect with the second direction X, for example, the first direction Y1 and the second direction X may be perpendicular. The first gate line 11 may include: a first extension part 111 and a second extension part 112, the orthographic projection of the first extension part 111 on the base substrate is opposite to the orthographic projection of at least part of the first conductive part 13 on the base substrate in the first direction Y1; the orthographic projection of the second extension part 112 on the base substrate is staggered with the orthographic projection of the first conductive part 13 on the base substrate in the first direction Y1. Both the first direction and the second direction may be directions parallel to the plane where the base substrate is located. Among them, "the orthographic projection of the first extension portion 111 on the substrate is opposite to the orthographic projection of at least part of the first conductive portion 13 on the substrate in the first direction Y1" can be understood as that the area covered by the orthographic projection of the first extension portion 111 on the substrate in the first direction Y1 and the third direction Y2 is infinitely moved and the area covered by the orthographic projection of at least part of the first conductive portion 13 on the substrate in the first direction Y1 and the third direction Y2 is completely overlapped, wherein the first direction Y1 and the third direction Y2 are opposite. "the orthographic projection of the second extension portion 112 on the substrate is staggered with the orthographic projection of the first conductive portion 13 on the substrate in the first direction Y1" can be understood as that the area covered by the orthographic projection of the second extension portion 112 on the substrate in the first direction Y1 and the third direction Y2 is infinitely moved and the area covered by the orthographic projection of the first conductive portion 13 on the substrate in the first direction Y1 and the third direction Y2 is not intersected, and similarly, the first direction Y1 and the third direction Y2 are opposite.

[0123] In this exemplary embodiment, the distance S1 between the orthographic projection of the first extension portion 111 on the substrate and the orthographic projection of the first conductive portion 13 on the substrate in the third direction Y2 may be smaller than the distance S2 between the orthographic projection of the second extension portion 112 on the substrate and the orthographic projection of the first conductive portion 13 on the substrate in the third direction Y2. Fig.28As shown, the distance S1 between the orthographic projection of the first extension portion 111 on the substrate and the orthographic projection of the first conductive portion 13 on the substrate in the third direction Y2 may refer to the distance between the edge of the orthographic projection of the first extension portion 111 on the substrate facing the first conductive portion 13 and the edge of the orthographic projection of the first conductive portion 13 on the substrate facing the first extension portion 111 in the third direction Y2. The distance S2 between the orthographic projection of the second extension portion 112 on the substrate and the orthographic projection of the first conductive portion 13 on the substrate in the third direction Y2 may refer to the distance between the edge of the orthographic projection of the second extension portion 112 on the substrate facing the first conductive portion 13 and the straight line where the edge of the orthographic projection of the first conductive portion 13 on the substrate facing the second extension portion 112 is located in the third direction Y2. This arrangement reduces the distance between the first extension portion 111 and the first conductive portion 13 in the third direction, increases the lateral capacitance between the first extension portion 111 and the first conductive portion 13, and thus can further increase the pull-up effect of the first gate line on the gate of the driving transistor.

[0124] In this exemplary embodiment, Fig.28 As shown, the size of the orthogonal projection of the first extension portion 111 on the substrate in the second direction X can be equal to the size of the orthogonal projection of the first conductive portion 13 on the substrate in the second direction X. This arrangement can greatly increase the capacitance value of the lateral capacitor formed by the first extension portion 111 and the first conductive portion 13, so as to further increase the pull-up effect of the first gate line on the gate of the driving transistor.

[0125] In this exemplary embodiment, at least part of the second extension portion 112 can be configured as the gate of the second transistor. Since the orthographic projection of the second extension portion 112 on the substrate is far away from the orthographic projection of the first conductive portion 13 on the substrate in the third direction Y2, this design can fully reserve space for arranging the second transistor.

[0126] In this exemplary embodiment, Fig.29 , 30 As shown, Fig.29 for Fig.21 Part of the layout structure of the third conductive layer, Fig.30 for Fig. 22The third conductive layer may include: the fourth conductive part 24, the seventh conductive part 23, and the first conductive line 21, wherein the fourth conductive part 24 is electrically connected to the first conductive part 13 through the first via 81; the seventh conductive part 23 may be configured as the first electrode of the first transistor, and the orthographic projection of the first gate line 11 on the substrate may be located between the orthographic projection of the fourth conductive part 24 on the substrate and the orthographic projection of the seventh conductive part 23 on the substrate; the first conductive line 21 is connected between the fourth conductive part 24 and the seventh conductive part 23, so that the first electrode of the first transistor is connected to the gate of the driving transistor, and the first conductive line 21 may extend along the first direction Y1, and the orthographic projection of the first conductive line 21 on the substrate intersects with the orthographic projection of the first gate line 11 on the substrate. Since the orthographic projection of the first conductive line 21 on the substrate intersects with the orthographic projection of the first gate line 11 on the substrate, part of the first conductive line 21 may form a parallel plate capacitor structure with part of the first gate line 11. By utilizing the coupling effect of the parallel plate capacitor structure, the first gate line 11 can pull up the first conductive line 21 after the compensation stage of the pixel driving circuit ends. Since the first conductive line 21 is electrically connected to the first conductive portion 13, this arrangement can further enhance the pull-up effect of the first gate line 11 on the first conductive portion 13.

[0127] In this exemplary embodiment, Fig.28 , 29As shown in , 30, the orthographic projection of the second gate line 12 on the substrate substrate may be located between the orthographic projection of the first gate line 11 on the substrate substrate and the orthographic projection of the seventh conductive portion 23 on the substrate substrate; the second gate line 12 may include a third extension portion 123 and a fourth extension portion 124 which are alternately connected in sequence along the second direction X, wherein the size of the orthographic projection of the third extension portion 123 on the substrate substrate in the first direction Y1 may be smaller than the size of the orthographic projection of the fourth extension portion 124 on the substrate substrate in the first direction Y1. The orthographic projection of the first conductive line 21 on the substrate substrate may intersect with the orthographic projection of the third extension portion 123 on the substrate substrate. Part of the third extension portion 123 may form a parallel plate capacitor structure with part of the first conductive line 21. Based on the coupling effect of the parallel plate capacitor structure, the third extension portion 123 may produce a pull-down effect on the first conductive line 21 after the compensation stage of the pixel driving circuit ends. Since the first conductive line 21 is electrically connected to the first conductive portion 13, the third extension portion 123 will produce a pull-down effect on the first conductive portion 13. In this exemplary embodiment, the size of the orthographic projection of the third extension portion 123 on the substrate in the first direction Y1 is smaller than the size of the orthographic projection of the fourth extension portion 124 on the substrate in the first direction Y1, that is, this exemplary embodiment reduces the size of the third extension portion 123 in the first direction Y1, thereby reducing the electrode area of ​​the parallel plate capacitor structure formed by the third extension portion 123 and the first conductive line 21. According to the capacitance calculation of the parallel plate capacitor, it is known that the capacitance of the parallel plate capacitor structure is proportional to its electrode area, that is, this setting reduces the capacitance of the parallel plate capacitor structure formed by the third extension portion 123 and the first conductive line 21, thereby reducing the pull-down effect of the third extension portion 123 on the first conductive portion 13. Among them, part of the fourth extension portion 124 can be configured as the first gate of the first transistor. The channel region of the first transistor can extend along the first direction Y1, so that the channel region of the first transistor can have a larger length to reduce the leakage current of the first transistor.

[0128] In this exemplary embodiment, Fig.30 As shown, the orthographic projection of the power line 26 on the substrate can intersect with the orthographic projection of the third extension portion 123 on the substrate. This setting can reduce the overlapping area between the power line 26 and the second gate line, thereby reducing the capacitive coupling effect caused by the power line 26 on the second gate line 12 when the voltage fluctuates.

[0129] like Fig.30 , 31 As shown, Fig.31 for Fig.24The power line 26 may include a fifth extension 265, the orthographic projection of the fifth extension 265 on the substrate substrate is opposite to the orthographic projection of at least part of the first conductive part 13 on the substrate substrate in the second direction X, and "the orthographic projection of the fifth extension 265 on the substrate substrate is opposite to the orthographic projection of at least part of the first conductive part 13 on the substrate substrate in the second direction X" can be understood as that the area covered by the orthographic projection of the fifth extension 265 on the substrate substrate in the second direction and the opposite direction to the second direction is infinitely moved and the area covered by the orthographic projection of at least part of the first conductive part 13 on the substrate substrate in the second direction and the opposite direction to the second direction completely overlaps. And the orthographic projection of part of the data line 31 on the substrate substrate can be located on the orthographic projection of the fifth extension 265 on the substrate substrate. Since the fifth extension portion 265 is stacked between the data line 31 and the first conductive portion 13, and the fifth extension portion 265 receives a stable voltage, the fifth extension portion 265 can be used as a shielding layer to reduce the coupling capacitance between the data line 31 and the first conductive portion 13, thereby reducing the coupling effect of the data line 31 on the first conductive portion 13. The fifth conductive portion 35 can be connected to the power line 26 through the via 34.

[0130] In this exemplary embodiment, when the width-to-length ratio of the driving transistor channel region in the R pixel unit, the G pixel unit, and the B pixel unit is the same, the R pixel unit, the G pixel unit, and the B pixel unit have different driving voltage intervals (i.e., the difference between the data signal voltage at the maximum brightness and the data signal voltage at the minimum brightness). The source driving circuit needs to provide data signals of different driving voltage intervals to the R pixel unit, the G pixel unit, and the B pixel unit, and the source driving circuit needs to switch between different driving voltage intervals, so the source driving circuit needs to consume a large amount of power. In this exemplary embodiment, the width-to-length ratio of the driving transistor channel region in the R pixel driving circuit, the width-to-length ratio of the driving transistor channel region in the G pixel driving circuit, and the width-to-length ratio of the driving transistor channel region in the G pixel driving circuit may not be all the same. That is, in the R pixel driving circuit, the G pixel driving circuit, and the B pixel driving circuit, the width-to-length ratio of the driving transistor channel region in at least one pixel driving circuit is not equal to the width-to-length ratio of the driving transistor channel region in other pixel driving circuits. For example, the width-to-length ratio of the driving transistor channel region in the R pixel driving circuit may be 3.5 / 40, and the width-to-length ratio of the driving transistor channel region in the B pixel driving circuit may be 3.5 / 25. Fig.15As shown, the driving transistor channel region in the B pixel unit is "Z" type, and the driving transistor channel region in the R pixel unit and the driving transistor channel region in the G pixel unit are "S" type. According to the simulation, it can be concluded that compared with the channel region of the driving transistor in the R pixel driving circuit, the channel region of the driving transistor in the G pixel driving circuit, and the channel region of the driving transistor in the R pixel driving circuit having the same width-to-length ratio, this setting can reduce the difference in driving voltage between the R pixel unit, the G pixel unit, and the B pixel unit, thereby reducing the power consumption of the source driving circuit.

[0131] This exemplary embodiment also provides a display device, wherein the display device may include the above array substrate. The display device may be a display device such as a mobile phone, a tablet computer, or a television.

[0132] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the generality of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered merely exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0133] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. An array substrate, the array substrate comprising a pixel driving circuit, the pixel driving circuit comprising a P-type driving transistor, an N-type first transistor, and a capacitor, the first electrode of the first transistor is connected to the gate of the driving transistor, the first electrode of the capacitor is connected to the gate of the driving transistor, wherein: The array substrate further includes: substrate substrate; A first conductive layer, stacked on one side of the base substrate, the first conductive layer includes a first conductive portion, and the first conductive portion is configured as a gate of the driving transistor and a first electrode of the capacitor; A first dielectric layer is stacked on a side of the first conductive layer facing away from the substrate; A first buffer layer, stacked on a side of the first dielectric layer away from the base substrate, the first buffer layer is provided with a groove, and the orthographic projection of the groove on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate; A second conductive layer is stacked on a side of the first buffer layer away from the base substrate, and the second conductive layer includes: a second conductive portion, the second conductive portion being configured as a gate of the first transistor; A third conductive portion, wherein the third conductive portion is at least partially located at the bottom of the groove, and an orthographic projection of the third conductive portion on the substrate at least partially overlaps with an orthographic projection of the first conductive portion on the substrate to form a second electrode of the capacitor.

2. The array substrate according to claim 1, wherein: The groove extends to the surface of the first dielectric layer, and the third conductive portion is located on a side of the first dielectric layer away from the substrate.

3. The array substrate according to claim 1, wherein: The array substrate further includes: A third conductive layer, the third conductive layer is stacked and arranged on a side of the second conductive layer away from the base substrate, and comprises a fourth conductive portion, the fourth conductive portion is electrically connected to the first conductive portion through a first via hole penetrating the third conductive portion; The orthographic projection of the fourth conductive part on the base substrate is located on the orthographic projection of the first conductive part on the base substrate, and the orthographic projection area of ​​the fourth conductive part on the base substrate is smaller than the orthographic projection area of ​​the first conductive part on the base substrate.

4. The array substrate according to claim 3, wherein: A ratio of an orthographic projection area of ​​the fourth conductive portion on the base substrate to an orthographic projection area of ​​the first via hole on the base substrate is 1-1.

5.

5. The array substrate according to claim 3, wherein: The ratio of the orthographic projection area of ​​the fourth conductive part on the base substrate to the orthographic projection area of ​​the first conductive part on the base substrate is 8%-15%.

6. The array substrate according to claim 3, wherein: A second via hole is formed on the third conductive portion, and the second via hole penetrates the first dielectric layer and extends to the surface of the first conductive portion. The array substrate further includes: A second dielectric layer is stacked between the second conductive layer and the third conductive layer and fills the second via hole. The first via hole is formed on the second dielectric layer. The first via hole penetrates the third conductive part and extends to the surface of the first conductive part. The orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the second via hole on the base substrate.

7. The array substrate according to claim 3, wherein: The third conductive layer further includes a power line for providing a power supply voltage, and the array substrate further includes: The fourth conductive layer is stacked on the side of the third conductive layer away from the base substrate, and the fourth conductive layer includes a fifth conductive part connected to the power line, and the orthographic projection of the fifth conductive part on the base substrate covers the orthographic projection of the first conductive part on the base substrate.

8. The array substrate according to claim 7, wherein: The second conductive layer further includes a sixth conductive portion connected to the third conductive portion, and the sixth conductive portion is connected to the power line through a via hole.

9. The array substrate according to claim 3, wherein: The array substrate further includes: A barrier layer, stacked on one side of the substrate; A second buffer layer is stacked and arranged on a side of the barrier layer away from the substrate; A first active layer, stacked on a side of the second buffer layer away from the base substrate, the first active layer comprising a first active portion, and the first active portion is configured as a channel region of the driving transistor; A second gate insulating layer is stacked on a side of the first active layer away from the base substrate, wherein the first conductive layer is stacked on a side of the second gate insulating layer away from the base substrate; A second active layer, stacked on a side of the first buffer layer away from the base substrate, comprising a second active portion, wherein the second active portion is configured as a channel region of the first transistor; A first gate insulating layer is stacked on a side of the second active layer away from the base substrate, wherein a second conductive layer is stacked on a side of the first gate insulating layer away from the base substrate; A second dielectric layer is stacked on a side of the second conductive layer away from the substrate, wherein a third conductive layer is stacked on a side of the second dielectric layer away from the substrate; The passivation layer is stacked on a side of the third conductive layer away from the substrate.

10. The array substrate according to claim 9, wherein: The array substrate comprises a non-display area, a strip groove is formed on the array substrate and is located in the non-display area, and the strip groove penetrates the passivation layer, the second dielectric layer, the first buffer layer, the first dielectric layer, the second gate insulating layer, the second buffer layer, and the barrier layer and extends to the surface of the base substrate; The array substrate further includes: A first planarization layer is stacked on a side of the passivation layer away from the substrate and fills the strip groove; The bendability of the material of the first planar layer is stronger than the bendability of the materials of the passivation layer, the second dielectric layer, the first buffer layer, the first dielectric layer, the second buffer layer, and the barrier layer.

11. The array substrate according to claim 1, wherein: The thickness of the first dielectric layer in the stacking direction is 1200-1400 angstroms.

12. The array substrate according to claim 1, wherein: The array substrate further includes: an enable signal line, an initial signal line, an anode layer, a first reset signal line, a second reset signal line, a power line, a first gate line, a second gate line, and a data line. The second electrode of the first transistor is connected to the second electrode of the driving transistor, and the gate is connected to the second gate line. The pixel driving circuit further includes: a second transistor, a first electrode of which is connected to the data line, a second electrode of which is connected to the first electrode of the driving transistor, and a gate of which is connected to the first gate line; a third transistor, a first electrode of which is connected to the gate of the driving transistor, a second electrode of which is connected to the initial signal line, and a gate of which is connected to the second reset signal line; a fourth transistor, a first electrode connected to the power line, a second electrode connected to the first electrode of the driving transistor, and a gate connected to the enable signal line; a fifth transistor, wherein a first electrode is connected to the second electrode of the driving transistor, a second electrode is connected to the anode layer, and a gate is connected to the enable signal line; A sixth transistor has a first electrode connected to the second electrode of the fifth transistor, a second electrode connected to the initial signal line, and a gate connected to the first reset signal line.

13. The array substrate according to claim 12, wherein: The driving transistor, the second transistor, the fourth transistor, the fifth transistor and the sixth transistor are P-type low temperature polysilicon transistors.

14. The array substrate according to claim 12, wherein: The first transistor and the third transistor are N-type metal oxide transistors.

15. A method for manufacturing an array substrate, wherein: The array substrate includes a pixel driving circuit, the pixel driving circuit includes a P-type driving transistor, an N-type first transistor, and a capacitor, the first electrode of the first transistor is connected to the gate of the driving transistor, and the first electrode of the capacitor is connected to the gate of the driving transistor. The array substrate manufacturing method includes: forming a substrate base; forming a first conductive layer on one side of the base substrate, wherein the first conductive layer includes a first conductive portion, and the first conductive portion is configured as a gate of the driving transistor and a first electrode of the capacitor; forming a first dielectric layer on a side of the first conductive layer facing away from the substrate; A first buffer layer is formed on a side of the first dielectric layer away from the base substrate, wherein a groove is provided on the first buffer layer, and an orthographic projection of the groove on the base substrate at least partially overlaps with an orthographic projection of the first conductive portion on the base substrate; A second conductive layer is formed on a side of the first buffer layer away from the first conductive layer, wherein the second conductive layer comprises: a second conductive portion, the second conductive portion being configured as a gate of the first transistor; A third conductive portion is located at the bottom of the slot, and an orthographic projection of the third conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first conductive portion on the base substrate to form a second electrode of the capacitor.

16. The method for manufacturing an array substrate according to claim 15, wherein: A first buffer layer is formed on a side of the first dielectric layer facing away from the first conductive layer, comprising: forming a first buffer material layer on a side of the first dielectric layer away from the substrate; forming a first gate insulating material layer on a side of the first buffer material layer away from the base substrate; The first buffer material layer and the first gate insulating material layer are etched to form the groove.

17. The array substrate manufacturing method according to claim 14, wherein the base substrate manufacturing method further comprises: forming a third conductive layer on a side of the second conductive layer away from the base substrate, wherein the third conductive layer comprises a fourth conductive portion, and the fourth conductive portion is electrically connected to the first conductive portion through a via hole penetrating the third conductive portion; The orthographic projection of the fourth conductive part on the base substrate is located on the orthographic projection of the first conductive part on the base substrate, and the orthographic projection area of ​​the fourth conductive part on the base substrate is smaller than the orthographic projection area of ​​the first conductive part on the base substrate.

18. The method for manufacturing an array substrate according to claim 17, wherein: Before forming a third conductive layer on a side of the second conductive layer away from the substrate, the method further includes: forming a second via hole on the third conductive portion, wherein the second via hole penetrates the first dielectric layer and extends to a surface of the first conductive portion; forming a second dielectric layer on a side of the second conductive layer facing away from the substrate, wherein the second dielectric layer fills the second via hole; forming a first via hole on the second dielectric layer, wherein the first via hole penetrates the third conductive portion and extends to the surface of the first conductive portion, and an orthographic projection of the first via hole on the base substrate is located within an orthographic projection of the second via hole on the base substrate; Wherein, the fourth conductive part fills the first via hole.

19. A display device, wherein: Comprising the array substrate according to any one of claims 1 to 14.

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