Large-grain copper interconnects for MRAM

Abstract

Large-grain metal bitlines are formed above the magnetic tunnel barrier pillars that serve as MRAM bits without materially affecting the magnetic properties of the magnetic tunnel barrier. Copper or copper alloy bitlines with relatively small grains are formed on the pillars. Laser annealing is used to melt the bitlines. Subsequent cooling and recrystallization results in a reduction in the number of grain boundaries in the bitline and a reduction in the effective resistivity of the bitline. Multiple melting / cooling cycles can be used. The bitline grains are vertically aligned with the pillars in the resulting structure.

Description

Background Art

[0001] The present invention relates generally to the electrical, electronic and computer fields, and more particularly to copper interconnects for magnetic tunnel barrier (MTJ) memory device arrays.

[0002] Magnetic tunnel barrier stacks are suitable for use in a variety of electronic applications, including nonvolatile memory devices and magnetic field sensors. Magnetic random access memory (MRAM) can, for example, offer faster operating speeds than flash memory. MRAM devices can replace dynamic random access memory (DRAM) devices in some applications.

[0003] A magnetic tunnel barrier consists of two magnetic layers and a tunnel barrier layer located between the magnetic layers. The magnetic layers can be characterized as a "reference" layer and a "free" layer, respectively, while the tunnel barrier can be a thin tunnel oxide layer. The magnetization direction of one layer of the barrier is fixed, allowing it to serve as a reference layer. The magnetization of the free layer can be determined by an electrical input. The MTJ has two stable resistance states for digital memory applications and multiple states for neuromorphic applications. A charge current from the reference layer to the free layer causes the MTJ to switch between states by overcoming the energy barrier.

[0004] Silicon-based devices typically include multiple interconnect metallization layers above the device (Front End of Line (FEOL)) layer containing field effect transistors (FETs) or other structures. FEOL processing includes high-temperature steps for manipulating semiconductor conductivity. Middle of Line (MOL) processing includes steps typically used to fabricate metal contacts for logic circuit components such as field effect transistors (FETs), resistors, diodes, and capacitors. MOL processing includes intermediate-temperature steps for forming semiconductor-metal compounds (silicides, silicides of germanium) for electrical contact. Back-end of Line (BEOL) processing involves establishing metal interconnect wires that connect the devices formed in the FEOL processing to form circuits. Metal lines comprising the interconnect wires are sequentially deposited (e.g., M1, M2, M3, etc.) above the FEOL layer and include a dielectric layer containing trenches and vias filled with electrical conductors. Trench openings are typically formed in the dielectric layer using, for example, known damascene or dual damascene techniques. The M2 and M3 lines can have a wider pitch than the M1 line. The interconnect wires within each metal line are electrically connected to the interconnect wires within other metal lines and to the devices in the FEOL layer. BEOL processing includes low temperature steps for forming the metal lines and preserving temperature sensitive FEOL and MOL structures. Dense MTJ structures (MRAM bits) are formed in the BEOL layers for memory and neuromorphic applications. Low temperature BEOL processing preserves the delicate MTJ devices, where both the magnetic and tunnel layers are highly sensitive to excessive temperature treatment during post-processing. These dense MTJ memory cells require narrow metal wires for access. The narrow wires are routed above and below the MTJ memory cells. The access speed and maximum size of a single memory group or array depends on the resistance of the narrow wires with faster access speeds and the larger single arrays obtained with lower wire resistance.

[0005] Due to copper's excellent electrical conductivity, copper wires are chosen to reduce wire resistance. However, lateral and vertical scaling of copper wires beyond 40 nm leads to a nonlinear increase in copper wire resistance, which is known as the interconnect size effect or, alternatively, the copper wire size effect. The physical mechanism behind the size effect is electron diffusion and scattering away from wire grain boundaries and interfaces. The average copper grain size decreases proportionally with wire size and is typically comparable to the wire width. This interconnect size effect becomes a major limitation to achieving low resistance in narrow copper wires. Summary of the Invention

[0006] Large-grain copper interconnects for MRAM are formed without substantially affecting the magnetic properties of the MTJ stack of the non-volatile memory device.

[0007] A method for forming a large-grain copper bitline for an electronic structure includes obtaining an MRAM structure, the MRAM structure comprising: a device wafer including an electronic device; a metallization layer above the device wafer and including a bottom electrode therein, the bottom electrode being electrically connected to the electronic device; and vertical pillars having sidewalls above the metallization layer, each vertical pillar including a magnetic tunnel barrier and a top electrode. A copper bitline having a copper line size effect is formed above the top electrode. The copper bitline has a width of forty nanometers or less, an area of ​​three thousand square nanometers or less, and copper grains of relatively small size relative to the width of the copper bitline. Laser annealing the copper bitline causes melting of the copper bitline. The method further includes recrystallizing the copper bitline during cooling after the laser annealing, thereby forming relatively large grains therein and reducing the copper line size effect of the copper bitline formed above the top electrode.

[0008] Another method for forming a large-grain copper bitline for an electronic structure includes obtaining an MRAM structure comprising vertical pillars having a pitch of sixty nanometers or greater, each of the vertical pillars comprising a magnetic tunnel barrier and a top electrode, a plurality of spaces between and separating each of the vertical pillars, and a dielectric layer filling each of the plurality of spaces between the vertical pillars. A copper bitline is formed on the top electrode and along the pitch of the vertical pillars. The copper bitline extends across the spaces between the vertical pillars and has a width of forty nanometers or less, an area of ​​three thousand square nanometers or less, and copper grains of relatively small size relative to the width of the copper bitline. The method further includes laser annealing the copper bitline to melt the copper bitline, and recrystallizing the copper bitline during a cooling period after the laser annealing. Relatively large grains are formed that are vertically aligned with the vertical pillars. The large grains have grain boundaries primarily located in the dielectric layer occupying the spaces between the vertical pillars.

[0009] In another aspect of the present invention, a magnetoresistive random access memory structure includes a plurality of vertical pillars having sidewalls. Each of the plurality of vertical pillars includes a magnetic tunnel barrier and a top electrode. The pillar pitch of the plurality of pillars is sixty nanometers or greater. The memory structure also includes a plurality of spaces, each of the plurality of spaces being located between a pair of opposing sidewalls of adjacent vertical pillars. A dielectric layer fills each of the plurality of spaces. A copper bit line is above each top electrode and electrically connected to each top electrode. The copper bit line has a line width of forty nanometers or less, a grain size greater than twice the line width, and an average grain size of 0.06 microns or greater. The pillar pitch is along the copper bit line.

[0010] The techniques and structures disclosed herein can provide substantial beneficial technical effects. By way of example only and not limitation, one or more embodiments can provide one or more of the following advantages:

[0011] Reducing the copper grain boundaries within the copper lines above the MTJ stack;

[0012] Reducing the resistance of the copper wire above the MTJ stack without affecting the magnetic properties of the MTJ stack;

[0013] It can speed up the access speed of the MRAM array.

[0014] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments of the invention, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following drawings are presented by way of example only, and not limitation, wherein like reference numerals (when used) designate corresponding elements throughout the several views, and in which:

[0016] Figure 1 is a schematic cross-sectional view showing a device wafer including FEOL devices / circuits, a first metal layer on the device wafer, and a second metal layer including a bottom electrode;

[0017] Figure 2 is a schematic cross-sectional view illustrating an exemplary MTJ stack, a dielectric cap layer, and an electrode layer above a second level metal layer;

[0018] Figure 3 Figure 1 shows the structure of the MTJ pillar after the MTJ stack is formed. Figure 2 A schematic cross-sectional view of the structure of

[0019] Figure 4 is a schematic cross-sectional view thereof after nitride encapsulation of the MTJ pillar and associated capping layers and electrodes;

[0020] Figure 5 is a schematic cross-sectional view after deposition of an interlayer dielectric layer and planarization;

[0021] Figure 6 is a schematic cross-sectional view showing a copper bitline having relatively small grains and a large number of grain boundaries;

[0022] Figure 7 is a schematic cross-sectional view thereof showing laser annealing to melt a top copper wire and form the top copper wire having relatively large grains and an improved interface upon recrystallization thereof;

[0023] Figure 8A It means in Figure 5 A graph of tunnel magnetoresistance as a function of laser light after forming a top copper line and depositing a top cap layer on the top copper line on the structure shown; annealing temperature; and

[0024] Figure 8Bis a graph showing the product of resistance and area (RA) as a function of laser annealing temperature.

[0025] It should be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be depicted in order to facilitate a less obstructed view of the illustrated embodiments. DETAILED DESCRIPTION

[0026] The principles of the present invention will be described herein in the context of illustrative embodiments. However, it should be understood that the specific embodiments and / or methods illustratively shown and described herein are to be considered exemplary and not restrictive. Furthermore, it will be apparent to those skilled in the art, given the teachings provided herein, that numerous modifications may be made to the illustrated embodiments, all of which are within the scope of the appended claims. That is, no limitation with respect to the embodiments shown and described herein is intended or should be inferred.

[0027] By integrating memory devices close to the FEOL layer rather than in a special section on the chip or using a separate dedicated memory chip, access time and overall circuit performance can be potentially enhanced. MRAM is a type of memory device that can be integrated with BEOL CMOS processing just above the FEOL layer, such as between the M2 and M3 lines or layers. After FEOL processing and the formation of metal lines M1 and M2, the Figure 1The monolithic structure 20 shown in FIG. FEOL layers include electronic devices, such as field effect transistors (FETs) comprising integrated circuits. A first metal layer, M1, includes contacts and via conductors (not shown) electrically connected to the electronic devices in the FEOL layer 22, and a second metal layer, M2, includes copper lines electrically connected to the M1 layer. The memory cell structure may include one access transistor or may be a cross-point type, in which all active elements (transistors) are located at the periphery of the array. In either case, the MTJ storage element has two connections, through the bottom M2 metal line and through the top M3 metal line. The bottom M2 line of the MTJ MRAM cell is connected to the source of the NFET access transistor, while the top M3 line of the MTJ MRAM cell is connected to the array periphery circuitry. Both the M3 and M2 lines may be referred to as bit lines. For a cross-point MRAM memory cell, both the M2 and M3 metal lines are connected to the array periphery circuitry. Large memory arrays or banks result in long M3 connection metal lines. In some embodiments, up to 64,000 individual MTJ cells or bits are connected to a single M3 bit line. Dense memory arrays require narrow M2 and M3 metal lines and tight M2 and M3 pitches. Long, narrow M3 lines introduce a substantial memory access time penalty, which in turn places a limit on the maximum array or bank size. Increasing the number of memory arrays or banks per memory die is detrimental to overall memory density due to the duplication of peripheral circuitry. Therefore, there is a continuing need to reduce the resistance of long, narrow bit lines, thereby enabling faster access times and / or larger individual memory arrays.

[0028] The trench opening is usually formed in the ILD layer 24 by using, for example, a known damascene technique. After the ILD layer is deposited, photolithography and etching steps are carried out. Specifically, a photoresist (not shown) is applied on the ILD layer. The photoresist can be applied by any suitable technique, including but not limited to coating or spin coating techniques. A mask (not shown) is provided on the photoresist, the mask being patterned with the shape of the trench opening (and possible contact hole) that will be formed, and the mask pattern is transferred to the photoresist using a photolithography process, which produces a depression in the uncovered area of ​​the photoresist. Subsequently, by conventional etching that is usually used to form trenches and contact holes, patterned photoresist is used to produce identical depression patterns in the ILD dielectric layer. Dry etching (for example, reactive ion etching) can be adopted to form such trenches and contact holes. Etching selectively removes a portion of the ILD layer 24, and the depth of the trench opening can be controlled by using a timed etching process. Or, the dielectric layer can comprise a plurality of layers that can be selectively etched. In this case, the etching process selectively removes the upper layer of the ILD layer and stops at the lower layer where the etch stop layer is formed. After the trench opening is formed, the photoresist can be stripped from the ILD layer by ashing or other suitable process. The resulting structure can be wet cleaned.

[0029] Another stage in the manufacturing process involves depositing a conformal layer of liner material. This conformal layer of liner material lines the sidewalls and bottom surfaces of the trenches or other openings within the ILD layer 24. The liner material can include one or more thin layers of materials such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), cobalt (Co), ruthenium (Ru), tungsten (W), tungsten nitride (WN), titanium-tungsten (TiW), tungsten nitride (WN), manganese (Mn), manganese nitride (MnN), or other liner materials (or combinations of liner materials) such as RuTaN, Ta / TaN, CoWP, NiMoP, or NiMoB, as appropriate for a given application. The thin liner acts as a diffusion barrier and adhesion layer. The conformal layer of liner material is deposited using known techniques, such as CVD, ALD, or PVD. PVD can be used to deposit a thin, conformal copper (Cu) seed layer on the surface of the liner, followed by electroplating of Cu to fill the damascene (or dual damascene) openings in the ILD layer. Electroplating is followed by a thermal annealing stage.

[0030] The overlying liner, seed, and metallization materials are then removed by performing a three-step chemical mechanical polishing (CMP) process to planarize the surface of the semiconductor structure down to the ILD layer 24. A metal capping layer (not shown) can be selectively deposited on the exposed metal interconnect layer within the trench. For example, a metal such as cobalt, ruthenium, or manganese can be deposited using chemical vapor deposition or atomic layer deposition to form the metal capping layer. Post-deposition cleaning may be required to ensure that no leakage or degradation occurs due to possible metal residues on the resulting structure.

[0031] The M2 layer may also be referred to as the bottom or lower line of a memory element or memory cell, or the bottom portion of a bit line. When forming the M2 layer, a SiCOH dielectric film having a dielectric constant (k) of approximately 2.7-2.8 may be used. This dielectric film may be deposited using PECVD. The film is patterned as described above to form a trench, which is then filled with copper to form the bottom electrode 26, which preferably has a relatively low resistance. A low-resistance electrode may be obtained by annealing and recrystallizing the deposited metal.

[0032] See Figure 2, using, for example, physical vapor deposition (PVD) or ion beam deposition (IBD) to deposit the MTJ stack thin film. The tunnel barrier layer 28 can be formed by oxidizing the metal layer without oxidizing the underlying reference layer 25. A metal capping layer 29 is formed on the free layer 27, and the capping layer can be composed of, for example, Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, Al or other high melting point metals or conductive metal nitrides. The capping layer 29 can have a thickness from two (2) nm to twenty-five (25) nm. A top electrode layer 30 is formed on the capping layer. The top electrode 30 can be composed of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride, ruthenium tantalum nitride, tantalum nitride, cobalt, tungsten nitride, tungsten nitride or any combination thereof. The top electrode 30 can have a thickness from two (2) nm to twenty-five (25) nm. The MTJ stack film is patterned by a stack etching process to form pillars 32, Figure 3 Several of the columns are shown. Ion milling (ion beam etching or IBE) is an effective MTJ stack etching technique. A dielectric cap layer (not shown) is formed by a hard mask (not shown) adjacent to the top surface of the top electrode layer 30. The dielectric cap layer may include silicon nitride or other composition suitable for ion beam etching of the MTJ stack film. The dielectric cap is removed after the ion beam etching.

[0033] Reference again Figure 3The exemplary structure shown shows the MTJ stack after deposition and patterning of a hard mask, ion beam etching of the MTJ stack film, and removal of the hard mask. Etching of the MTJ stack film results in the formation of vertical pillars 32 from the stack film, each of which contains a magnetic tunnel barrier consisting of a tunnel barrier layer 28 between a reference layer 25 and a free layer 27. The tunnel barrier layer 28 is made as thin as possible and is typically only 3 nm or less to allow significant tunneling current. The ultra-thin tunnel barrier layer 28 makes the MTJ structure sensitive to high temperature heat treatments because adjacent metal elements can diffuse into and change their properties through such an ultra-thin layer. Annealing of the formed MTJ with an ultra-thin tunnel barrier 28 in excess of 500°C is generally avoided. The free layer 27 can be formed of magnetically active metals such as Fe and / or Co, FeCoB, and combinations thereof, as well as other interlayers known in the art, and can include multiple layers. The reference layer 25 is adjacent to a bottom electrode 26 formed within an electrically insulating (ILD) interlayer 24 and may include multiple layers, including a pinned layer, a ferromagnetic layer, and a spacer layer between the ferromagnetic layers. Exemplary materials for forming the magnetic reference layer include iron, nickel, cobalt, chromium, boron, manganese, and alloys thereof. A large single array of MTJ pillars (MRAM bits) can be formed (64 kb to 256 Mb or greater). A large single array of MTJ pillars can be replicated several times to achieve a target capacity per product die (e.g., to one (1) Gb). In some embodiments, the MTJ pillars can be formed in a "checkerboard" pattern with a pillar spacing (pitch) of sixty nanometers or greater along the subsequently formed top bit line.

[0034] Intermediate layer 24 can be formed, for example, from silicon oxide or a low-k dielectric material such as SiCOH, as described above, and include multiple dielectric sublayers. Chemical vapor deposition (CVD), including plasma-enhanced CVD, can be used to deposit low-k (k less than 4.0) dielectric materials, such as porous SiCOH. Bottom electrode 26 is electrically connected to metal contact vias Q1 / V1, which in turn are electrically connected to the M1 layer. A portion of metal cap layer 29 abuts the top surface of the free layer of each exemplary pillar 32, and a top electrode layer 30 abuts the top surface of metal cap layer 29 of each pillar and forms a top electrode, such as Figure 3 As shown, the layers of posts 32 are not necessarily drawn to scale.

[0035] An encapsulation layer 34 is formed on the MTJ pillar 32 and may include multiple layers. For example, a manganese oxide or other oxide (e.g., metal silicate or metal oxynitride) compound may be formed on the MTJ pillar, followed by the deposition of a conformal dielectric layer such as silicon nitride. By encapsulating the pillar and the optional oxygen-containing barrier layer with a silicon nitride layer, the barrier properties can be enhanced. In embodiments where the encapsulation layer is a conformal layer of silicon nitride, a layer thickness of twelve to fifteen nanometers is formed in one or more exemplary embodiments. The silicon nitride layer extends over the pillar 32 and the top surface of the M2 layer. When used in conjunction with an underlying manganese silicate layer having a thickness of two to three nanometers adjacent to the sidewalls of the pillar, for example, a silicon nitride layer having a thickness of five to six nanometers is sufficient to provide an acceptable copper and oxygen diffusion barrier layer. The combined manganese silicate / silicon nitride diffusion barrier layer will have a lower average dielectric constant (k) than a barrier layer consisting solely of silicon nitride. The relatively thin copper / oxygen diffusion barrier layer makes nano-MTJ device fabrication compatible with advanced CMOS scaling.

[0036] In some embodiments, a liner is deposited on the MnSiOx layer to improve barrier properties. For example, a manganese nitride (MnN) liner having a thickness of one to five nanometers (1-5 nm) can be used. Such a liner can be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The MnSiOx / MnN barrier layer provides an effective oxidation barrier layer as well as a copper diffusion barrier layer. In some embodiments, a 2-3 nm MnSiOx layer and a 5 nm MnN liner are used to form a barrier layer on the MJT column 32. In embodiments including a MnN liner, a stable phase MnNx material such as a Mn3N2 phase or Mn4N is preferred because excess Mn will act as an oxygen scavenger and subsequently become a good / better oxidation barrier layer. In the MnO x In embodiments formed or deposited on the sidewalls of pillars 32, the value of x is preferably less than two (2) to act as an oxygen scavenger and serve as an oxygen barrier. In preferred embodiments, 1.5 <x<1.0。

[0037] Techniques for encapsulating the MTJ pillar within a diffusion / oxidation barrier layer and oxidation residues may, for example, involve Figure 3 MnO is deposited directly on the entire structure 35 shown in FIG. x or MnSiO x, or selectively deposit Mn and then oxidize it. Atomic layer deposition (ALD) can be used to deposit the oxidized barrier material, thereby encapsulating the MTJ column 32 and extending above the M2 wiring layer. The oxygen in the deposited compound can oxidize the residues that may be present on the MTJ column. Manganese oxide has multiple empirical formulas, such as MnO, MnO2, MnO3, Mn3O4 and Mn2O3. In some embodiments, manganese oxide with a relatively high oxygen content is deposited closest to the MTJ column, while a manganese oxide compound with a lower oxygen content is deposited later in the deposition process, thereby forming a gradient diffusion barrier. Once the oxygen in the inner portion of the diffusion barrier layer is used for oxidation of the metal residue, the inner portion can eventually have a relatively low oxygen concentration. ALD deposited MnSiO x The oxygen content of the MnSiO2 can also be graded, at least initially with a higher oxygen content in the region adjacent to the pillar 32 where metal residues are expected to be oxidized. x In embodiments deposited on the MTJ stack, in some embodiments, the atomic percentage compositions of manganese, silicon, and oxygen are 12.8%, 28.5%, and 58.7%, respectively. In some embodiments, the composition of the manganese silicate film adjacent to the MTJ stack can therefore be given as Mn(SiO2)2. It will be understood that MnSiO2, as used herein, is a x The layers may not be completely uniform in composition, nor do they need to be. For example, the manganese silicate (Mn(SiO2)2) layer may have a manganese atomic concentration of 13.7% to 11.9%, a silicon concentration of 31.2% to 25.9%, and an oxygen concentration of 61.2% to 56.2%. The manganese silicate described herein has a dielectric constant of approximately 3.7, compared to a dielectric constant of 6.8-7.0 for silicon nitride.

[0038] An interlayer dielectric (ILD) layer 36 is deposited on the encapsulation layer 34 of the structure 40. The ILD layer 36, similar to the intermediate layer 24, can be formed of silicon oxide or a low-k dielectric material such as SiCOH as described above, and can include multiple dielectric sublayers. Due to the underlying topography, such as the ability to fill between MTJ pillars, the deposition process for the ILD layer 36 should have gap filling capabilities. For this reason, it is preferred to deposit a flowable ILD material. Chemical vapor deposition (CVD), including plasma enhanced CVD, can be used to deposit low-k (k less than 4.0) dielectric materials, such as porous SiCOH. Alternatively, spin coating deposition of a flowable low-k material can be used. The ILD layer 36 fills the space between the pillars 32 and is adjacent to the encapsulation (barrier) layer 34. The ILD layer 36 can be optionally cured using various known curing techniques, including UV light assisted curing at less than 400°C. The resulting structure is then chemically mechanically planarized (CMP) down to the top surface of the top electrode 30 to obtain a structure such as Figure 5The structure 50 is shown schematically.

[0039] A top copper bit line 38, or equivalently, an MRAM bit line, is formed using an upper metallization layer such as M3. An M3 layer similar to the M2 layer is formed using a damascene method. An ILD layer (not shown) is first deposited over the MTJ pillar 32, encapsulation layer 34, and ILD material 36. Conventionally, trench openings are formed in the ILD layer using known damascene techniques. Specifically, a photoresist (not shown) is applied over the ILD layer. The photoresist can be applied by any suitable technique, including but not limited to coating or spin coating techniques. A mask (not shown) is provided over the photoresist, the mask being patterned with a shape defining the trench openings (and possible contact vias) to be formed, and the mask pattern is transferred to the photoresist using a photolithography process, which creates recesses in the uncovered areas of the photoresist. The patterned photoresist is then used to create the same recessed pattern in the ILD dielectric layer by conventional etching, typically used to form trenches and contact vias. Such trenches and contact vias can be formed using dry etching (e.g., reactive ion etching). The etching selectively removes a portion of the ILD layer. The depth of the trench opening can be controlled by using a timed etching process. Alternatively, the dielectric layer may include multiple layers that can be selectively etched. In this case, the etching process selectively removes the upper layer of the ILD layer, stopping at the lower layer where the etching stop layer is formed. After the trench opening is formed, the photoresist can be stripped from the ILD layer by ashing or other suitable process. The resulting structure can be wet cleaned. The contact via at this M3 level directly contacts the top electrode 30 of the MTJ pillar 32 to form an MRAM bit line. In some embodiments, the width of the M3 bit line trench is 15nm to 40nm, and its depth is 30nm to 80nm, or approximately twice its width. In some embodiments, the M3 bit line pitch is two or four times larger than the M3 bit line trench width, or from 30nm to 160nm.

[0040] Another stage of the manufacturing process includes depositing a conformal conductive layer of liner material 39, which lines the sidewalls and bottom surfaces of the trench or other opening in the ILD, wherein the top copper bitline is formed in the ILD. The liner material 39 may include one or more thin layers of materials, such as tantalum (Ta) and / or ruthenium (Ru). Other liner materials (or combinations of liner materials) suitable for a given application may be used instead. The thin liner serves as a barrier diffusion layer and an adhesion layer. The conformal layer of liner material 39 is deposited using known techniques, such as CVD, ALD, or PVD. In some embodiments, the adhesion layer or copper wetting layer is deposited on the barrier material (e.g., TaN) and includes a material that is immiscible with liquid copper, such as Ta or Ru. In a preferred embodiment, materials that are miscible with liquid copper (e.g., cobalt) are not used as the liner material. The total thickness of the liner 39 is three (3) nm to six (6) nm. A thin copper (Cu) seed layer may be deposited on the surface of the liner using PVD, followed by electroplating of Cu (MRAM bit line 38) to fill the damascene (or dual damascene) openings in the ILD layer of the M3 level of the structure. Low temperature thermal annealing (<200°C) may be performed after electroplating.

[0041] The covering liner, seed crystal, and metallization materials are then removed by performing a three-step chemical mechanical polishing (CMP) process to flatten the surface of the semiconductor structure down to the top surface of the M3 ILD layer (not shown). A metal capping layer (not shown) can be selectively deposited on the exposed metal bitline layer within the trench. For example, chemical vapor deposition or atomic layer deposition can be used to deposit a metal such as cobalt, ruthenium, or manganese to form the metal capping layer. In some embodiments, the metal capping layer includes a material that is immiscible with liquid copper, such as Ta or Ru. Post-deposition cleaning may be required to ensure that leakage or degradation does not occur due to possible metal residues on the resulting structure. In some embodiments, the copper cross-sectional area of ​​the M3 bitline 38 is 300nm 2 to 3000nm 2 The M3 metal bit line 38 is generally orthogonal to the M2 metal line, forming a crossover point at their intersection.

[0042] A top dielectric cap layer 42 is sequentially deposited over the formed M3 metal bit line and the associated vias electrically connecting the M3 bit line to the top electrode 30. In a preferred embodiment of the present invention, the top dielectric cap layer comprises a substantially non-porous dielectric material. A low-k silicon carbonitride material, such as NBLoK, may be deposited over the M3 metal bit line 38 using plasma enhanced chemical vapor deposition at 375°C. TM This material includes Si, C, O, H, and N and is sold by Applied Materials. Silicon nitride and silicon oxynitride are non-limiting examples of other materials that may be deposited on the top copper line 38. In some embodiments, the top capping layer 42 may include multiple layers.

[0043] The deposition of dielectric cap layer 42 provides an ideal thermal treatment of the formed copper metal bitline 38 and its associated vias at 375°C. As a result of this treatment, the average copper grain size increases slightly, but remains relatively small and is generally smaller than the width of the copper portion of the M3 metal bitline 38. Specifically, for copper line widths of 40 nanometers or less, the average copper grain size is less than 40 nanometers. As a result, the resulting copper bitline 38 has relatively small grains and a large number of grain boundaries. Such boundaries are illustrated in FIG. Figure 6 While layer 39 is depicted with its diffusion barrier, adhesion or wetting layer, and metal capping layer, M3 metal bitline 38 is essentially an elemental copper structure with low levels of impurities inadvertently introduced during the deposition process, or, alternatively, a copper alloy that melts in a temperature range similar to elemental copper. Elemental copper melts at approximately 1090°C. Thus, the term "copper bitline" encompasses both elemental copper bitlines that may contain impurities as well as copper alloy bitlines that melt at or below approximately 1150°C.

[0044] The resistance of a copper wire per unit length is determined by two factors: copper resistivity and copper wire cross-sectional area. For standard macroscale wires, copper resistivity is a material property that is independent of the wire cross-sectional area, and the wire resistance per unit length is the copper resistivity divided by the copper cross-sectional area. For nanoscale wires, such as the case of the M3 metal bitline 38, this relationship breaks down, and the wire resistivity becomes dependent on the wire geometry. This is because electrons within a copper nanowire collide with wire walls and grain boundaries, and electrons transfer momentum more frequently to wire walls and grain boundaries than to copper lattice vibrations and copper crystal defects. In bulk copper, the average distance between electron collisions, known as the electron mean free path, is approximately 40 nm. Once the wire cross-sectional size becomes comparable to or smaller than the electron mean free path in bulk copper, or ~40 nm, interfacial and grain boundary electron collisions cause the wire resistivity to rise. This effect is known as the interconnect size effect, and the resulting nanowire resistivity is known as the effective resistivity of the copper nanowire, which is defined as the product of the measured copper wire resistance per unit length and the copper cross-sectional area. For example, the effective copper conductor resistivity of an 80 nm wide line is close to the bulk copper resistivity of about 1.7 μΩ cm, while the copper cross-sectional area is about 300 nm. 2 The effective resistivity of the 18 nm wide line is more than five (5) times higher at about ˜9 μΩ cm.

[0045] Growing large copper grains in narrow copper lines can reduce the effective resistivity of copper, partially reversing the interconnect size effect. Making the average copper grain size larger than about 80nm can actually eliminate the grain boundary scattering component of the interconnect size effect. In addition, electrons scattered from the line interface can be diffuse or specular. Diffuse scattering is responsible for the transfer of electron momentum into the line sidewalls, thereby negatively affecting the effective resistivity of copper. Specular scattering does not cause electron momentum transfer and does not affect the effective resistivity of copper. The goal of designing copper line interfaces is to increase the specular scattering component over the diffuse scattering component. This can further suppress the interconnect size effect, making the effective copper resistivity closer to the bulk value.

[0046] The top (M3) copper bit line 38 is electrically connected to the underlying top electrode 30 of the MTJ pillar by a through-hole conductor, and the top copper bit line is laser annealed and then cooled. The laser annealing process melts the top copper line for a very short duration, while the liner 39, top electrode 30, metal cap layer 29 and free layer 27 remain solid. The magnetic properties of the MTJ pillar 32 are substantially unaffected by the laser annealing and recrystallization of the M3 copper bit line 38, the recrystallization of the M3 copper bit line 38 originating from the top surface of the top electrode 30 or the liner portion 39 thereon. The grain size of the metal or single-phase metal alloy is an estimate of the average grain size. A recrystallized top (M3) copper bit line 38' is formed, which has relatively large grains (e.g., greater than 0.06 μM), increased specular scattering at the line interface, and therefore lower resistance and effective resistivity, as shown in FIG. Figure 7 As schematically shown in FIG, some embodiments optionally deposit an optically opaque sacrificial absorbing layer (not shown) on the top dielectric cap layer 42 prior to laser annealing. The purpose of such a sacrificial layer is to uniformly absorb the laser radiation regardless of the metal line material, including any of its capping and liner materials, and their pattern density. The sacrificial absorbing layer can be a conductive film, such as tantalum nitride or titanium nitride, having a thickness sufficient to absorb all or most of the laser radiation. After laser annealing, the sacrificial absorbing film is removed selectively relative to the top dielectric cap layer 42.

[0047] The term "laser annealing" refers to an annealing method that uses a laser to introduce heat into the metal interconnect being processed. A laser is an electro-optical device that emits coherent radiation 44. In some embodiments, a typical laser emits light of a defined wavelength in a narrow, low-divergence beam. One advantage of using laser irradiation for the annealing process is that its light can be easily shaped and focused onto a specific area of ​​the annealing surface to achieve very high radiation intensity or energy density with a short exposure duration.

[0048] In some embodiments, short exposure durations are achieved by raster scanning a focused laser beam over the substrate surface, including the dielectric passivation layer 42, the top (M3) copper bitline 38, and the MTJ pillars 32. In this case, the exposure duration, measured at the incident intensity full width at half maximum (FWHM), is the beam width in the scan direction divided by the scan speed. In an alternative embodiment, short exposure durations are achieved by employing a pulsed laser. In this case, the laser beam is shaped to achieve the desired peak intensity over a selected substrate area, such as over the entire product die or a portion thereof, and the laser is operated in a pulsed mode, such as in the case of a Q-switched laser. The pulse duration of the Q-switched laser at the intensity FWHM determines the substrate exposure time. The exposure process is repeated over the entire wafer surface in a step-and-repeat approach, with some target beams overlapping in adjacent exposures. In some embodiments, exposure of the wafer surface to the laser beam comprises exposures of 1 to 100 pulses. In the case of multiple laser pulses, the total cumulative duration (defined by multiplying the number of pulses by their respective durations at half maximum) is 100 nanoseconds to 3,000 nanoseconds.

[0049] In some embodiments, the laser type used in the laser annealing method of the present application is selected from a solid-state Nd:YAG laser emitting at 1064nm and a frequency-doubled or tripled Nd:YAG laser emitting at 532nm or 355nm, respectively, or an excimer laser emitting at less than 400nm. Excimer lasers can be powered by chemical reactions involving excited dimers or excimers, which are short-lived dimer or heterodimer molecules formed by two substances (atoms), at least one of which is in an excited electronic state. Commonly used excimers include F2 (fluorine, emitting at 157nm), and rare gas compounds such as ArF (193nm), KrCl (222nm), KrF (248nm), XeCl (308nm), and XeF (351nm). Excimer lasers are typically operated in a Q-switched, pulsed mode suitable for step-and-repeat pulse wafer exposure. Solid-state Nd:YAG lasers offer an alternative to excimer lasers due to their stable, high-power output at 1,064 nm, which can be efficiently frequency-doubled or frequency-tripled to emit radiation at 532 nm or 355 nm. Solid-state lasers can be configured in continuous, pulsed, or Q-switched pulse modes, which are suitable for raster scanning and step-and-repeat pulse operation. Laser wavelength selection is important for coupling the laser radiation into a suitable absorbing material. Ordinary dielectric materials do not absorb or only absorb weakly (e.g., absorbing less than 5% of the coupled radiation) even at short wavelengths of about 350 nm to about 250 nm. On the other hand, metals and metal compounds absorb radiation with wavelengths of about 600 nm or shorter, making shorter wavelength lasers more preferred for structures with metal layers, such as the copper bit lines described herein. In some embodiments, a XeCl laser (308 nm) can be used, which couples about 30-70% of its incident radiation into the top (M3) copper bit line 38 and the MTJ pillar 32.

[0050] Once the substrate including the dielectric passivation layer 42, the top copper bitline 38 and the MTJ pillar 32 is exposed to laser radiation by raster scanning or by laser pulses, the temperature of the top copper bitline 38 and the MTJ pillar 32 begins to rise from its base value and falls shortly thereafter. The increased temperature of the top copper bitline 38 and the MTJ pillar 32 causes thermal energy or heat to flow into the adjacent structures including the dielectric passivation layers 34, 36, 42 and the underlying bottom electrode structure 26, thereby raising their temperatures in a step locked to the temperature of the top copper bitline 38 and the MTJ pillar 32. A representative temperature-time trajectory of a nanosecond laser annealing process includes four (4) distinct temperature regions: an initial or base substrate temperature, a heating portion, a temperature peak point, and a cooling portion. This triangular temperature-time profile or trajectory is often referred to as a spike anneal or laser spike anneal. The initial or base substrate temperature can range from 23°C (room temperature) to 400°C. This temperature is typically set by a hot plate on which the substrate is located. Alternative heating devices can also be used to maintain the substrate at the base temperature. Such alternative or additional heating devices may include backside or frontside lamp annealing, microwave heating, and a millisecond secondary preheating laser beam. A laser beam having a wavelength of approximately 308 nm raises the surface temperature of the substrate, including the top (M3) copper bitline 38 and the MTJ pillar 32, from base temperature to peak temperature at a ramp rate of approximately 1,000,000,000°C / second to approximately 100,000,000,000°C / second. The temperature of adjacent structures, including the bottom electrode structure 26, rises in lock-in step with the temperature of the copper line 38 and the MTJ pillar 32, but at a slightly reduced rate, such that its peak temperature is 20°C to 100°C lower than the peak temperature of the copper bitline 38. After the laser irradiation exposure, the surface temperature, including the top copper bitline 38 and the MTJ pillar 32, quickly drops back to base temperature, with a temperature ramp rate of approximately 300,000,000°C / second to 30,000,000,000°C / second. The annealing duration, measured near the peak temperature point, is typically about 1 nanosecond to about 500 nanoseconds, but more typically about 10 nanoseconds to about 100 nanoseconds, measured at a level 50°C below the peak temperature. The laser annealing process duration is typically specified in terms of the radiation exposure duration at full width half maximum (FWHM) rather than the annealing duration at a temperature level 50°C below the peak temperature. These durations are related to each other, and in some embodiments, the annealing duration is a fraction (e.g., about 1 / 3) of the radiation exposure duration.

[0051] The laser-induced surface temperature rise is determined by the laser incident radiation intensity, the laser pulse or exposure duration, and the optical and thermal properties of the dielectric passivation layer 42, the top copper bitline 38, the MTJ pillar 32, and the underlying substrate structures. Short front-side laser exposures result in non-uniform heating of these substrate structures. With nanosecond laser pulses, the heat penetration depth in uniform metal structures, such as copper lines, is about 1 micron to about 5 microns, and in typical interconnect dielectrics, it is about 100 nanometers to about 500 nanometers. Furthermore, the temperature drop across the heterojunction is typically less than 10°C for metal-metal interfaces and less than 100°C for dielectric interfaces. Consequently, the top copper bitline 38 and MTJ pillar 32 are heated with a small top-to-bottom temperature gradient of approximately 0.1-0.3°C / nm, with the top copper bitline 38 having a higher peak temperature than the bottom electrode 26. The temperature gradient in the dielectric structure is several times larger, typically 0.3-3°C / nm.

[0052] It should be understood that the radiation intensity required to reach the target annealing temperature range above the copper melting point (1090°C) for the M3 copper bitline 38 depends on the specific underlying substrate structure, laser pulse duration, and selected laser wavelength. However, for a specific substrate structure and annealing parameters, the required incident radiation intensity can be experimentally determined by observing the copper bitline 38 melting at approximately 1090°C. In some embodiments, the nanosecond laser wavelength is 308 nm, the substrate base temperature is 250°C, the pulse duration at FWHM is 160 nanoseconds, and the coupled laser energy density at which the top copper bitline 38 begins to melt at the M3 level or higher is 0.1 J / cm 2 (This corresponds to 0.16 J / cm 2 The incident laser energy density can be varied. The precise metal level of the top copper bitline 38, or equivalently, the amount of thermal isolation from the FEOL substrate 22, can change this threshold. The presence of metal capping layers, barrier layers, and wetting layers such as TaN, Ru, Co, and Ta in the copper bitline 38 can also change this threshold. The pattern density of the top copper bitline 38, MTJ pillars 32, and bottom interconnect structures can also change this threshold. Although the substrate structure and laser parameters can be varied, thereby affecting the choice of incident laser energy density, a range from approximately 0.05 J / cm 2 to about 3J / cm 2 The top copper bit line 38 is melted with an incident laser energy density ranging from about 100 nanoseconds to about 3,000 nanoseconds and a laser radiation exposure duration from about 5 to about 200 nanoseconds. In some embodiments, the top copper bit line 38 is melted multiple times by exposing to multiple laser pulses with a cumulative duration from about 100 nanoseconds to about 3,000 nanoseconds.

[0053] After exposure to laser radiation, the temperature of the top copper bitline 38 begins to drop rapidly, causing the liquid copper to reach below its melting / freezing point. The liquid copper begins the solidification process by nucleating a solid copper seed and growing copper grains laterally from the seed. Excessive random nucleation of the solid copper seed may result in small copper grains due to lateral growth competing with adjacent, closely spaced copper seeds. The presence of the MTJ pillar 32 below the copper bitline 38 provides an effective local heat sink, thereby causing relatively cool spots in the portion of the copper bitline 38 directly above the MTJ pillar and promoting nucleation of solid copper seeds in these cooler locations. This effectively programs the position of the solid copper seed in the top copper bitline 38.

[0054] Spacing adjacent MTJ pillars by about 60 nm or more along the top copper bitline 38 results in having Figure 7 The large grain copper wire 38' of the structure 70 schematically illustrated in FIG, additionally, pushes any impurities that are immiscible with the liquid copper from the copper to the surface and grain boundaries, thereby producing a purer copper wire with superior electrical properties. Furthermore, the solidification of the liquid copper reforms the copper / liner interface, thereby increasing the specular scattering component. The use of a copper material that is not soluble in the liquid in the liner 39 and the bitline 38 cover cap (not shown) directly adjacent to the elemental copper ensures that these materials will not be incorporated into the interior of the copper wire, and the interior of the wire will comprise substantially pure elemental copper (or copper alloy if an alloy is used) with its excellent electrical conductivity. Performing multiple, sequential copper melt anneals is advantageous in increasing the average grain size and purifying the copper from immiscible impurities. As Figure 7 As illustrated in the figure, the bit line grains 38A', 38B', 38C' obtained after completing the laser annealing / recrystallization cycle as described herein are vertically aligned with the three illustrated underlying MTJ pillars 32, respectively, and the grain boundaries are mainly located in the bit line region between the MTJ pillars and above the space containing the encapsulation layer 34 and the dielectric layer 36.

[0055] As a result of the copper wire melting and recrystallization, the effective copper resistivity is reduced to close to the bulk copper resistivity of 1.7 μΩ cm. In some embodiments, the copper wire size effect is reduced by half or more, which means that the relative increase in effective copper wire resistivity relative to the bulk copper resistivity per given wire cross-sectional area is cut in half or more. For example, a copper cross-sectional area of ​​2000 nm is 2 The effective resistivity of the copper bit line is reduced from about 3.7 to about 2.7, or by more than 25%, or equivalently, the increase in effective bulk resistivity over bulk resistivity (~2 μΩcm) is halved to 1 μΩcm.

[0056] The ultrashort laser pulses described above avoid damage to the dielectric materials in the dielectric cap layer 42 and the ILD layer 36 as well as the layers including the MTJ pillar 32. Figure 8A and Figure 8BThe feasibility of the above-mentioned laser annealing technique for the top copper bitline formed above the MRAM pillar is illustrated in Figure 3. The graphs in both figures also show the temperatures at which copper and CoFeB melt and the threshold for MTJ functional degradation. The exemplary MTJ pillar 32 (shown in the earlier figure) contains a functional material comprising a CoFeB alloy that is sensitive to high-temperature (above 400°C) annealing due to its relatively low melting point. In addition, low-temperature (below 400°C) post-processing is typically required to prevent metal elements from diffusing across the tunnel barrier layer of the MTJ pillar 32, which can cause device shorting. For an exemplary overlay MTJ stack and exemplary laser annealing parameters, the melting point of the MTJ functional material and the corresponding damage threshold in the incident laser energy density were experimentally determined by observing the electrical functionality of the MTJ stack before and after laser annealing. The exemplary MTJ stack includes a copper top electrode capped with a ruthenium (Ru) cap. Different optical reflectivities of Ru at 308nm and different pattern densities (capping film) shift the copper melting threshold to 0.37J / cm of incident laser radiation. 2 Therefore, in this embodiment, a target annealing temperature range of about 1000°C to about 1300°C would require an incident laser energy density of 0.33 J / cm 2 Up to 0.46J / cm 2 .

[0057] Figure 8A Shown for J / cm 2 The measured incident laser energy density range and the obtained calibrated peak annealing temperature are used to determine the change in the MTJ parameter called tunneling magnetoresistance. A higher magnetoresistance is required. Figure 8A As shown, the top copper bit line ( Figure 6 Laser annealing of element 38 in FIG. 3 can be performed up to 1150°C without causing material degradation of the magnetic tunnel barrier, since the magnetoresistance is essentially unchanged at and below this temperature. 2 At higher annealing temperatures and higher laser energy densities, the magnetoresistance decreases / degrades significantly. Similarly, Figure 8B Different MTJ parameters called resistance-area (RA) product before and after laser annealing are shown, showing that the MTJ 2 There is no degradation when the copper bit line 38 / 38' is melted. At a given magnetoresistance value, a relatively low RA is required. RA increases / degrades at higher laser annealing energy densities. This demonstrates that the copper bit line 38 can be melted for durations ranging from 10 nanoseconds to 100 nanoseconds without causing any degradation of the MTJ pillar 32 located beneath the copper line 38 / 38'.

[0058] The accompanying figures, as described above, depict exemplary processing steps / stages in the fabrication of exemplary structures. Although the overall fabrication method and the structures formed thereby are completely novel, certain individual processing steps required to implement the method can utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tools. These techniques and tools will be familiar to those skilled in the relevant art given the teachings herein. In addition, one or more processing steps and tools for fabricating semiconductor devices are described in a number of readily available publications, including, for example, James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Molded 1. st Edition, Prentice Hall, 2001, incorporated herein by reference. It is emphasized that although some individual processing steps are set forth herein, these are illustrative only and those skilled in the art may be familiar with several equally suitable alternatives that may be applied.

[0059] It should be understood that the various layers and / or regions shown in the accompanying drawings may not be drawn to scale. In addition, for ease of explanation, one or more semiconductor layers of the type commonly used in such integrated circuit devices or other layers may not be explicitly shown in a given figure. This does not mean that the semiconductor layers or other layers not explicitly shown are omitted in actual integrated circuit devices.

[0060] Based on the discussion thus far, it can be understood that, in general, a method of forming an MRAM structure including an improved large-grain copper top interconnect (bit line) includes obtaining a first structure including a device wafer 22 containing electronic devices and a metallization layer M2 on the device wafer, and including a bottom electrode 26 electrically connected to the electronic devices. Vertical pillars 32 having sidewalls are formed above the metallization layer, each of the vertical pillars including a magnetic tunnel barrier and a top electrode 30. A barrier (encapsulation) layer 34 is formed on the sidewalls of the pillars 32 and may initially encapsulate the pillars, such as Figure 4 A dielectric layer 36 is deposited between the sidewalls of the vertical pillars. A top copper bit line 38 is formed on the top electrode and has relatively small grains, such as Figure 6 As shown, the width is 40nm or less and the cross-sectional area is 3,000nm 2 or less. A capping layer 42 is deposited on the top copper bit line, where a Figure 6The exemplary structure 60 shown. The top or M3 copper bit line is melted one or more times by laser irradiation without substantially affecting the magnetic properties of the magnetic tunnel barrier within the pillar 32. The method also includes recrystallizing the top copper bit line 38 during a cooling period after the laser irradiation to form relatively large grains and improved interfaces therein. The recrystallization of the top copper bit line proceeds upward from the top electrode 32, and the laser annealing parameters are selected to form large grains in the bit line without damaging the MTJ pillar. Exemplary parameters include a laser wavelength of less than 600 nm, a laser exposure time range of 1-500 nanoseconds, and a cumulative laser exposure time of 100-3000 nanoseconds. The structure can withstand, for example, 1-100 cycles of laser annealing and cooling at a temperature below 1150°C.

[0061] In one or more embodiments, adjacent MTJ pillars 32 and their top electrodes 30 are spaced apart by more than 60 nm along the bit line 38', resulting in an average copper grain size of more than 60 nm. The copper grain boundaries are primarily located between adjacent MTJ pillars, such as Figure 7 In one or more embodiments, an MTJ pillar pitch greater than sixty nanometers along the bit line 38' still allows for a high density of MTJ cells, with the area of ​​individual MTJ cells being less than 0.01 μm 2 . Refer to the above Figure 6 Compared with the bit line 38, the effective resistivity of the bit line 38' is reduced by more than 25%, and the increase of the effective bulk resistivity to the bulk resistivity is reduced by half or more. Figure 7 The structure 70 is schematically shown in FIG.

[0062] The memory array obtained according to the principles of the invention described herein includes MTJ and has a structure less than 3,000 nm. 2 The cross-sectional area of ​​the large grain top copper bit line, low access resistance, vertical alignment of the grains with the vertically extending MTJ pillars, and the grain boundaries mainly located between adjacent pillars. In one or more embodiments, the pitch of the MTJ pillars along the bit line 38' is sixty nanometers (60nm) or greater, which allows the formation of opposing grains. In the exemplary memory array, less than 0.01μm is provided. 2 After recrystallizing the copper bit lines, the relatively large grains of the recrystallized copper bit lines have an average grain size greater than 0.06 μm (or more than two (2) times greater than the bit line width).

[0063] At least a portion of the above techniques can be implemented in integrated circuits. When forming an integrated circuit, identical bare dies are typically fabricated in a repeating pattern on the surface of a semiconductor wafer. Each die includes the devices described herein and may include other structures and / or circuits. Individual dies are cut or sliced ​​from the wafer and then packaged into integrated circuits. Those skilled in the art will understand how to cut wafers and package dies to produce integrated circuits.

[0064] Those skilled in the art will appreciate that the exemplary structures discussed above may be distributed in raw form (i.e., a single wafer having multiple unpackaged chips) as a bare die, distributed in a packaged form, or incorporated as part of an intermediate or final product that benefits from having a structure including a magnetic tunnel barrier and associated bit lines formed according to one or more of the exemplary embodiments.

[0065] The descriptions of the embodiments described herein are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all elements and features of devices and systems that may utilize the circuits and techniques described herein. Many other embodiments will become apparent to those skilled in the art based on the teachings herein; other embodiments may be utilized and derived therefrom so that structural and logical substitutions and changes may be made without departing from the scope of the invention. It should also be noted that in some alternative implementations, some steps of the exemplary method may not occur in the order shown in the figures. For example, two steps shown in succession may actually be performed substantially simultaneously, or certain steps may sometimes be performed in the opposite order, depending on the functions involved. The figures are also merely representative and are not drawn to scale. Therefore, the description and drawings should be considered illustrative rather than restrictive.

[0066] In this document, if more than one embodiment is actually shown, the embodiments may be referred to individually and / or collectively as the term "embodiment", which is merely for convenience and is not intended to limit the scope of this application to any single embodiment or inventive concept. Therefore, although specific embodiments have been shown and described herein, it should be understood that arrangements that achieve the same purpose may replace the specific embodiment(s) shown. Combinations of the above embodiments, as well as other embodiments not specifically described herein, will become apparent to those skilled in the art from the teachings herein.

[0067] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprise" and / or "include", when used in this specification, specify the presence of stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Terms such as "above" and "below" and "vertical" are used to indicate the relative positioning of elements or structures relative to each other, as opposed to relative height.

[0068] The corresponding structures, materials, actions, and equivalents of any means or step plus function elements in the claims below are intended to include any structure, material, or action for performing the function in combination with other claimed elements as specifically claimed. The descriptions of various embodiments have been presented for the purposes of illustration and description, but are not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The embodiments are selected and described in order to best explain the principles and practical applications, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications that are suitable for the specific purposes envisioned.

[0069] The Abstract is provided to comply with 37 CFR §1.72(b). It is understood that it is not intended to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, the claimed subject matter may lie in less than all the features of a single embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

[0070] Given the teachings provided herein, one of ordinary skill in the art will be able to envision other implementations and applications of the technology and disclosed embodiments. Although illustrative embodiments have been described herein with reference to the accompanying drawings, it should be understood that the illustrative embodiments are not limited to those precise embodiments and that various other changes and modifications may be made therein by those skilled in the art without departing from the scope of the appended claims.

[0071] In a preferred embodiment of the present invention described herein, a method for forming a large-grain copper bitline for an electronic structure is provided, comprising: obtaining an MRAM structure comprising: vertical pillars having a pitch of sixty nanometers or greater, each of the vertical pillars comprising a magnetic tunnel barrier and a top electrode; a plurality of spaces, respectively located between and separating each of the vertical pillars; and a dielectric layer filling each of the plurality of spaces between the plurality of vertical pillars; forming a copper bitline over the top electrode and along the pitch of the vertical pillars, the copper bitline extending over the spaces between the vertical pillars, the copper bitline having a width of forty nanometers or less and an area of ​​three thousand square nanometers or less, and copper grains having a relatively small size relative to the width of the copper bitline; laser annealing the copper bitline to melt the copper bitline; and recrystallizing the copper bitline during a cooling period after the laser annealing to form therein relatively large grains vertically aligned with the vertical pillars and having grain boundaries located above the dielectric layer primarily in the spaces between the vertical pillars. Preferably, the laser annealing of the copper bit line comprises a plurality of consecutive copper melt anneals, and the recrystallization of the copper bit line comprises a plurality of cooling periods between the consecutive copper melt anneals. The laser annealing is preferably performed at a power of 0.05 to 3 J / cm 2 The MRAM structure preferably further comprises a metal liner that is immiscible with liquid copper and extends onto the top electrode and the dielectric layer, and further comprises forming a copper bitline directly on the metal liner. Laser annealing the copper bitline preferably comprises annealing at a temperature equal to or lower than 1150° C., with the metal liner remaining solid during the laser annealing.

Claims

1. A method for forming a large-grain copper bitline for an electronic structure, comprising: An MRAM structure is obtained, comprising: Device wafers, including electronic devices; a metallization layer over the device wafer and including a bottom electrode in the metallization layer, the bottom electrode being electrically connected to the electronic device; and vertical pillars having sidewalls above the metallization layer, the vertical pillars each comprising a magnetic tunnel barrier and a top electrode; forming a copper bitline exhibiting a copper line size effect over the top electrode, the copper bitline having a width of forty nanometers or less, an area of ​​three thousand square nanometers or less, and copper grains having a relatively small size relative to the width of the copper bitline; performing laser annealing on the copper bit line to melt the copper bit line; and The copper bit line is recrystallized during cooling after the laser annealing, thereby forming relatively large grains in the copper bit line and reducing the copper line size effect of the copper bit line formed above the top electrode.

2. The method of claim 1 , wherein the relatively large grains formed by recrystallizing the copper bitline are vertically aligned with the vertical pillars and include grain boundaries overlying a plurality of spaces between the vertical pillars, and further wherein the vertical pillars have a pitch of sixty nanometers or greater along the copper bitline. 3 . The method of claim 1 , wherein after recrystallizing the copper bitline, the relatively large grains have an average grain size greater than 0.06 μm, further wherein recrystallizing the copper bitline comprises reducing the copper line size effect by half or more.

4. The method of claim 3, wherein the copper bitline comprises copper at an atomic concentration of at least ninety percent. 5 . The method of claim 4 , wherein the MRAM structure further comprises a dielectric layer between each of the vertical pillars, the relatively large grains comprising grain boundaries extending above the dielectric layer.

6. The method according to claim 5, wherein the laser annealing is performed at a rate of from 0.05 J / cm 2 Up to 3J / cm 2 The laser annealing density is carried out. 7 . The method of claim 6 , wherein the tunnel magnetoresistance of each magnetic tunnel barrier is substantially the same before recrystallizing the copper bit line and after recrystallizing the copper bit line.

8. The method of claim 6, wherein the MRAM structure further comprises a metal liner immiscible in liquid copper, and the metal liner extends over the top electrode and the dielectric layer, and the copper bit line is further formed directly on the metal liner.

9. The method of claim 1, wherein the vertical pillars have a pitch along the copper bit lines of at least sixty nanometers.

10. The method of claim 9, wherein laser annealing the copper bit line comprises a plurality of consecutive copper melt anneals.

11. A magnetoresistive random access memory structure, comprising: a plurality of vertical pillars having sidewalls, each vertical pillar of the plurality of vertical pillars comprising a magnetic tunnel barrier and a top electrode, the plurality of vertical pillars having a pillar pitch of sixty nanometers or greater; a plurality of spaces, each of the plurality of spaces being located between a pair of opposite side walls of adjacent vertical columns; a dielectric layer filling each of the plurality of spaces; and A copper bit line is above and electrically connected to each top electrode, the copper bit line having a line width of forty nanometers or less, grains having a grain size greater than twice the line width and an average grain size of 0.06 microns or greater, the pillar pitch being along the copper bit line. 12 . The magnetoresistive random access memory structure of claim 11 , wherein grains of the copper bit lines are vertically aligned with the vertical pillars, the grains comprising grain boundaries located above the plurality of spaces.

13. The magnetoresistive random access memory structure of claim 11, further comprising a metal liner comprising a material immiscible in liquid copper, the metal liner directly contacting the top electrode and extending above the dielectric layer.

14. The magnetoresistive random access memory structure according to claim 13, wherein the copper bit line has a thickness less than 3000 nm. 2 cross section.

15. The magnetoresistive random access memory structure of claim 13, wherein the vertical pillar comprises one or more MRAM cells, each of the one or more MRAM cells having a 0.01 μm 2 or smaller area.

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