Low formation voltage OxRAM memory cell and related manufacturing method

Abstract

Aspects of the invention relate to an OxRAM resistive memory cell (50) comprising a lower electrode (2), an upper electrode (53) and an active layer (54) extending between the lower electrode and the upper electrode. The active layer comprises a first electrically insulating oxide (EOx) layer, in which conductive filaments can be formed, subsequently broken and reformed several times in succession. The upper electrode comprises a reservoir layer (55) capable of receiving oxygen, the reservoir layer comprising an upper portion (551) made of a metal (M) and a lower portion (552) made of a second oxide (MOy), the second oxide being an oxide of the metal and containing a proportion (y) of oxygen such that the second oxide is conductive. The invention also relates to a method for manufacturing such a memory cell.

Description

Technical Field

[0001] The technical field of the present invention is the technical field of microelectronics, and more specifically the technical field of filamentary type nonvolatile resistive memories.

[0002] The invention relates more particularly to an oxide-based resistive memory cell of the OxRAM type (acronym for “Oxide-based Resistive Random Access Memory”) and to a method for manufacturing such a cell. Background Art

[0003] In recent years, a new type of non-volatile memory has been developed, known as resistive memory, or sometimes ReRAM (short for "resistive random access memory"). This type of memory comprises different memory cells, sometimes called "memory points", each of which stores a piece of binary data. The binary data in question is represented by the resistance level (high or low) of the memory cell under consideration.

[0004] Such a memory cell is usually manufactured by making a stack of several layers, the stack comprising a lower electrode, an upper electrode and an active layer extending between the lower and upper electrodes. The stack in question, initially of considerable lateral dimensions, is etched so as to obtain several memory cells that are different from one another (this etching making it possible to define each memory cell laterally). These are usually the upper electrode and the active layer that are etched so as to define the lateral dimensions of the "active" part of each memory cell (i.e. the part that records the data to be stored).

[0005] In OxRAM memory cells, such as Figure 1 In the cell 1 shown in , the active layer 4 is made of a metal oxide or a semiconductor oxide, EOx, for example, hafnium oxide or silicon oxide. Initially, the active layer 4 is completely electrically insulating. But for each memory cell, a step called "forming" is then carried out. During this step, a conductive filament is formed in the active layer by carrying out a controlled breakdown of this layer. The filament thus formed then extends from one end to the other through the active layer by electrically connecting the lower electrode 2 and the upper electrode 3.

[0006] To carry out this formation step, for example, a voltage may be applied between the lower electrode and the upper electrode of the memory cell under consideration, and the value of this voltage is then gradually increased to a threshold voltage, referred to as the formation voltage U F , exceeding the threshold voltage, the breakdown of the active layer is obtained.

[0007] Once formed, the conductive filament can be destroyed, then reformed, then destroyed again, etc. during successive write cycles (SET), then reset cycles (RESET), i.e., erasure of the memory cell (SET operation when the filament is reformed, and RESET operation when the filament is destroyed again). The threshold voltages (SET voltage and RESET voltage) to be applied to the memory cell to destroy the filament and reform it are typically lower than the formation voltage U required to form the filament the first time. F .

[0008] The mechanism for forming the filaments may require the recombination of oxygen vacancies within the oxide forming the active layer. In addition, in order to facilitate this recombination, a reservoir layer 5 capable of storing oxygen is usually integrated in the upper electrode 3. This reservoir layer, which extends above the active layer 4 against the latter, is most often made of a (unoxidized) metal M, such as titanium, lanthanum or zirconium. This reservoir layer 5 is usually covered with a protective layer 6, for example, made of a nitride MN of the metal in question.

[0009] In practice, it is of interest to etch memory cells with reduced lateral dimensions in order to increase the density of information stored in the memory.

[0010] However, it has been observed in practice that when the cross section of the memory cell is reduced, the forming voltage U that must be applied in order to produce the conductive filaments for the first time increases. F For the range from 1μm 2 To about 100×100nm 2 However, below a size of about a hundred nanometers, when the cross-section of the memory cell decreases (more precisely, when the surface area of ​​the upper electrode decreases), a voltage U F This increase then leads to the formation of a voltage U F The high value of, for example, greater than 5 or 6 volts, is much higher than the SET and RESET voltages of the memory cell which are typically less than 1 or 2 volts.

[0011] In order to carry out the formation operation, the chip receiving the memory must then be equipped with additional electronics specifically dedicated to the formation operation, making it possible to transmit the high voltages (in addition to the control electronics of the memory cells, which make it possible to carry out the SET and RESET operations). These additional electronics then increase the cost of manufacturing the memory, as well as the size it occupies on the electronic chip.

[0012] Therefore, reducing the formation voltage U of such a memory cell F , without increasing the surface occupied by each of these cells would be useful. Summary of the invention

[0013] In this context, the present invention proposes an OxRAM resistive memory cell comprising a specific type of storage layer, due to which the formation voltage U of the cell can be reduced. F , however, the surface occupied by the cell is not increased.

[0014] More specifically, the present invention proposes an OxRAM resistive memory cell, which includes a lower electrode, an upper electrode and an active layer extending between the lower electrode and the upper electrode, the active layer including at least one layer of a first electrically insulating oxide, wherein a conductive filament can be formed, and then the conductive filament is continuously destroyed and reformed several times, the upper electrode includes a reservoir layer capable of accommodating oxygen, at least part of the reservoir layer is made of metal, wherein the reservoir layer includes an upper part made of the metal and a lower part made of a second oxide, the second oxide is an oxide of the metal and contains oxygen in a ratio such that the second oxide is conductive and has a conductivity greater than 100 mhos (Siemens) / meter.

[0015] The inventors have observed that the lower portion of the reservoir layer made of the second oxide conductor makes it possible to significantly reduce the formation voltage U of the memory cell relative to a memory cell having the same outer dimensions but without this portion made of a conductive oxide. F (exist Fig. 9 The discussed reduction in forming voltage is shown in FIG. 1 , by way of example, for a first type of memory cell according to the teachings of the present invention).

[0016] In the case of the voltage U F An explanation of the improvement provided by this particular reservoir layer is presented below, following the mechanism of the high values ​​of .

[0017] Firstly, it can be noted that the "forming" operation is based on a controlled breakdown mechanism of the oxide EOx of the active layer 4. This breakdown is associated with the formation of defects in the active layer, which lead to the formation of a conductive path. However, the formation of this defect is more likely when the cross section of the cell is larger. Stated otherwise, the smaller the cross section of the cell, the fewer positions there are suitable for triggering (or in other words, starting the breakdown in question), and therefore a higher voltage is required to obtain the breakdown.

[0018] This effect is enhanced by lateral etching of the memory cell and is more or less pronounced depending on the layer considered. Figure 1In the cell of the prior art shown, the reservoir layer 5, which is completely made of metal M, is less resistant to etching than the other layers of the memory (made of the nitride MN of said metal, or of the oxide EOx). After etching, the reservoir layer 5 therefore has a cross-section that is smaller than the active layer 4 and smaller than the upper surface of the memory cell. Figure 1 This lateral etching, which is more pronounced for the metal layer 5, is schematically shown in FIG. 1 , and is sometimes referred to as "undercutting" (or "grooving"). For cells with a larger cross-section, the reduction in the cross-section of the reservoir layer 5 due to this differential etching remains low relative to a value. On the other hand, for small-sized memory cells, such as cells with a size of 40 nm, this "undercutting" effect can result in the surface area A of the cross-section of the reservoir layer 5 being reduced to a value of 0.0400 nm. M is the surface area A of the upper surface of the memory cell T A quarter smaller.

[0019] Thus, the potential applied to the upper surface of the active layer 4 in order to obtain the breakdown of this layer is ultimately applied (via the reservoir layer 5) to the active surface A. M On the effective surface A M Than the apparent surface A occupied by the memory cell T This explains the fact that the upper surface of the 2 For memory cells with a surface area of ​​1000 Å or less, particularly high values ​​of the formation voltage are observed.

[0020] The specific structure of the reservoir layer of the memory cell according to the invention makes it possible to at least partially overcome the cross-section reduction described above (ie “undercut”), which makes it possible to reduce the formation voltage of the cell.

[0021] In fact, for metals commonly used as reservoir layers, such as titanium, lanthanum or zirconium, the enthalpy of formation corresponding to the metal-metal bond MM is lower than the enthalpy of formation corresponding to the metal-oxygen bond MO. Moreover, the enthalpy of formation of the metal-oxygen bond MO in question is greater than the enthalpy of formation of the metal-chlorine bond M-Cl (chlorine is often used as plasma etchant during the manufacture of this type of memory).

[0022] In the memory cell according to the invention, the second oxide MOy is therefore a priori more resistant to etching, in particular to halogenated plasma etching, than the metal M itself. And, moreover, it has been observed in practice that the "undercut" of the reservoir layer is lower for the portion made of oxide MOy than for the portion made of metal M.

[0023] Due to its portion made of conductive oxide MOy, this reservoir layer has, after etching, a conductive area under the metal M and the cross section of this area is larger than that obtained with a layer made only of metal M. Therefore, the specific reservoir layer used here makes it possible to achieve both:

[0024] - thanks to its upper part made of said metal, the desired "oxygen reservoir" effect is obtained, and

[0025] - On the upper surface of the active layer, over a surface area A that is larger than the cross section of the upper part made of metal M A given potential is applied to the effective surface of the electrode (due to both the conductive and etching resistant properties of the second oxide Moy).

[0026] The relatively high electrical conductivity of the component made of conductive metal oxide (greater than 100 mho / m) makes it possible to effectively use a large part of the cross-section of this component made of metal oxide (advantageously, a cross-section greater than that of the component made of metal M) to apply the potential in question on the upper surface of the active layer.

[0027] Therefore, the particular reservoir layer used here makes it possible to T , and thus for a given size of memory cell, relative to prior art cells (e.g., as in Figure 1 The unit shown in FIG. 1 ) reduces the voltage U F .

[0028] In addition to the characteristics just mentioned above, the memory cell according to one aspect of the present invention may have one or more of the following optional additional features, taken alone or in any technically permissible combination:

[0029] - the reservoir layer comprises a proportion of oxygen which gradually changes from a lower portion of the reservoir layer to an upper portion thereof;

[0030] - the lower part of the reservoir layer is made of a first sublayer made of said second oxide, and the upper part of the reservoir layer is made of a second sublayer, different from the first sublayer, and made of said metal;

[0031] - the cell has been laterally defined by etching, the cross-section of a lower part of the reservoir layer made of the second oxide being larger, for example at least 20% larger, than the cross-section of an upper part of the reservoir layer made of said metal;

[0032] - the metal is one of the following: titanium, tantalum, gadolinium, lanthanum, aluminum, zirconium, hafnium;

[0033] - the first oxide is an oxide of a chemical element different from said metal;

[0034] - the metal is titanium and the proportion of oxygen in the second oxide is less than 1.7 oxygen atoms per titanium atom;

[0035] - the first oxide is silicon oxide;

[0036] The upper surface of the memory cell has a surface area of ​​less than 1 square micrometer, or even less than 0.1 square micrometer, or even less than 0.01 square micrometer.

[0037] Another aspect of the present invention relates to a method for manufacturing an OxRAM resistive memory cell, comprising the following steps:

[0038] -Deposition of the lower electrode, then

[0039] - depositing an active layer on the lower electrode, the active layer comprising at least one layer made of a first oxide, the first oxide being electrically insulating and being able to serve as a carrier for the formation of conductive filaments passing through said first oxide, the filaments being able to be destroyed and then reformed several times in succession, and then,

[0040] - The upper electrode covering the active layer is manufactured by performing the following steps:

[0041] - manufacturing a reservoir layer capable of receiving oxygen, at least a portion of which is made of metal, and

[0042] - etching the upper electrode in such a way as to laterally delimit the memory cell, the etching step being carried out after the step of manufacturing the reservoir layer,

[0043] - wherein the step of manufacturing the reservoir layer is carried out in such a way that the reservoir layer comprises an upper portion made of said metal and a lower portion made of a second oxide, the second oxide being an oxide of said metal containing a proportion of oxygen such that the second oxide is electrically conductive, having an electrical conductivity greater than 100 mho / meter.

[0044] In addition to the features just mentioned in the preceding paragraph, a memory cell according to an aspect of the invention may have one or more of the following additional features, taken alone or in any technically permissible combination:

[0045] - The step of manufacturing the reservoir layer comprises the following sub-steps:

[0046] - depositing the metal layer on the active layer, then

[0047] - performing an annealing at a temperature and for a period of time such that, after the annealing, the previously deposited layer comprises: said upper portion made of said metal and said lower portion made of a conductive second oxide;

[0048] - The step of manufacturing the reservoir layer comprises the following sub-steps:

[0049] - depositing a first sublayer on the active layer, the first sublayer being made of a second oxide, and then,

[0050] - depositing a second sub-layer on the first sub-layer, the second sub-layer being made of said metal;

[0051] - a sub-step of depositing a first sub-layer by cathode sputtering from a target made of said conductive second oxide;

[0052] - a sub-step of depositing a first sub-layer by cathode sputtering from a target made of said metal, in an atmosphere comprising oxygen, wherein the oxygen partial pressure in said atmosphere is such that the deposited first sub-layer is made of said second oxide, said second oxide having said proportion of oxygen;

[0053] - the etching step is a halogenated plasma etch;

[0054] - The plasma is a chlorine and / or hydrogen bromide plasma.

[0055] The invention and its various applications will be better understood when the following description is read and the accompanying drawings are examined. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] These figures are shown for informational purposes and in no way limit the invention.

[0057] Figure 1 is a schematic illustration of a prior art OxRAM resistive memory cell viewed from the side.

[0058] Figure 2 Schematically illustrated are the different steps of a first method for manufacturing an OxRAM resistive memory cell according to the teachings of the present invention.

[0059] Figure 3 Schematically shows the Figure 2 The method is performed according to the teachings of the present invention at an intermediate stage of the fabrication of a first type OxRAM resistive memory cell.

[0060] Figure 4 Schematically shows Figure 3 A memory cell at a higher stage of its fabrication.

[0061] Figure 5 Schematic diagram showing the etching process Figure 3 of memory cells.

[0062] Figure 6 Schematically shows Figure 5 An alternative to memory cells.

[0063] Figure 7 Different steps of a second method for manufacturing an OxRAM resistive memory cell according to the teachings of the present invention are schematically shown.

[0064] Figure 8 Schematically showing the Figure 7 The method is performed according to the teachings of the present invention for a second type of OxRAM resistive memory cell.

[0065] Fig. 9 The prior art memory cell (such as Figure 1 Memory cell according to the teachings of the present invention) and memory cell according to the teachings of the present invention (according to Figure 2 The value of the forming voltage obtained by the method of (obtaining).

[0066] Fig.10 The prior art memory cell (eg, Figure 1 The memory cell has a low resistance value and a high resistance value.

[0067] Fig.11 Shown are low and high resistance values ​​of a memory cell according to the teachings of the present invention obtained during several consecutive write and erase cycles of the memory cell. DETAILED DESCRIPTION

[0068] As already mentioned, the present invention relates to an OxRAM resistive memory cell comprising a lower electrode 2, an upper electrode 53; 63; 83 and an active layer 54; 64; 84 extending between the lower electrode and the upper electrode (see attached Figure 5 , 6 and 8).

[0069] The active layer 54; 64; 84 comprises at least one layer of an electrically insulating first oxide EOx. This first oxide EOx is a sufficient carrier for forming a conductive filament that passes through the active layer from one side to the other to electrically connect the lower electrode to the upper electrode and can be destroyed during successive write and erase (RESET), i.e., reset cycles of the memory and then successively reformed several times. As explained in the preamble, such a conductive filament is first produced during a controlled electrical breakdown of the active layer ("formation" operation).

[0070] The first oxide EOx mentioned above is a stoichiometric or substoichiometric metal oxide or semiconductor oxide. This is an oxide of the chemical element E, so it can be a metal or a semiconductor, and for example, can be selected from: hafnium Hf, zirconium Zr, titanium Ti, tantalum Ta, niobium Nb, vanadium V, tungsten W, molybdenum Mo, aluminum Al, gadolinium Gd, or silicon Si.

[0071] The active layer can be made of the same insulating layer of oxide EOx ( Figure 8 The case of the active layer 84).

[0072] The lower portion of the active layer may be made of a first oxide EOx, and the upper portion may be made of an oxide EOx' of the same chemical element E, but the oxide EOx' has a lower oxygen fraction x' ( Figure 5 and 6 )

[0073] Alternatively, the active layer can also be formed by a stack of several insulating sublayers made of oxides of different elements selected from the list mentioned above. For example, the stack can include a hafnium oxide HfOx sublayer and an aluminum oxide Al2Oz sublayer on top. For this alternative, then, one of the sublayers of the stack in question is made of a first oxide EOx.

[0074] The formation mechanism of the conductive filaments in the oxide EOx layer generally requires the recombination of oxygen vacancies within the oxide. In order to facilitate this recombination, the upper electrode 53; 63; 83 includes a reservoir layer 55; 65; 85 (sometimes called a "getter") capable of accepting oxygen. At least a portion of this reservoir layer 55; 65; 85 is made of a (unoxidized or minimally oxidized) metal M, which may be titanium Ti, lanthanum, aluminum, zirconium, gadolinium, tantalum or hafnium. Preferably, the metal M is titanium Ti, which is particularly suitable for realizing such a reservoir layer.

[0075] The reservoir layer 55; 65; 85 extends over the active layer 54; 64; 84 and covers the active layer. Here, the reservoir layer extends directly on the active layer 54; 64; 84, against the active layer, without an intermediate layer between them (which facilitates oxygen exchange between these two layers). Alternatively, one or more intermediate layers that are at least partially permeable to oxygen may be inserted between the active layer and the reservoir layer.

[0076] The upper electrode 53 ; 63 ; 83 as here may comprise one or more additional layers in addition to the reservoir layer 55 ; 65 ; 85 .

[0077] Here, the upper electrode 53; 63; 83 comprises an upper layer 6 which covers the reservoir layer 55; 65; 85 (see Figure 5 , 6, 8). The upper layer 6 acts as a protective layer (in particular to prevent total oxidation of the reservoir layer) and as a contact layer making it possible to electrically connect the memory cell to its control and readout electronics. The upper layer 6 is more resistant to etching than the portion of the reservoir layer 55; 65; 85 made of metal M. Here, the upper layer 6 is made of a nitride MN of the above-mentioned metal M (thus, for example, it can be made of titanium nitride TiN).

[0078] The lower electrode 2 deposited on a substrate (not shown) comprises a metal layer that is neutral with respect to oxygen, for example a layer made of a nitride MN of a metal M, or a layer made of a nitride of another metal (typically made of titanium nitride TiN, of tungsten W or of tantalum nitride TaN).

[0079] Here, the individual layers of the memory cell 50; 60; 80 are parallel to each other (and to the substrate in question). Together they form a stack extending along an axis z perpendicular to the plane of the layers. Thus, the individual layers of the memory cell 50; 60; 80 occupy different positions (different coordinates) along the axis z.

[0080] It is noteworthy that the above-mentioned reservoir layer 55; 65; 85 comprises an upper portion 551; 651; 851 made of metal M and a lower portion 552; 652; 852 made of a second oxide MOy. The second oxide MOy is an oxide of the metal M and contains a proportion y of oxygen, making it conductive.

[0081] As explained in the section entitled "Summary of the Invention", the second oxide MOy is both electrically conductive and more etch-resistant than the metal M forming the upper portion of the reservoir layer 55; 65; 85.

[0082] Once the memory cell 50; 60; 80 has been laterally defined by etching, the lower portion 552; 652; 852 of the reservoir layer 55; 65; 85 (made of the second oxide MOy) is removed due to its better resistance to lateral etching (see Figure 5 , 6 , 8), whose cross-section is therefore larger than the cross-section of the upper part 551; 651; 851 of the reservoir layer (made of metal M).

[0083] This lower portion 552; 652; 852 of the reservoir layer 55; 65; 85 is made of the second oxide MOy, thus making it possible:

[0084] - for the reservoir layer, maintaining its oxygen storage function (particularly due to its upper part being made of metal M),

[0085] - While still benefiting from a conductive zone above the active layer 54; 64; 84 having a larger cross-section than the upper portion made of metal M (due to the conductive and etch-resistant properties of the second oxide MOy).

[0086] As explained in the "Summary of the Invention" section, the extended nature of the conductive region 552; 652; 852 advantageously makes it possible to reduce the forming voltage U to be applied to the memory cell. F The value of , in order to produce a conductive filament 54; 64; 84 through the active layer 54. The forming voltage U of the memory cell 50; 60; 80 F In particular, it is lower than the forming voltage U of the memory cell which will have the same cross-section of the upper surface. F , but where the reservoir layer will be made only of metal (less etch-resistant than oxide MOy).

[0087] This region 552; 652; 852 is realized from a metal oxide, which is an oxide of the same metal as the metal M forming the upper part 551; 651; 851 of the reservoir layer, which region is electrically conductive and resistant to etching, allowing convenient fabrication of the memory cell.

[0088] In practice, after etching, when the memory cell 50; 60; 80 has a small cross-section (typically less than 10 -2 square micrometers), the surface area A of the cross section of the lower portion 552; 652; 852 (made of oxide MOy) of the reservoir layer 55; 65; 85 OX，5 ; A OX，6 ; A OX，8 The surface area A of the cross section of the upper portion 551; 651; 851 of the reservoir layer made of metal M is M Moreover, even when the memory cell 50; 60; 80 has a diameter of about forty nanometers (the diameter of its upper layer 6), the surface area A of the lower portion made of oxide MOy is OX，5 ; A OX，6 ; A OX，8 It can be the surface area A of its upper part (made of metal M) M The cross sections mentioned above are cross sections of the memory cell according to a cutting plane parallel to the lower electrode 2, and therefore perpendicular to the axis z introduced previously. These correspond to a "complete" cross section of the memory cell (at the considered cutting plane) defined by its external lateral surfaces.

[0089] Note that the second oxide MOy forming the lower portion of the reservoir layer 55; 65; 85 is actually different from the first oxide EOx of the active layer 54; 64; 84.

[0090] In fact, the conductivity σ2 of the second oxide MOy (which is conductive) is higher here, and even much higher than the conductivity σ1 of the first oxide EOx (which is electrically insulating, except at the conductive filaments mentioned above). For example, the conductivity σ2 of the second oxide MOy is greater than or equal to 100 mho / meter. And, in practice, it is usually at least a thousand times, or even a million times, greater than σ1 of the first oxide EOx. Moreover, the metal M of the reservoir layer (which can store oxygen from the layer made of the first oxide EOx) is different here from the element E present in oxidized form (EOx) in the active layer 54; 64; 84. By way of example, the metal M can be titanium Ti, and the active layer is then implemented with silicon oxide SiOx.

[0091] Apart from this, the portion of the reservoir layer made of the second oxide MOy has a composition which is also very different from the composition of the upper portion of the reservoir layer made of the metal M.

[0092] In fact, even if this upper part 551; 651; 851 may contain small amounts of oxygen, the relative difference between the amount of oxygen y present in the second oxide MOy on the one hand and the amount of oxygen ε possibly present in said upper part on the other hand is here greater than 50%, even greater than 70%. The amount (y-ε) / (y+ε) furthermore formulated is here greater than 0.5, even greater than 0.7, y being the number of oxygen atoms per atom of metal M in the second oxide MOy and ε being the number of oxygen atoms per atom of metal M in the upper part made of metal M (i.e., more precisely, in the upper part of the reservoir layer, made predominantly of said metal M which is not oxidized or is only slightly oxidized).

[0093] For example, when the metal M is titanium, the proportion y of oxygen in the second oxide MOy can be comprised between 1 and 1.7, which makes it possible to obtain a conductivity σ2 greater than 100 mhos / meter, wherein the amount ε of oxygen that may be present in the upper part made of metal is less than 0.5 or even less than 0.2.

[0094] In the figures, the second oxide is marked with the reference symbol MOy. However, its chemical (empirical) formula may be MOy (for example, in the case of titanium oxide TiOy, hafnium oxide HfOy, or zirconium oxide ZrOy) and M2Oz (where z=2y) (for example, in the case of aluminum oxide Al2O z＜3 situation).

[0095] At least two different techniques can be considered for implementing the above-mentioned specific reservoir layer 55; 65; 85. The first technique is based on a specific annealing performed before etching the memory cell. The second technique is based on the successive deposition of several different sub-layers (e.g. a first sub-layer and then a second sub-layer) containing different proportions of oxygen to each other.

[0096] In a first step, a first manufacturing method corresponding to a first technique (by annealing) is presented below, as well as an embodiment of a memory cell obtained in this way ( Figures 2 to 6 ). Then, see Figure 7 and 8 A second manufacturing method corresponding to the second technique (by continuous deposition) is presented. Finally, see Fig. 9 , presenting the measurement results as well as the results of the durability test ( Fig.10 and 11 ), which measurement shows a decrease in the resulting forming voltage.

[0097] like Figure 2 As shown, the first manufacturing method includes the following steps:

[0098] - Step St1: Deposition of the lower electrode 2, then

[0099] - Step St2: depositing an active layer on the lower electrode 2, then

[0100] - Step St3: manufacturing the upper electrode 53; 63, which covers the active layer, and then

[0101] - Step St4: Formation of conductive filaments in the active layer by controlled electrical breakdown of the active layer (forming step).

[0102] The manufacturing step St3 of the upper electrode 53; 63 is performed more accurately by performing the following steps:

[0103] - Step St31 : manufacturing a reservoir layer 55 ; 65 (intended to be able to receive oxygen coming from the active layer) by means of the annealing technique mentioned above;

[0104] - Step St32: Deposition of a protective layer 6 which covers the reservoir layer 55; 65; and

[0105] - Step St33: etching the upper electrode 53; 63 and the active layer 54; 64 in such a way as to laterally delimit the memory cells 50; 60.

[0106] In step St31, in order to manufacture the reservoir layer 55; 65, it is provided to perform the following sub-steps:

[0107] -St310: depositing a layer 35 of the metal M on the active layer, then

[0108] -St311: The above-mentioned annealing is performed.

[0109] As in Figure 2 As can be seen in the figure, after depositing the layer 35 made of metal M, and even after depositing the upper protective layer 6 made of nitride MN, an annealing operation is performed here (St311). However, alternatively, after depositing the layer 35 made of metal M, but before depositing the upper protective layer, an annealing operation may be performed (in the framework of this alternative, steps St310, St311 and St32 will then be performed in the following order: St310, then St311 and then St32). However, in the framework of this alternative, annealing must be performed without exposure to the air of the memory, and until the upper protective layer is deposited (then, annealing is performed in an oxygen-free atmosphere or in a vacuum).

[0110] Here, a layer 35 made of metal M is deposited directly on the active layer, against it (without intermediate layers). Figure 3 The stacking is schematically shown before annealing and before etching (ie, immediately after sub-step St32).

[0111] During annealing, the high temperature (or temperatures) applied to the memory cell allows the diffusion of oxygen from the active layer to the layer 35 made of metal M (initially free of oxygen).

[0112] After annealing, instead of the initially deposited layer 35 made of metal M, a layer 45 comprising oxide MOy in the lower part and metal M in the upper part is then obtained. Figure 4 The stack of layers of a memory cell is schematically shown after annealing and before etching (for a relatively short annealing duration, the portion of the layer 45 situated lowest among the layers remains conductive).

[0113] The reservoir layer 55; 65 obtained according to this annealing technique has a proportion of oxygen that gradually increases from the bottom to the top of the layer (see Figure 5 and Figure 6 ). Within the reservoir layer, the concentration of oxygen thus increases gradually and continuously with the coordinate z of the point under consideration (eg the concentration of oxygen may have a non-zero gradient over the entire thickness of the reservoir layer).

[0114] The duration and the temperature(s) for the annealing are selected here in such a way that the upper part of the layer 35 is not oxidized, or at least in such a way that it is only very slightly oxidized (for this reason, the annealing duration is limited to values ​​that are not too high). Thus, after the annealing, the proportion of oxygen in the part of the layer 45 that is situated at the top of the layer is preferably less than 0.5, or even less than 0.2 oxygen atoms per atom of metal M.

[0115] Select the duration and (one or more) temperatures for annealing in such a way that: in the lower part of the layer 45 made of the second oxide MOy, the proportion y of oxygen is at least greater than 1 (in this lower part, the metal M is at least partially oxidized – to increase the etch resistance of this part), while remaining low enough so that the second oxide MOy is conductive.

[0116] For example, for a storage layer having a thickness included between 1 nanometer and 15 nanometers, an annealing temperature included between 220 degrees Celsius and 280 degrees Celsius (preferably, 260 degrees Celsius) and an annealing duration from 1 minute to 10 minutes (preferably, 3 minutes) make it possible to obtain the desired structure for the storage layer, where the upper part is made of the metal M and the lower part is made of the second oxide MOy.

[0117] After the annealing sub-step St311, the memory cell is etched to laterally delimit the upper electrodes 53; 63 and the active layers 54; 64. This etching is a halogenated plasma etching. Here, more precisely, this is a chlorine Cl2 and hydrogen bromide HBr plasma etching.

[0118] This type of etching is sufficiently effective for etching the upper layer of the electrode made of the nitride MN. Since the formation enthalpy of the metal-metal bond M-M is less than the formation enthalpy corresponding to the metal-oxygen bond M-O, the part of the storage layer 55; 65 made of the second oxide MOy is etched less laterally than its upper part made of the metal M (see Figure 5 and Figure 6 ).

[0119] Furthermore, for most of the metals in the list from which the metal M can be selected (including the list of the following elements as already indicated: Ti, La, Al, Zr, Hf, Ta, Gd), the formation enthalpies corresponding to the metal-metal M-M, metal-nitrogen M-N, metal-chlorine M-Cl, and metal-oxygen M-O bonds follow the following order: M-M < M-N < M-Cl < M-O, which explains the good etch resistance of the lower part 552; 652 of the storage layer made of the second oxide MOy.

[0120] In practice, during the etching step, several memory cells are etched simultaneously. During this etching, it is possible to provide for not etching the lower electrode 2 so that it remains common to the different memory cells of the memory. However, during the same etching step, or during a previous step of constructing the lower electrode 2 ( Figure 2 not shown in), it is also possible to etch the lower electrode 2, for example, between the deposition of the lower electrode 2 (step St1) and the deposition of the active layer (step St2).

[0121] After the etching step St33 , the control electronics of the different memory cells are usually manufactured (this step is not shown in the figure). These electronics make it possible in particular to carry out the shaping operation St4 .

[0122] During the step of forming St4, the conductive filaments mentioned above are formed for the first time in the active layer 54; 64. To this end, a voltage is applied between the lower electrode 2 of the memory cell and the upper layer 6. The value of this voltage is gradually increased until it becomes greater than the formation voltage U for forming the conductive filaments in the active layer. F . Alternatively, the "forming" step can be carried out by injecting a controlled current into one of the electrodes of the memory cell, wherein the current value is gradually increased until the conductive filament is formed. More generally, the "forming" step can be carried out by controlling the voltage and / or the current applied to the memory cell according to a predetermined control cycle. But whatever the selected control mode (with current, with voltage or mixed), during this step, the voltage between the lower electrode 2 and the upper layer 6 of the memory cell is made higher than the forming voltage U F .

[0123] Figure 5 A first embodiment of a memory cell 50 obtained by this first method is shown after etching.

[0124] For this first embodiment, the annealing is relatively short, so that the portion of the reservoir layer 55 located at the bottom in the reservoir layer 55 remains relatively little oxidized and is therefore conductive. The portion of the reservoir layer made of the second oxide conductor MOy designated above as "the lower portion 552 of the reservoir layer" then corresponds to the portion of the reservoir layer 55 located at the bottom of the reservoir layer. Therefore, the lower portion 552 of the reservoir layer occupies an area extending directly against the upper surface of the active layer 54 for a certain thickness, which represents a part of the total thickness of the reservoir layer. This area extends over the entire cross section of the reservoir layer, that is, to its outer lateral surface. Even if it is not separated from the rest of the reservoir layer by a steep boundary, the lower portion 552 made of the conductive oxide MOy thus forms a layer parallel to the lower electrode 2.

[0125] The upper portion 551 of the reservoir layer occupies the topmost region of the reservoir layer 55 and it extends over a thickness representing a fraction of the total thickness of the reservoir layer. By forming a layer parallel to the lower electrode 2, this region also extends over the entire cross section of the memory cell (to the outer lateral surfaces of the memory cell).

[0126] The annealing that makes it possible to obtain the lower portion 552 made of the conductive oxide MOy in the reservoir layer also has the effect of slightly modifying the active layer 54. Due to the annealing, a difference in oxygen concentration occurs between the bottom and the top of the active layer 54. Thus, the active layer 54 contains a lower proportion x' of oxygen in its upper part than in its lower part. However, the lower part of the active layer 54 made of the first oxide EOx remains completely electrically insulating (except at the conductive filaments mentioned above).

[0127] After etching, the cross section of the upper layer 6 of the memory cell 50 (made of nitride MN) has a surface area A T (This is the surface area of ​​the upper surface of this layer.) The cross section of the upper portion 551 of the less etch-resistant reservoir layer 55 has a surface area A M , the surface area A M Significantly smaller than the surface area A of the upper layer T (labeled as "undercut" effect). The surface area A of the lower portion 552 of the reservoir layer that is more resistant to lateral etching ox，5 The cross-sectional area A of the upper portion 551 of the reservoir layer made of metal M is M The cross section of the lower portion 552 has a larger surface area A. ox，5 The surface area of ​​the cross section of the active layer 54 is close to (or even equal to) that of the cross section of the active layer 54. As explained in detail above, this makes it possible to significantly reduce the forming voltage U relative to the case of a reservoir layer that would be made entirely of metal M. F The value of .

[0128] As for the lower electrode 2, whether etched or not, its cross section is more extended than that of the active layer 54 and more extended than that of the upper layer 6. The lateral dimensions of the upper electrode and the active layer thus define the lateral extension of the "active" part of the memory cell.

[0129] Figure 6 A second embodiment of a memory cell 60 obtained by the first method described above after etching is shown. The etching duration of this second embodiment is greater than Figure 5 The etching duration of the first embodiment.

[0130] Due to this more pronounced annealing duration, the portion of the reservoir layer 65 which is situated lowest among the layers and which abuts against the active layer 64 is then electrically insulating.

[0131] But starting from a certain height, the material forming the reservoir layer becomes conductive as the oxygen concentration gradually decreases from the bottom to the top of the reservoir layer 65. In other aspects, starting from this height, the oxygen concentration is low enough to make the material correspond to a conductive second oxide MOy.

[0132] For this second embodiment, the reservoir layer 65 thus comprises:

[0133] - an insulating portion at the very bottom made of a third oxide MOy′, which is an oxide of the metal M having an oxygen proportion y′, such that the third oxide is electrically insulating,

[0134] - at the very top, the upper part 651 is made of metal M, and

[0135] - Between the insulating part and the upper part 651 , the lower part 652 is made of a conductive second oxide MOy.

[0136] When the metal M is titanium, the third oxide may have the formula TiO2, or more generally TiO y’>1,7 .

[0137] exist Figure 6 In FIG. 6 , the transition between the insulating portion and the conductive portion of the reservoir layer 65 is schematically represented by a line with reference sign T. For example, the transition may correspond to a passage from a conductivity of less than 100 mhos / meter to a conductivity of more than 100 mhos / meter.

[0138] In this embodiment, it can be seen that the portion of the reservoir layer 65 designated as the "lower portion of the reservoir layer" is necessarily located below the upper portion made of metal, but not necessarily at the very bottom of the reservoir layer. Here, the lower portion 652 of the reservoir layer (made of the conductor oxide MOy) occupies more precisely the area located just above the transition T between the insulating portion and the conductive portion.

[0139] In any case, if Figure 5 In the memory cell 50 , the lower portion 652 of the reservoir layer made of the second oxide MOy occupies an area extending over the entire cross-section of the reservoir layer (ie, to its outer lateral surfaces) and over a thickness representing a portion of the total thickness of the reservoir layer.

[0140] After etching, the cross section of the upper layer 6 of the memory cell 60 (made of nitride MN) again has a surface area A T The cross section of the less etch-resistant upper portion 651 of the reservoir layer has a surface area A M , the surface area A M Significantly smaller than the surface area A of the upper layer T (labeled "undercut"). Also, the lower portion 652 of the reservoir layer that is more resistant to lateral etching also has a surface area A ox，6 The cross section, the surface area A ox，6 The surface area A of the cross section of the upper portion 651 made of metal M is MBigger.

[0141] Therefore, despite the formation of the isolation portion at the bottom of the reservoir layer 65 above the active layer 64, even a conductive region is thus obtained whose surface area A is 1.33mm. ox，6 is larger than the portion made of metal 651, which makes it possible to reduce the forming voltage U F value (because above the active layer the corresponding potential is applied over a larger surface area than a reservoir layer made entirely of metal M).

[0142] Regarding the lower electrode 2, similarly Figure 5 The memory cell has a cross section that is more extended than the cross section of the active layer 54 and than the cross section of the upper layer 6.

[0143] Comparison of the first and second embodiments of the memory cells 50, 60 shows that a longer or shorter annealing duration can be chosen with a certain degree of freedom as long as the top of the reservoir layer (essentially made of metal M) remains little oxidized and the bottom of the layer is at least partially oxidized (e.g., having at least one oxygen atom per metal M atom).

[0144] The annealing duration and temperature that allows the reservoir layer 55 or 65 described above to be obtained can be determined by performing tests for several different durations, for example, until the desired reduced forming voltage is obtained (see Fig. 9 During these tests, it is possible to probe the structure of the reservoir layer (for example by making cross-sections of the “EdX” type, ie by “Energy Dispersive X-ray” type characterization methods) in order to test its chemical composition.

[0145] It should be noted again that, before the etching step St33 of the memory cell, a sub-step St311 of annealing is performed, so that the lower portion 552; 652 of the reservoir layer already acquires a good etch resistance before etching the cell.

[0146] In addition to the steps described above, this first manufacturing method may include additional steps, such as steps of depositing additional layers ( Figure 5 and 6 not shown).

[0147] exist Figure 7 A second method for manufacturing a memory cell 80 according to the invention is schematically shown in . As already indicated, during this second method, the reservoir layer 85 is realized by successive deposition of different sub-layers which differ from each other and contain different proportions of oxygen.

[0148] The second method comprises the following steps:

[0149] - Step St1: Deposition of the lower electrode 2, then

[0150] - Step St2: depositing an active layer 84 on the lower electrode 2, where the active layer is entirely made of the first oxide EOx described above, and then

[0151] - Step St3': manufacturing the upper electrode 83, which covers the active layer 84, and then

[0152] - Step St4: Formation of conductive filaments in the active layer 84 by controlled electrical breakdown of the active layer (forming step).

[0153] Here, steps St1 , St2 and St4 are identical, or at least substantially identical, to steps St1 , St2 and St4 of the first method.

[0154] Furthermore, the step St3' of manufacturing the upper electrode 83 further includes the following steps:

[0155] - Step St31 ′: manufacturing a reservoir layer 85 intended to be able to receive oxygen coming from the active layer;

[0156] - Step St32: depositing a protective layer 6 which covers the reservoir layer 55; 85; and

[0157] - Step St33 : etching the upper electrode 83 and the active layer 84 in such a way as to laterally delimit the memory cell 80 .

[0158] However, step St31 ′ of manufacturing the reservoir layer 85 actually differs from step St31 of the first method, based on the successive deposition of different sub-layers (and not on annealing with oxygen diffusion).

[0159] Here, step St31' more precisely includes the following sub-steps:

[0160] - St310': depositing a first sub-layer, which forms the lower portion 852 of the reservoir layer 85, and then

[0161] St 311 ′: depositing a second sub-layer which covers the first sub-layer 852 and forms the upper portion 851 of the reservoir layer 85 .

[0162] The first sublayer 852 is made of the second oxide MOy. For example, it is deposited by cathode sputtering. This cathode sputtering can be performed from a target itself made of the second oxide MOy. Cathode sputtering can be performed from a target made of metal M, but in an atmosphere containing oxygen. In the latter case, in the chamber where the deposition is performed, the oxygen partial pressure in the atmosphere in question is such that the deposited first sublayer 852 is effectively made of the second oxide MOy having the desired oxygen proportion y (i.e., such that the second oxide MOy is conductive).

[0163] Here again, after etching, the cross-section of the lower portion 852 of the reservoir layer 85 has a surface area A ox，8 , the surface area A ox，8 Greater than the surface area A of the cross section of the upper portion 851 made of metal M M (See Figure 8 ).

[0164] The second manufacturing method may also include additional steps in addition to the steps described above, such as a step of depositing an additional layer ( Figure 8 ), or a step of constructing the lower electrode 2, for example, is performed between the deposition of the lower electrode 2 (step St1) and the deposition of the active layer (step St2).

[0165] Fig. 9 The obtained forming voltage U F Values:

[0166] - For a memory cell whose reservoir layer is made of metal M only (value U 40 , U 80 and U 120 ),like Figure 1 The memory cell 1 of the prior art is shown, and

[0167] - For the memory cell according to the invention, the lower part of the reservoir layer is made of a conductive second oxide MOy (value U' 40 , U' 80 and U' 120 ) is made.

[0168] Here, Fig. 9 The voltage U F Different values ​​of correspond to memory cells in which the metal M is titanium Ti and in which the first oxide EOx of the active layer is silicon oxide SiO 2. These values ​​correspond to memory cells of different sizes, the upper surface of the cell having diameters of approximately 40 nanometers, 80 nanometers and 120 nanometers, respectively.

[0169] Value U' 40 , U' 80 and U' 120 is directed to a memory cell according to the present invention (such as Figure 5 or Figure 6 The memory cell) obtains the formation voltage U F , by annealing with the aid of the first manufacturing method described above. It should be recalled that the annealing in question is carried out before etching the cells, but after depositing the layer 35 made of metal M, which is intended to become the reservoir layer 55; 65 (annealing is carried out after depositing the layer 35 in order to allow the formation of the conductive oxide MOy in this layer). Value U'40 , U' 80 and U' 120 Corresponding to diameters of 40 nm, 80 nm and 120 nm, respectively, of the upper surface of the cell.

[0170] About Value U" 40 ,U” 80 and U" 120 , these values ​​are Figure 1 The voltage U obtained for the memory cell is obtained in the case of F but with annealing, which is done before depositing the reservoir layer 5 made of metal M. Value U" 40 ,U” 80 and U" 120 This also corresponds to diameters of 40 nm, 80 nm and 120 nm, respectively, of the upper surface of the cell.

[0171] Except for the differences noted above (which relate to the presence or absence of annealing), the Fig. 9 Different memory cells forming voltage values ​​are given in FIG.

[0172] Fig. 9 The embodiment shows the formation voltage U obtained with the reservoir layer F The value of U' 40 , U' 80 and U' 120 Compared with the value U obtained with a conventional reservoir layer made of metal M alone 40 , U 80 and U 120 Smaller, the lower part of the reservoir layer is made of the second oxide conductor MOy.

[0173] For example, for a memory cell having a top surface with a diameter of about 40 nanometers:

[0174] - having a reservoir layer made only of metal M ( Figure 1 The value of the voltage formed by the memory cell) is U 40 is about 4.8 volts,

[0175] - And for the memory cell implemented according to the first method ( Figure 5 or Figure 6 The value of the voltage formed by the memory cell) is U' 40 Only 2 volts.

[0176] Note that the observed drop in the forming voltage due to the annealing cannot be explained solely by the modification of the active layer 54; 64. In fact, when the annealing is carried out before the deposition of the layer 35 made of metal M (and, therefore, when it affects only the active layer and not the reservoir layer), a value of the forming voltage U" is obtained.40 ,U” 80 and U" 120 , these values ​​are of course lower than those without annealing, but remain higher than those obtained when annealing is carried out after deposition of the layer 35 made of metal M.

[0177] For a memory cell whose upper surface has a diameter of about 40 nanometers, for example, when annealing is carried out before depositing the layer 35 made of metal, a value U″ of the voltage is formed 40 is about 3.7 V, whereas when annealing is carried out after the deposition of the layer 35 made of metal M (the layer that ultimately forms the reservoir layer), a value U' of only 2 V is obtained 40 .

[0178] Fig.10 and 11 The memory cells of the prior art are shown separately. Figure 1 The memory cell ( Fig.10 ) and according to Figure 2 The memory unit implemented by the method (such as Figure 5 The memory cell 50 or Figure 6 The results of the durability test performed on the memory cell 60).

[0179] Each of these figures shows the low resistance R of the considered memory cell during ten thousand consecutive write and reset cycles of the memory cell. L and the value of the high resistance RH.

[0180] The high resistance R H It is the resistance thereof measured between the lower electrode 2 and the upper layer 6 of the upper electrode when the conductive filament passing through the active layer is broken (ie after a reset step - RESET step - of the memory cell).

[0181] The low resistance R of the memory cell L It is the resistance thereof measured between the lower electrode and the upper layer of the upper electrode when the conductive filament has been reformed (ie after the writing step - SET step - of the memory cell).

[0182] for Figure 1 The memory cell with low resistance R L The value of remains stable during successive write and reset cycles, approximately 3 kOhm (see Fig.10 ). Regarding the high resistance R H values, which gradually increase during the write and reset cycles, starting from about 6 kOhm, and then stabilize at about 40 kOhm after about 1000 cycles.

[0183] for Figure 5 (or 6) memory cell, low resistance RL The value of also remains stable during successive write and reset cycles, approximately 5 kOhm (see Fig.11 ). High resistance R H The value of is equal to about 20 kiloohms and remains stable also during successive write and reset cycles. Thus, a ratio R between the high resistance and the low resistance of about 4 is obtained. H / R L , this ratio is quite high, and this ratio remains very stable during these multiple write and reset cycles. H With low resistance R L The significant and stable difference obtained between φ and φ facilitates the reading of the memory cell proposed herein and increases the reliability of this reading.

Claims

1. An OxRAM resistive memory cell (50; 60; 80) comprising a lower electrode (2), an upper electrode (53; 63; 83) and an active layer (54; 64; 84) extending between the lower electrode (2) and the upper electrode (53; 63; 83), - the active layer (54; 64; 84) comprises at least one layer of a first electrically insulating oxide (EOx), wherein Conductive filaments can form, then break and reform several times in succession, - the upper electrode (53; 63; 83) comprises a reservoir layer (55; 65; 85) capable of receiving oxygen, at least a portion of the reservoir layer (55; 65; 85) being made of metal (M), - characterised in that the reservoir layer (55; 65; 85) comprises an upper part (551; 651; 851) made of the metal (M) and a lower part (552; 652; 852) made of a second oxide (MOy), the second oxide (MOy) being an oxide of the metal (M) and containing a proportion (y) of oxygen such that the second oxide is electrically conductive, having an electrical conductivity greater than 100 mho / m; The OxRAM resistive memory cell has been laterally defined by etching, wherein the cross section (AO) of the lower portion (552; 652; 852) of the reservoir layer (55; 65; 85) made of the second oxide X，5 AO X，6 AO X，8 ) than the cross-section (A) of the upper portion (551; 651; 851) of the reservoir layer made of the metal (M) M )big.

2. The memory unit (50; 60) according to claim 1, wherein: The reservoir layer (55; 65) includes a proportion of oxygen that gradually changes from a lower portion (552; 652) of the reservoir layer to an upper portion (551; 651) thereof.

3. The memory unit (80) of claim 1, wherein: - the lower part of the reservoir layer (85) is a first sublayer (852) made of a second oxide (MOy), and wherein, - The upper part of the reservoir layer (85) is a second sub-layer (851), which is different from the first sub-layer (852) and is made of said metal (M).

4. The memory unit (50; 60; 80) according to claim 1, wherein: The metal (M) is one of the following metals: titanium, lanthanum, aluminum, zirconium, hafnium, gadolinium, and tantalum.

5. The memory unit (50; 60; 80) according to claim 1, wherein: The first electrically insulating oxide (EOx) is an oxide of a chemical element (E) different from the metal (M).

6. The memory unit (50; 60; 80) according to claim 1, wherein: The metal (M) is titanium, and wherein the proportion (y) of oxygen in the second oxide (MOy) is less than 1.7 oxygen atoms per titanium atom.

7. The memory unit (50; 60; 80) according to claim 1, wherein: The first electrically insulating oxide (EOx) is silicon oxide.

8. A method for manufacturing an OxRAM resistive memory cell (50; 60; 80), comprising the following steps: - (St1) depositing the lower electrode (2), then - (St2) depositing an active layer (54; 64; 84) on the lower electrode (2), the active layer comprising at least one layer made of a first electrically insulating oxide (EOx), the first oxide being electrically insulating and being able to serve as a carrier for the formation of conductive filaments passing through said first oxide, the filaments being able to be destroyed and then successively reformed again several times, and then -(St3; St3') The upper electrode (53; 63; 83) covering the active layer is manufactured by performing the following steps: o (St31; St31'), manufacturing a reservoir layer (55; 65; 85) capable of receiving oxygen, at least a portion of the reservoir layer being made of metal (M), and o (St33) etching the upper electrode (53; 63; 83) in such a way as to laterally delimit the memory cell, the etching step (St33) being carried out after the step of manufacturing the reservoir layer (St31; St31'), a step (St31; St31') of manufacturing a reservoir layer (55; 65; 85) in such a way that the reservoir layer comprises an upper portion (551; 651; 851) made of said metal (M) and a lower portion (552; 652; 852) made of a second oxide (MOy), the second oxide (MOy) being an oxide of said metal (M) containing a proportion (y) of oxygen such that the second oxide (MOy) is electrically conductive and has an electrical conductivity greater than 100 mho / m; The method comprises the step of laterally defining an OxRAM resistive memory cell by etching, wherein a cross section (AO) of a lower portion (552; 652; 852) of a reservoir layer (55; 65; 85) made of a second oxide X，5 AO X，6 AO X，8 ) than the cross-section (A) of the upper portion (551; 651; 851) of the reservoir layer made of the metal (M) M )big.

9. The method according to claim 8, wherein: The step (St31) of manufacturing the reservoir layer (55; 65) comprises the following sub-steps: - (St310) depositing a layer (35) of said metal (M) on the active layer (54; 64), and then - (St311) Annealing is performed at a certain temperature and for a period of time so that the previously deposited layer comprises, after annealing,: the upper part (551; 651) made of the metal (M) and the lower part (552; 652) made of the conductive second oxide (MOy).

10. The method according to claim 8, wherein: The step (St31') of manufacturing the reservoir layer (85) comprises the following sub-steps: - (St310′) depositing a first sub-layer (852) on the active layer (84), wherein the first sub-layer (852) is made of the second oxide (MOy), and then - (St311′) depositing a second sub-layer (851) on the first sub-layer (852), the second sub-layer (851) being made of the metal (M).

11. The method according to claim 10, wherein: The sub-step (310') of depositing the first sub-layer (852) is performed: - by cathode sputtering from a target made of said conductive second oxide (MOy), or by - sputtering from a cathode of a target made of said metal (M) in an atmosphere comprising oxygen, the oxygen partial pressure in said atmosphere being such that the deposited first sublayer (852) is made of said second oxide (MOy) having said oxygen proportion (y).

12. The method according to any one of claims 8 to 11, wherein: The etching step (St33) is halogenated plasma etching.

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