A memory access method and device of a thread, an apparatus, and a storage medium

Abstract

This invention discloses a method, apparatus, device, and storage medium for thread memory access. It schedules at least one target thread in a scheduling process; when a target thread accesses memory, it sends a memory address request to a memory management unit to obtain a linear address in the linear address space and the target thread's corresponding private thread page table; based on the target private thread page table, it maps the linear address corresponding to the memory address request to a physical address, enabling the target thread to access memory based on the physical address; it allocates a private thread page table for each thread, allowing each target thread to access memory according to its own target private thread page table, ensuring that the memory access processes between target threads do not interfere with each other, thus reducing the probability of memory access errors between threads and improving the execution stability of threads.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and storage medium for thread memory access. Background Technology

[0002] Currently, many terminals use virtual memory technology to run large programs with limited physical memory. This technology mainly utilizes the Memory Management Unit (MMU) to map virtual addresses to physical addresses. The virtual addresses correspond to the program code space, while the program code is actually stored in physical memory.

[0003] When an operating system executes a multithreaded task, each thread maps linear addresses in the linear address space to physical addresses through the memory management unit (MMU) to access the data in the memory corresponding to those physical addresses. However, because multiple threads within the same process use a process page table to perform this mapping process, one thread can access the data of all other threads in the process, making memory access errors prone to occur. If one thread experiences a memory access error, it can affect the execution of other threads and may even cause the entire process to crash and terminate. Summary of the Invention

[0004] This invention provides a method, apparatus, device, and storage medium for thread memory access. Each thread is allocated a private thread page table, enabling each target thread to access memory according to its own target private thread page table. The memory access processes between target threads do not interfere with each other, reducing the probability of memory access errors between threads and improving the execution stability of threads.

[0005] According to one aspect of the present invention, a thread memory access method is provided, comprising:

[0006] At least one target thread in the scheduling process;

[0007] When the target thread accesses memory, a memory address request is sent to the memory management unit to obtain the linear address in the linear address space and the target private thread page table corresponding to the target thread;

[0008] Based on the target private thread page table, the linear address corresponding to the memory address request is mapped to a physical address, so that the target thread can access memory based on the physical address.

[0009] According to another aspect of the present invention, a memory access device for a thread is provided, comprising:

[0010] The thread scheduling module is used to schedule at least one target thread in a process.

[0011] The address request module is used to send a memory address request to the memory management unit when the target thread accesses memory, and to obtain the linear address in the linear address space and the target private thread page table corresponding to the target thread;

[0012] The address mapping module is used to map the linear address corresponding to the memory address request to a physical address based on the target private thread page table, so that the target thread can access memory based on the physical address.

[0013] Furthermore, at least one target thread in the scheduling process includes:

[0014] Create and start the target thread in the process;

[0015] Alternatively, the current thread in the process that is running can be switched to the target thread, which is a thread that is in a waiting state.

[0016] Furthermore, the step of sending a memory address request to the memory management unit to obtain the linear address in the linear address space and the target private thread page table corresponding to the target thread includes:

[0017] For the target thread that has been created and started, a first memory address request is sent to the memory management unit;

[0018] The memory management unit determines the linear address in the linear address space based on the first memory address request and allocates the corresponding target private thread page table for the target thread.

[0019] Furthermore, the step of sending a memory address request to the memory management unit to obtain the linear address in the linear address space and the target private thread page table corresponding to the target thread includes:

[0020] For the target thread obtained by switching the current thread, a second memory address request is sent to the memory management unit;

[0021] The memory management unit determines the linear address in the linear address space based on the second memory address request, and switches the current private thread page table corresponding to the current thread to the target private thread page table corresponding to the target thread.

[0022] Furthermore, the linear address includes: the address in the target private dynamic heap memory corresponding to the target thread, wherein the target private dynamic heap memory is the dynamic heap memory private to the target thread in the linear address space.

[0023] Furthermore, the step of switching the current private thread page table corresponding to the current thread to the target private thread page table corresponding to the target thread includes:

[0024] The value of the page table register of the memory management unit is modified from the current representation data corresponding to the current private thread page table to the target representation data corresponding to the target private thread page table.

[0025] Furthermore, the target representation data includes the target thread identifier corresponding to the target private thread page table.

[0026] Furthermore, it also includes:

[0027] When the target thread is created, the target thread identifier is generated by the memory management unit.

[0028] Record the mapping relationship between the target thread identifier and the target private thread page table allocated to the target thread.

[0029] Furthermore, after sending the memory address request to the memory management unit, the process also includes:

[0030] If a memory access error signal for the target thread is received from the process, the process takes over the target thread to prevent the process from exiting.

[0031] Furthermore, the conditions for receiving a memory access error signal from the target thread sent by the process include:

[0032] The target thread accesses addresses in the private dynamic heap memory corresponding to other threads besides the target thread;

[0033] Alternatively, the target private thread page table obtained by the target thread may be the private thread page table corresponding to other threads besides the target thread.

[0034] Furthermore, if the target thread accesses an address in the private dynamic heap memory corresponding to another thread other than the target thread, the private dynamic heap memory corresponding to the other thread other than the target thread will not change.

[0035] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0036] At least one processor; and

[0037] A memory communicatively connected to the at least one processor; wherein,

[0038] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to execute the thread memory access method described in any embodiment of the present invention.

[0039] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the thread memory access method described in any embodiment of the present invention.

[0040] The technical solution of this invention involves scheduling at least one target thread in a process; when a target thread accesses memory, it sends a memory address request to the memory management unit to obtain the linear address in the linear address space and the target private thread page table corresponding to the target thread; based on the target private thread page table, it maps the linear address corresponding to the memory address request to a physical address, so that the target thread accesses memory based on the physical address; and it allocates a private thread page table to each thread, enabling each target thread to access memory according to its own target private thread page table, and the memory access process between each target thread does not interfere with each other, thereby reducing the probability of memory access errors between threads and improving the execution stability of the threads.

[0041] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1A It is the organization structure of the linear address space of a process's memory in the Linux system;

[0044] Figure 1B This is a schematic diagram illustrating the process of converting a virtual address to a physical address.

[0045] Figure 1C This is a diagram illustrating the conversion of linear addresses to physical addresses based on a paging mechanism;

[0046] Figure 2 This is a flowchart of a thread memory access method according to Embodiment 1 of the present invention;

[0047] Figure 3 This is a flowchart of a thread memory access method according to Embodiment 2 of the present invention;

[0048] Figure 4 This is a flowchart of a thread memory access method according to Embodiment 3 of the present invention;

[0049] Figure 5 This is a flowchart of a thread memory access method according to Embodiment 4 of the present invention;

[0050] Figure 6 This is a diagram illustrating how a target thread correctly obtains the physical address of memory.

[0051] Figure 7 This is a schematic diagram illustrating how a target thread generates a memory access error signal.

[0052] Figure 8 This is a schematic diagram of the structure of a thread memory access device according to Embodiment 3 of the present invention;

[0053] Figure 9 This is a schematic diagram of the structure of an electronic device that implements the thread memory access method of this invention. Detailed Implementation

[0054] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0055] It should be noted that the terms "current," "target," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0056] Example 1

[0057] Embodiment 1 of the present invention provides a method for accessing memory in a thread. This embodiment is applicable to one or more threads in a process that access memory while performing tasks. The method can be executed by a memory access device for the thread, which can be implemented in hardware and / or software. The memory access device for the thread can be configured in an electronic device or the operating system of the electronic device.

[0058] A process is a running program in a computer and is the basic unit for system resource allocation. A thread, also known as a lightweight process (LWP), is the smallest unit of execution and the basic unit of scheduling.

[0059] Threads have the following characteristics:

[0060] (1) Threads are the basic unit of resource contention.

[0061] Processes need to compete for operating system resources. When a process requests a certain amount of resources, they are allocated to its threads. Within a process, multiple threads serve as the basic unit of resource contention, competing for the resources acquired by the process.

[0062] (2) A thread is the smallest unit of program execution.

[0063] When a process executes a task, the process breaks the task down into smaller parts, and a scheduling thread executes each of these smaller parts.

[0064] (3) Threads can share process data, but they also have private data, such as thread identifier (thread ID), page table register, global variables (errno value) and thread signals.

[0065] During thread access to memory addresses within a process, because the linear address space defined by a multitasking system is typically much larger than its physical memory capacity, a method of "virtualizing" the linear address space is needed, i.e., using virtual memory technology. Each process has its own linear address space after startup, which can only be accessed by its constituent threads. The linear address space refers to the virtual address storage space. The size of the linear address space is determined by the computer platform, specifically by the bitness of the operating system and the width of the CPU's address bus. The CPU's address bus width determines the theoretical upper limit of the address space. For example, the addressable range of a 32-bit hardware platform is 0x00000000 to 0xFFFFFFFF, which is 4GB.

[0066] Figure 1A It refers to the organization of the linear address space of a process's memory in a Linux system. For example... Figure 1AAs shown, the linear address space of this memory, from high address to low address, includes: kernel virtual memory, user stack created at runtime, dynamic link libraries, memory-mapped regions, dynamic heap memory created at runtime, and data segments. The high-address memory region is occupied by the operating system kernel and is used to house kernel code and data. Data segments start from low addresses and include read-only data segments such as program code and read-write data segments such as global variables. Dynamic heap memory created at runtime begins after the data segments and grows upwards using the malloc function.

[0067] When a thread in a process accesses an address in the linear address space of memory, the processor needs to translate the linear address into a physical address and then perform the required read or write operation at that physical address in memory. The Memory Management Unit (MMU) is a piece of computer hardware responsible for handling memory access requests from the central processing unit (CPU). It can perform virtual address to physical address translation (i.e., virtual memory management), memory protection, and control of the CPU cache. Figure 1B This is a schematic diagram illustrating the process of converting virtual addresses to physical addresses. For example... Figure 1B As shown, virtual memory technology is supported through the segmentation and paging mechanisms of the memory management unit, enabling the translation from memory addresses to physical addresses. In virtual memory technology, a large linear address space includes a small physical memory space (such as RAM or ROM) and a large external storage space (such as a large-capacity hard drive). The segmentation mechanism translates logical addresses into linear addresses, while the paging mechanism, based on the segmentation mechanism, divides the linear address space into pages and then maps these pages to pages in the physical address space, thus achieving the translation from linear addresses to physical addresses.

[0068] Figure 1C This is a diagram illustrating the translation of linear addresses into physical addresses based on a paging mechanism. For example... Figure 1C As shown, the process requests a specified amount of memory from the system; it calculates whether there is remaining memory in the linear address space based on the current process information. If so, it allocates the corresponding linear address and modifies the segment table; using the base address of the memory page in the page directory contained in the page directory's base register (CR3) and the upper limit of the "directory pointer" part of the highest-order or highest-order bit of the linear address, it selects a page directory entry within the page directory. Then, it selects the corresponding paging table based on the page directory entry, and the paging table contains multiple paging table entries. Finally, it obtains the physical address corresponding to the linear address based on the page frame of the paging table entry and the offset of the linear address; it returns the physical address of the successfully allocated memory.

[0069] During their research, the inventors discovered that because multiple threads within a process request memory addresses through the same process page table, these threads can share process data, and any thread can access data belonging to other threads within the same process. If, during task execution, a thread makes an erroneous access to a memory address and accidentally accesses data belonging to another thread, it can affect the task execution of other threads and may even cause the entire process to crash.

[0070] Therefore, in order to address the above-mentioned problems, this embodiment of the invention allocates a private thread page table to each thread in the process, so that each target thread accesses memory according to its own target private thread page table, and the memory access process between the target threads does not interfere with each other, thereby reducing the probability of memory access errors between threads and improving the execution stability of the threads.

[0071] Figure 2 This is a schematic diagram of a thread memory access method provided in Embodiment 1 of the present invention, as shown below. Figure 2 As shown, an embodiment of the present invention provides a method for accessing memory in a thread, specifically including:

[0072] S110, at least one target thread in the scheduling process.

[0073] In computer programming, a process is a running program and serves as the basic unit for resource allocation. One or more execution units within a process are called threads. Each thread, as the basic unit of scheduling and the smallest unit of execution, can be used to execute tasks specified in the program. The target thread refers to the process that is being scheduled or will be scheduled.

[0074] Specifically, the states of a thread can include: creation state, running state, waiting state, and exit state. The target thread in the scheduling process can be: created and started to put the target thread in the running state, or the target thread can be determined from a thread in the waiting state and the currently running thread in the process can be switched to become the target thread.

[0075] S120. When the target thread accesses memory, a memory address request is sent to the memory management unit to obtain the linear address in the linear address space and the target private thread page table corresponding to the target thread.

[0076] The target private thread page table is a thread page table private to the target thread. The structure of the thread page table is basically the same as that of the process page table, both including a page directory and page table entries. The main difference between the thread page table and the process page table is that the process page table is shared by multiple threads within a process, with each thread using the same process page table for linear address translation; while the target private thread page table proposed in this embodiment is private to each target thread, thus ensuring that the memory address requests of each target thread do not interfere with each other.

[0077] Specifically, when each target thread accesses data in memory to execute a task, it first needs to send a memory address request to the memory management unit to obtain a memory address in the linear address space. When the memory management unit receives the memory address access request from the target thread, it allocates a target-private thread page table corresponding to the target thread for each target thread, and calculates whether there is remaining memory space in the linear address space based on the information of the task executed by each target thread. If so, it allocates the corresponding linear address.

[0078] S130. Based on the target private thread page table, map the linear address corresponding to the memory address request to the physical address so that the target thread can access memory based on the physical address.

[0079] Specifically, although the target private thread page table is private to each target thread, its function still follows that of the process page table in existing technology. It uses the base address of the memory page in the page directory contained in the base register (CR3) of the target private thread page table, along with the upper limit of the "directory pointer" part of the highest-order or highest-order bit of the linear address, to select a page directory entry within the page directory. Then, it selects the corresponding paging table based on the page directory entry of the target private thread page table, where each paging table contains multiple paging table entries. Finally, it obtains the physical address corresponding to the linear address in the linear address space based on the page frame of the paging table entry and the offset of the linear address, thus enabling the target thread to access memory based on the requested physical address.

[0080] The technical solution provided by this invention involves scheduling at least one target thread in a process; when a target thread accesses memory, it sends a memory address request to the memory management unit to obtain the linear address in the linear address space and the target private thread page table corresponding to the target thread; based on the target private thread page table, it maps the linear address corresponding to the memory address request to a physical address, so that the target thread accesses memory based on the physical address; and it allocates a private thread page table to each thread, enabling each target thread to access memory according to its own target private thread page table, ensuring that the memory access processes between target threads do not interfere with each other, reducing the probability of memory access errors between threads, and improving the execution stability of the threads.

[0081] Example 2

[0082] Figure 3 This is a flowchart of a thread memory access method provided in Embodiment 2 of the present invention. This embodiment further refines step S110 in Embodiment 1, wherein at least one target thread in the scheduling process includes: creating and starting at least one target thread in the process. Figure 3 As shown, the method includes:

[0083] S210. Create and start at least one target thread in the process.

[0084] Specifically, if a new thread needs to be scheduled, the thread needs to create and start a new target thread.

[0085] For example, the method for creating and starting the target thread can employ any existing thread creation and thread startup method, such as creating and starting the thread by defining a Run function that inherits from the Thread class, a Runnable interface Run function, or a Callable interface call function. This embodiment of the invention does not impose any limitations in this regard.

[0086] S220. For the target thread that has been created and started, when the target thread accesses memory, a first memory address request is sent to the memory management unit.

[0087] The first memory address request may include information about the target thread, such as the target thread identifier and the task information being executed by the thread.

[0088] Specifically, for a target thread that has been created and started, when the target thread accesses memory, it sends a first memory address request to the memory management unit, which then determines and returns the memory address.

[0089] S230. The memory management unit determines the linear address in the linear address space based on the first memory address request, and allocates the corresponding target private thread page table for the target thread.

[0090] Specifically, for a newly created and started target thread, since the target thread does not have a corresponding target private thread page table, the memory management unit needs to determine the linear address of the memory to be accessed based on the memory address request, and at the same time allocate the corresponding target private thread page table for the target thread, so that the target thread can independently map the linear address to the physical address based on the target private thread page table.

[0091] S240. Based on the target private thread page table, map the linear address corresponding to the memory address request to the physical address so that the target thread can access memory based on the physical address.

[0092] The technical solution of this invention involves creating and starting at least one target thread in a process. For each created and started target thread, when the target thread accesses memory, it sends a first memory address request to the memory management unit. The memory management unit determines a linear address in the linear address space based on the first memory address request and allocates a corresponding target private thread page table for the target thread. Based on the target private thread page table, the linear address corresponding to the memory address request is mapped to a physical address, so that the target thread accesses memory based on the physical address. This allows each created and started thread to be allocated a private thread page table, enabling each target thread to access memory according to its own target private thread page table. The memory access processes between target threads do not interfere with each other, reducing the probability of memory access errors between threads and improving the execution stability of the threads.

[0093] Example 3

[0094] Figure 4 This is a flowchart of a thread memory access method provided in Embodiment 3 of the present invention. This embodiment further refines step S110 in Embodiment 1, wherein at least one target thread in the scheduling process includes: switching one of the current threads in the process to the target thread. Figure 4 As shown, the method includes:

[0095] S310. Switch the current thread in the process that is running to the target thread, where the target thread is the thread that is waiting.

[0096] Specifically, scheduling a target thread in a process can involve creating and starting a new target thread, or, if there are multiple threads in a waiting state in the process, determining one of them as the target thread and switching the currently running thread in the process to the target thread.

[0097] S320. For the target thread obtained by switching the current thread, send a second memory address request to the memory management unit.

[0098] The second memory address request may include information about the target thread, such as the target thread identifier, task information of the thread being executed, and the value of the page directory and page table register. The value of the page directory and page table register indicates the identifier of the target private thread page table allocated to the target thread.

[0099] Specifically, for the target thread obtained by switching the current thread, it is the same as the target thread that was created and started. It also needs to send a second memory address request to the memory management unit so that the memory management unit can determine the linear address in the linear address space based on the second memory address request.

[0100] S330. The memory management unit determines the linear address in the linear address space based on the memory address request; and switches the current private thread page table corresponding to the current thread to the target private thread page table corresponding to the target thread.

[0101] Specifically, the difference between a target thread obtained by switching the current thread and a target thread that has been created and started is that, since the target thread is in a waiting state, the memory management unit has already allocated a corresponding target private thread page table for the target thread when it was created. Therefore, when it is scheduled again, a new target private thread page table needs to be allocated. Simply switching the current private thread page table corresponding to the current thread to the target private thread page table corresponding to the target thread allows the target thread to map the linear address corresponding to the memory address request to the physical address based on the target private thread page table.

[0102] S340. Based on the target private thread page table, map the linear address corresponding to the memory address request to the physical address so that the target thread can access memory based on the physical address.

[0103] The technical solution of this invention involves switching the current thread in a running state within a process to a target thread, where the target thread is a thread in a waiting state. For the target thread obtained by switching the current thread, a second memory address request is sent to the memory management unit. The memory management unit determines the linear address in the linear address space based on the memory address request. The current private thread page table corresponding to the current thread is switched to the target private thread page table corresponding to the target thread. Based on the target private thread page table, the linear address corresponding to the memory address request is mapped to a physical address, enabling the target thread to access memory based on the physical address. This allows the current private thread page table to be switched to the target private thread page table synchronously as the current thread switches to the target process. This ensures that each target thread accesses memory according to its own target private thread page table, and the memory access processes between target threads do not interfere with each other, reducing the probability of memory access errors between threads and improving the execution stability of the threads.

[0104] Optionally, switching the current private thread page table corresponding to the current thread to the target private thread page table corresponding to the target thread includes:

[0105] Modify the value of the page table register of the memory management unit from the current representation data corresponding to the current private thread page table to the target representation data corresponding to the target private thread page table.

[0106] The page table register CR3 stores the representation data of the thread's page table. By modifying the representation data of the thread's page table, the corresponding private thread's page table can be matched. The current representation data is used to represent the current private thread's page table, and the target representation data is used to represent the target private thread's page table.

[0107] Specifically, when the current thread switches to the target thread, by modifying the value of the page table register of the memory management unit from the current representation data corresponding to the current private thread page table to the target representation data corresponding to the target private thread page table, the target thread can access memory according to the corresponding target private thread page table.

[0108] For example, the target representation data may include: the target thread identifier corresponding to the target private thread page table. The page directory base address of the target private thread page table can be obtained based on the target thread identifier.

[0109] Optionally, when creating the target thread, the target thread identifier is generated by the memory management unit;

[0110] Record the mapping relationship between the target thread identifier and the target private thread page table allocated to the target thread.

[0111] Specifically, the target thread page table representation data used to modify the page table register value is generated when the target thread is created. This is achieved by allocating a corresponding target private thread page table through the memory management unit and generating a target thread identifier for the target thread. The mapping relationship between the target thread identifier and the allocated target private thread page table is recorded. By using this mapping relationship, the corresponding target private thread page table can be automatically matched to the target thread.

[0112] Optionally, based on the above embodiments one to three, the linear address includes: the address in the target private dynamic heap memory corresponding to the target thread, where the target private dynamic heap memory is the dynamic heap memory private to the target thread in the linear address space.

[0113] The linear address space corresponding to a process includes dynamic heap memory created at runtime. In the existing technology, dynamic heap memory is shared by each thread in the process, that is, each thread can access the address in the dynamic heap memory. There may be problems such as an error or address overflow when one thread accesses the memory, which will affect the dynamic heap memory access of other threads.

[0114] In this embodiment of the invention, the dynamic heap memory in the linear address space accessible to each target thread is private to each target thread. Each target thread can only access the address in its own target private dynamic heap memory and cannot access the address in the target private dynamic heap memory of other target threads. This further ensures that the memory access process between target threads does not interfere with each other, reduces the probability of memory access errors between threads, and improves the execution stability of threads.

[0115] Example 4

[0116] Figure 5 This is a flowchart of a thread memory access method provided in Embodiment 4 of the present invention. This embodiment adds a new technical feature to the technology of Embodiment 1: after sending a memory address request to the memory management unit, it further includes: if a memory access error signal sent by the target thread is received, then the target thread is taken over to prevent other threads in the process from exiting. Figure 5 As shown, the method includes:

[0117] S410, at least one target thread in the scheduling process.

[0118] S420. When the target thread accesses memory, a memory address request is sent to the memory management unit.

[0119] S430. If a memory access error signal for the target thread is received from the process, the process takes over the target thread to prevent the process from exiting.

[0120] Specifically, if a target thread encounters an error while accessing memory, it sends a memory access error signal to the process. The process then feeds back the memory access error signal to the operating system, causing the operating system to take over the target thread. This prevents the entire process from crashing and exiting even if a memory access error occurs in one target thread, ensuring the normal operation of other threads.

[0121] The technical solution provided by this invention involves scheduling at least one target thread in a process; when the target thread accesses memory, it sends a memory address request to the memory management unit; if a memory access error signal of the target thread sent by the process is received, the target thread in the process is taken over to prevent other threads in the process from exiting. This allows the process to be taken over when a thread encounters a memory access error, ensuring that the entire process does not crash and exit, and other threads can continue to run normally.

[0122] Optionally, the conditions for receiving a memory access error signal from the target thread sent by the process include:

[0123] The target thread accesses an address in the private dynamic heap memory corresponding to another thread outside the target thread;

[0124] Alternatively, the target thread may obtain the target private thread page table as the private thread page table of another thread outside the target thread.

[0125] Specifically, a memory access error signal will be generated if the target thread accesses an address in the private dynamic heap memory of another thread (i.e., the target thread accesses an address in dynamic heap memory that is not its own); or if the private thread page table obtained by the target thread is the private thread page table of another thread (i.e., an error occurs when the target thread tries to match the target private thread page table, matching an address that does not belong to its own target private thread page table). In other words, if the target thread encounters an error while matching the target private thread page table or accessing an address in private dynamic heap memory, a memory access error signal will be generated, causing the operating system to receive the memory access error signal from the process.

[0126] Optionally, if the target thread accesses an address in the private dynamic heap memory of another thread, the private thread page table of that other thread will not be modified.

[0127] Specifically, if the target thread accesses an address in the private dynamic heap memory of another thread, the data in the private dynamic heap memory of the other thread will not be modified because the target thread does not have access to the private dynamic heap memory of the other thread. This protects the private data of the other thread.

[0128] In one specific implementation, the target thread matches its private thread page table by calling the `private_malloc` function, and the process takes over the target thread's memory access error signals by calling a custom function. For example... Figure 6 As shown, when a thread accesses memory normally, the value of the page table register is modified to match the target thread 1 with the corresponding target private thread page table 1, and the linear address is mapped to the physical address through the target private thread page table 1.

[0129] In another specific embodiment, such as Figure 7 As shown, if the page table register value is modified to match the target thread 1 with the target private thread page table 2 when accessing the memory corresponding to the target thread 2, that is, when the matching of the target private thread page table is incorrect, the access of the target thread 1 is prohibited. The target thread 1 generates a memory access error signal and feeds it back to the process. Thus, the erroneous access of thread 1 does not affect other threads, including the target thread 2, and the entire process does not need to exit and can continue to run normally.

[0130] Example 5

[0131] Figure 8 This is a schematic diagram of a thread memory access device provided in Embodiment 5 of the present invention. Figure 8As shown, the device includes: a thread scheduling module 510, an address request module 520, and a memory access module 530;

[0132] The thread scheduling module 510 is used to schedule at least one target thread in the process;

[0133] The address request module 520 is used to send a memory address request to the memory management unit when the target thread accesses memory, and to obtain the linear address in the linear address space and the target private thread page table corresponding to the target thread.

[0134] The address mapping module 530 is used to map the linear address corresponding to the memory address request to a physical address based on the target private thread page table, so that the target thread can access memory based on the physical address.

[0135] Optionally, the thread scheduling module 510 includes:

[0136] The thread creation unit is used to create and start the target thread in the process.

[0137] The thread switching unit is used to switch the current thread in the running state of the process to the target thread, wherein the target thread is a thread in the waiting state.

[0138] Optionally, the address request module 520 includes:

[0139] The first address request unit is used to send a first memory address request to the memory management unit for the target thread that has been created and started.

[0140] The thread page table allocation unit is used to determine the linear address in the linear address space based on the first memory address request by the memory management unit, and allocate the corresponding target private thread page table for the target thread.

[0141] Optionally, the address request module 520 includes:

[0142] The second address request unit is used to send a second memory address request to the memory management unit for the target thread obtained by switching the current thread;

[0143] The thread page table switching unit is used to determine the linear address in the linear address space based on the second memory address request by the memory management unit, and switch the current private thread page table corresponding to the current thread to the target private thread page table corresponding to the target thread.

[0144] Optionally, the linear address includes: the address in the target private dynamic heap memory corresponding to the target thread, wherein the target private dynamic heap memory is the dynamic heap memory private to the target thread in the linear address space.

[0145] Optionally, the thread page table switching unit includes:

[0146] The value of the page table register of the memory management unit is modified from the current representation data corresponding to the current private thread page table to the target representation data corresponding to the target private thread page table.

[0147] The target representation data includes the target thread identifier corresponding to the target private thread page table.

[0148] Optionally, the device further includes:

[0149] The thread identifier generation module is used to generate a target thread identifier number for the target thread through the memory management unit when the target thread is created;

[0150] The identifier mapping record module is used to record the mapping relationship between the target thread identifier and the target private thread page table allocated to the target thread.

[0151] Optionally, the device further includes:

[0152] The thread takeover module is used to take over the target thread in the process and prevent the process from exiting if a memory access error signal of the target thread is received from the process after the memory address request is sent to the memory management unit.

[0153] Optionally, the conditions for receiving a memory access error signal from the target thread sent by the process include:

[0154] The target thread accesses addresses in the private dynamic heap memory corresponding to other threads besides the target thread;

[0155] Alternatively, the target private thread page table obtained by the target thread may be the private thread page table corresponding to other threads besides the target thread.

[0156] Optionally, if the target thread accesses an address in the private dynamic heap memory corresponding to another thread, the private dynamic heap memory corresponding to the other thread will not change.

[0157] The thread memory access device provided in the embodiments of the present invention can execute the thread memory access method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0158] Example 6

[0159] Figure 9 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0160] like Figure 9 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0161] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0162] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as thread memory access methods.

[0163] In some embodiments, the thread memory access method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the thread memory access method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to execute the thread memory access method by any other suitable means (e.g., by means of firmware).

[0164] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0165] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0166] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0167] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0168] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0169] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0170] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0171] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method of memory access of a thread, characterized by, The method comprises: scheduling at least one target thread in a process; sending a memory address request to a memory management unit when the target thread accesses memory, obtaining a linear address in a linear address space and a target private thread page table corresponding to the target thread; mapping the linear address corresponding to the memory address request to a physical address based on the target private thread page table, so that the target thread accesses memory based on the physical address; The at least one target thread in the scheduling process comprises: creating and starting a target thread in a process; or, switching the current thread in the running state in the process to a target thread, the target thread being a thread in the waiting state; The sending of the memory address request to the memory management unit, the obtaining of the linear address in the linear address space and the target private thread page table corresponding to the target thread comprises: for the created and started target thread, sending a first memory address request to the memory management unit, wherein the first memory address request comprises a target thread identification number and task information executed by the thread; determining a linear address in a linear address space based on the first memory address request through the memory management unit, and allocating a corresponding target private thread page table for the target thread; for the target thread obtained by switching the current thread, sending a second memory address request to the memory management unit, wherein the second memory address request comprises a target thread identification number, task information executed by the thread, and a value of a page directory page table register; determining a linear address in a linear address space based on the second memory address request through the memory management unit, and switching a current private thread page table corresponding to the current thread to a target private thread page table corresponding to the target thread.

2. The method of claim 1, wherein, The linear address comprises an address in a target private dynamic heap memory corresponding to the target thread, and the target private dynamic heap memory is a dynamic heap memory private to the target thread in the linear address space.

3. The method of claim 1, wherein, The switching of the current private thread page table corresponding to the current thread to the target private thread page table corresponding to the target thread comprises: modifying the value of the page table register of the memory management unit from current representation data corresponding to the current private thread page table to target representation data corresponding to the target private thread page table.

4. The method of claim 3, wherein, The target representation data comprises a target thread identification number corresponding to the target private thread page table.

5. The method of claim 4, wherein, The method further comprises: generating a target thread identification number of the target thread through the memory management unit when the target thread is created; recording a mapping relationship between the target thread identification number and the target private thread page table allocated for the target thread.

6. The method of claim 1, wherein, After the sending of the memory address request to the memory management unit, the method further comprises: if a memory access error signal of the target thread sent by the process is received, taking over the target thread in the process to prevent the process from exiting.

7. The method of claim 6, wherein, The condition of receiving the memory access error signal of the target thread sent by the process comprises: the target thread accesses an address in a private dynamic heap memory corresponding to another thread other than the target thread; Alternatively, the target private thread page table acquired by the target thread is a private thread page table corresponding to another thread other than the target thread.

8. The method of claim 7, wherein, If the target thread accesses an address in a private dynamic heap memory corresponding to another thread other than the target thread, the private dynamic heap memory corresponding to the another thread other than the target thread does not change.

9. An apparatus for memory access of a thread, the apparatus comprising: The method comprises the steps of: a thread scheduling module configured to schedule at least one target thread in a process; an address request module configured to send a memory address request to a memory management unit when the target thread accesses memory, to acquire a linear address in a linear address space and a target private thread page table corresponding to the target thread; an address mapping module configured to map the linear address corresponding to the memory address request to a physical address based on the target private thread page table, so that the target thread accesses memory based on the physical address; the thread scheduling module comprises: a thread creation unit configured to create and start a target thread in a process; a thread switching unit configured to switch a current thread in a running state in the process to a target thread, the target thread being a thread in a waiting state; the address request module comprises: a first address request unit configured to send a first memory address request to the memory management unit for a created and started target thread, wherein the first memory address request comprises a target thread identification number and task information of thread execution; a thread page table allocation unit configured to determine a linear address in a linear address space based on the first memory address request by the memory management unit, and allocate a corresponding target private thread page table for the target thread; a second address request unit configured to send a second memory address request to the memory management unit for a target thread obtained by switching a current thread, wherein the second memory address request comprises a target thread identification number, task information of thread execution, and a value of a page directory page table register; the thread page table switching unit is further configured to determine a linear address in a linear address space based on the second memory address request by the memory management unit, and switch a current private thread page table corresponding to the current thread to a target private thread page table corresponding to the target thread.

10. An electronic device, comprising: The electronic device comprises: at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the thread memory access method of any one of claims 1-8.

11. A computer readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for enabling the processor to execute the thread memory access method of any one of claims 1-8 when executed.

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