Method for Automatic Signal Mapping in HIL Testing

Abstract

The present invention discloses a method for automatically mapping signals between a Simulink model and a Veristand project in HIL testing, which includes: searching for keywords in the C language file of the Simulink project to obtain all input and output interface information in the C language file, specifically including a table of interface signal names, paths, and types; extracting the hardware interface signals and CAN interface signals in the NI Veristand project, and obtaining a table containing interface signal names and paths; merging the two tables into one table, and writing the same interface signal names on the same line to obtain a new merged table; generating a MAPPING file in txt format according to the new merged table, where each interface signal corresponds to a line in the TXT file. The present invention can realize automatic mapping of signals between the Simulink model and the Veristand project.

Description

Technical Field

[0001] The present invention relates to the field of HIL testing, and in particular to a method and system for realizing automatic mapping of a simulink model and a Veristand engineering signal in HIL testing. Background Art

[0002] At present, in HIL testing, the more common practice is to use simulink to build models to implement algorithms for simulating peripheral controllers (for example, vehicle controllers, gateways, transmission controllers, electronic stability control system controllers, etc.), and generate .c .h files that meet the requirements of NIVeristand in simulink according to the TLC file NIVeristand.tlc provided by NIVeristand, and compile them into dll files. Combined with the use of NI Veristand software as the host computer to build the host computer project, the dll file generated by simulink is referenced in the NI Veristand project, and the board in the HIL runs according to the DLL algorithm to achieve hardware-in-the-loop simulation of the HIL and the controller under test. When establishing the NI Veristand project, there is a mapping link to realize the mapping of the ports used in the simulink project to the corresponding channels of the HIL hardware board; the CAN signals used in the simulink project are mapped to the CAN signals in the Veristand project.

[0003] At present, the common practice for mapping is to manually operate the configuration interface of the Veristand project, select a source signal, select a destination signal, and click connect on the configuration interface to implement mapping. Now, with the rise of autonomous driving technology and the advancement of artificial intelligence technology, software-defined cars have become the inevitable direction of development for major OEMs, which has directly led to an exponential increase in the software code, hardware interface, DBC signal, etc. of the vehicle controller. Manual mapping is tedious and prone to errors, and cannot solve the pain points of HIL testers. Summary of the invention

[0004] The main purpose of the present invention is to provide a method and system which has high working efficiency and is not prone to errors and can realize automatic mapping of simulink models and Veristand engineering signals in HIL testing.

[0005] The technical solution adopted by the present invention is:

[0006] A method for realizing automatic mapping of simulink model and Veristand engineering signal in HIL test is provided, comprising the following steps:

[0007] Find the path of the referenced TLC file in the settings of the Simulink project, analyze the TLC file, and find the name of the generated C-language interface initialization function in the description part of the NI interface initialization function. Use this as the keyword to search in the C-language file generated when compiling the DLL in Simulink, and search for all input and output interface information in the C-language file, specifically including the table of interface signal names, paths, and types.

[0008] Extract the hardware interface signals and CAN interface signals in the NI Veristand project, and obtain a table containing the interface signal names and paths.

[0009] Merge the two tables into one table, and write the rows with the same interface signal name on the same line to get a new merged table.

[0010] Generate a MAPPING file in txt format according to the new merged table, where each interface signal corresponds to one line of the TXT file.

[0011] According to the above technical solution, in the MAPPING file, for the interfaces of input type, the path extracted by the Simulink project is at the back, and for the interfaces of output type, the path extracted by the Simulink project is at the front.

[0012] According to the above technical solution, in the MAPPING file, separate the two paths in each line with a space.

[0013] According to the above technical solution, the specific steps for extracting the hardware interface signals in the NI Veristand project include:

[0014] Open the established NI Veristand project configuration interface, and obtain the naming of the default device from the interface.

[0015] Search for the field name in the NI Veristand project using the naming of the default device as the keyword.

[0016] Search for all secondary field names in the row of the previous step. One secondary field name is equivalent to one secondary path, and search for the channel name in the last-level field name. Generate one path for each encountered channel name.

[0017] According to the above technical solution, the specific steps for extracting the CAN interface signals in the NI Veristand project include:

[0018] Open the established NI Veristand project configuration interface, and obtain the naming of the communication interface from the interface.

[0019] Search for the field name in the NI Veristand project using the name of the communication interface as the keyword;

[0020] Search all secondary field names in the line where the previous step is located. A secondary field name is equivalent to a secondary path, and search for the channel name in the last-level field name. Generate a path every time a channel name is encountered.

[0021] According to the above technical solution, the default name of the default device obtained from the interface is "Custom Devices".

[0022] According to the above technical solution, the default name of the communication interface obtained from the interface is "NI-XNET".

[0023] The present invention also provides a system for realizing automatic mapping of simulink model and Veristand project signals in HIL testing, which is characterized by including:

[0024] A simulink project interface extraction module, which is used to find the path of the referenced TLC file in the settings of the simulink project, analyze the TLC file, find the name of the generated C language interface initialization function in the description part of the NI interface initialization function, and use it as the keyword to search in the C language file generated when the simulink compiles the DLL, and search for all input and output interface information in the C language file, specifically including a table of interface signal names, paths, and types;

[0025] An NI Veristand project interface extraction module, which is used to extract the hardware interface signals and CAN interface signals in the NI Veristand project, and obtain a table containing interface signal names and paths;

[0026] An automatic MAPPING module, which is used to merge the two tables into one table, write the same interface signal names in one line to obtain a new merged table; and generate a MAPPING file in txt format according to the new merged table, where each interface signal corresponds to a line of the TXT file.

[0027] According to the above technical solution, the NI Veristand project interface extraction module includes:

[0028] The hardware interface signal extraction sub-module is used to open the established NI Veristand project configuration interface, obtain the name of the default device from the interface; search for the field name in the NI Veristand project with the name of the default device as the keyword; search for all secondary field names in the line where the previous step is located. One secondary field name is equivalent to a secondary path, and search for the channel name in the field name of the last level. Each time a channel name is encountered, a path is generated.

[0029] The CAN interface signal extraction sub-module is used to open the established NI Veristand project configuration interface, obtain the name of the communication interface from the interface; search for the field name in the NI Veristand project with the name of the communication interface as the keyword; search for all secondary field names in the line where the previous step is located. One secondary field name is equivalent to a secondary path, and search for the channel name in the field name of the last level. Each time a channel name is encountered, a path is generated.

[0030] The present invention also provides a computer storage medium, which stores a computer program executable by a processor. The computer program implements the method for automatically mapping the simulink model and Veristand project signals in the HIL test described in any one of claims 1-7.

[0031] The beneficial effects produced by the present invention are as follows: By automatically extracting the simulink project interface information, hardware interface signals and CAN interface signals in the NI Veristand project, and automatically matching the extracted information to generate a table, the present invention realizes the automatic mapping between the simulink project and the NI Veristand project. Specifically, scripts or programs can be used for automatic mapping to replace manual mapping one by one, which greatly improves the efficiency, has higher accuracy, and avoids errors caused by humans. Brief Description of the Drawings

[0032] The present invention will be further described below in conjunction with the drawings and embodiments. In the drawings:

[0033] Figure 1 is the flowchart of the method for automatically mapping the simulink model and Veristand project signals in the HIL test of the embodiment of the present invention;

[0034] Figure 2 is the flowchart of the method for automatically mapping the simulink model and Veristand project signals in the HIL test of another embodiment of the present invention;

[0035] Figure 3It is a schematic diagram of the system structure for realizing the automatic mapping of the simulink model and Veristand project signals in the HIL test of the embodiment of the present invention;

[0036] Figure 4 It is a description diagram of the part of the input / output interface initialization function found when analyzing the TLC file of NI Verstand version 2018 used during simulink compilation in the embodiment of the present invention;

[0037] Figure 5 It is a schematic diagram of the.C file in the simulink project in the embodiment of the present invention;

[0038] Figure 6 It is a schematic diagram of the configured Veristand project interface in the embodiment of the present invention;

[0039] Figure 7 It is a schematic diagram of searching for custom device fields and secondary field Section Name in the embodiment of the present invention;

[0040] Figure 8 It is a code diagram of searching for the keyword "Channel Name" (channel name) in the last-level Section Name in the embodiment of the present invention. Detailed implementation manners

[0041] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0042] As Figure 1 shown, the method for realizing the automatic mapping of the simulink model and Veristand project signals in the HIL test of the embodiment of the present invention includes the following steps:

[0043] S1. Find the path of the referenced TLC file in the settings of the simulink project, analyze the TLC file, find the name of the generated C language interface initialization function in the description part of the NI interface initialization function, use it as the keyword to search in the C language file generated during simulink compilation of the DLL, and search for all input / output interface information in the C language file, specifically including a table of interface signal names, paths, and types;

[0044] S2. Extract the hardware interface signals and CAN interface signals in the NI Veristand project, and obtain a table containing interface signal names and paths;

[0045] S3. Combine the two tables into one table, and write the interface signal names that are the same on one line to obtain a new combined table;

[0046] S4. Generate a MAPPING file in txt format according to the new combined table, where each interface signal corresponds to one line of the TXT file.

[0047] As Figure 2 shown, the method steps of the specific embodiment of the present invention are as follows. When extracting hardware interface signals, it specifically includes the following steps:

[0048] Open the established NI Veristand project configuration interface, and obtain the name of the default device from the interface. Generally, the default is "Custom Devices";

[0049] Search for the field name in the NI Veristand project: "<Section Name="the device name obtained in the previous step"";

[0050] Search for all secondary (a line with more indentation characters at the beginning than the current line is called the secondary of the current line) Section Names in the line of the previous step. One secondary Section Name is equivalent to a secondary path, and search for the channel name "Channel Name" inside the last-level SectionName (the content in the middle with the same indentation as <Section Name> is called inside the current-level SectionName). Each time a channel name is encountered, a path is generated.

[0051] When extracting CAN interface signals, it specifically includes the following steps:

[0052] Open the established NI Veristand project configuration interface, and obtain the name of the communication interface from the interface. Generally, the default is "NI-XNET";

[0053] Search for the field name in the NI Veristand project: "<Section Name="the name of the communication interface obtained in the previous step"";

[0054] Search for all secondary (a line with more indentation characters at the beginning than the current line is called the secondary of the current line) Section Names in the line of the previous step. One secondary Section Name is equivalent to a secondary path, and search for the channel name "Channel Name" inside the last-level SectionName (the content in the middle with the same indentation as <Section Name> is called inside the current-level SectionName). Each time a channel name is encountered, a path is generated.

[0055] After both the hardware interface signals and the CAN interface signals are extracted, a table containing all the NI Veristand project interface signal names and paths is obtained. Then, it is merged with the table extracted from the Simulink project. The two tables are combined into one table, and the signal names that are the same are written on the same line to obtain a table in the format shown in the figure. A TXT format MAPPING file is generated according to the table. Each signal corresponds to one line of the TXT file. For those of the type input (EXT_IN), the path extracted from the Simulink project is at the back. For those of the type output (EXT_OUT), the path extracted from the Simulink project is at the front. A space is used to separate the two paths in each line.

[0056] It can be seen that through the above method, it directly inputs the Simulink project and the NI Veristand project, and automatically outputs a TXT format MAPPING file, thus completing the automatic mapping of the Simulink model and the Veristand project signals in the HIL test. The present invention greatly improves the efficiency and has higher accuracy, avoiding errors caused by humans.

[0057] The system for realizing the automatic mapping of the Simulink model and the Veristand project signals in the HIL test of the embodiment of the present invention mainly includes a Simulink project interface extraction module, a NI Veristand project interface extraction module, and an automatic MAPPING module.

[0058] Among them, the Simulink project interface extraction module is used to extract the Simulink project interface information. The NI Veristand project interface extraction module includes a NI Veristand project hardware interface signal extraction sub-module and a NI Veristand project CAN signal extraction sub-module, which are respectively used to extract the hardware interface signals and CAN signals of the NI Veristand project. The automatic MAPPING module is used to merge the Simulink project interface information and the interface signals of the NI Veristand project to generate a table, and generate a TXT format MAPPING file according to the new merged table, where each interface signal corresponds to one line of the TXT file.

[0059] Specifically, the functions of each module are as follows:

[0060] 1. The Simulink project input and output signal path extraction module (i.e., the Simulink project interface extraction module)

[0061] ① When creating a new Simulink project, the input / output interfaces interacting with the VeriStand project, the naming of CAN signals should be consistent and unique with the interface naming of the VeriStand project (consistency does not necessarily mean being exactly the same, it can also differ by a fixed prefix or suffix. For example, if the signal XX_ToBus is used in the Simulink project and the signal XX is used in the VeriStand project, it can also be considered consistent because the two differ by a fixed suffix _ToBus).

[0062] ② Use a script or programming language program (the implemented languages are diverse, such as Python, VB, VC++, etc. The type of language is not limited here, only the programming implementation idea is described and will not be elaborated further below). Open all the C language files (files with the extension.C) generated when compiling the DLL in Simulink in text mode. TLC (Target Language Compiler) is an interpretive language existing for conversion to the target language, and its purpose is to convert the rtw files compiled from the Simulink model into target code (such as C / C++). In the Simulink software, the TLC file referenced when generating C code can be set. In the TLC file, find the description of the input / output interface initialization function part, and then find the keywords related to generating the input / output interface initialization function. Search for the keywords in the generated C code to find the input / output interface. The specific keyword content is related to the TLC file of NI VeriStand used during Simulink compilation. For example, for the 2018 version of the NI VeriStand TLC file used during Simulink compilation, analyze the TLC file to find the description of the input / output interface initialization function part, as Figure 3 shown.

[0063] Among them, there is content about the NI interface initialization function. From the analysis of the TLC file referenced when generating C code from Simulink, the format of the NI interface initialization function when generating C code can be known. From the above example, the generated function name is: static NI_ExternalIO NI_ExtList[] DataSection(".NIVS.extlist"), and the format inside the function is {count, interface name, TID, type, width, XDIM, YDIM}. Therefore, search for the keyword "NI_ExternalIO NI_ExtList[]" in the C code, and extract the content related to the interface name and type inside the outermost layer of {} after the keyword. The interface name is the signal path. For example Figure 5 shown in the.C file. The extraction results (searched) are shown in Table 1 below (where the signal name is the last level of the path):

[0064] Table 1: Path extraction results of the.C files in the Simulink project

[0065]

[0066] The default paths for the input and output of the NI Veristand project to reference the Simulink model are Targets / Controller / Simulation Models / Models / G59HEV_C15TRD_For_HRBench / Inports / ; Targets / Controller / Simulation Models / Models / G59HEV_C15TRD_For_HRBench / Outports / ; (G59HEV_C15TRD_For_HRBench is the name of the object for which the DLL is generated for the referenced model. This is just an example and will not be elaborated further below. Additionally, the actual path may not use the default path. In the NI Veristand project, the specific path can be set manually. The input and output paths in the project can also be obtained by manually mapping a signal in the project and then viewing the content of the mapping), the path of type "EXT_IN" is prefixed with the input path of the NI Veristand project to reference the DLL: Targets / Controller / Simulation Models / Models / G59HEV_C15TRD_For_HRBench / Inports / , and the path of type "EXT_OUT" is prefixed with the output path of the NI Veristand project to reference the DLL: Targets / Controller / Simulation Models / Models / G59HEV_C15TRD_For_HRBench / Outports / ; to obtain the complete paths as shown in Table 2 below:

[0067] Table 2: Input and output path table of the NI Veristand project to reference the Simulink model

[0068]

[0069] 2. NI Veristand project hardware interface signal extraction sub-module

[0070] ① Open the Veristand project definition file with a script or programming language program (the file generated when creating a Veristand project with the extension.nivssdf). For different versions of NI Veristand software, the extension of the project definition file may vary. For the project definition file of the 2015 version of NI Verstand software, it is a file with the extension.nivssdf. When creating a Veristand project, resources for custom device boards need to be created. The custom process is actually the path of the custom interface. For example, for the Veristand project configured as shown in Figure 6 Search for the keyword "Custom Devices" in the custom device field. Search for the secondary field Section Name (field name) (secondary means indented by several characters relative to the superior). As shown below Figure 7 Search for all secondary Section Names after "<Section Name="Custom Devices"". One secondary Section Name is equivalent to a secondary path. For example Figure 7 For the code shown, get the path Custom Devices / TB2720. Search for the keyword "Channel Name" (channel name) in the innermost Section Name (the Section Name with the same indentation as <Section Name> is called the current-level Section Name). Each time a "Channel Name" is encountered, a path is obtained. For example Figure 8 For the code shown, get three paths: Custom Devices / TB2720 / AI1, Custom Devices / TB2720 / AI2, Custom Devices / TB2720 / AI3. Combine with the input and output port paths of the NI Veristand project (the default path is Targets / Controller. The actual input and output port paths may not use the default path and are related to the settings in the NI Veristand project. The path can be obtained by manually mapping a signal in the project) to get three complete paths, as shown in Table 3 below:

[0071] Table 3: NI Veristand Project Hardware Input / Output Signal Extraction Table

[0072]

[0073] 3. NI Veristand Project CAN Signal Extraction Submodule

[0074] ① Search for the communication interface keyword: "NI-XNET" in the same way as in the second step, search for the secondary field name: "<Section Name>", and obtain the path CAN / HCAN / Outgoing / Cyclic / GCU1 (275). Search for the channel name "Channel Name" in the innermost "SectionName", and obtain three paths: CAN / HCAN / Outgoing / Cyclic / GCU1 (275) / GCU_RollingCount_GCU1; CAN / HCAN / Outgoing / Cyclic / GCU1 (275) / GCU_CheckSum_GCU1; CAN / HCAN / Outgoing / Cyclic / GCU1 (275) / GCU_GeneratorDCCurrent;

[0075] Add the CAN signal root directory path of the NI Veristand project. For example, the default CAN signal root directory path is Targets / Controller / Hardware / Chassis / NI-XNET, and obtain three complete CAN signal paths as shown in Table 4 below:

[0076] Table 4: NI Veristand Project CAN Signal Extraction Table

[0077] 4. Automatic mapping module

[0078] The results obtained in the first three steps are as follows, as shown in Table 5 below:

[0079] Table 5: NI Veristand Project and SIMULINK Project Interface Path Mapping Table

[0080]

[0081] Generate a mapping file according to the format requirements of the NI Veristand project. For each signal, for the input / output interface of type "EXT_IN", the path extracted by the SIMULINK project is at the back, and for the input / output interface of type "EXT_OUT", the path extracted by the SIMULINK project is at the front, and generate a map file with the following content:

[0082] Targets / Controller / Custom Devices / TB2720 / AI1 Targets / Controller / Simulation Models / Models / G59HEV_C15TRD_For_HRBench / Inports / I0_NIBoard / Sig_AN_IN / EMSActuator_AN_IN_TPS2PD / AI1

[0083] Targets / Controller / Custom Devices / TB2720 / AI2 Targets / Controller / Simulation Models / Models / G59HEV_C15TRD_For_HRBench / Inports / I0_NIBoard / Sig_AN_IN / EMSActuator_AN_IN_APPS1_5V / AI2

[0084] Targets / Controller / Custom Devices / TB2720 / AI3 Targets / Controller / Simulation Models / Models / G59HEV_C15TRD_For_HRBench / Inports / I0_NIBoard / Sig_AN_IN / EMSActuator_AN_IN_APPS2_5V / AI3

[0085] Targets / Controller / Simulation Models / Models / G59HEV_C15TRD_For_HRBench / Outports / CAN_BUS / MDLSoftECUData_HCAN_ToBus / GCU / GCU1_0x113 / GCU_RollingCount_GCU1 Targets / Controller / Hardware / Chassis / NI-XNET / CAN / HCAN / Outgoing / Cyclic / GCU1 (275) / GCU_RollingCount_GCU1

[0086] Targets / Controller / Simulation Models / Models / G59HEV_C15TRD_For_HRBench / Outports / CAN_BUS / MDLSoftECUData_HCAN_ToBus / GCU / GCU1_0x113 / GCU_CheckSum_GCU1 Targets / Controller / Hardware / Chassis / NI-XNET / CAN / HCAN / Outgoing / Cyclic / GCU1 (275) / GCU_CheckSum_GCU1

[0087] Targets / Controller / Simulation Models / Models / G59HEV_C15TRD_For_HRBench / Outports / CAN_BUS / MDLSoftECUData_HCAN_ToBus / GCU / GCU1_0x113 / GCU_GeneratorDCCurrent Targets / Controller / Hardware / Chassis / NI-XNET / CAN / HCAN / Outgoing / Cyclic / GCU1 (275) / GCU_GeneratorDCCurrent

[0088] Save the above content as a TXT file, which can be imported into the NI software interface, thus realizing automatic mapping with scripts or programs.

[0089] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations shall fall within the protection scope of the appended claims of the present invention.

Claims

1. A method for automatically mapping a Simulink model and Veristand project signals in HIL testing, characterized in that, it includes the following steps: Find the path of the referenced TLC file in the settings of the Simulink project, analyze the TLC file, find the name of the generated C language interface initialization function in the description part of the NI interface initialization function, and use it as the keyword to search in the C language file generated when the Simulink compiles the DLL. Search for all input and output interface information in the C language file, specifically including a table of interface signal names, paths, and types; Extract the hardware interface signals and CAN interface signals in the NI Veristand project, and obtain a table containing interface signal names and paths; Merge the two tables into one table, and write the rows with the same interface signal name into one line to get a new merged table; Generate a MAPPING file in txt format according to the new merged table, where each interface signal corresponds to one line of the TXT file.

2. The method for automatically mapping a Simulink model and Veristand project signals in HIL testing according to claim 1, characterized in that, In the MAPPING file, for the interface type of input, the path extracted by the SIMULINK project is at the back, and for the interface type of output, the path extracted by the SIMULINK project is at the front.

3. The method for automatically mapping a Simulink model and Veristand project signals in HIL testing according to claim 1, characterized in that, In the MAPPING file, the two paths in each line are separated by a space.

4. The method for automatically mapping a Simulink model and Veristand project signals in HIL testing according to claim 1, characterized in that, The extraction of hardware interface signals in the NI Veristand project specifically includes the following steps: Open the established NI Veristand project configuration interface, and obtain the naming of the default device from the interface; Search for the field name in the NI Veristand project using the naming of the default device as the keyword; Search for all secondary field names in the line where the previous step is located. One secondary field name is equivalent to a secondary path, and search for the channel name in the last-level field name. Each time a channel name is encountered, a path is generated.

5. The method for automatically mapping a Simulink model and Veristand project signals in HIL testing according to claim 1, characterized in that, The extraction of CAN interface signals in the NI Veristand project specifically includes the following steps: Open the established NI Veristand project configuration interface, and obtain the naming of the communication interface from the interface; Search for the field name in the NI Veristand project using the naming of the communication interface as the keyword; Search all secondary field names in the line where the previous step is located. A secondary field name is equivalent to a secondary path, and search for the channel name in the field name of the last level. Generate a path every time a channel name is encountered.

6. The method for automatically mapping a Simulink model and Veristand project signals in the HIL test according to claim 4, wherein, The default naming of the default device obtained from the interface is "Custom Devices".

7. The method for automatically mapping a Simulink model and Veristand project signals in the HIL test according to claim 5, wherein, The default naming of the communication interface obtained from the interface is "NI-XNET".

8. A system for automatically mapping a Simulink model and Veristand project signals in the HIL test, wherein, comprising: A Simulink project interface extraction module, which is used to find the path of the referenced TLC file in the settings of the Simulink project, analyze the TLC file, find the name of the generated C language interface initialization function in the description part of the NI interface initialization function, and use it as the keyword to search in the C language file generated when the Simulink compiles the DLL, and search for all input and output interface information in the C language file, specifically including a table of interface signal names, paths, and types; An NI Veristand project interface extraction module, which is used to extract the hardware interface signals and CAN interface signals in the NI Veristand project, and obtain a table containing interface signal names and paths; An automatic MAPPING module, which is used to merge the two tables into one table, write the same interface signal names in one line to obtain a new merged table; and generate a MAPPING file in txt format according to the new merged table, where each interface signal corresponds to a line of the TXT file.

9. The system for automatically mapping a Simulink model and Veristand project signals in the HIL test according to claim 8, wherein, The NI Veristand project interface extraction module includes: A hardware interface signal extraction sub-module, which is used to open the established NI Veristand project configuration interface, and obtain the naming of the default device from the interface; use the naming of the default device as the keyword to search for field names in the NI Veristand project; search all secondary field names in the line where the previous step is located. A secondary field name is equivalent to a secondary path, and search for the channel name in the field name of the last level. Generate a path every time a channel name is encountered; The CAN interface signal extraction sub-module is used to open the established NI Veristand project configuration interface, obtain the naming of the communication interface from the interface; search for the field name in the NI Veristand project with the naming of the communication interface as the keyword; search for all secondary field names in the line where the previous step is located, and a secondary field name is equivalent to a secondary path, and search for the channel name in the field name of the last level. Each time a channel name is encountered, a path is generated.

10. A computer storage medium, characterized in that, it stores a computer program executable by a processor, and the computer program implements the method for automatically mapping the simulink model and Veristand project signals in the HIL test described in any one of claims 1-7.

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