Lightweight On-Chip Learning Method, System and Processor Based on Simplified SDSP Algorithm

Abstract

The present invention belongs to the technical field of microprocessors, and specifically discloses a lightweight on-chip learning method based on a simplified SDSP algorithm for training spiking neural networks, including: performing rate encoding on an input image to convert a static frame image into a spiking form, and regarding each pixel point as a presynaptic neuron; the output layer of the spiking neural network consists of leaky integrate-and-fire neurons, where each neuron is a postsynaptic neuron, and the presynaptic neurons and the postsynaptic neurons are connected in a fully connected manner. Among them, the spikes emitted by the presynaptic neurons are presynaptic spikes, and the spikes emitted by the postsynaptic neurons are postsynaptic spikes; during the training of the spiking neural network, the weights of each synapse are updated according to a simplified spike-driven synaptic plasticity weight update method based on the calcium concentration Ca of the postsynaptic neuron. The present invention also discloses a system and a processor based on this method.

Description

Technical Field

[0001] The present invention belongs to the technical field of microprocessors, and particularly relates to a lightweight on-chip learning method, system and processor based on a simplified SDSP algorithm. Background Art

[0002] Compared with traditional artificial neural networks (ANNs), spiking neural networks (SNNs) have higher biological plausibility and have become a research hotspot in the fields of neuromorphic science and artificial intelligence in recent years. At the same time, the characteristics of low power consumption, high computing efficiency and on-chip learning ability of SNNs have made them more and more widely used in application scenarios with limited hardware resources and strict energy consumption requirements, such as edge computing and mobile devices. STDP (Spike-Timing-Dependent Plasticity) is the most popular SNN learning algorithm at present. The weight update depends on the time order of the presynaptic spike and the postsynaptic spike. If the presynaptic spike arrives earlier than the postsynaptic spike, it is considered that there is a causal relationship between the presynaptic-postsynaptic spikes, and its synaptic weight will be strengthened; conversely, if the postsynaptic spike arrives earlier than the presynaptic spike, the corresponding synaptic weight will be weakened. In addition, another highly biomimetic SNN learning method, SDSP (Spike-Driven Synaptic Plasticity), is considered to have a learning ability similar to that of STDP. Since it only updates the weight when the presynaptic spike arrives, SDSP has the advantages of low area and low power consumption in hardware implementation compared with STDP. However, the performance of SDSP in recognition tasks is not as good as that of STDP, so it has not been widely used. Here, we have improved and optimized the original SDSP algorithm for hardware, while maintaining the hardware-friendly features of the original SDSP algorithm, improving the recognition performance of the network. The teacher signal acts on the output neuron from the input end, rather than acting on the output end like the teacher signal in traditional supervised learning. When the activity of the neuron is consistent with the expectation, the teacher signal will no longer act, providing an overlearning prevention mechanism. In addition, the local global inhibitory neuron applies an inhibitory signal to all neurons when the presynaptic spike arrives to replace the role of lateral inhibition or winner-takes-all network. The algorithm we proposed shows the advantages of simple operation, low power consumption, high speed, high energy efficiency and support for on-chip learning after hardware implementation. Therefore, the present invention has practical application significance and promotion prospects in scenarios with high real-time requirements, limited resources and strict power consumption requirements, such as mobile devices and edge computing. Summary of the Invention

[0003] The present invention aims to design a small neuromorphic system with low power consumption and high computing efficiency, while meeting the requirements of application scenarios with limited hardware resources and strict power consumption requirements, and improving the performance of the system in recognition tasks.

[0004] The lightweight on-chip learning method based on the Simplified SDSP algorithm in the present invention is used for the training of spiking neural networks, including:

[0005] Performing rate encoding on the input image, converting the static frame image into a pulse form, and regarding each pixel point as a presynaptic neuron;

[0006] The output layer of the spiking neural network consists of Leaky Integrate-and-Fire (LIF) neurons, where each neuron is a postsynaptic neuron. The presynaptic neurons and the postsynaptic neurons are connected in a fully connected manner. The pulses emitted by the presynaptic neurons are presynaptic pulses, and the pulses emitted by the postsynaptic neurons are postsynaptic pulses;

[0007] During the training of the spiking neural network, the weights of each synapse are updated according to the Simplified-Spike-Driven-Synapse-Plasticity (Simplified-SDSP) weight update method based on the calcium concentration Ca of the postsynaptic neuron.

[0008] Furthermore, in the Simplified-Spike-Driven-Synapse-Plasticity weight update method based on the calcium concentration of the postsynaptic neuron, the weights of each synapse are updated after the arrival of the presynaptic pulse, and the weight update method is as follows:

[0009]

[0010] where w i is the synaptic weight, Δw is the weight update step size, also known as the learning rate, Ca represents the calcium concentration of the postsynaptic neuron, and θ1, θ2, and θ3 are the calcium concentration thresholds for weight update, with θ1 < θ2 < θ3.

[0011] Furthermore, the calcium concentration Ca will be gradually updated as the training progresses. If the postsynaptic neuron triggers a pulse, the value of the calcium concentration Ca is incremented by 1; otherwise, the calcium concentration decays with a time constant τ Ca

[0012] Furthermore, the calculation formula of the calcium concentration Ca is expressed as follows:

[0013]

[0014] where Ca(t i ) represents the calcium concentration of the postsynaptic neuron at time t i , and Ca(t post ) represents the calcium concentration of the postsynaptic neuron at time t post ​The calcium concentration of the neuron at a moment, that is, the calcium concentration at the moment of the previous trigger pulse of the postsynaptic neuron. If the neuron triggers a pulse, the value of the calcium concentration Ca is incremented by 1. After that, the calcium concentration of the neuron decays exponentially with a time constant τ Ca represents the time constant of calcium concentration decay.

[0015] Furthermore, the calcium concentration Ca is obtained by looking up a table. The calculation formula of the calcium concentration Ca is as follows:

[0016] Ca(t i ) = Ca(t post )LUT ca [Δt ca + 1,

[0017] where LUT Ca is the lookup table for calcium concentration decay, and Δt Ca represents the time difference between t i and t post .

[0018] Furthermore, the working mode of the postsynaptic neuron is that when there is a pulse input, the membrane potential rises rapidly, and when there is no pulse input, the membrane potential decays exponentially. If the membrane potential exceeds the threshold, a pulse is emitted and the resting state is restored;

[0019] where the formula of the neuron membrane potential is as follows:

[0020]

[0021] where V(t i ) represents the membrane potential of the neuron at time t i , V(t prev ) represents the membrane potential of the neuron at time t prev , that is, the membrane potential of the neuron when the previous presynaptic pulse arrives. After that, the neuron membrane potential decays exponentially with a time constant τ m represents the time constant of membrane potential decay, and w i represents the magnitude of the synaptic weight. When the presynaptic pulse arrives, the corresponding weight w i is added to the membrane potential V(t i ).

[0022] Furthermore, the decay of the membrane potential of the LIF neuron is obtained by looking up a table. The formula of the neuron membrane potential is as follows:

[0023] V(t i ) = V(t prev )LUT[Δt] + w i ,

[0024] where LUT is the lookup table for membrane potential decay, and Δt represents ti The time difference with t prev ;

[0025] Furthermore, the spiking neural network further includes a teacher cluster global inhibitory neuron;

[0026] Each postsynaptic neuron corresponds one-to-one with a node in the teacher cluster, and each output neuron receives separate teaching with different teacher signals;

[0027] The global inhibitory neuron emits a global inhibitory signal that directly acts on all postsynaptic neurons;

[0028] The learning method further includes training using labeled training samples;

[0029] During training, when a presynaptic pulse arrives, the teacher signal, the global inhibitory signal, and the input pulse will act on the postsynaptic neuron together. The teacher signal can be expressed as follows:

[0030] If the output of the current neuron corresponds to the label, then for the moment when the next presynaptic pulse arrives at this neuron, the teacher signal has,

[0031]

[0032] If the output of the current neuron does not correspond to the label, then for the moment when the next presynaptic pulse arrives at this neuron, the teacher signal has,

[0033]

[0034] where θ stop_high and θ stop_low are the calcium concentration thresholds of the teacher signal;

[0035] T i represents the actual value of the current teacher signal, T target and T non-target represent the values of the target teacher signal and the non-target teacher signal respectively, where T target is a positive value, while T non-target is a negative value;

[0036] When the presynaptic pulse arrives, the update of the membrane potential of the postsynaptic neuron follows the following formula:

[0037] V(n + 1) = V(n) + Ti + w i - Inh,

[0038] where V(n) represents the current membrane potential value, V(n + 1) represents the updated membrane potential value, T i is the teacher signal, w i is the weight value of the corresponding synapse, and Inh is the global inhibitory signal;

[0039] If the membrane potential exceeds the threshold, the postsynaptic neuron membrane emits a pulse.

[0040] The present invention also proposes a lightweight on-chip learning system based on the simplified SDSP algorithm, which is used to perform on-chip learning according to the foregoing method and form a corresponding pulsed neural network.

[0041] The present invention also proposes a lightweight on-chip learning processor based on the simplified SDSP algorithm, and the foregoing lightweight on-chip learning system based on the simplified SDSP algorithm is integrated in the processor.

[0042] Technical effects of the present invention:

[0043] Although the currently mainstream pulsed neural network learning algorithms STDP and Tempotron can be applied at the edge, the power consumption and resource overhead are still relatively large. The simplified learning algorithm proposed by the present invention has simple operations, which is beneficial to saving resources and power consumption. At the same time, the learning speed can be improved due to the extremely simple calculation.

[0044] The recognition rate of the original SDSP algorithm on image data sets is low and it is difficult to be applied to more complex recognition tasks. The method in the present invention improves the SDSP algorithm, and the recognition rate is significantly increased when performing classification tasks.

[0045] The lightweight on-chip learning system based on the simplified SDSP algorithm proposed by the present invention supports on-chip learning, and its high real-time performance and high-performance processing are very suitable for edge computing and mobile computing. Description of the Drawings

[0046] Figure 1 It is the topological structure diagram of the pulsed neural network in the embodiment of the present invention.

[0047] Figure 2 It is the architecture diagram of the lightweight on-chip learning processor based on the simplified SDSP algorithm in the embodiment of the present invention.

[0048] Figure 3 It is the schematic block diagram of the LIF neuron update logic module in the embodiment of the present invention.

[0049] Figure 4 It is the schematic block diagram of the weight update logic module in the embodiment of the present invention. Detailed Embodiments

[0050] The topological structure of the pulsed neural network used in this embodiment is as Figure 1As shown, each pixel point is regarded as a presynaptic neuron, that is, the Inputs Nodes in the figure. Poisson encoding is performed on the input image to convert the static frame image into a pulse form. That is to say, the rate at which the presynaptic neuron emits pulses within the time window T is proportional to the pixel value corresponding to the pixel point; the output neurons in the output layer, that is, the postsynaptic neurons, adopt LIF (Leaky Integrate-and-Fire) leaky integrate-and-fire neurons. The presynaptic neurons and the postsynaptic neurons are connected in a fully connected manner, and each connection is a synapse; the global inhibitory neuron emits a global inhibitory signal that directly acts on all the output layer neurons. Each output neuron corresponds one-to-one with the nodes in the teacher cluster. Therefore, each output neuron receives separate teaching with different teacher signals.

[0051] The working mode of the LIF neuron is described as follows. When there is a pulse input, the membrane potential rises rapidly. When there is no pulse input, the membrane potential decays exponentially. If the membrane potential exceeds the threshold, a pulse is emitted and it returns to the resting potential. The calculation formula for the membrane potential of the LIF neuron is expressed as follows:

[0052]

[0053] Where V(t i ) represents the membrane potential of the neuron at time t i , V(t prev ) represents the membrane potential of the neuron at time t prev , that is, the membrane potential of the neuron when the previous presynaptic pulse arrives. After that, the membrane potential of the neuron decays exponentially. τ m represents the time constant of the membrane potential decay. w i represents the magnitude of the synaptic weight. When the presynaptic pulse arrives, the corresponding weight w i is accumulated to the membrane potential V(t i ). Considering hardware implementation, in this embodiment, the neuron model in Equation (1) is discretized, and the discretized LIF neuron model is expressed as Equation (2):

[0054] V(t i ) = V(t prev )LUT[Δt] + w i , (2)

[0055] LUT is the lookup table for the membrane potential decay. Δt represents the time difference between t i and t prev ; since the exponential operation is not hardware-friendly, the membrane potential decay values for the corresponding time differences are stored in the memory in the form of a lookup table LUT, and are directly retrieved for multiplication during the operation, saving hardware overhead.

[0056] In this embodiment, the learning method of the neural network is supervised learning, that is, the neurons are trained using the training samples with labels. It is not difficult to see that the form of the labels in this example is the same as the form of the output signals of the output layer;

[0057] During training, when a presynaptic pulse arrives, the teacher signal, the global inhibition signal, and the input pulse will act on the output neuron together. That is to say, for the neurons in the learning stage, it will be determined whether the teacher signal still works at the next time step according to the calcium concentration state of the current neuron and whether the activity of the neuron is consistent with the expectation (whether the output of the neuron at the time step corresponds to the label of the training sample). Thus, the teacher signal can be expressed as equations (3) and (4):

[0058] If the output of the current neuron corresponds to the label, the teacher signal corresponding to the arrival moment of the next presynaptic pulse of this neuron is as follows,

[0059]

[0060] If the output of the current neuron does not correspond to the label, the teacher signal corresponding to the arrival moment of the next presynaptic pulse of this neuron is as follows,

[0061]

[0062] Among them, Ca represents the calcium concentration of the postsynaptic neuron, θ stop_high and θ stop_low are the calcium concentration thresholds of the teacher signal;

[0063] T i represents the actual value of the current teacher signal, T target and T non-target respectively represent the values of the target teacher signal and the non-target teacher signal, where T target is a positive value, while T non-target is a negative value.

[0064] The calcium concentration Ca will be gradually updated as the training progresses. If the postsynaptic neuron triggers a pulse, the value of the calcium concentration Ca is incremented by 1, otherwise the calcium concentration decays with the time constant τ Ca . The calculation formula for the calcium concentration Ca is expressed as follows:

[0065]

[0066] Among them, Ca(t i ) represents the calcium concentration of the postsynaptic neuron at time t i , Ca(t post ) represents the calcium concentration of the postsynaptic neuron at time t postThe calcium concentration of the neuron at a moment, that is, the calcium concentration at the moment of the previous trigger pulse of the postsynaptic neuron. If the neuron triggers a pulse, the value of the calcium concentration Ca is incremented by 1. After that, the calcium concentration of the neuron decays exponentially with a time constant of τ Ca represents the time constant for the decay of the calcium concentration;

[0067] Similarly, considering hardware implementation, it is necessary to discretize the calculation of the calcium concentration Ca in Equation (5). The calculation formula for the discretized calcium concentration is as follows:

[0068] Ca(t i ) = Ca(t pos t)LUT ca [Δt ca + 1; (6)

[0069] where LUT Ca is the look-up table for the decay of the calcium concentration, and Δt Ca represents the time difference between t i and t post . The decay values of the calcium concentration for the corresponding time differences are stored in the memory in the form of a look-up table and directly retrieved for multiplication during operation, saving hardware overhead.

[0070] As can be seen from the above content, during the training process of the neuron, when the calcium concentration of the neuron corresponding to the output and the label is higher than θ stop_high , or the calcium concentration of the neuron not corresponding to the output label is lower than θ stop_low , it indicates that the neuron has learned well and the teacher signal will no longer act. Otherwise, the teacher signal is T target or T non-target .

[0071] Whenever a presynaptic pulse arrives, the inhibitory signal generated by the global inhibitory neuron is input to the postsynaptic neuron together with the encoded pulse sequence, affecting the membrane potential of the neuron. Here, the role of the inhibitory neuron is equivalent to lateral inhibition or a winner-takes-all network.

[0072] In summary, the update of the neuron membrane potential follows Equation (7).

[0073] V(n + 1) = V(n) + Ti + w i -Inh (7)

[0074] where V(n) represents the current membrane potential value, V(n + 1) represents the updated membrane potential value, T i is the teacher signal, and w iis the weight value of the corresponding synapse, and Inh is the global inhibition signal. It should be noted that only when the presynaptic pulse arrives, the membrane potential of the neuron is updated according to formula (7), and it is not necessary to update the membrane potential at each time step. If the membrane potential exceeds the threshold, a pulse is emitted.

[0075] Finally, in this embodiment, the Simplified-SDSP (Simplified-Spike-Driven-Synapse-Plasticity) weight update method based on the calcium concentration of the postsynaptic neuron is used to update the weights of each synapse. The weights of each synapse are updated after the arrival of the presynaptic pulse, and the weight update method is as shown in formula (8):

[0076]

[0077] where w i is the synaptic weight, Δw is the weight update step size, also known as the learning rate, Ca represents the calcium concentration of the postsynaptic neuron, and θ1, θ2, θ3 are the calcium concentration thresholds for weight update, with θ1 < θ2 < θ3.

[0078] The recognition performance of the method we adopted and the methods in the prior art can be compared through experiments, and the comparison results are shown in Table 1.

[0079] Table 1 Performance Comparison Table

[0080]

[0081] Table 1 shows the comparison of the recognition rates obtained by each method through simulation experiments using the C# language in the Visual Studio environment. In the simulation experiments, the performance of each method in the table was tested on the MNIST and / or Fashion-MNIST datasets, and all parameters were fixed-point quantized and could be directly used on hardware.

[0082] Among them, the SDSP method refers to the literature C. Frenkel, M. Lefebvre, J. Legat, and D. Bol, “A 0.086-mm2 12.7-pJ / SOP 64k-synapse 256-neuron online-learning digital spiking neuromorphic processor in 28-nm CMOS,” IEEE Trans. Biomed. Circuits Syst., vol. 13, no. 1, pp. 145–158, Feb. 2019.

[0083] The reference literature for the No Mention method: Juncheng, SHEN, De, MA, Zonghua, GU, Ming, ZHANG, Xiaolei, ZHU, Xiaoqiang, XU, Qi, XU, Yangjing, SHEN, Gang, & PAN. (2016). Darwin: aneuromorphic hardware co-processor based on Spiking Neural Networks., 59(2), 232-236.;

[0084] The reference literature for the STDP method: Wang. "Energy efficient parallel neuromorphic architectures with approximate arithmetic on FPGA". NEUROCOMPUTING, 221(2017):146-158.;

[0085] The reference literature for the Tempotron method: Wang, Tengxiao, Shi, Cong, Zhou, Xichuan, Lin,, Yingcheng, He,, Junxian, Gan,, Ping, Li, Ping, Wang,, Ying, Liu,, Liyuan, Wu,, Nanjian, Luo,, & Gang. (2021). CompSNN: A lightweight spiking neural network based on spatiotemporally compressive spike features. NEUROCOMPUTING, 425, 96-106.;

[0086] The Triplet R-STDP method refers to the literature: He, Zhen, Shi, Cong, Wang, Tengxiao, Wang, Ying, Tian, Min, Zhou, Xichuan, Li, Ping, Liu, Liyuan, Wu, Nanjian, Luo, & Gang. (2022). A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 69(3), 1657-1661.;

[0087] In the method (Simplified-SDSP) proposed in this embodiment, the initial weights of each synapse are randomly generated between 0 and 5. After training, the upper and lower limit values of the weights are 7 and 0 respectively. The specific values of the important parameters used are shown in Table 2.

[0088] Table 2: Parameter settings

[0089] Parameter Name Set Value Δw 0.3 θ1 3 θ2 5 θ3 7 <![CDATA[θ stop_low > 4 <![CDATA[θ stop_high > 6 <![CDATA[T target > 6 <![CDATA[T non-target > -1 inh 4 <![CDATA[τ Ca > 32 <![CDATA[τ m > 64

[0090] It is not difficult to find from the results in Table 1 that the method in the present invention uses a simpler network structure and learning method to achieve a better recognition rate. The recognition rate reaches 90.00% on the MNIST dataset and 79.13% on the Fashion-MNIST dataset.

[0091] This embodiment also exemplarily discloses a lightweight on-chip learning system based on the simplified SDSP algorithm for implementing the above learning method. In this embodiment, the system is integrated into a neuromorphic chip to form a lightweight on-chip learning processor based on the simplified SDSP algorithm, and its architecture is as Figure 2 shown. The entire hardware architecture is composed of a global controller, an input event FIFO buffer module, an output event FIFO buffer module, neuron cores, synapse cores, and a small amount of storage logic (not shown in the figure). Among them, the neuron cores and synapse cores together form a spiking neural network.

[0092] In this embodiment, the processor includes 4 neuron cores. Each neuron core can support up to 32 LIF neurons at most. The address of the input pulse supports up to 32×32, that is, 1024 pixel points. Therefore, the processor designed in this example supports a single-layer fully connected network of up to 1024×128 at most.

[0093] The global controller controls four neuron cores to execute the update of neuron membrane potential and calcium concentration. The block memories and registers within each neuron core store all the parameters and variables related to the update of neuron states.

[0094] The synaptic core updates the weights according to the current neuron calcium concentration when each presynaptic pulse arrives.

[0095] The inputs and outputs of the entire hardware processor, AER (Address Event Driven), are both cached using FIFOs, that is Figure 2 the input event FIFO buffer module and the output event FIFO buffer module in . Among them, the presynaptic pulses based on the Poisson coding of the input image are input as the input address time (18 bits), cached in the input event FIFO buffer module and then input to the spiking neural network. The pulses emitted by each LIF neuron are cached through the output event FIFO buffer module and then output as the output address event (13 bits). At the same time, the input event FIFO buffer module also receives input requests from the outside and feedbacks an acceptance enable signal. The output event FIFO buffer module also sends output requests to the outside and accepts the acceptance enable signal feedback from the outside.

[0096] As Figure 2 shown in the enlarged part of the neuron core in , the neuron core includes modules such as LIF neuron update logic, local inhibitory neurons, teacher signal decision logic, weight up / down registers, calcium concentration update logic, and neuron membrane potential and calcium concentration registers.

[0097] As Figure 2 shown in the enlarged part of the synaptic core in , the synaptic core includes modules such as weight update logic and 32KB - synaptic weight registers.

[0098] Figure 3 More vividly shows in the update logic of the LIF neuron membrane potential implemented by the LIF neuron update logic module, which is expressed by Equation (7). The LIF neuron update logic includes the leakage and accumulation of the membrane potential. When leaking, the corresponding decay constant value is retrieved from the LUT lookup table according to the time difference Δt between the current presynaptic pulse arrival time step and the previous presynaptic pulse arrival time step to decay the membrane potential, and when accumulating, the membrane potential is added with the corresponding weight w i; During the training process using training samples, when the pre-pulse arrives, the local inhibitory neurons generate an inhibitory signal Inhibitory_signal to all synaptic neurons, restricting the pulses triggered by the neurons; at the end of each time step, the teacher signal decision logic determines whether the teacher signal Teacher_signal still works according to the conditions and mathematical relationships in equations (3) and (4). In addition, according to equation (8), the calcium concentration variable also determines the update direction of the synaptic weight. The up / down signal of the weight update is temporarily stored in the weight up / down register and sent to the synaptic nucleus for weight update. The calcium concentration update logic module is used to specifically implement the mathematical relationship shown in equation (6) to update the calcium concentration Ca of each LIF neuron, where the decay constant value LUT ca [Δt ca , and the same look-up table method is also used to obtain it.

[0099] The learning unit of the network, that is, the weight update logic is as Figure 4 shown. In this embodiment, a weight update logic with a weight overflow check circuit is adopted. And the acquisition of the learning rate Lr corresponding to Δw in equation (8) is set to be obtained by looking up a preset learning rate look-up table LearingRate LUT according to the learning iteration number iteration_number. That is to say, the value of the learning rate Lr can change with the increase of the learning iteration number or remain unchanged (that is, the preset values of the learning rate Lr in the table are all equal).

[0100] The sign of the learning rate Lr is called Trace (+1, 0, -1) here, which is determined by the up / down signal of the weight update. The up signal corresponds to the case of θ2 < Ca < θ3 in equation (8), and Trace is +1. The down corresponds to the case of θ1 < Ca < θ2 in equation (8), and Trace is -1. In other cases, Trace is 0, and the weight is not updated. The two signals come from the weight up / down register, and the current up / down signal values of each neuron in the weight up / down register depend on the current membrane potential of the current neuron and the current calcium concentration value Ca of each neuron in the calcium concentration register; according to the product of the learning rate Lr and Trace and the weight w i _current read from the synaptic weight memory, after addition, w i _new is obtained and written into the weight storage. At this time, if w i _new does not overflow, the synaptic weight w i _next of the next time is w i _new, otherwise w i _next = w i _current.

[0101] As can be easily seen from the figure, the update of the weight is activated by the pre-synaptic pulse spike_pre signal. Additionally, since the synaptic weights do not affect each other, in this embodiment, multiple weight update logic modules are used to process the update of the synaptic weights in parallel to shorten the processing time.

[0102] The lightweight neuromorphic system proposed in this embodiment is an organic integration of three mechanisms: pulse information processing, teacher signal adaptation, and local neuron global inhibition. While maintaining the original learning algorithm of the SDSP pulse neural network, it improves the recognition rate of the network. Due to the biological rationality and hardware-friendly characteristics of this algorithm itself, it provides the possibility for the application of this algorithm at the edge and on mobile devices.

[0103] The algorithm proposed in this embodiment has been optimized for hardware based on the original algorithm. The algorithm itself has simple calculations, and the designed hardware framework can ensure the recognition performance of the network while consuming extremely few resources and having extremely low power consumption. Moreover, all parameters of the network are dynamically configurable, and the network topology can be changed according to user needs.

[0104] The lightweight neuromorphic system proposed in this embodiment supports on-chip learning. Its high real-time performance and high-performance processing are very suitable for edge computing and embedded mobile devices. This system processes asynchronous pulse events, has simple operations, extremely low resource consumption, and fast processing speed, solving the problems of large resource consumption, high cost, and low real-time performance caused by the synchronous dense calculations and complex operations of traditional deep neural networks.

[0105] The learning method based on calcium concentration update is more biologically rational and closer to the human brain. After integrating a series of hardware-friendly mechanisms, the recognition rate is improved, and the problem of low recognition rate of shallow pulse neural networks is solved. Since the update of the weight only occurs when the pre-synaptic pulse arrives, this learning method still has the potential of low power consumption and high energy efficiency when extended to multi-layer networks.

[0106] The hardware architecture in this embodiment achieves a high-performance network with the least resource consumption and power consumption. Due to its fast processing speed, low cost, and lightweight characteristics, it is very easy to be applied to edge computing and mobile computing, integrated into miniaturized devices, and has practical application significance and promotion prospects in scenarios with high real-time performance such as mobile computing and edge computing.

[0107] Based on the pulsed neural network structure for processing pulse information in this embodiment, the synaptic weights are updated only when the pre-synaptic pulse arrives, rather than updating the weights when both pre-synaptic and post-synaptic pulses arrive as in the STDP algorithm. This update method reduces the computational complexity. In addition, the update of the weights depends only on the calcium concentration of the post-synaptic neuron when the pre-synaptic pulse arrives. Except for the calcium concentration and membrane potential, there is no need to record other neuron state variables. The teacher signal changes dynamically according to the current state of the neuron during the learning process to avoid overlearning. The local inhibitory neurons generate a global inhibitory signal, thus replacing the winner-takes-all network and simplifying the network structure. The algorithm has been optimized for hardware. After all parameters are fixed-point, a hardware architecture of a neuromorphic system with on-chip learning ability is designed.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A lightweight on-chip learning method based on the simplified SDSP algorithm for training spiking neural networks, characterized in that, Including: Performing rate encoding on the input image, converting the static frame image into a pulse form, and regarding each pixel point as a presynaptic neuron; The output layer of the spiking neural network consists of leaky integrate-and-fire neurons, where each neuron is a postsynaptic neuron. The presynaptic neurons and the postsynaptic neurons are connected in a fully connected manner. The pulses emitted by the presynaptic neurons are presynaptic pulses, and the pulses emitted by the postsynaptic neurons are postsynaptic pulses; The spiking neural network further includes a teacher population global inhibitory neuron; Each postsynaptic neuron corresponds one-to-one with a node in the teacher population, and each output neuron is taught separately by a different teacher signal; The global inhibitory neuron emits a global inhibitory signal that directly acts on all postsynaptic neurons; During the training of the spiking neural network, the weights of each synapse are updated according to a simplified spike-driven synaptic plasticity weight update method based on the calcium concentration Ca of the postsynaptic neuron; It also includes training using the training samples with labels; During training, when a presynaptic pulse arrives, the teacher signal and the global inhibitory signal input pulse will act on the postsynaptic neuron together. The teacher signal can be expressed as follows: If the output of the current neuron corresponds to the label, then for the teacher signal corresponding to the arrival time of the next presynaptic pulse of this neuron, there is If the output of the current neuron does not correspond to the label, then for the teacher signal corresponding to the arrival time of the next presynaptic pulse of this neuron, there is: where, θ stop_high and θ stop_low are the calcium concentration thresholds of the teacher signal; T i represents the actual value of the current teacher signal, T target and T non-target represent the values of the target teacher signal and the non-target teacher signal respectively, where T target is a positive value, while T non-target is a negative value; When a presynaptic pulse arrives, the update of the membrane potential of the postsynaptic neuron follows the following formula: V(n + 1) = V(n) + Ti + w i -Inh, where V(n) represents the current membrane potential value, V(n + 1) represents the updated membrane potential value, T i is the teacher signal, w i is the weight value of the corresponding synapse, and Inh is the global inhibition signal; If the membrane potential exceeds the threshold, the postsynaptic neuron membrane emits a pulse.

2. The method according to claim 1, wherein In the simplified spike-driven synaptic plasticity weight update method based on the calcium concentration of the postsynaptic neuron, the weights of each synapse are updated after the arrival of the presynaptic pulse, and the weight update method is as follows: where w i is the synaptic weight, Δw is the weight update step size, also known as the learning rate, Ca represents the calcium concentration of the postsynaptic neuron, and θ1, θ2, and θ3 are the calcium concentration thresholds for weight update, with θ1 < θ2 < θ3.

3. The method according to claim 1, characterized in that, The calcium concentration Ca will be gradually updated as the training progresses. If the postsynaptic neuron triggers a pulse, the value of the calcium concentration Ca is incremented by 1; otherwise, the calcium concentration decays with a time constant τ Ca and decays.

4. The method according to claim 3, characterized in that, The calculation formula of the calcium concentration Ca is expressed as follows: where Ca(t i ) represents the calcium concentration of the postsynaptic neuron at time t i , and Ca(t post ) represents the calcium concentration of the neuron at time t post , that is, the calcium concentration at the time of the previous trigger pulse of the postsynaptic neuron. If the neuron triggers a pulse, the value of the calcium concentration Ca is incremented by 1. After that, the calcium concentration of the neuron decays exponentially, and τ Ca represents the time constant of the calcium concentration decay.

5. The method according to claim 4, wherein The calcium concentration Ca is obtained by looking up a table. The calculation formula of the calcium concentration Ca is expressed as follows: Ca(t i ) = Ca(t post )LUT ca [Δt ca +1 Among them, the LUT Ca is a look-up table for the calcium concentration decay, and Δt Ca represents the time difference i between t post and t 6. The method according to claim 1, wherein The working mode of the postsynaptic neuron is that when there is a pulse input, the membrane potential rises rapidly. When there is no pulse input, the membrane potential decays exponentially. If the membrane potential exceeds the threshold, it emits a pulse and returns to the resting state; Among them, the formula of the neuron membrane potential is expressed as follows: where V(t i ) represents the membrane potential of the neuron at time t i , V(t prev ) represents the membrane potential of the neuron at time t prev , that is, the membrane potential of the neuron when the previous presynaptic pulse arrives. After that, the neuron membrane potential decays exponentially, and τ m represents the time constant of the membrane potential decay, and w i represents the magnitude of the synaptic weight. When the presynaptic pulse arrives, the corresponding weight w i is added to the membrane potential V(t i ).

7. The method according to claim 6, characterized in that, The decay of the membrane potential of the leaky integrate-and-fire neuron is obtained by looking up a table. The formula of the neuron membrane potential is expressed as follows: V(t i ) = V(t prev )LUT[Δt] + w i , Among them, the LUT is a look-up table for the decay of the membrane potential, and Δt represents the time difference between t i and t prev themselves.

8. A lightweight on-chip learning system based on a simplified SDSP algorithm, characterized in that This system is used to perform on-chip learning according to any one of the methods described in claims 1-7 and form a corresponding spiking neural network.

9. A lightweight on-chip learning processor based on the simplified SDSP algorithm, characterized in that, This processor integrates a lightweight on-chip learning system based on the simplified SDSP algorithm as described in claim 8.

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