Select gate gate-induced drain leakage enhancement

Abstract

This application relates to select gate gate-induced drain leakage enhancement. Various applications can include memory devices designed to provide enhanced gate-induced drain leakage (GIDL) current during memory erase operations. Enhanced operation can be provided to a string of memory cells by enhancing an electric field in a channel structure of a topmost select gate transistor after a voltage is applied to the gate of the topmost select gate transistor. This electric field can be provided to the channel structure of the topmost select gate transistor by using a split plug as a contact, where the split plug has one or more conductive regions that contact the channel structure and one or more non-conductive regions that contact the channel structure. The split plug can be part of a contact between a data line and the channel structure. Additional devices, systems, and methods are discussed.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory devices and operations of memory devices, and more specifically to structures and methods related to erase operations of memory devices. BACKGROUND

[0002] Memory devices are typically provided as internal, semiconductor, integrated circuit devices in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory needs power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain its stored data when not powered and includes flash memory, read only memory (ROM), electrically TM erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or three-dimensional (3D) XPoint memory, among others. 3D XPoint memory is a non-volatile memory (NVM) technology with a stackable cross-point data access array where bit storage is based on changes in bulk resistance.

[0003] Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically include one or more groups of single transistor, floating gate or charge trap memory cells that allow high memory density, high reliability and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named for the logic form in which the basic memory cells of each are arranged. The memory cells of a memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a string of the array are coupled together in a source-to-drain manner between a source line and a data line.

[0004] Using 3D architectures for memory devices, such as NAND memory devices, can provide increased capacity over planar structures. Memory arrays for 3D structures can include vertically stacked memory cells as strings of memory cells. In selecting one or more strings for accessing a given memory cell, gate structures can be located at the top and bottom of the strings with memory cells storing data therebetween. The gate structures can include select gate transistors having their drains coupled to a data line, such as a bit line, at one end of the string, and their sources coupled to a source line at the other end of the string.

[0005] In NAND flash devices, an erase operation is performed on a string of memory cells by applying a higher positive voltage to the string body. In the case of 3D NAND architectures, with the string body of memory cells electrically isolated, holes can be generated and injected into the string body in order to maintain a positive potential in the string during erase of the memory cells of the string. Gate induced drain leakage (GIDL) is a technique to enable high performance and reliable erase operations. It is a leakage mechanism in devices such as insulated gate field effect transistors (IGFETs) due to large field effects in the drain junction. Existing methods to enhance GIDL operation in 3D NAND flash memory devices include attempting to optimize the device doping profile of the select transistor to the string of memory cells such that the junction of the select transistor is abrupt. With the number of layers of memory cells having a floating channel structure in the vertical strings in 3D NAND flash memory devices rising to hundreds, it is important to provide sufficient GIDL current during erase operations. SUMMARY

[0006] Aspects of the present application relate to a memory device comprising: a string of memory cells; a data line; a transistor coupling the data line to the string of memory cells, the transistor having a channel structure and a gate, the channel structure separated from the gate; and a plug coupling the data line to the channel structure, wherein the plug covers the channel structure, the plug having one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure, such that the plug is a split contact between the data line and the channel structure.

[0007] Another aspect of this disclosure is directed to a memory system comprising: a plurality of memory devices, wherein one or more of the memory devices include: a data line; a memory array having strings of memory cells, wherein each string is formed in a pillar and is coupled to a transistor formed in the pillar, the transistor coupling the string to one of the data lines, the transistor having a channel structure and a gate, the channel structure being separated from the gate, the transistor structured with a contact plug to couple to the channel structure of the data line, wherein the plug covers the channel structure, the plug having one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure, such that the plug is a split contact between the data line and the channel structure; and a memory controller including processing circuitry including one or more processors, the memory controller configured to perform operations including performing an erase operation on a selected string of the memory array by applying an erase voltage to the gate of the transistor that couples the selected string to a data line associated with the selected string.

[0008] Yet another aspect of this disclosure is directed to a method of forming a memory array of a memory device, the method comprising: forming strings of memory cells; forming transistors coupling data lines to the strings of memory cells, including forming the transistors having channel structures and gates, the channel structures being separated from the gates; forming plugs to couple the data lines to the channel structures, wherein the plugs cover the channel structures, such that the plugs have one or more conductive regions contacting the channel structures and one or more non-conductive regions contacting the channel structures, such that the plugs are split contacts of the channel structures; and forming the data lines coupled to the plugs. BRIEF DESCRIPTION OF DRAWINGS

[0009] The drawings, which are not necessarily to scale, generally illustrate various embodiments discussed herein.

[0010] Figure 1 A representation of a three-dimensional memory array of a memory die according to various embodiments, wherein the three-dimensional memory array has a memory block including a plurality of sub-blocks.

[0011] Figure 2 Illustrating a top view of a side of a top of a pillar having a split plug for providing a conductive contact of a channel structure of a transistor to a data line according to various embodiments.

[0012] Figure 3 Illustrating a top view of a structure of Figure 2 according to various embodiments.

[0013] Figures 4A to 4C Illustrating three different arrangements of an interface of a split plug having a channel structure of a transistor relative to a gate of the transistor according to various embodiments.

[0014] Figure 5 An example of a mask having a pattern of split plugs for processing a channel structure in a select transistor in a pillar for coupling a data line to a memory array is illustrated in accordance with various embodiments.

[0015] Figure 6 A functional block diagram of an example memory device including a memory array having a plurality of memory cells and one or more circuits or components that provide communication with or perform one or more memory operations on the memory array is illustrated in accordance with various embodiments.

[0016] Figure 7 A flow diagram of features of an example method of forming a memory array of a memory device in accordance with various embodiments.

[0017] Figure 8 A flow diagram of features of an example method of forming a plug that couples a data line to a channel structure, providing a split contact to the channel structure in accordance with various embodiments.

[0018] Figure 9 A block diagram of an example machine having one or more memory devices structured to enhance interband tunneling in a select gate transistor of a string of memory cells in a memory array of the one or more memory devices during an erase operation in accordance with various embodiments. DETAILED DESCRIPTION

[0019] The following detailed description makes reference to the accompanying drawings, which are numbered for illustrative purposes. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments, and it is to be understood that other embodiments can be utilized and that structural, logical, mechanical, and electrical changes can be made without departing from the scope of the embodiments. The following detailed description is, therefore, not to be taken in a limiting sense.

[0020] Both NOR and NAND flash architecture semiconductor memory arrays are accessed by decoders that activate a particular memory cell by selecting an access line (WL) coupled to the gate of the particular memory cell. In a NOR architecture semiconductor memory array, once activated, the selected memory cell places its data value on a data line, causing different current to flow depending on the state the particular cell is programmed to. In a NAND architecture semiconductor memory array, a relatively high bias voltage is applied to a drain side select gate (SGD) line. An access line coupled to the gates of unselected memory cells of each group is driven with a specified pass voltage (e.g., Vpass) to cause the unselected memory cells of each group to operate as pass transistors (e.g., to pass current in a manner not limited by their stored data values). Current then flows in a line between a source line and a data line through each series-coupled group limited only by the selected memory cell of each group, placing the current-encoded data value of the selected memory cell on the data line.

[0021] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively into one or several program states. For example, a single level cell (SLC) can represent one of two program states (e.g., 1 or 0), representing one bit of data. Flash memory cells can also represent more than two program states, allowing higher density memory to be manufactured without increasing the number of memory cells, since each cell can represent more than one binary digit (e.g., more than one bit). Such cells can be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLC). In certain examples, MLC has been referred to as a memory cell that can store two bits of data per cell (e.g., one of four program states). MLC is used herein in its broader context to refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programmed states). A memory cell that can store two bits of data per cell (e.g., one of four program states) is referred to herein as a dual level cell (DLC). A triple level cell (TLC) refers to a memory cell that can store three bits of data per cell (e.g., one of eight program states). A quad level cell (QLC) can store four bits of data per cell, and a penta level cell (PLC) can store 5 bits of data per cell.

[0022] In a string of memory cells in a 3D memory device, such as a 3D NAND memory, the string is accessed to operate on a memory cell in the string of cells can be controlled by a gated selector device, such as a select gate, that is in series with the memory cell in the string. To simplify processing in a 3D NAND memory die, the gated structure defined by the selector device can be similar to the structure of the memory cell fabricated.

[0023] In various embodiments, increased generation of interband charge in a channel structure of a transistor at a data line side of a 3D NAND flash pillar is based on a lift-off of the channel structure of the transistor at a top of the pillar. The channel structure can be disposed as a cylindrical channel structure in the pillar. The channel structure is split by using a non-continuous conductive contact plug at the data line side of the pillar to the channel structure. The pillar can include a string of memory cells at one end of the pillar coupled to a source line by one or more select gate transistors (SGS) in the pillar that are coupled to the string of memory cells disposed in series with the source line. At the other end, the string of memory cells can be coupled to a data line by one or more select gate transistors (SGD) in the pillar that couple the string of memory cells to the data line. The channel structure can run through the memory cells of the string from a bottom-most SGS to a top-most SGD. In various embodiments, the pillars of memory cells in a 3D NAND memory array can each include one SGD and one SGS.

[0024] The increased generation of interband charge can further enhance drain side current GIDL in an erase operation based on the structural interface of the contact plug to the channel structure of the top-most SGD. This interface structure using a segmented conductive contact to the channel structure of the top-most SGD provides a different approach to the doping optimization between the contact and the channel structure of the top-most SGD. The interband tunneling field that generates the GIDL current is enhanced by using a segmented conductive contact plug to the channel structure to cross-split the channel structure. The cross-split channel structure breaks the uniformity of the electric field and allows the electric field lines to concentrate in the split regions, enhancing the interband displacement. When processing the pillars of selector devices and memory cells to data lines of a memory array of a memory device, the segmented conductive plug to the channel structure that provides the split channel structure can be implemented using an additional mask to cut the plug that couples the data line to the channel structure. An additional conductive region can be used to connect the plug having the separate conductive segment of the channel structure that contacts the top-most SGD to the associated data line.

[0025] Figure 1A representation of a 3D memory array 100 for a memory die, where the 3D memory array 100 has a memory block 101 that includes sub-blocks 102-0, 102-1, 102-2, and 102-3. Although one memory block of memory cells is shown, a memory die can include more than one block of memory cells. Although four sub-blocks are shown in the memory cell block 101, a memory cell block can include more or less than four sub-blocks. The sub-block 102-0 includes a string 107-0 structured as a pillar with selector devices 125-0-0...125-0-4 arranged vertically in series with a topmost selector device 125-0-4-0 coupled at one end of the series to couple the string 107-0 to a data line 110-0. Coupling the string 107-0 to the data line 110-0 can include providing a segmented conductive contact to a split plug 111-0 of a channel structure of the selector device 125-0-4. The selector device 125-0-0 of the sub-block 102-0 is coupled to a topmost memory cell 104-0-N of a set of memory cells 104-0-0...104-0-N arranged vertically in the string of the sub-block 102-0.

[0026] The memory cells 104-0-0...104-0-N are respectively coupled to access lines 106-0...106-N. A bottommost memory cell 104-0-0 of a set of memory cells of a string is coupled to a topmost selector device 130-0-3 of selector devices 130-0-0...130-0-3 arranged vertically in series with a bottommost selector device 130-0-0 coupled to a source line 135-0 of the sub-block 102-0. The selector devices 125-0-0...125-0-4 can be select gates SGD of transistors fabricated with the structure of the memory cells 104-0-0...104-0-N and referred to as SGD0, SGD1, SGD2, SGD3, and SGD4 of the sub-block 102-0. The selector devices 130-0-0...130-0-3 can be source side select gates SGS of transistors fabricated with the structure of the memory cells 104-0-0...104-0-N and referred to as SGS0, SGS1, SGS2, and SGS3 of the sub-block 102-0. The string of the sub-block 102-0 can repeat along a direction 103-0 in a y direction, with select lines to the selector devices 125-0-0...125-0-4 and to the selector devices 130-0-0...130-0-3 effectively along the direction 103-0.

[0027] Sub-block 102-1 includes a string 107-1 structured as a pillar having selector devices 125-1-0...125-1-4 arranged vertically in series with a topmost selector device 125-1-4 coupled at one end of the series to couple string 107-1 to data line 110-1. Coupling string 107-1 to data line 110-1 can include providing segmented conductive contacts to the split plugs 111-1 of the channel structures of selector devices 125-1-4. Selector device 125-1-0 of sub-block 102-1 is coupled to a topmost memory cell 104-1-N of a set of memory cells 104-1-0...104-1-N arranged vertically in string 107-1 of sub-block 102-1.

[0028] Memory cells 104-1-0...104-1-N are respectively coupled to access lines 106-0...106-N. A bottommost memory cell 104-1-0 of a set of memory cells of a string is coupled to a topmost selector device 130-1-3 of selector devices 130-1-0...130-1-3 arranged vertically in series with a bottommost selector device 130-1-0 coupled to a source line 135-1 of sub-block 102-1. Selector devices 125-1-0...125-1-4 can be select gates SGD of transistors fabricated with the structure of memory cells 104-1-0...104-1-N and referred to as SGD0, SGD1, SGD2, SGD3, and SGD4 of sub-block 102-1. Selector devices 130-1-0...130-1-3 can be select gates SGS of transistors fabricated with the structure of memory cells 104-1-0...104-1-N and referred to as SGS0, SGS1, SGS2, and SGS3 of sub-block 102-1. The string of sub-block 102-1 can be repeated along direction 103-1 in the y-direction with select lines to selector devices 125-1-0...125-1-4 and to selector devices 130-1-0...130-1-3 effectively along direction 103-1.

[0029] Sub-block 102-2 includes a string 107-2 structured as a pillar, the string 107-2 having selector devices 125-2-0...125-2-4 arranged vertically in series with a topmost selector device 125-2-4 coupled at one end of the series to couple the string 107-2 to a data line 110-2. Coupling the string 107-2 to the data line 110-2 can include providing a segmented conductive contact to a split plug 111-2 of a channel structure of the selector device 125-2-4. The selector device 125-2-0 of sub-block 102-2 is coupled to a topmost memory cell 104-2-N of a set of memory cells 104-2-0...104-2-N arranged vertically in the string of sub-block 102-2.

[0030] The memory cells 104-2-0...104-2-N are respectively coupled to access lines 106-0...106-N. A bottommost memory cell 104-2-0 of a set of memory cells of a string is coupled to a topmost selector device 130-2-3 of selector devices 130-2-0...130-2-3 arranged vertically in series with a bottommost selector device 130-2-0 coupled to a source line 135-2 of sub-block 102-2. The selector devices 125-2-0...125-2-4 can be select gates SGD of transistors fabricated with the structure of the memory cells 104-2-0...104-2-N and referred to as SGD0, SGD1, SGD2, SGD3, and SGD4 of sub-block 102-2. The selector devices 130-2-0...130-2-3 can be select gates SGS of transistors fabricated with the structure of the memory cells 104-2-0...104-2-N and referred to as SGS0, SGS1, SGS2, and SGS3 of sub-block 102-2. The string of sub-block 102-0 can be repeated along direction 103-2 in the y direction with select lines to the selector devices 125-2-0...125-2-4 and to the selector devices 130-2-0...130-2-3 effectively along direction 103-2.

[0031] Sub-block 102-3 includes a string 107-3 structured as a pillar, the string 107-3 having selector devices 125-3-0...125-3-4 arranged vertically in series with a topmost selector device 125-3-4 coupled at one end of the series to couple the string 107-3 to a data line 110-3. Coupling the string 107-3 to the data line 110-3 can include providing a segmented conductive contact to a split plug 111-3 of a channel structure of the selector device 125-3-4. The selector device 125-3-0 of sub-block 102-3 is coupled to a topmost memory cell 104-3-N of a set of memory cells 104-3-0...104-3-N arranged vertically in the string of sub-block 102-3.

[0032] The memory cells 104-3-0...104-3-N are respectively coupled to access lines 106-0...106-N. A bottommost memory cell 104-3-0 of a set of memory cells of a string is coupled to a topmost selector device 130-3-3 of selector devices 130-3-0...130-3-3 arranged vertically in series with a bottommost selector device 130-3-0 coupled to a source line 135-3 of sub-block 102-3. The selector devices 125-3-0...125-3-4 can be select gates SGD of transistors fabricated with the structure of the memory cells 104-3-0...104-3-N and referred to as SGD0, SGD1, SGD2, SGD3, and SGD4 of sub-block 102-3. The selector devices 130-3-0...130-3-3 can be select gates SGS of transistors fabricated with the structure of the memory cells 104-3-0...104-3-N and referred to as SGS0, SGS1, SGS2, and SGS3 of sub-block 102-3. The string of sub-block 102-3 can be repeated along direction 103-3 in the y direction with select lines to the selector devices 125-3-0...125-3-4 and to the selector devices 130-3-0...130-3-3 effectively along direction 103-3.

[0033] The memory array 100 can be implemented in a replacement gate (RG) NAND memory die. The term RG refers to a process of fabricating a NAND memory die, which process can also be referred to as a "gate-last" processing technique. In the RG processing technique, a sacrificial region is deposited to be later removed in processing of the memory die, followed by formation of material for transistor gates of memory cells in a string. The RG process can be used to process the SGS and SGD devices of the memory array 100.

[0034] In a non-limiting example, each of the four sub-blocks 102-0, 102-1, 102-2, and 102-3 of the memory block 101 can be structured for, but not limited to, implementing 16K x 8 data lines of 16 KB. Each of the four sub-blocks 102-0, 102-1, 102-2, and 102-3 can have 16K x 8 strings along directions 103-0, 103-1, 103-2, and 103-3, respectively, where each string is formed in a semiconductor pillar along its respective direction. Each string can have a number of horizontal levels, referred to as tiers, for example, the strings of the memory array 100 can have 128 tiers. At the tiers (horizontal levels), the strings can have memory cells, SGD, or SGS. The SGD and SGS do not share the cross sub-blocks 102-0, 102-1, 102-2, and 102-3 for reading from or writing to the memory cells. In some examples, the SGD0, SGD1, SGD2, SGD3, and SGD4 of each string can be arranged with a number of uppermost SGD, for example, SGD3 and SGD4 arranged as switches to operate as GIDL generators. The SGS0, SGS1, SGS2, and SGS3 of each string can also be arranged with a number of lowermost SGS, for example, SGS0 arranged as a switch to operate as a GIDL generator. These GIDL generators can be used to assist in accelerating the charging of the bulk of the string of memory cells in the selected sub-block during an erase operation. With SGD3 and SGD4 arranged with respect to the GIDL generators, SGD0, SGD1, and SGD2 in each string can operate as a single select gate on the drain side, and SGS1, SGS2, and SGS3 in each string can operate as a single select gate on the source side. Alternatively, SGD0, SGD1, SGD2, SGD3, and SGD4 can be arranged as a single SGD that can include GIDL functionality in an erase operation.

[0035] Figure 1Selector devices of a memory array 100 can be structured like memory cells of the memory array 100 such that common processing can be used to reduce manufacturing complexity and cost relative to using different processes for fabrication. Since each layer of the memory array is fabricated in the same way, the layer fabrication follows the way each access line or memory cell is fabricated. The structure of the memory cell effectively dictates the way the selector devices, e.g., select gates, are also fabricated. Typically, the design of the memory cell is such that the memory cell is as small as possible so that more memory cells can be stacked in a given pillar. Although the memory cells are scaled to thinner and thinner vertical levels, this scaling for the selector devices has issues associated with the responsibility of the selector devices to select the entire string. This responsibility of the selector devices can be more critical than for the conventional memory cells. Selector devices like the memory cells are built with smaller feature sizes, which can cause current leakage. With smaller channel structure features, the selector devices can not have good control to break the string. One option is to create thicker selector devices, e.g., select gates, with relatively longer channel structures. However, in this option, the selector devices and the memory cells will not have a common fabrication process, and different from the process that forms the memory cells, switches will be used to fabricate the selector devices. To use selector devices with the memory cell structure, compensation for the smaller size of the selector devices can be provided by having multiple selector devices. These multiple selector devices, e.g., on the drain side of the string, can operate as a single selector device, where only one electrical signal controls it; and in some examples, the multiple selector devices at one end of the string can operate as two or more groups that are separately operated. In such examples, each such selector device can be coupled to an individual respective select line, or each group of selector devices can be coupled to a respective select line. For example, with SGD3 and SGD4 arranged relative to a GIDL generator, Figure 1 SGD0, SGD1, and SGD2 of the memory array 100 can be electrically joined together and controlled like a single large channel structure or a single longer channel structure select gate.

[0036] "Jointed" means that the same voltage is applied to multiple components or devices that are electrically joined together or to which signals (e.g., pulses for write or read operations) are applied. Such applied pulses may be called joint pulses. An example of vertical jointing is applying the same voltage to SGD0, SGD1, and SGD2 in a single given sub-block. Vertical jointing can be performed, for example, during a read or write operation. An example of horizontal jointing is applying the same voltage to similar devices spanning sub-blocks 102-0, 102-1, 102-2, and 102-3. Horizontal jointing can be performed by applying a programming voltage (VPGM) to SGD0 in each of sub-blocks 102-0, 102-1, 102-2, and 102-3 and simultaneously applying the VPGM voltage to all SGD0 in these four sub-blocks. In this horizontal example, a VPGM driver can be selectively connected to drive four SGD0s in different sub-blocks.

[0037] When the selector devices of memory array 100 are structured as memory cells like those of memory array 100, these selector devices are programmable. After manufacturing in the production process, the selector devices are programmed once to set the threshold voltage (Vt) for the operation of the memory die. For memory cells of a memory array fabricated as charge trap structures in a vertical string, the selector devices can also be fabricated as charge trap structures in the vertical string. The charge trap structures of the memory cells and selector devices can be fabricated to have the same structural parameters, such as channel length, material, and the size of the regions of the charge trap structure. At the end of manufacturing, the selector devices are programmable to have a set Vt by controlling the charge stored in the charge trap structure that serves as the selector device. After setting, this Vt is intended to be stable at the end of the NAND memory die's lifetime. A program can be used to maintain this stability.

[0038] Figure 2 The illustration shows a side view of the top of a pillar having conductive contacts for coupling a data line to a channel structure 217. The split plug 211 comprises components shown as... Figure 2 The non-conductive regions 211-1, 211-2, 211-3, and 211-4 in the gap are separated. The gap may be filled with dielectric material. The gap may be left as a void to provide the non-conductive regions of the plug 211. Although four conductive regions are shown, the segmented plug 211 may be structured with one or more conductive regions on and in contact with the channel structure 217 and one or more non-conductive regions on and in contact with the channel structure 217, thereby providing a segmented channel structure relative to the contact associated data line. The channel structure 217 may be the channel structure in the select transistor 225 in the strut of the memory cell string. For ease of presentation, Figure 2The data lines, pillars, and structures of the select transistors 225 between the channel structures 217 and the gates 219 are not shown. The pillars can be formed vertically above the source lines as cylindrical structures or cylindrical-like structures. The cylindrical-like structures can be circular cylindrical structures or non-circular cylindrical structures. The material of the channel structures 217 can extend along the pillars, forming memory cells in the channel structures and pillars of the select gate transistors. The split plugs, such as split plug 211, can be used to plug the split data lines to the junctions 231 with the channel structures 217. Figure 1 The strings 107-0, 107-1, 107-2, and 107-3 of the memory array 100 are coupled to the data lines 110-0, 110-1, 110-2, and 110-3.

[0039] The split plug 211 can be formed to reach or exceed the junctions 231 with the channel structures 217. The channel structures 217 can be low doped channel structures that are heavily doped with respect to the channel structures 217, having Figure 2 The conductive regions 211-1, 211-2, 211-3, and 211-4 of the split plug 211 shown in FIG. 1 1 1. The channel structures 217 can be n-type material or p-type material. The conductive regions 211-1, 211-2, 211-3, and 211-4 of the split plug 211 can be structured to have n + doped material, where the channel structures 217 are n-doped material. The conductive regions 211-1, 211-2, 211-3, and 211-4 of the split plug 211 can be, but are not limited to, polysilicon material. The channel structures 217 can be, but are not limited to, polysilicon material. The use of the split plug 211 that contacts the channel structures 217 allows for an enhanced electric field to be applied that can enhance the interband tunneling in the channel structures 217. The enhancement can be several or orders of magnitude enhancement.

[0040] Figure 3 A top view of a pillar structure of the split plug 211 is shown having Figure 2 The pillar includes a core 333 that can have the select gate transistors and transistor structures of the memory cells disposed about it. The core 333 is composed of a non-conductive material, such as one or more dielectric materials. The core 333 can be, but is not limited to, an insulating oxide that fills the interior of the pillar. The oxide can be a dielectric silicon-based oxide. Figure 2 The conductive regions 211-1, 211-2, 211-3, and 211-4 of the split plug 211 shown in FIG. 1 1 1. The channel structures 217 can be n-type material or p-type material. The conductive regions 211-1, 211-2, 211-3, and 211-4 of the split plug 211 can be structured to have n Figure 2on and contact the channel structures 217. The split plugs 211 can cover the channel structures in a continuous manner in a direction similar to the periphery of the pillars forming the channel structures. For those regions of the channel structures 217 not covered by the split plugs 211, these regions can be covered by dielectric material vertically adjacent to and contacting the split plugs 211. The conductive regions 211-1, 211-2, 211-3, and 211-4 are non-continuous regions separated by non-conductive regions 337-1, 337-2, 337-3, and 337-4 of the plugs 211 with respect to one another. The non-conductive regions 337-1, 337-2, 337-3, and 337-4 can be dielectric material. In various embodiments, the dielectric material of the non-conductive regions 337-1, 337-2, 337-3, and 337-4 and the material of the core 333 can have the same material structure. Figure 2

[0041] In this top view, the structure of the top transistor of the pillar is shown, where the top transistor can be a select gate transistor. The structure shown is adjacent to the channel structure covered by the conductive regions 211-1, 211-2, 211-3, and 211-4 and the non-conductive regions 337-1, 337-2, 337-3, and 337-4. Figure 2

[0042] ​​A blocking dielectric 323 is on and contacts the charge-trap region 321. The charge-trap region 321 can be a nitride region, such as a region including dielectric silicon nitride, or other suitable dielectric region to trap charge. The charge-trap region 321 is separated from the channel structure 217 by a tunneling region 317. The tunneling region 317 can be engineered to meet selected criteria, such as but not limited to equivalent oxide thickness (EOT). In terms of representative physical thickness, EOT quantifies the electrical properties of a dielectric tunneling region 317, such as capacitance. For example, EOT can be defined as the thickness of a theoretical SiO2 layer that would be required to have the same capacitance density as a given dielectric (tunneling region 317), ignoring leakage current and reliability considerations. The tunneling region 317 can include oxides and nitrides. The tunneling region 317 can include a collection of dielectric barriers. The tunneling region 317 can be a vertical three-component tunneling region arranged as a horizontal stack from the channel structure 217 to the charge-trap region 321. The three-component tunneling region 317 can be structured with a region of dielectric oxide, then dielectric nitride, then another region of dielectric oxide. Alternatively, the tunneling region 317 can be a two-component tunneling region or a single-component tunneling region. Further, the tunneling region 317 can have four or more regions, with the selection of materials and thicknesses depending on the ability of a material having a given thickness to perform the tunneling region to the charge-trap region 321.

[0043] The junction with the channel structure at the location of the conductive region of the split plug that contacts the non-conductive region of the plug enhances the electric field at the channel structure where voltage is applied to the gate of the GIDL generator, thereby enhancing the interband charge generation in the channel structure. This results in an enhanced GIDL operation. In simulations relative to a split data line plug and a conventional data line, the interband charge generation in the channel structure at the location of the conductive region of the split plug that contacts the non-conductive region of the split plug can reach an order of magnitude greater than that of a conventional data line plug having the same doping of the plug and channel structure. The split data line plug can have an increased cut depth (i.e., the vertical extent of the conductive region of the split plug) without impacting the interband charge generation. Further enhancement of the interband charge generation can be achieved by optimizing the junction doping between the split plug and the channel structure. This combination of junction doping optimization plus plug peeling can provide enhanced future high aspect ratio layers due to the use of larger pillars of the memory cells. As taught herein, the split contact plug can be used for other applications.

[0044] Figures 4A to 4C Three different arrangements of the interface of the split plug having a channel structure of a transistor relative to the gate of the transistor are illustrated. The transistor can be used as the topmost select gate transistor of a string of memory cells in a memory array. Figure 4AAn interface 431-1 of the conductive region 411-1 of the plug having the channel structure 417-1 of the transistor is illustrated relative to an arrangement of the gate 419-1 of the transistor. The position of the interface 431-1 indicates that the junction of the conductive region 411-1 of the plug with the channel structure 417-1 is out of alignment relative to the top of the gate 419-1. This alignment relative to the doping has the interface 431-1 above the top of the gate 419-1, with the cut between the conductive regions extending vertically below the interface 431-1. A non-limiting example of the out of alignment is 5 nm.

[0045] Figure 4B An interface 431-2 of the conductive region 411-2 of the plug having the channel structure 417-2 of the transistor is illustrated relative to an arrangement of the gate 419-2 of the transistor. The position of the interface 431-2 indicates that the junction of the conductive region 411-2 of the plug with the channel structure 417-2 is in alignment relative to the top of the gate 419-2. This alignment relative to the doping has the interface 431-2 below the top of the gate 419-2, with the cut between the conductive regions ending vertically above the interface 431-2. A non-limiting example of the in alignment is 5 nm.

[0046] Figure 4C An interface 431-3 of the conductive region 411-3 of the plug having the channel structure 417-3 of the transistor is illustrated relative to an arrangement of the gate 419-3 of the transistor. The position of the interface 431-3 indicates that the junction of the conductive region 411-3 of the plug with the channel structure 417-3 is in alignment relative to the top of the gate 419-3. This alignment relative to the doping of the interface 431-3 at the top of the gate 419-3 can have the cut between the conductive regions ending in vertical alignment with the top of the gate 419-3.

[0047] Figure 5 An example of a mask 582 illustrating a pattern of split plugs having channel structures for processing select gate transistors in pillars for coupling data lines to memory arrays is illustrated. Pillars 507-0, 507-1, 507-2, 507-3, 507-4, 507-5, and 507-6 of strings of memory cells of a memory array can be formed vertically from a source line in the memory array. Memory cells and select gate devices can be formed in the pillars 507-0, 507-1, 507-2, 507-3, 507-4, 507-5, and 507-6. Select gate transistors can be formed with the same structure as the memory cells. After forming the pillars 507-0, 507-1, 507-2, 507-3, 507-4, 507-5, and 507-6 that contact the select gate transistors and the memory cells, and before forming data lines coupled to the pillars, a conductive material of the plug can be formed on the channel structure of the topmost select gate transistor.

[0048] A mask 582 having a particular pattern can be formed on the plug. The mask 582 can be used to remove portions of the conductive material in the plug, thereby forming a split plug having conductive regions separated by slots. The portions can be removed using an appropriate etching process. The slots can be filled with a dielectric material that provides contact to the channel structures of the split channel structures. The resulting split plug is a plug of conductive regions separated by regions of non-conductive material. The split plug can be implemented with the mask 582 as an additional mask to conventionally form strings of memory cells that are coupled to data lines and source lines in a memory array of a memory device. The mask 582 results in four conductive regions and four non-conductive regions for each plug. Other masks or combinations of masks can be used to result in split plugs having different numbers of conductive and non-conductive regions. Although six pillars are shown, substantially more pillars can be formed for strings of memory cells in a memory array of a memory device.

[0049] Figure 6 A functional block diagram illustrating an example memory device 600 including a memory array 602 having a plurality of memory cells 604 and one or more circuits or components to provide communication with or perform one or more memory operations on the memory array 602 is described. The memory device 600 can be a memory die, such as a NAND memory die. The memory array 602 can be similar to the memory array 100 of FIG. 1 implemented. Figure 1 The memory device 600 can include a row decoder 612, a column decoder 614, a sub- block driver 609, a sense amplifier 620, a page buffer 622, a selector 624, an I / O circuit 626, and a memory controller 630. The memory controller 630 can include processing circuitry including one or more processors 605 and can be configured to perform operations of the memory device 600 by executing instructions 615. For the purposes of this example, the instructions 615 can be executed by memory within the memory controller 630 or dedicated to the memory controller 630. In other examples, at least some portions of the instructions executed by the memory controller 630 can be stored in other memory structures and loaded into local (memory controller) memory, for example, for execution by the memory controller 630. The operations can include an erase algorithm that uses split plugs as contacts to select gate transistors between data lines and select gate transistors of strings of memory cells, as taught herein.

[0050] The memory cells 604 of the memory array 602 can be arranged in blocks, such as a first block 602A and a second block 602B. Each block can include sub-blocks. For example, the first block 602A can include a first sub-block 602A0 and a second sub-block 602A N and the second block 602B can include a first sub-block 602B0 and a second sub-block 602B NEach sub-block can include a number of physical pages, where each page includes a number of memory cells 604. Although illustrated herein as having two blocks, where each block has two sub-blocks, and each sub-block has a number of memory cells 604, in other examples, the memory array 602 can include more or fewer blocks, sub-blocks, memory cells, etc. In other examples, the memory cells 604 can be arranged in a number of rows, columns, pages, sub-blocks, blocks, etc., and accessed using, for example, access lines 606, first data lines 610, or one or more select gates, source lines, etc.

[0051] The memory controller 630 can control memory operations of the memory device 600 according to one or more signals or instructions received on control lines 632, including, for example, one or more clock signals or control signals indicative of a desired operation (e.g., write, read, erase, etc.), or address signals (AO to AX) received on one or more address lines 616. One or more devices external to the memory device 600 can control the values of the control signals on the control lines 632 or the address signals on the address lines 616. Examples of devices external to the memory device 600 can include, but are not limited to, a host, an external memory controller, a processor, or Figure 6 one or more circuits or components not illustrated in FIG. 6.

[0052] The memory device 600 can use the access lines 606 and the first data lines 610 to transfer (e.g., write or erase) data into or transfer (e.g., read) data from one or more of the memory cells 604. The row decoder 612 and the column decoder 614 can receive address signals (AO to AX) from the address lines 616 and decode them, can determine which memory cells 604 are to be accessed, and can provide signals to one or more of the access lines 606 (e.g., one or more of a plurality of access lines (WL0 to WLN)) or the first data lines 610 (e.g., one or more of a plurality of data lines (BL0 to BLN)), for example, as described above. M ) into or transfer (e.g., read) data from one or more of the memory cells 604. The row decoder 612 and the column decoder 614 can receive address signals (AO to AX) from the address lines 616 and decode them, can determine which memory cells 604 are to be accessed, and can provide signals to one or more of the access lines 606 (e.g., one or more of a plurality of access lines (WL0 to WLN)) or the first data lines 610 (e.g., one or more of a plurality of data lines (BL0 to BLN)), for example, as described above.

[0053] The memory device 600 can include sensing circuitry, such as the sense amplifiers 620, configured to determine (e.g., read) values of data on the memory cells 604 using the first data lines 610, or to determine values of data to be written to the memory cells 604. For example, in a selected string of memory cells 604, one or more of the sense amplifiers 620 can read a logic level in the selected memory cells 604 in response to a read current flowing in the memory array 602 through the selected string associated with the data line 610.

[0054] One or more devices external to the memory device 600 can communicate with the memory device 600 using the I / O lines (DQ0 through DQN) 608, the address lines 616 (A0 through AX), or the control lines 632. The I / O circuitry 626 can use the I / O lines 608 to transfer data values into or out of the memory device 600, e.g., into or out of the page buffer 622 or the memory array 602, e.g., according to the control lines 632 and the address lines 616. The page buffer 622 can store data received from one or more devices external to the memory device 600 prior to programming the data into the relevant portion of the memory array 602, or can store data read from the memory array 602 prior to transmission to one or more devices external to the memory device 600.

[0055] The column decoder 614 can receive the address signals (A0 through AX) and decode them into one or more column address signals (CSEL1 through CSEL N ). The selector 624 (e.g., a selection circuit) can receive the column selection signals (CSEL1 through CSEL N ) and select data in the page buffer 622 that represents data values to be read from or programmed into the memory cells 604. The selected data can be transferred between the page buffer 622 and the I / O circuitry 626 using the second data lines 618.

[0056] The memory controller 630 can receive positive and negative power signals, e.g., a power supply voltage (Vcc) 634 and a negative power supply (Vss) 636 (e.g., a ground potential) relative to Vcc, from an external source or power supply (e.g., an internal or external battery, an AC-to-DC converter, etc.). In certain examples, the memory controller 630 can include a regulator 628 to internally provide the positive or negative power signals.

[0057] To program or write data to the memory cells, a VPGM (e.g., one or more program pulses, etc.) can be applied to a selected access line (e.g., WL i ), and thus to the control gate of each memory cell coupled to the selected access line. For example, a program pulse can start at or near 15 V, and in certain examples, can increase in magnitude during each program pulse application. While applying the program voltage to the selected access line, a potential, e.g., a ground potential (e.g., Vss), can be applied to the data line and the substrate (and thus, the channel structure between the source and drain) of the memory cell targeted for programming, resulting in a charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the channel structure to the floating gate of the target memory cell.

[0058] In contrast, a Vpass can be applied to one or more access lines having memory cells that are not targeted for programming, or a inhibit voltage (e.g., Vcc) can be applied to data lines having memory cells that are not targeted for programming, to, for example, inhibit charge transfer from the channel structure to the floating gates of such non-target memory cells. The pass voltage can vary, for example, depending on proximity of the applied pass voltage to the access line that is targeted for programming. The inhibit voltage can include a power supply voltage (Vcc), for example, a voltage from an external source or power supply (e.g., a battery, an AC-to-DC converter, etc.) relative to a ground potential (e.g., Vss).

[0059] As an example, if a program voltage (e.g., 15V or higher) is applied to a particular access line (e.g., WL4), a pass voltage of 10V can be applied to one or more other access lines (e.g., WL3, WL5, etc.) to inhibit programming of non-target memory cells, or to preserve values stored on such memory cells that are not targeted for programming. As the distance between the applied program voltage and the non-target memory cells increases, the pass voltage needed to avoid programming the non-target memory cells can decrease. For example, where a program voltage of 15V is applied to WL4, a pass voltage of 10V can be applied to WL3 and WL5, a pass voltage of 8V can be applied to WL2 and WL6, a pass voltage of 7V can be applied to WL1 and WL7, etc. In other examples, the pass voltage or number of word lines, etc. can be higher or lower, or greater or smaller.

[0060] Between application of one or more program pulses (e.g., VPGM), a verify operation can be performed to determine whether the selected memory cells have reached their intended programmed state. If the selected memory cells have reached their intended programmed state, further programming thereof can be inhibited. If the selected memory cells have not reached their intended programmed state, additional program pulses can be applied. If the selected memory cells have not reached their intended programmed state after a particular number of program pulses (e.g., a maximum number), the selected memory cells or string, block, or page associated with such selected memory cells can be flagged as defective.

[0061] To erase a memory cell or group of memory cells (e.g., erasing is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically VPGM) can be applied (e.g., using one or more data lines, select gates, etc.) to the substrate of the memory cells targeted for erasing (and thus, the channel structure between the source and drain), while the access line of the target memory cells is held at a potential, for example, a ground potential (e.g., Vss), resulting in charge transfer (e.g., direct injection or FN tunneling, etc.) from the floating gate to the channel structure of the target memory cells.

[0062] When a host as a user device sends an address to the memory device 600, it can typically have an identification of a block, a page, and a column. The identification of a block is used to select the block of interest in an operation. The identification of a page is used to select the WL on which the page resides, and it is also used to select one particular sub-block when the WL is shared among sub-blocks of the block. The sub-block on which the page resides is decoded and selected. The address provided by the user device is used to turn on and off the selector devices and to access the memory cells. In a typical operation, only one sub-block is selected so that the SGD of one sub-block is active.

[0063] Based on the address provided by the user device, the memory controller 630 can select any one sub-block or all sub-blocks. The memory controller 630 can generate the sub-block address of the sub-block driver 609 and select any one sub-block or all sub-blocks.

[0064] The memory controller 630 can send the WL information to the row decoder 612 and the column address to the column decoder 614.

[0065] The sub-block driver 609 can include a number of independent drivers that generate the signals 613SL 0-0 …SL K-J of the select lines. For an architecture that includes a string of SGD0, SGD1, and SGD2 devices for each string, each of the SGD0, SGD1, and SGD2 devices in each sub-block has its own driver so that it can be controlled individually, so that there are three SGD drivers per sub-block. For N sub-blocks with M SGDs, there are MxN individual drivers that can be addressed. For example, for four sub-blocks with three SGDs, the sub-block driver 609 can have 12 drivers that can be addressed. There is full flexibility to turn on one SGD (SGD0, SGD1, or SGD2) in one sub-block or all sub-blocks. Similarly, there is full flexibility to turn on all SGDs (SGD0, SGD1, or SGD2) on one sub-block or all sub-blocks at the same time. Similarly, the sub-block driver 609 can include RxN drivers for R SGS devices in N sub-blocks. Multiple input signals can be assigned to each individual driver depending on different voltages designed for operation of the respective driver during erase, program, and read operations. From the sub-block driver 609, the appropriate operation signals can be sent to the memory array 602 via the select lines 613 (SL (子块#)-(SGD#或SGS#) )SL 0-0 …SL K-J .

[0066] In a typical read and write operation, the SGD0, SGD1, SGD2 devices in one sub-block can be driven by one particular regulator, while the select gates in the other sub-blocks are driven to another voltage, such as ground (0V). This is the case of vertical association, where one signal drives all the select gates in a given sub-block. The instructions to accomplish the erase verify operation can be provided by instructions 615 in the memory controller 630 on the memory device 600.

[0067] Figure 7 A flowchart of features of an embodiment of an example method 700 of forming a memory array of a memory device. At 710, a string of memory cells is formed. At 720, a transistor is formed to couple a data line to the string of memory cells. The transistor is formed with a channel structure and a gate, where the channel structure is separated from the gate. At 730, a plug is formed to couple the data line to the channel structure, where the plug covers the channel structure. The plug has one or more conductive regions that contact the channel structure and one or more non-conductive regions that contact the channel structure, such that the plug is a split contact to the channel structure. For those regions of the channel structure that are not covered by the plug, these regions can be covered by a dielectric material that is vertically adjacent and contacts the plug. Forming the one or more conductive regions can include forming four or more conductive regions. At 740, a data line is formed to couple to the plug.

[0068] Variations of the method 700 or methods similar to the method 700 can include several different embodiments that can be combined depending on the application of such a method and / or the architecture of a memory device implementing such a method. Such a method can include selecting a first dopant for the one or more conductive regions and a second dopant for the channel structure relative to a junction between the one or more conductive regions and the channel structure, such that the first dopant and the second dopant have properties that enhance band-to-band tunneling characteristics in operation of the transistor in addition to the split contact provided by the plug. Variations can include forming the channel structure to enclose a core of the dielectric material and forming the one or more non-conductive regions to be composed of the dielectric material.

[0069] Variations of the method 700 or methods similar to the method 700 can include forming the one or more conductive regions of the plug to have a first dopant and forming the channel structure to have a second dopant, such that the one or more conductive regions are more heavily doped relative to the channel structure. Forming the one or more conductive regions can include forming the one or more conductive regions to have a tip of the first dopant that is aligned with or above a top level of the gate. Forming the one or more conductive regions can include forming the one or more conductive regions to have a slot between the one or more conductive regions, such that a tip of the slot is aligned with or above the top level of the gate.

[0070] Figure 8To form a plug to couple a data line to a channel structure of a transistor, a flowchart of features of an embodiment of an example method 800 of providing a split contact to a channel structure. The method 800 can be used for the method 700 or a method similar to the method 700. At 810, for one or more conductive regions of the plug, conductive material is formed on and contacting a channel structure of a transistor. At 820, a mask is formed on the conductive material. At 830, portions of the conductive material from a top of the conductive material to the channel structure are removed. The removal can be performed using an appropriate etching process. The removed portions of the conductive material serve to form a slot in the conductive material where the conductive material of the plug does not contact the channel structure. At 840, non-conductive material is formed on and contacting the channel structure in the slot to form one or more non-conductive regions of the plug. Forming the non-conductive material on and contacting the channel structure forms the plug as a split contact to the channel structure.

[0071] In various embodiments, a memory device includes a string of memory cells, a transistor to couple a data line to the string of memory cells. The transistor has a channel structure and a gate, where the channel structure is separated from the gate. The memory device includes a plug to couple the data line to the channel structure of the transistor. The plug can cover the channel structure, where the plug has one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure, such that the plug is a split contact between the data line and the channel structure. The one or more conductive regions of the plug can be doped relative to a doping concentration of the channel structure.

[0072] Variations of such a memory device or similar memory devices can include a number of different embodiments that can be combined depending on the application of such a memory device and / or the architecture in which such a memory device is implemented. Such a memory device can include an end of the heavily doped conductive region of the one or more conductive regions aligned with a top level of the gate. In another embodiment, the end of the heavily doped conductive region of the one or more conductive regions is above a top level of the gate. Alternatively, the end of the heavily doped conductive region of the one or more conductive regions is below a top level of the gate. Variations can include an end of the one or more non-conductive regions of the plug aligned with a top of the gate. Variations can include the one or more conductive regions having four or more conductive regions.

[0073] A material of a channel structure of a transistor coupled to a string extends to a memory cell and through a memory cell of the string as a channel structure of the memory cell, where the channel structure of the transistor and the memory cell is structured as a cylindrical-like region in a pillar above a substrate. The channel structure can enclose a core of dielectric material, where the one or more non-conductive regions of the plug include the dielectric material.

[0074] In various embodiments, a memory system includes a plurality of memory devices. One or more of the memory devices can include a data line and a memory array having strings of memory cells, where each string is formed in a pillar and is coupled to a transistor formed in the pillar. The transistor is arranged to couple the string to one of the data lines, where the transistor has a channel structure and a gate, where the channel structure is separated from the gate. The transistor can be structured where the channel structure contacts a plug to couple to the data line, where the plug covers the channel structure. The plug can have one or more conductive regions that contact the channel structure and one or more non-conductive regions that contact the channel structure, such that the plug is a split contact between the data line and the channel structure. For those regions of the channel structure that are not covered by the plug, these regions can be covered by a dielectric material that is vertically adjacent and contacts the plug. One or more of the memory devices include a memory controller that includes processing circuitry including one or more processors. The memory controller can be configured to perform an erase operation that includes performing an erase operation on a selected string of the memory array by applying an erase voltage to the gate of the transistor that couples the selected string to a data line associated with the selected string. The erase operation can be applied to a plurality of memory array strings.

[0075] Variations of such a memory system or similar memory systems can include several different embodiments that can be combined depending on the application of such a memory system and / or the architecture in which such a memory system is implemented. Such a memory system can include one or more conductive regions of the plug that are heavily doped relative to the doping of the channel structure. Variations can include an end of the heavily doped conductive region of the one or more conductive regions that is aligned with a top level of the gate. In another embodiment, an end of the heavily doped conductive region of the one or more conductive regions is above a top level of the gate. Variations can include an end of the one or more non-conductive regions of the plug that is aligned with a top of the gate. Variations can include a number of the one or more conductive regions that is four. More or less than four conductive regions can be used.

[0076] Electronic devices such as mobile electronic devices (e.g., smartphones, tablet computers, etc.), electronic devices for automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and internet-connected appliances or devices (e.g., Internet of Things (IoT) devices, etc.) have varying storage needs, among other things, depending on the type of electronic device, the usage environment, performance expectations, etc.

[0077] An electronic device can be decomposed into several major components: a processor (e.g., a central processing unit (CPU) or other main processor); a memory (e.g., one or more volatile or non-volatile RAM memory devices such as DRAM, mobile or low power double data rate synchronous DRAM (DDR SDRAM), etc.); and a storage device (e.g., a non-volatile memory (NVM) device such as flash memory, ROM, SSD, MMC, or other memory card structure or assembly, etc.). In certain examples, an electronic device can include a user interface (e.g., a display, a touchscreen, a keyboard, one or more buttons, etc.), a graphics processing unit (GPU), a power management circuit, a baseband processor or one or more transceiver circuits, etc.

[0078] Figure 9 A block diagram of an example machine having one or more memory devices structured to enhance interband tunneling in select gate transistors that couple data lines to strings of memory cells in a memory array of the one or more memory devices during erase operations. The machine 900 having one or more such memory devices can operate as a standalone machine or can be connected, e.g., networked to other machines.

[0079] In a networked deployment, the machine 900 can operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine 900 can act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine 900 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, an IoT device, an automotive system, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations. The example machine 900 can be arranged to operate with one or more memory devices having split channel structures for topmost select gate transistors that couple strings of memory cells to associated data lines in the one or more memory devices as taught herein. The example machine 900 can include one or more memory devices having structures as discussed with respect to Figure 1 the memory array 100 and split plug 211 structures associated with Figure 2 and 3 the memory device 600. Figure 6

[0080] ​Examples, as described herein, can include, or can operate by, logic, components, devices, packages, or mechanisms. Circuitry is a collection of circuits (e.g., package, component, module, circuitry, implementation, etc.) implemented in tangible

[0081] Machine (e.g., computer system) 900 can include a hardware processor 950 (e.g., a CPU, a GPU, a hardware processor core, or any combination thereof), main memory 954 and static memory 956, some or all of which can communicate with one another via an interlink (e.g., bus) 958. The machine 900 can further include a display device 960, an alphanumeric input device 962 (e.g., a keyboard), and a user interface (UI) navigation device 964 (e.g., a mouse). In an example, the display device 960, input device 962 and UI navigation device 964 can be a touch screen display. The machine 900 can additionally include a storage device (e.g., drive unit) 951, a signal generation device 968 (e.g., a speaker), a network interface device 953, and one or more sensors 966, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine 900 can include an output controller 969, such as a serial (e.g., USB, parallel, or other wired or wireless (e.g., infrared(IR), near field communication(NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

[0082] The machine 900 can include a machine-readable medium 952 on which is stored one or more sets of data structures or instructions 955 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 955 can also reside completely, or at least partially, within the main memory 954, static memory 956, mass storage device(s) 951, or hardware processor 950 during execution, or any combination thereof. In an example, one or any combination of the hardware processor 950, the main memory 954, the static memory 956, or the mass storage device(s) 951 can constitute machine-readable media.

[0083] Although the machine-readable medium 952 is illustrated as a single medium, the term "machine-readable medium" can include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store the one or more instructions 955. The term "machine-readable medium" can include any medium that is capable of storing or encoding a set of instructions for execution by the machine 900 and that cause the machine 900 to perform any one or more of the techniques of the present disclosure, or that are capable of storing or encoding data structures utilized by or associated with such instructions. Non-limiting machine-readable medium examples can include solid-state memories, and optical and magnetic media. In an example, a centralized machine-readable medium includes a machine-readable medium having a plurality of particles having invariant (e.g., rest) mass. Accordingly, centralized machine-readable media do not transiently propagate signals. Particular examples of centralized machine-readable media can include nonvolatile memory, such as semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices); magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0084] Instructions 955 (e.g., software, programs, operating systems (OS), etc.) or other data stored on mass storage device 951 can be accessed by main memory 954 for use by processor 950. Main memory 954 (e.g., DRAM) is typically fast but volatile, and is therefore a different type of memory from mass storage device 951 (e.g., SSD), which is suitable for long-term storage, including when in a "disconnected" state. Instructions 955 or data for use by the user or machine 900 are typically loaded into main memory 954 for use by processor 950. When main memory 954 is full, virtual space from mass storage device 951 can be allocated to supplement main memory 954; however, because mass storage device 951 is typically slower than main memory 954 and its read speed is at least twice as fast as its write speed, the use of virtual memory can significantly degrade the user experience due to storage device latency (compared to main memory 954, such as DRAM). Furthermore, the use of a large-capacity storage device 951 for virtual memory may greatly shorten the lifespan of the large-capacity storage device 951.

[0085] Compared to virtual memory, virtual memory compression (e.g., The kernel feature “ZRAM” uses portions of memory as compressed blocks to avoid paging to data storage device 951. Paging occurs within the compressed blocks until it is necessary to write such data to mass storage device 951. Virtual memory compression increases the available size of main memory 954 while reducing wear and tear on mass storage device 951.

[0086] Storage devices optimized for mobile electronic devices or mobile storage devices traditionally include MMC solid-state storage devices (e.g., microSD cards). TM (e.g., cards, etc.) MMC devices contain several parallel interfaces (e.g., 8-bit parallel interfaces) with the host device and are typically removable and detachable components from the host device. In contrast, eMMC... TM The device, attached to a circuit board and considered a component of the host device, boasts read speeds comparable to SATA-based SSDs. However, the demand for mobile device performance continues to grow to fully enable virtual or augmented reality devices, take advantage of increased network speeds, and so on. In response to this demand, storage devices have shifted from parallel to serial communication interfaces. UFS devices, including controllers and firmware, communicate with host devices using a Low Voltage Differential Signaling (LVDS) serial interface with dedicated read / write paths, further advancing read / write speeds.

[0087] The instructions 955 can further be transmitted or received over a communications network 959 using a transmission medium via the network interface device 953 utilizing any one of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks can include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as Wi-Fi®, IEEE 802.16 family of standards known as WiMax®), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, among others. In an example, the network interface device 953 can include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to the communications network 959. In an example, the network interface device 953 can include a plurality of antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term "transmission medium" shall be taken to include any intangible medium that is capable of storing, communicating, and / or carrying the instructions 955 for use by or in connection with the machine 900, including digital or analog communications signals or IEEE 802.16 family of standards, known as WiMAX® ), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, among others. In an example, the network interface device 953 can include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to the communications network 959. In an example, the network interface device 953 can include a plurality of antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term "transmission medium" shall be taken to include any intangible medium that is capable of storing, communicating, and / or carrying the instructions 955 for use by or in connection with the machine 900, including digital or analog communications signals or

[0088] The following are example embodiments of devices and methods according to the teachings herein.

[0089] An example memory device 1 can include a string of memory cells, a data line, a transistor coupling the data line to the string of memory cells, the transistor having a channel structure and a gate, the channel structure being separate from the gate, and a plug coupling the data line to the channel structure, wherein the plug covers the channel structure, the plug having one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure, such that the plug is a split contact between the data line and the channel structure.

[0090] An example memory device 2 can include features of example memory device 1 and can include one or more conductive regions of the plug that are more heavily doped relative to a doping of the channel structure.

[0091] An example memory device 3 can include features of example memory device 2 and example memory device 1 and can include an end of a heavily doped conductive region of the one or more conductive regions aligned with a top level of the gate.

[0092] Example memory device 4 can include features of example memory device 2 and any of memory devices 1 and 3, and can include ends of heavily doped conductive regions of one or more conductive regions above a top level of gates.

[0093] Example memory device 5 can include features of example memory device 2 and any of memory devices 1, 3, and 4, and can include ends of heavily doped conductive regions of one or more conductive regions below a top level of gates.

[0094] Example memory device 6 can include features of any of the preceding example memory devices, and can include one or more conductive regions to include four or more conductive regions.

[0095] Example memory device 7 can include features of any of the preceding example memory devices, and can include a material of a channel structure of a transistor that extends to a memory cell and through the memory cell as a channel structure of the memory cell, where the channel structure of the transistor and the memory cell structure are structured as cylindrical-like regions in a pillar above a substrate.

[0096] Example memory device 8 can include features of any of the preceding example memory devices, and can include a channel structure that encloses a core of a dielectric material and one or more non-conductive regions that include the dielectric material.

[0097] In example memory device 9, any of the memory devices in example memory devices 1-8 can include a memory device incorporated into an electronic memory apparatus that further comprises a host processor and a communication bus extending between the host processor and the memory device.

[0098] In example memory device 10, any of the memory devices in example memory devices 1-9 can be modified to include any structure presented in another of example memory devices 1-9.

[0099] In example memory device 11, any of the memory devices in example memory devices 1-10 can be modified to include any structure presented in another of example memory devices 1-10.

[0100] In example memory device 12, any apparatus associated with a memory device in example memory devices 1-11 can further include a machine-readable storage configured to store instructions as physical states, where the instructions can be used to perform one or more operations of the apparatus.

[0101] In example memory device 13, any of the memory devices in example memory devices 1-12 can be operated in accordance with any of the following example methods 1-11.

[0102] An example memory device 14 can include a memory system including a plurality of memory devices, wherein one or more of the memory devices includes a data line, a memory array having strings of memory cells, wherein each string is formed in a pillar and is coupled to a transistor formed in the pillar, the transistor coupling the string to one of the data lines, the transistor having a channel structure and a gate, the channel structure being separated from the gate, the transistor being structured with a contact plug to couple to the channel structure of the data line, wherein the plug covers the channel structure, the plug having one or more conductive regions that contact the channel structure and one or more non-conductive regions that contact the channel structure, such that the plug is a split contact between the data line and the channel structure, and a memory controller including processing circuitry including one or more processors, the memory controller configured to perform operations including performing an erase operation on a selected string of the memory array by applying an erase voltage to the gate of the transistor that couples the selected string to a data line associated with the selected string.

[0103] An example memory device 15 can include features of example memory device 14 and can include one or more conductive regions of the plug that are more heavily doped relative to a doping of the channel structure.

[0104] An example memory device 16 can include features of memory device 15 and features of example memory device 14 and can include an end of one or more conductive regions that are more heavily doped conductive regions aligned with a top level of the gate.

[0105] An example memory device 17 can include features of memory device 15 and features of example memory devices 14 and 16 and can include an end of one or more conductive regions that are more heavily doped conductive regions above a top level of the gate.

[0106] An example memory device 18 can include features of any of the preceding example memory devices 14-17 and can include one or more conductive regions that are four in number.

[0107] In example memory device 19, any of the memory devices in example memory devices 14-18 can include a memory device incorporated into an electronic memory apparatus that further includes a host processor and a communication bus extending between the host processor and the memory device.

[0108] In example memory device 20, any of the memory devices in example memory devices 14-19 can be modified to include any structure presented in another of example memory devices 14-19.

[0109] In example memory device 21, any of the devices associated with the memory devices in example memory devices 14-20 can further include a machine-readable storage configured to store instructions as physical states, where the instructions can be used to perform one or more operations of the device.

[0110] In example memory device 22, any of the memory devices in example memory devices 14-21 can operate according to any of the following example methods 1-11.

[0111] Example method 1 of forming a memory array of a memory device can include forming a string of memory cells; forming a transistor to couple a data line to the string of memory cells, including forming the transistor with a channel structure and a gate, the channel structure being separate from the gate; forming a plug to couple the data line to the channel structure, where the plug covers the channel structure such that the plug has one or more conductive regions that contact the channel structure and one or more non-conductive regions that contact the channel structure such that the plug is a split contact to the channel structure; and forming the data line coupled to the plug.

[0112] Example method 2 of forming a memory array of a memory device can include the features of example method 1 of forming a memory array of a memory device, and can include forming the plug to include: forming a conductive material on the channel structure and contacting the channel structure for the one or more conductive regions; forming a mask on the conductive material; removing portions of the conductive material from a top of the plug to the channel structure, forming a slot in the plug, where the conductive material of the plug does not contact the channel structure; and forming a non-conductive material on the channel structure and in the slot contacting the channel structure to form the one or more non-conductive regions of the plug.

[0113] Example method 3 of forming a memory array of a memory device can include the features of any of the preceding example methods of forming a memory array of a memory device, and can include selecting a first dopant for the one or more conductive regions and a second dopant for the channel structure relative to a junction between the one or more conductive regions and the channel structure such that the first dopant and the second dopant have properties that enhance interband tunneling characteristics in operation of the transistor in addition to the split contact provided by the plug.

[0114] Example method 4 of forming a memory array of a memory device can include the features of any of the preceding example methods of forming a memory array of a memory device, and can include forming the one or more conductive regions to include forming four or more conductive regions.

[0115] Example method 5 of forming a memory array of a memory device can include the features of any of the preceding example methods of forming a memory array of a memory device, and can include forming the channel structure to enclose a core of dielectric material, and forming the one or more non-conductive regions to be composed of the dielectric material.

[0116] Example method 6 of forming a memory array of a memory device can include features of any of the foregoing example methods of forming a memory array of a memory device, and can include forming one or more conductive regions with a first dopant, and forming a channel structure with a second dopant, such that the one or more conductive regions are doped relative to a doping density of the channel structure.

[0117] Example method 7 of forming a memory array of a memory device can include features of example method 6 of forming a memory array of a memory device and any of the foregoing example methods of forming a memory array of a memory device, and can include forming one or more conductive regions to include forming one or more conductive regions with a first dopant aligned with or above a top level of a gate.

[0118] In example method 8 of forming a memory array of a memory device, any of example methods 1-7 of forming a memory array of a memory device can be performed in an electronic memory apparatus further comprising a host processor and a communication bus extending between the host processor and the memory device.

[0119] In example method 9 of forming a memory array of a memory device, any of example methods 1-8 of forming a memory array of a memory device can be modified to include operations set forth in any of the other ones of example methods 1-6 of forming a memory array of a memory device.

[0120] In example method 10 of forming a memory array of a memory device, any of example methods 1-9 of forming a memory array of a memory device can be implemented at least in part by use of instructions stored as physical states in one or more machine-readable storage devices.

[0121] Example method 11 of forming a memory array of a memory device can include features of any of the foregoing example methods 1-10 of forming a memory array of a memory device and can include performing functions associated with any features of example memory devices 1-22.

[0122] Example machine-readable storage device 1 storing instructions can include instructions to perform functions associated with any features of example memory devices 1-13 and memory devices 14-22 or to perform methods associated with any features of example methods 1-11, which when executed by one or more processors cause a machine to perform operations.

[0123] While specific embodiments have been illustrated and described herein, it will be appreciated that any arrangement of the application purposely implemented to achieve the same purpose can substitute for the specific embodiments shown. Various embodiments use permutations and / or combinations of the embodiments described herein. The foregoing description is intended to be illustrative rather than limiting, and the word "comprising" or variations such as "comprise" or "comprises" is not used herein as a limitation. Furthermore, in the foregoing description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without some or all of these specific details.

Claims

1. A memory device comprising: a string of memory cells; a data line; a transistor coupling the data line to the string of memory cells, the transistor having a channel structure and a gate, the channel structure being separate from the gate; and a plug coupling the data line to the channel structure, wherein the plug covers the channel structure, the plug having one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure, such that the plug is a split contact between the data line and the channel structure.

2. The memory device of claim 1, wherein the one or more conductive regions of the plug are doped relative to a doping heaviness of the channel structure.

3. The memory device of claim 2, wherein an end of a heavily doped conductive region of the one or more conductive regions aligns with a top level of the gate.

4. The memory device of claim 2, wherein an end of a heavily doped conductive region of the one or more conductive regions is above a top level of the gate.

5. The memory device of claim 2, wherein an end of a heavily doped conductive region of the one or more conductive regions is below a top level of the gate.

6. The memory device of claim 1, wherein the one or more conductive regions include four or more conductive regions.

7. The memory device of claim 1, wherein a material of the channel structure of the transistor extends to the memory cell and through the memory cell as a channel structure of the memory cell, wherein the channel structure of the transistor and the memory cell are structured as cylindrical-like regions in a pillar above a substrate.

8. The memory device of claim 1, wherein the channel structure encloses a core of dielectric material, and the one or more non-conductive regions include the dielectric material.

9. A memory system comprising: a plurality of memory devices, wherein one or more of the memory devices include: a data line; a memory array having strings of memory cells, wherein each string is formed in a pillar and is coupled to a transistor formed in the pillar, the transistor coupling the string to one of the data lines, the transistor having a channel structure and a gate, the channel structure being separate from the gate, the transistor being structured with a contact plug to couple to the channel structure of the data line, wherein the plug covers the channel structure, the plug having one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure, such that the plug is a split contact between the data line and the channel structure; and a memory controller including processing circuitry including one or more processors, the memory controller configured to perform operations including performing an erase operation on a selected string of the memory array by applying an erase voltage to the gate of the transistor coupling the selected string to the data line associated with the selected string.

10. The memory system of claim 9, wherein the one or more conductive regions of the plug are heavily doped relative to a doping of the channel structure.

11. The memory system of claim 10, wherein an end of a heavily doped conductive region of the one or more conductive regions is aligned with a top level of the gate.

12. The memory system of claim 10, wherein an end of a heavily doped conductive region of the one or more conductive regions is above a top level of the gate.

13. The memory system of claim 9, wherein a number of the one or more conductive regions is four.

14. A method of forming a memory array of a memory device, the method comprising: forming a string of memory cells; forming a transistor to couple a data line to the string of memory cells, including forming the transistor with a channel structure and a gate, the channel structure being separate from the gate; forming a plug to couple the data line to the channel structure, wherein the plug covers the channel structure such that the plug has one or more conductive regions that contact the channel structure and one or more non-conductive regions that contact the channel structure, such that the plug is a split contact to the channel structure; and forming the data line to couple to the plug.

15. The method of claim 14, wherein forming the plug includes: forming a conductive material of the one or more conductive regions on and contacting the channel structure; forming a mask on the conductive material; removing portions of the conductive material from a top of the plug to the channel structure, forming a slot in the plug where the conductive material of the plug does not contact the channel structure; and forming a non-conductive material on and in the slot of the channel structure that contacts the channel structure to form the one or more non-conductive regions of the plug.

16. The method of claim 14, wherein the method includes selecting a first dopant for the one or more conductive regions and a second dopant for the channel structure relative to a junction between the one or more conductive regions and the channel structure, such that the first dopant and the second dopant have properties that enhance band-to-band tunneling characteristics in operation of the transistor in addition to the split contact provided by the plug.

17. The method of claim 14, wherein forming the one or more conductive regions includes forming four or more conductive regions.

18. The method of claim 14, wherein the method includes forming the channel structure to enclose a core of dielectric material, and forming the one or more non-conductive regions to be composed of the dielectric material.

19. The method of claim 14, wherein the method includes forming the one or more conductive regions of the plug to have a first dopant, and forming the channel structure to have a second dopant, such that the one or more conductive regions are heavily doped relative to a doping of the channel structure.

20. The method of claim 19, wherein forming the one or more conductive regions includes forming the one or more conductive regions with an end of the first dopant aligned with or above a top level of the gate.

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