Semiconductor chip, processed wafer, and method of manufacturing a semiconductor chip

Abstract

A method of manufacturing a semiconductor chip includes: preparing a GaN wafer; manufacturing a processed wafer to have a plurality of chip formation regions adjacent to a first surface of the processed wafer by forming an epitaxial film on a surface of the GaN wafer; forming a first surface side element part of a semiconductor element in each chip formation region; forming a wafer transformation layer in a planar direction of the processed wafer by irradiating an inside of the processed wafer with a laser beam from a second surface of the processed wafer; dividing the processed wafer into a chip formation wafer and a recovery wafer at the wafer transformation layer; taking out a semiconductor chip from the chip formation wafer; and after the preparing of the GaN wafer and before the dividing of the processed wafer, forming a mark in an inside of one of the gallium nitride wafer or the processed wafer by irradiating with the laser beam, the mark being formed from a deposition of gallium.

Description

Technical Field

[0001] This disclosure relates to a semiconductor chip made of gallium nitride (hereinafter also referred to as GaN), a processed wafer, and a method for manufacturing said semiconductor chip. Background Technology

[0002] It is known to use GaN wafers to manufacture semiconductor chips. For example, JP 2015-119087 A describes forming identification marks on GaN wafers. Specifically, the marks are formed by using a laser beam to perform a process of forming a recess on the surface of the GaN wafer and then polishing the surface of the GaN wafer to retain the recess. Summary of the Invention

[0003] In fact, GaN wafers are very fragile. Therefore, when a recess is formed on a GaN wafer, there is a problem that cracks may originate from the recess.

[0004] One object of this disclosure is to provide a semiconductor chip, a processed wafer, and a method for manufacturing a semiconductor chip, which are able to suppress breakage while forming identification marks.

[0005] According to one aspect of this disclosure, the method relates to a method for manufacturing a semiconductor chip on which semiconductor elements are formed. The method includes: preparing a gallium nitride wafer made of gallium nitride; manufacturing a processed wafer by forming an epitaxial film on the surface of the gallium nitride wafer, wherein the processed wafer has a first surface on the epitaxial film side and a second surface on the gallium nitride wafer side, and the processed wafer includes a plurality of chip forming regions adjacent to the first surface of the processed wafer; forming a first surface-side element component of a semiconductor element in each of the plurality of chip forming regions; and irradiating the interior of the processed wafer from the second surface side of the processed wafer with a laser beam along the... A wafer transformation layer is formed in the planar direction of the processed wafer, wherein the nitride and gallium are separated; the processed wafer is divided into a wafer forming wafer including a first surface of the processed wafer and a recycling wafer including a second surface of the processed wafer by means of the wafer transformation layer; a semiconductor chip is removed from the wafer forming wafer; and, after the preparation of the gallium nitride wafer and before the division of the processed wafer, a mark is formed inside the gallium nitride wafer and the processed wafer by irradiating the interior of one of the gallium nitride wafer and the processed wafer with a laser beam, the mark being formed by gallium deposition.

[0006] In this method, the marking is provided by gallium deposited inside the processed wafer, and no recesses as markings are formed on the processed wafer. Therefore, it is possible to suppress the processing wafer from cracking at the marking.

[0007] According to one aspect of this disclosure, a processed wafer includes a semiconductor chip on which semiconductor elements are formed. The processed wafer includes a gallium nitride wafer, an epitaxial film disposed on the surface of the gallium nitride wafer, and a marking disposed inside at least one of the gallium nitride wafer and the epitaxial film, the marking being provided by gallium deposition.

[0008] In this structure, the marking is provided by gallium deposited inside the processed wafer, and no recesses as markings are formed on the processed wafer. Therefore, it is possible to suppress the processing wafer from cracking at the marking.

[0009] According to one aspect of this disclosure, a semiconductor chip includes: a chip constituting substrate made of gallium nitride having a first surface and a second surface opposite to the first surface, and including semiconductor elements; and a mark disposed inside the chip constituting substrate, the mark being a gallium deposit.

[0010] In this structure, the marking is provided by gallium deposited inside the processed wafer, and no recesses are formed on the processed wafer. Therefore, it is possible to suppress the semiconductor chip from cracking starting from the marking. Attached Figure Description

[0011] The object, features and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings, in which like parts are indicated by like reference numerals and wherein:

[0012] Figure 1A This is a cross-sectional view illustrating the manufacturing process of a semiconductor chip according to a first embodiment of the present disclosure;

[0013] Figure 1B The diagram is in Figure 1A A cross-sectional view of the subsequent semiconductor chip manufacturing process;

[0014] Figure 1C The diagram is in Figure 1B A cross-sectional view of the subsequent semiconductor chip manufacturing process;

[0015] Figure 1D The diagram is in Figure 1C A cross-sectional view of the subsequent semiconductor chip manufacturing process;

[0016] Figure 1E The diagram is in Figure 1D A cross-sectional view of the subsequent semiconductor chip manufacturing process;

[0017] Figure 1F The diagram is in Figure 1E A cross-sectional view of the subsequent semiconductor chip manufacturing process;

[0018] Figure 1G The diagram is in Figure 1F A cross-sectional view of the subsequent semiconductor chip manufacturing process;

[0019] Figure 1H The diagram is in Figure 1G A cross-sectional view of the subsequent semiconductor device manufacturing process;

[0020] Figure 1I The diagram is in Figure 1H A cross-sectional view of the subsequent semiconductor chip manufacturing process;

[0021] Figure 1J The diagram is in Figure 1I A cross-sectional view of the subsequent semiconductor chip manufacturing process;

[0022] Figure 1K The diagram is in Figure 1J A cross-sectional view of the subsequent semiconductor chip manufacturing process;

[0023] Figure 1L The diagram is in Figure 1K A cross-sectional view of the subsequent semiconductor chip manufacturing process;

[0024] Figure 2A This is a schematic diagram of a structure where a wafer transformation layer is formed but a chip transformation layer is not formed; and

[0025] Figure 2B This is a schematic diagram of the structure after the chip transformation layer is formed, in the case where the wafer transformation layer is formed. Detailed Implementation

[0026] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. In the embodiments described below, the same or equivalent parts are indicated by the same reference numerals.

[0027] (First Embodiment)

[0028] The first embodiment will be described with reference to the accompanying drawings. Hereinafter, a method for manufacturing a semiconductor chip 100 will be described, wherein semiconductor elements are formed on a chip fabrication substrate 110 comprising GaN.

[0029] First, such as Figure 1A As shown, a bulk wafer shape GaN wafer 1 is fabricated. GaN wafer 1 has a first surface 1a and a second surface 1b. For example, as GaN wafer 1, a material doped with silicon, oxygen, germanium, etc., and having a surface area of ​​5 × 10⁻⁶ mm is used. 17 cm -3 Up to 5×1019 cm -3 The GaN wafer 1 has an impurity concentration of [specific value]. The thickness of the GaN wafer 1 can be arbitrary. For example, a wafer with a thickness of approximately 400 μm is prepared as GaN wafer 1. In the GaN wafer 1 of this embodiment, the first surface 1a is a Ga surface, and the second surface 1b is an N surface. Further, after performing the manufacturing process of the semiconductor chip 100 described below, [the impurity concentration is determined by] recycling [the impurity concentration]. Figure 1L The recycled wafer 40 is used to prepare GaN wafer 1, which will be described later.

[0030] The second surface 1b of the GaN wafer 1 is ground or polished when necessary, so that the second surface 1b has a surface roughness of 10 nm or less. As a result, when a laser beam L is applied to the second surface 1b side of the GaN wafer 1, as described later, the laser beam L is less likely to cause diffuse reflection on the second surface 1b of the GaN wafer 1.

[0031] Next, as Figure 1B As shown, a laser beam L is applied to the second surface 1b of a GaN wafer 1 to form a wafer mark WM inside the GaN wafer 1, for example, to identify the lot number of the wafer 1. Specifically, a laser device is fabricated having a laser source, a dichroic mirror, a focusing lens, a movable stage, etc. The laser source causes the laser beam L to oscillate. The dichroic mirror is arranged to change the direction of the optical axis (i.e., the optical path) of the laser beam L. The focusing lens (i.e., the focusing system) is arranged to converge the laser beam L. When forming the wafer mark WM, the GaN wafer 1 is placed on the stage, and the position of the stage, etc., is adjusted so that the convergence point of the laser beam L is set to a predetermined position within the GaN wafer 1.

[0032] In GaN wafer 1, gallium and nitrogen atoms are separated by thermal energy. Simultaneously with gallium deposition, nitrogen evaporates into gas. As a result, a wafer marker WM is formed through gallium deposition. In this embodiment, the position of the formed wafer marker WM is adjusted such that after the processed wafer 10 (described later) is divided into chip forming wafer 30 and recycled wafer 40, the wafer marker WM remains on the recycled wafer 40 side.

[0033] The wafer marker WM can have any identifiable shape or pattern, such as lines or polygons, or numbers. While not particularly limited, a solid-state laser beam, such as a green laser beam with a wavelength of 532 nm, is used as the laser beam L to form the wafer marker WM in this embodiment. The laser beam L is emitted with a processing point output of 2 μJ, a pulse width of 500 ps, ​​and a processing speed of 500 mm / s. However, these conditions are merely examples, and the inventors of this application have confirmed that wafer markers can be properly formed even when the processing point output of the laser beam L is reduced or even when the pulse width is narrowed. Furthermore, the inventors of this application have confirmed that wafer marker WMs can be properly formed even when the processing point output of the laser beam L is increased or even when the pulse width is increased.

[0034] After forming the wafer marker WM, GaN wafer 1 is heat-treated to promote gallium deposition and improve the visibility of the wafer marker WM. In this case, GaN wafer 1 without semiconductor devices is heat-treated. Therefore, the heat treatment temperature is equal to or higher than the melting point of gallium (i.e., 29.76°C) and equal to or lower than 1000°C.

[0035] Next, as Figure 1C As shown, a processed wafer 10 having multiple chip formation regions RA is prepared by forming an epitaxial film 3 on the first surface 1a of a GaN wafer 1. The epitaxial film 3 is made of GaN with a thickness of approximately 10 μm to 60 μm. In this embodiment, a wafer marker WM has been formed inside the GaN wafer 1. Therefore, the processed wafer 10 is configured with a wafer marker formed inside.

[0036] In this embodiment, n is deposited sequentially on GaN wafer 1. + Type epitaxial layers 3a and n - The epitaxial layer 3b forms the epitaxial film 3. For example, n + The epitaxial layer 3a is doped with silicon, oxygen, germanium, etc., and has a density of approximately 5 × 10⁻⁶. 17 cm -3 Up to 1×10 18 cm -3 The concentration of impurities. - The epitaxial layer 3b is doped with silicon and has a density of approximately 1 × 10⁻⁶. 17 cm -3 Up to 4×10 17 cm -3 The concentration of impurities.

[0037] n - The epitaxial layer 3b is the portion in which the first surface-side element component 11 (e.g., diffusion layer 12), described later, is formed. For example, n- The epitaxial layer 3b has a thickness of approximately 8 μm to 10 μm. + The epitaxial layer 3a is the portion used to ensure the thickness of the semiconductor chip 100, and will be described later. For example, n + The epitaxial layer 3a has a thickness of approximately 40 μm to 50 μm. + The thickness of epitaxial layer 3a and n - The thickness of the epitaxial layer 3b can be arbitrary. In this case, for example, n + Type epitaxial layer 3a ratio n - The epitaxial layer 3b is thick to ensure the thickness of the semiconductor chip 100. In the following text, the surface of the processed wafer 10 on the side of the epitaxial film 3 is referred to as the first surface 10a of the processed wafer 10, and the surface of the processed wafer 10 on the side of the GaN wafer 1 is referred to as the second surface 10b of the processed wafer 10. The chip formation region RA is formed adjacent to the first surface 10a of the processed wafer 10.

[0038] Next, as Figure 1D As shown, general semiconductor manufacturing processes are performed. In each chip formation region RA, processes for forming first surface-side element components 11 of a semiconductor element, such as a diffusion layer 12, a gate electrode 13, a surface electrode (not shown), a wiring pattern (not shown), and a passivation film (not shown), are performed. In this case, devices with various configurations are employed as semiconductor elements. Examples of semiconductor elements include power devices such as high electron mobility transistors (HEMTs) and optical semiconductor elements such as light-emitting diodes. Subsequently, if desired, a surface protective film made of a resist or the like is formed on the first surface 10a of the processed wafer 10.

[0039] Subsequently, as Figure 1E As shown, a holding member 20 is formed adjacent to the first surface 10a of the processed wafer 10a. As the holding member 20, for example, a dicing tape having a substrate 21 and an adhesive 22 may be used. The substrate 21 is made of a material that is not easily warped during manufacturing. For example, the substrate 21 may be made of glass, a silicon substrate, ceramic, etc. The adhesive 22 is made of a material whose adhesive strength can be varied. For example, the adhesive 22 may be made of an adhesive whose adhesive strength changes according to temperature or light. In this case, the adhesive 22 may be made of, for example, ultraviolet curable resin, wax, double-sided tape, etc. Here, the adhesive 22 may be made of a material that maintains adhesive strength even when the second surface-side element component 60 is formed, as will be referred to later. Figure 1J Describe the second surface-side element component 60.

[0040] Next, as Figure 1F As shown, a laser beam L is applied from the second surface 10b side of the processed wafer 10 to form a chip transformation layer 14 at the portion corresponding to the outer edge of the boundary including adjacent chip formation regions RA. Specifically, a process similar to... Figure 1B The laser device used in the process. When forming the chip transformation layer 14, the processed wafer 10 is placed on a stage, and the position of the stage is adjusted so that the focusing point of the laser beam L scans relative to the outer edge of each chip formation region RA.

[0041] As a result, a chip transformation layer 14 is formed on the outer edge of each chip formation region RA, in which gallium and nitrogen are thermally decomposed. More specifically, the chip transformation layer 14 is formed by irradiating the processed wafer 10 with a laser beam L, in which nitrogen is evaporated into gas and gallium is deposited. As nitrogen atoms are separated and evaporated, the chip transformation layer 14 is in a state with fine pores. Furthermore, the chip transformation layer 14 is shared between adjacent chip formation regions RA at the boundary between them. That is, the chip transformation layer 14 is formed along the boundary of adjacent chip formation regions RA at the adjacent portions of each chip formation region RA.

[0042] Furthermore, in this embodiment, when forming the chip transformation layer 14, the stage or the like is appropriately moved and a laser beam L is applied, causing the focusing point to move at two or more different locations in the thickness direction of the processed wafer 10 at the outer edge of each chip formation region RA. In this case, the chip transformation layer 14 is formed at different locations in the thickness direction of the processed wafer 10. However, the chip transformation layers 14 can be separated from each other or connected to each other. Furthermore, when the focusing point moves at two or more different locations in the thickness direction of the processed wafer 10, the focusing point moves from the first surface 10a side of the processed wafer 10 to the second surface 10b side.

[0043] Chip transformation layer 14 is formed as when formed Figure 1H When the wafer transformation layer 15 is formed, nitrogen generated during the formation of the wafer transformation layer 15 is discharged to the outside through the apertures of the chip transformation layer 14. While not particularly limited, in this embodiment, a solid-state laser beam, such as a green laser beam with a wavelength of 532 nm, is used as the laser beam L during the formation of the chip transformation layer 14. The laser beam L is emitted with a processing point output of 2 μJ, a pulse width of 500 ps, ​​and a processing speed of 500 mm / s. These conditions are merely examples; the inventors of this application have confirmed that the chip transformation layer 14 can be properly formed even if the processing point output of the laser beam L is reduced or even if the pulse width is narrowed. Furthermore, the inventors of this application have confirmed that the chip transformation layer 14 can be properly formed even if the processing point output of the laser beam L is increased or even if the pulse width is increased.

[0044] Subsequently, as Figure 1G As shown, a laser beam L is applied to the processed wafer 10 from the second surface 10b side to form a chip mark TM within each chip formation region RA. The chip mark TM is, for example, a batch number used to identify the semiconductor chip 100 during the manufacturing of the semiconductor chip 100, which will be described later.

[0045] Specifically, preparation similar to in Figure 1B The laser apparatus used in the process is described. Then, when forming the chip mark TM, the processed wafer 10 is placed on a stage, and the position of the stage, etc., is adjusted so that the focusing point of the laser beam L is located at a predetermined position in each chip formation region RA. The chip mark TM has various identifiable shapes or patterns, such as lines or polygons, or numbers. Although not particularly limited, in this embodiment, the conditions of the laser beam L used to form the chip mark TM are the same as those used to form the wafer mark WF.

[0046] Subsequently, a heat treatment is performed to promote gallium deposition and improve the visibility of the chip marker TM. Since the heat treatment is performed on the processed wafer 10 on which the first surface-side element component 11 has already been formed, the temperature of the heat treatment is equal to or higher than the melting point of gallium (i.e., 29.76°C) and equal to or lower than 200°C.

[0047] Subsequently, as Figure 1H As shown, a laser beam L is applied to the processed wafer 10 from the second surface 10b side to form a wafer transformation layer 15 along the planar direction of the processed wafer 10 at a predetermined depth D from the first surface 10a. In this embodiment, the wafer transformation layer 15 is formed by using a laser beam L to form a wafer transformation layer 15 along the planar direction of the processed wafer 10. Figure 1B The same laser device used in the process is formed.

[0048] During the formation of the wafer transformation layer 15, the position of the stage, etc., is adjusted so that the focusing point of the laser beam L scans relative to the plane of the processed wafer 10. As a result, the wafer transformation layer 15 is formed in the processed wafer 10 along the plane. The wafer transformation layer 15 has a configuration in which nitrogen is evaporated into gas and gallium is deposited, similar to the chip transformation layer 14.

[0049] In this embodiment, the wafer transformation layer 15 is formed to intersect with or extend directly below the chip transformation layer 14. As a result, it is unlikely that large deformations will be applied to each wafer formation region RA during the formation of the wafer transformation layer 15.

[0050] In other words, without forming the chip transformation layer 14, such as Figure 2AAs shown, nitrogen generated during the formation of the wafer transition layer 15 is difficult to release to the outside. Therefore, the deformation of the processed wafer 10 may increase due to the ongoing formation of the wafer transition layer 15. In this embodiment, on the other hand, a chip transition layer 14 is formed, and the wafer transition layer 15 is formed to intersect with or pass directly beneath the chip transition layer 14. Therefore, as Figure 2B As shown, nitrogen generated during the formation of the wafer transformation layer 15 can easily be released to the outside through the pores of the chip transformation layer 14. In this way, it is possible to suppress the expansion of deformation of the processed wafer 10 due to the formation of the wafer transformation layer 15, and it is possible to suppress the deformation applied to each chip formation region RA.

[0051] While not particularly limiting, in this embodiment, a solid-state laser beam, such as a green laser beam with a wavelength of 532 nm, is used as the laser beam L when forming the wafer transformation layer 15. The laser beam L is emitted with a processing point output of 0.1 μJ to 0.3 μJ, a pulse width of 500 ps, ​​and a processing speed of 50 mm / s to 500 mm / s. These conditions are merely examples; the inventors of this application have confirmed that the wafer transformation layer 15 can be appropriately formed even if the processing point output of the laser beam L is reduced or the pulse width is narrowed. Furthermore, the inventors of this application have confirmed that the wafer transformation layer 15 can be appropriately formed even if the processing point output of the laser beam L is increased or the pulse width is increased.

[0052] Furthermore, the predetermined depth D of the wafer transformation layer 15 is determined based on factors such as the ease of operation of the semiconductor chip 100 and the voltage it can withstand. For example, the predetermined depth D is approximately 10 μm to 200 μm. In this case, the position of the wafer transformation layer 15 varies depending on the thickness of the epitaxial film 3. The wafer transformation layer 15 is formed at least inside the epitaxial film 3, at the boundary between the epitaxial film 3 and the GaN wafer 1, or inside the GaN wafer 1. Figure 1H This shows an example where the wafer transformation layer 15 is formed at the boundary between the epitaxial film 3 and the GaN wafer 1.

[0053] It is worth noting that at least a portion of the GaN wafer 1 in the processed wafer 10 is recycled as a recycled wafer 40, as described later. Therefore, the wafer transformation layer 15 can preferably be formed inside the epitaxial film 3 or at the boundary between the epitaxial film 3 and the GaN wafer 1. When the wafer transformation layer 15 is formed inside the GaN wafer 1, the wafer transformation layer 15 is preferably formed adjacent to the first surface 1a of the GaN wafer 1.

[0054] When the wafer transformation layer 15 is formed inside the epitaxial film 3, the wafer transformation layer 15 is formed on n + The interior of the epitaxial layer 3a, rather than the n that constitutes the semiconductor device. -The interior of the epitaxial layer 3b. In the following text, the portion from the wafer transformation layer 15 to the processed wafer 10 on the first surface 10a side is referred to as the chip forming wafer 30, and the portion from the wafer transformation layer 15 to the processed wafer 10 on the second surface 10b side is referred to as the recycled wafer 40.

[0055] Next, as Figure 1I As shown, an auxiliary member 50 is arranged on the second surface 10b side of the processed wafer 10. For example, the auxiliary member 50 includes a substrate 51 and an adhesive 52 capable of changing the adhesive force, similar to the holding member 20. In this case, the substrate 51 of the auxiliary member 50 is made of, for example, glass, silicon substrate, ceramic, etc. Furthermore, the adhesive 52 of the auxiliary member 50 is made of, for example, UV-curable resin, wax, double-sided tape, etc. Then, the holding member 20 and the auxiliary member 50 are held, and tension is applied in the thickness direction of the processed wafer 10, thereby dividing the processed wafer 10 into a chip forming wafer 30 and a recycled wafer 40 with the wafer transformation layer 15 as the boundary (i.e., the starting point of separation).

[0056] As described above, the wafer marker WM is preferably formed and retained in the recycled wafer 40. As a result, when the recycled wafer 40 is used as GaN wafer 1 (as described later), it is possible to extract [wafer markings / markers]. Figure 1C The process shown begins the manufacturing process or is in progress. Figure 1C Following the illustrated process, a manufacturing process is performed. Thereafter, the surface on which the first surface-side element component 11 is formed of the chip forming wafer 30 will be referred to as the first surface 30a, and the separating surface of the chip forming wafer 30 will be referred to as the second surface 30b. The separating surface of the recycled wafer 40 will be referred to as the first surface 40a. Furthermore, in Figure 1I In each view shown in the following figures, the wafer transformation layer 15, etc., retained on the second surface 30b of the chip forming wafer 30 and the first surface 40a of the recycled wafer 40 are appropriately omitted.

[0057] like Figure 1J As shown, a general semiconductor manufacturing process is performed. The process of forming a second surface-side element component 60 for a semiconductor element (e.g., forming a metal film 61 for a back electrode located on the second surface 30b of the chip forming wafer 30) will be performed.

[0058] Before the process of forming the second surface-side element component 60, a process of planarizing the second surface 30b of the chip forming wafer 30 by means of chemical mechanical polishing (CMP) or the like may be performed as needed. Figure 1JAn example is shown when the second surface 30b of the chip forming wafer 30 is planarized. Furthermore, after the process of forming the second surface-side element component 60 is performed, heat treatments such as laser annealing may be performed as needed to achieve ohmic contact between the metal film 61 and the second surface 30b of the chip forming wafer 30.

[0059] Subsequently, as Figure 1K As shown, the retaining member 20 is expanded such that the chip formation regions RA are separated with the chip transformation layer 14 as the boundary (i.e., the starting point of separation). Then, the adhesive force of the adhesive 22 is weakened by heat treatment or by using light irradiation, and the semiconductor chip 100 is picked up. The semiconductor chip 100 is manufactured in this manner. Before dividing the chip formation wafer 30 into chip formation regions RA, if necessary, slits or the like can be formed in the metal film 61 at the boundary between the chip formation regions RA to facilitate the separation of the metal film 61 used for the chip formation regions RA. In this case, in Figure 1J During the process, a metal mask can be prepared to cover the part to be separated, so that no metal film 61 is formed on the part to be separated.

[0060] The semiconductor chip 100 manufactured as described above includes a chip substrate 110, which has a first surface 110a, a second surface 110b located on the opposite side of the first surface 110a, and a side surface 110c connecting the first surface 110a and the second surface 110b. The chip substrate 110 has an epitaxial film 3 made of GaN. A first surface-side element component 11 is formed on the first surface 110a side of the chip substrate 110, and a second surface-side element component 60 is formed on the second surface 110b side. Furthermore, the semiconductor chip 100 is provided with a chip mark TM formed as described above.

[0061] Since the semiconductor chip 100 of this embodiment is constructed by dividing the chip formation substrate 30 with the chip transition layer 14 as the boundary, the chip transition layer 14 is retained on the side surface 110c. In this case, the chip transition layer 14 is a layer in which gallium and nitrogen are separated and gallium is deposited, and it is in a state with minor irregularities. Therefore, in the manufacturing method of this embodiment, an easy-to-operate semiconductor chip 100 is manufactured.

[0062] In addition, such as Figure 1L As shown, through Figure 1I The first surface 40a of the recycled wafer 40 formed in the process shown is planarized using a polishing apparatus 70 or the like via CMP technology. Then, the planarized recycled wafer 40 is used as GaN wafer 1, and the process is repeated. Figure 1ASubsequent processes. As a result, GaN wafer 1 can be reused multiple times to form semiconductor chip 100. Note that when the recycled wafer 40 has a wafer marker WM formed, the following steps are performed. Figure 1C The subsequent process, without execution Figure 1B The process.

[0063] According to the above embodiment, gallium is deposited inside the processed wafer 10 to form a wafer mark WM. Therefore, no recesses are formed on the first surface 10a and the second surface 10b of the processed wafer 10. This makes it possible to suppress the formation of cracks in the processed wafer 10 starting from the wafer mark WM.

[0064] According to the above embodiment, gallium is deposited inside the semiconductor chip 100 to form a chip mark TM. Therefore, no recesses are formed on the first surface 110a and the second surface 110b of the chip substrate 110 constituting the semiconductor chip 100. This makes it possible to suppress the formation of cracks in the semiconductor chip 100 starting from the chip mark TM.

[0065] Furthermore, since the wafer marker WM is formed inside the processed wafer WM, the generation of minute dust particles during the formation of the wafer marker WM can be suppressed. Similarly, since the chip marker TM is formed inside the semiconductor chip 100, the generation of minute dust particles during the formation of the chip marker TM can be suppressed. Therefore, it is possible to prevent dust particles from adhering to the processed wafer 10 and the semiconductor chip 100 during the formation of these markers WM and TM.

[0066] (1) In this embodiment, the wafer mark WM is formed before the first surface-side element component 11 is formed. Therefore, compared with the case where the wafer mark WM is formed after the first surface-side element component 11 is formed, the selection of conditions such as heat treatment can be expanded.

[0067] (2) In this embodiment, the wafer marker WM is formed in a portion that can be used as a recycled wafer 40. As a result, when the recycled wafer 40 is reused as a GaN wafer 1, it is not necessary to reformat the wafer marker WM, thus simplifying the manufacturing process.

[0068] (3) In this embodiment, the chip mark TM is formed before the wafer transformation layer 15 is formed. Therefore, compared with the case where the chip mark TM is formed after the wafer transformation layer 15 is formed, the scattering of the laser beam L used to form the chip mark TM by the wafer transformation layer 15 can be suppressed. As a result, the chip mark TM can be formed well.

[0069] (4) In this embodiment, heat treatment is performed after the formation of the wafer marker WM and the chip marker TM. Therefore, it is possible to promote the deposition of gallium in each of the wafer marker WM and the chip marker TM, and to improve the visibility of each of the wafer marker WM and the chip marker TM.

[0070] (5) In this embodiment, the processed wafer 10 is divided into a chip forming wafer 30 and a recycled wafer 40, and the recycled wafer 40 is reused as a GaN wafer 1. Therefore, it is not necessary to re-process the GaN wafer 1 each time the semiconductor chip 100 is manufactured, and the GaN wafer 1 can be used efficiently. In this way, the productivity of the semiconductor chip 100 can be improved.

[0071] (Other embodiments)

[0072] Although this disclosure has been described with reference to embodiments, it should be understood that this disclosure is not limited to such embodiments or structures. This disclosure includes various modifications and variations within the scope of equivalents. Furthermore, various combinations and aspects, as well as other combinations and aspects including only one element, more than one element, or less than one element, are also within the spirit and scope of this disclosure.

[0073] For example, in the first embodiment described above, the epitaxial film 3 may also be composed of only n - The epitaxial layer 3b is formed.

[0074] Furthermore, in the first embodiment described above, in Figure 1J In the illustrated process, the metal film 61 can also be formed without polishing the second surface 30b of the chip forming wafer 30. For example, when forming a semiconductor element such as an optical semiconductor element, a rough structure can be formed on the second surface 110b of the semiconductor chip 100. In this case, light can be effectively extracted from the second surface 110b side. Immediately after dividing the processed wafer 10 into the chip forming wafer 30 and the recycled wafer 40, the second surface 30b of the chip forming wafer 30 is in a state where the wafer transformation layer 15 is retained and has minor unevenness. Therefore, when forming an optical semiconductor element, the second surface 30b of the chip forming wafer 30 can be formed without polishing, and the unevenness of the wafer transformation layer 15 can be utilized.

[0075] Furthermore, in the first embodiment described above, in Figure 1B In the process of forming the epitaxial film 3 shown, the epitaxial film can also be formed on the second surface 1b of the GaN wafer 1. In this case, for example, even if the wafer transformation layer 15 is formed in the GaN wafer 1, it is easy to maintain the thickness of the recycled wafer 40 equal to or greater than the predetermined thickness of the recycled wafer 40, and it is possible to increase the number of times the recycled wafer can be recycled.

[0076] In the first embodiment described above, only one of the steps of forming wafer marker WM and forming chip marker TM may be performed.

[0077] In the first embodiment described above, the process of forming the wafer marker WM can be performed in... Figure 1C The process of forming the epitaxial film 3 shown below and in Figure 1D The process shown is performed before the formation of the first surface-side element component 11. Furthermore, a wafer marker WM can be formed in the portion of the processed wafer 10 corresponding to the chip forming wafer 30.

[0078] In the first embodiment described above, the process of forming the chip marker TM can be performed at... Figure 1H The process shown is performed after the formation of the wafer transformation layer 15.

[0079] In the first embodiment described above, instead of forming the chip transition layer 14, a groove can be formed at the position corresponding to the chip transition layer 14. In the first embodiment described above, after forming the chip forming wafer 30 without forming the chip transition layer 14 and the trench portion, the chip forming wafer 30 can be divided into chip units as wafers of the semiconductor chip 100 by using a dicing saw, laser dicing, or the like.

Claims

1. A method for manufacturing a semiconductor chip having semiconductor elements formed thereon, the method comprising: Preparation of gallium nitride wafers made of gallium nitride; A processed wafer is manufactured by forming an epitaxial film on the surface of the gallium nitride wafer. The processed wafer has a first surface on one side of the epitaxial film and a second surface on one side of the gallium nitride wafer. The processed wafer includes a plurality of chip forming regions adjacent to the first surface of the processed wafer. A first surface-side element component of the semiconductor element is formed in each of the plurality of chip forming regions; A wafer transformation layer in which nitride and gallium are separated is formed along the planar direction of the processed wafer by irradiating the interior of the processed wafer from the second surface side of the processed wafer with a laser beam. The processed wafer is divided into a chip forming wafer including a first surface of the processed wafer and a recycled wafer including a second surface of the processed wafer, using the wafer transformation layer as a boundary. The semiconductor chip is removed from the wafer formed from the chip; and After the gallium nitride wafer is fabricated and before the dicing of the processed wafer, a mark is formed inside one of the gallium nitride wafer and the processed wafer by irradiating the interior of the gallium nitride wafer and the processed wafer with a laser beam. The mark is formed by gallium deposition. Forming the mark includes forming a wafer mark as the mark after the gallium nitride wafer is fabricated and before the formation of the first surface-side component, wherein In the formation of the wafer marker, the wafer marker is formed at a portion included in the recycled wafer, and, In the formation of the wafer marker, a laser beam having the same wavelength as the laser beam used in the formation of the wafer transformation layer is used to form the wafer marker.

2. The method according to claim 1, wherein The formation of the mark includes forming a chip mark as a mark in each of the plurality of chip formation regions after the formation of the first surface-side element component and before the formation of the wafer transformation layer.

3. The method according to claim 1, further comprising: Heat treatment is performed after the markings are formed.

4. The method according to any one of claims 1 to 3, wherein The preparation of the gallium nitride wafer includes reusing the recycled wafer as a gallium nitride wafer.

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