Method of manufacturing a semiconductor structure, semiconductor structure, memory and storage system

Abstract

The application provides a semiconductor structure preparation method, a semiconductor structure, a memory and a storage system. The semiconductor structure preparation method comprises the following steps: forming a first stack structure on a substrate; forming an isolation cutting groove and a mark cutting groove by using a first mask, the isolation cutting groove and the mark cutting groove pass through the first stack structure along a first direction perpendicular to the substrate and extend into the substrate; and then filling a medium material into the isolation cutting groove and the mark cutting groove to form an isolation structure and a mark structure. The application effectively reduces the process cost of preparing the semiconductor structure by simultaneously forming the isolation cutting groove and the mark cutting groove by using one mask.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a preparation method of semiconductor structure, semiconductor structure, memory and storage system. BACKGROUND

[0002] Generally, in the process of preparing 3D NAND flash memory, a plurality of trenches are etched for subsequent formation of structures with different functions, such as mark structures, isolation structures, etc.

[0003] Therefore, how to reduce the process cost in the process of preparing the memory is a problem to be solved at present. SUMMARY

[0004] To solve the above problems or other problems, the present application provides the following technical solutions.

[0005] In a first aspect, the present application provides a preparation method of semiconductor structure, comprising:

[0006] forming a first stack structure on a substrate;

[0007] forming an isolation cut groove and a mark cut groove using a first mask, the isolation cut groove and the mark cut groove passing through the first stack structure and extending into the substrate along a first direction perpendicular to the substrate; and

[0008] filling a dielectric material into the isolation cut groove and the mark cut groove to form an isolation structure and a mark structure.

[0009] According to the preparation method of one embodiment of the present application, the isolation structure has a first top surface parallel to the substrate, and the mark structure has a second top surface parallel to the substrate, wherein the first top surface is flush with the second top surface.

[0010] According to the preparation method of one embodiment of the present application, after the step of filling the dielectric material into the isolation cut groove and the mark cut groove to form the isolation structure and the mark structure, the method further comprises:

[0011] forming a second stack structure on the first stack structure;

[0012] forming a first gate slit cut groove using a second mask, the first gate slit cut groove passing through the second stack structure and the first stack structure along the first direction and extending into the substrate;

[0013] filling the dielectric material into the first gate slit cut groove to form a first gate slit structure.

[0014] According to the manufacturing method of one embodiment of the present application, the entire bottom surface of the first gate slit trench is planar.

[0015] According to the manufacturing method of one embodiment of the present application, the first stack structure and the second stack structure jointly constitute a memory stack structure, the memory stack structure includes a plurality of dielectric layers and a plurality of sacrificial layers which are alternately stacked in the first direction, and before the step of filling the dielectric material into the first gate slit trench to form a first gate slit structure, the method further includes:

[0016] The plurality of sacrificial layers are replaced by a plurality of gate layers through the first gate slit trench, and the material of the plurality of gate layers includes conductive material.

[0017] The plurality of gate layers are etched back through the first gate slit trench to remove the conductive material between the first gate slit trench and the isolation structure.

[0018] According to the manufacturing method of one embodiment of the present application, after the step of filling the dielectric material into the first gate slit trench to form a first gate slit structure, the method further includes:

[0019] The substrate is cut through the mark structure, and the mark structure is removed.

[0020] In a second aspect, the present application provides a semiconductor structure, which includes:

[0021] a substrate;

[0022] a memory stack structure disposed on the substrate; and

[0023] a separation structure including an isolation structure, the isolation structure extending into the substrate along a first direction perpendicular to the substrate.

[0024] According to the semiconductor structure of one embodiment of the present application, the substrate includes a substrate and a stop layer, the stop layer is located between the substrate and the memory stack structure, and the isolation structure extends into the stop layer along the first direction.

[0025] According to the semiconductor structure of one embodiment of the present application, the separation structure further includes a first gate slit structure, the first gate slit structure and the isolation structure are arranged along a second direction parallel to the substrate, and the entire bottom surface of the first gate slit structure is planar.

[0026] According to the semiconductor structure of one embodiment of the present application, the isolation structure is in contact with the first gate slit structure.

[0027] The semiconductor structure according to an embodiment of the present application, wherein the isolation structure and the first gate slit structure have a spacing therebetween.

[0028] The semiconductor structure according to an embodiment of the present application, wherein the memory stack structure comprises a plurality of dielectric layers and a plurality of gate layers alternately stacked in the first direction, and a material of the plurality of dielectric layers comprises a dielectric material, wherein the spacing comprises a void and the dielectric material.

[0029] The semiconductor structure according to an embodiment of the present application, wherein the memory stack structure comprises a first stack structure and a second stack structure sequentially arranged on the substrate, wherein the isolation structure passes through the first stack structure along the first direction, and the first gate slit structure passes through the second stack structure and the first stack structure along the first direction.

[0030] The semiconductor structure according to an embodiment of the present application, wherein the first stack structure is a bottom select gate stack structure, and the isolation structure is a bottom select gate trench.

[0031] The semiconductor structure according to an embodiment of the present application, wherein the semiconductor structure further comprises a second gate slit structure, the second gate slit structure passes through the memory stack structure along the first direction and extends along the second direction, wherein the second gate slit structure is used to divide the semiconductor structure into a plurality of block memory areas, and the separation structure is used to divide each of the block memory areas into a plurality of finger memory areas.

[0032] The semiconductor structure according to an embodiment of the present application, wherein the isolation structure has a first width in a third direction, and the first gate slit structure has a second width in the third direction, wherein the first width is greater than the second width, and the third direction is parallel to the substrate and perpendicular to the second direction.

[0033] In a third aspect, the present application provides a memory, comprising:

[0034] The semiconductor structure according to any one of the above; and,

[0035] A peripheral circuit, the peripheral circuit being electrically connected with the semiconductor structure.

[0036] In a fourth aspect, the present application provides a memory system, comprising:

[0037] The memory according to the above; and,

[0038] A controller, the controller being electrically connected with the memory and used to control the memory.

[0039] The application has the beneficial effects that: the application provides a semiconductor structure preparation method, a semiconductor structure, a memory and a storage system, wherein the semiconductor structure preparation method comprises: forming a first stack structure on a substrate, forming an isolation cutting groove and a mark cutting groove using a first mask, the isolation cutting groove and the mark cutting groove pass through the first stack structure along a first direction perpendicular to the substrate and extend into the substrate, then filling a medium material into the isolation cutting groove and the mark cutting groove to form an isolation structure and a mark structure, the application effectively reduces the process cost of preparing the semiconductor structure by using one mask to form the isolation cutting groove and the mark cutting groove at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the application, the drawings needed in the following description of the embodiments according to the application will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0041] Figure 1 A flowchart of a semiconductor structure preparation method provided by an embodiment according to the application is shown.

[0042] Figure 2 A further flowchart of a semiconductor structure preparation method provided by an embodiment according to the application is shown.

[0043] Figures 3a to 3h A process flowchart of a semiconductor structure preparation method provided by an embodiment according to the application is shown.

[0044] Figure 4 A structure diagram of a semiconductor structure in an embodiment is shown.

[0045] Figure 5 A structure diagram of a semiconductor structure in an embodiment and a mask layout diagram corresponding to an isolation structure and a first gate slit structure in the semiconductor structure are shown.

[0046] Figure 6 A structure diagram of a semiconductor structure provided by another embodiment according to the application and a mask layout diagram corresponding to an isolation structure and a first gate slit structure in the semiconductor structure are shown.

[0047] Figure 7 A cross-sectional structure diagram of a semiconductor structure provided by an embodiment according to the application is shown.

[0048] Figure 8 A top view structure diagram of a semiconductor structure provided by an embodiment according to the application is shown.

[0049] Figure 9 A structural diagram of a memory according to an embodiment of the present application is shown.

[0050] Figure 10 A structural diagram of a memory system according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0052] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0053] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For a person of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0054] In the present disclosure, unless specifically defined otherwise, a first feature "on" or "above" a second feature can include the first and second features being directly in contact with each other, or the first and second features not being directly in contact with each other but being in contact with each other through another feature therebetween. Also, the first feature "over", "above" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or just means that the first feature is higher in level than the second feature. The first feature "under", "below" and "underneath" the second feature includes the first feature being directly below and obliquely below the second feature, or just means that the first feature is lower in level than the second feature.

[0055] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For purposes of simplicity and clarity, the description is divided into sections. Of course, these sections are merely provided for ease of understanding, and the present application can be practiced in a variety of ways. Furthermore, the present application can be implemented in a wide variety of contexts and with many different types of structures. Therefore, the following description is not meant to limit the application in any way.

[0056] Reference is made to Figure 1 and Figures 3a to 3h wherein, Figure 1 and Figures 3a to 3h respectively show a flowchart and a process flowchart of a method for fabricating a semiconductor structure 100 according to an embodiment of the present application.

[0057] As shown in Figure 1 , Figure 3a , Figure 3b and Figure 3c , the method for fabricating the semiconductor structure 100 can include the following steps:

[0058] A first stack structure forming step S101: forming a first stack structure 120 on a substrate 110;

[0059] A slot forming step S102: forming an isolation slot 130' and a mark slot 140' using a first mask, the isolation slot 130' and the mark slot 140' passing through the first stack structure 120 along a first direction Y perpendicular to the substrate 110 and extending into the substrate 110;

[0060] A deposition step S103: filling a dielectric material into the isolation slot 130' and the mark slot 140' to form an isolation structure 130 and a mark structure 140.

[0061] Next, reference is made toFigure 4 The diagram shown is a schematic representation of the semiconductor structure 200 in one embodiment. Figure 4 As shown, in these embodiments, two photomasks are used to fabricate the isolation structure 230 and the marking structure 240, respectively. Specifically, the marking structure 240 is first fabricated on a substrate 210 using a photomask. The substrate 210 includes a substrate 211 and a stop layer 212 located on the substrate 211. The marking structure 240 extends into the stop layer 212 along a first direction Y. Then, a first stacked structure 220 is formed on the substrate 210, and the marking structure 240 extending through the first stacked structure 220 along the first direction Y is formed using another photomask.

[0062] Furthermore, in these embodiments, the marking structure 240 is located in the scribe line next to the semiconductor structure 200 and is used as a structure to mark the position of each semiconductor structure 200 (also called a die). The isolation structure 230 is located in the semiconductor structure 200. In this embodiment, the isolation structure 230 is used as the bottom select gate cut (BSG cut) of the semiconductor structure 200, and the first stack structure 220 is a bottom select gate (BSG) stack structure.

[0063] However, because a large number of masks are used in the fabrication process, this method usually results in high processing costs.

[0064] The inventors of this case have discovered that since the materials that make up the isolation structure 230 and the marking structure 240 are the same, and the height and position of the isolation structure 230 and the marking structure 240 in the first direction Y are approximately the same, it is possible to use a single photomask to simultaneously form the isolation structure 230 and the marking structure 240 in order to reduce the manufacturing cost.

[0065] Now return to the reference Figure 3b In this embodiment of the invention, by using a first photomask to simultaneously form an isolation groove 130' and a marking groove 140', the process cost of fabricating the semiconductor structure 100 is effectively reduced.

[0066] Specifically, in the embodiments of the present invention, such as Figure 3a As shown, the substrate 110 includes a substrate 111 and a stop layer 112 located on the substrate 111, and the first direction Y is the thickness direction of the substrate 110.

[0067] It is to be noted that, since the isolation structure 130 is required as a bottom select gate cut (BSG CUT), the isolation cut 130' and the mark cut 140' formed in the cut forming step S102 will pass through the first stack structure 120 along the first direction Y, and, since the mark structure 140 is required for positioning function, the isolation cut 130' and the mark cut 140' formed in the cut forming step S102 will extend into the stop layer 112 along the first direction Y.

[0068] It is to be understood that, in other variants according to the present application, the isolation structure 130 can also be other structures in the semiconductor structure 100 for isolation or support, which will also pass through the first stack structure 120, or structures with similar thickness and position to the first stack structure 120, and the present application does not limit thereto.

[0069] Further, please refer to Figure 3c , Figure 3c , it is shown that the isolation structure 130 has a first top surface (not labeled) parallel to the substrate 110, and the mark structure 140 has a second top surface (not labeled) parallel to the substrate 110, since the isolation structure 130 and the mark structure 140 are formed in one process, the first top surface is flush with the second top surface.

[0070] Further, please refer to Figure 2 , Figure 3d , Figure 3e and Figure 3h , wherein, Figure 2 a further flowchart of the method for preparing the semiconductor structure 100 according to the embodiment of the present application is shown.

[0071] As shown in Figure 2 , Figure 3d , Figure 3e and Figure 3h , after the deposition step S103, the following steps are further included:

[0072] The second stack structure forming step S104: forming a second stack structure 150 on the first stack structure 120;

[0073] The first gate slit cut forming step S105: using a second mask to form a first gate slit cut 160' which passes through the second stack structure 150 and the first stack structure 120 along the first direction Y, and extends into the substrate 110;

[0074] The first gate slit structure forming step S106: filling the dielectric material into the first gate slit trench 160' to form the first gate slit structure 160.

[0075] Specifically, Figures 3a to 3d is a sectional view of the semiconductor structure 100 in the third direction X1, Figures 3e to 3h is a sectional view of the semiconductor structure 100 in the second direction X2, wherein the third direction X1 is the arrangement direction of the isolation structure 130 and the mark structure 140, and the second direction X2 is the arrangement direction of the isolation structure 130 and the first gate slit structure 160.

[0076] It should be noted that in the 3D NAND flash memory, each Die can contain a plurality of Block arranged in an array in a Giant Block, each Block is the smallest erasable unit of the 3D NAND flash memory, and each Block can be further divided into a plurality of Fingers.

[0077] Specifically, please continue to refer to Figure 3h In the embodiment of the present application, the isolation structure 130 and the first gate slit structure 160 arranged along the second direction X2 are used to divide the Block of the semiconductor structure 100 into a plurality of Fingers. Further, in the embodiment of the present application, the semiconductor structure 100 further comprises a second gate slit structure (not shown) extending through the second stack structure 150 and the first stack structure 120 along the first direction Y and extending along the second direction X2, which is used to divide the Giant Block of the semiconductor structure 100 into a plurality of Blocks.

[0078] Next, please refer to Figure 5 The structure of the semiconductor structure 300 in one embodiment and the corresponding mask layout of the isolation structure 330 and the first gate slit structure 360 in the semiconductor structure 300 are shown.

[0079] The inventors have found that, as Figure 5As shown, in these embodiments, when the semiconductor structure 300 is prepared, the first pattern M-330 and the second pattern M-360 of the isolation structure 330 and the first gate slit structure 360 in the mask layout M have an overlapping portion 4, due to the fact that during the preparation of the isolation structure 330, the isolation trench (not shown) needs to extend along the first direction Y into the stop layer 312 together with the marker trench (not shown), and the above-mentioned overlapping portion 4 corresponds to the portion in the semiconductor structure 300 which is composed of the oxide, thus, when the first gate slit trench (not shown) is prepared, the materials of the second pattern M-360 corresponding to the portions in the semiconductor structure 300 which are located in and not located in the above-mentioned overlapping portion 4 are not completely the same (for example, composed of the oxide / nitride oxide, respectively), which will result in that the etching speed of the second pattern M-360 corresponding to the portions in the semiconductor structure 300 which are located in the overlapping portion 4 is faster, so that the structure corresponding to the overlapping portion 4 in the semiconductor structure 300 will be etched too deep in the above-mentioned stop layer 312 and extend into the substrate 311, thus resulting in that the first gate slit trench has a recess 5, specifically, the recess 5 is located in the substrate 311. After that, when the gate replacement process is performed on the semiconductor structure 300 through the first gate slit trench, the above-mentioned recess 5 will remain the conductive material such as tungsten, which will affect the electrical properties of the semiconductor structure 300.

[0080] Now back to referring to Figure 3e wherein, Figure 3e The mask layout M corresponding to the isolation structure 130 and the first gate slit structure 160 in the semiconductor structure 100 is also shown.

[0081] As Figure 3e shown, in the embodiments of the present application, in the mask layout M corresponding to the isolation structure 130 and the first gate slit structure 160 designed by the inventors, the first pattern M-130 and the second pattern M-160 are spaced apart by a certain distance (for example, 0-20 nm), thus, during the preparation of the first gate slit trench 160', it can be ensured that the entire bottom surface of the first gate slit trench 160' is planar, specifically, the bottom surface is located in the stop layer 112, thus, after the gate replacement process is performed on the semiconductor structure 100 through the first gate slit trench 160', the conductive material will not be left in the substrate 111, which ensures that the semiconductor structure 100 has excellent electrical isolation and effectively avoids the occurrence of the leakage situation.

[0082] Further, please refer to Figure 3e and Figure 3fIn the embodiment of the present application, the first stack structure 120 and the second stack structure 150 jointly constitute a memory stack structure (not shown), which comprises a plurality of dielectric layers 1 and a plurality of sacrificial layers 2 alternately stacked in the first direction. It is to be noted that, in the process of preparing the semiconductor structure 100, the plurality of sacrificial layers 2 are replaced by a plurality of gate layers 3 through the first gate slit cut 160', so that a controller coupled to the semiconductor structure 100 can control the corresponding memory cells through the gate layers 3.

[0083] For example, please continue to refer to Figure 2 After the above-mentioned first gate slit cut forming step S105, the following steps are further included:

[0084] Replacement step S107: replacing the plurality of sacrificial layers 2 by a plurality of gate layers 3 through the first gate slit cut 160', and the material of the plurality of gate layers 3 comprises a conductive material.

[0085] Specifically, the exemplary material of the above-mentioned conductive material comprises tungsten (element symbol: W).

[0086] It is to be noted that, after the above-mentioned first gate slit cut forming step S105, the isolation structure 130 and the first gate slit cut 160' are separated by a certain distance due to the interval of the mask patterns (M-130 and M-160), and therefore, after the above-mentioned replacement step S107, the isolation structure 130 and the first gate slit cut 160' have a conductive material therebetween. Since the isolation structure 130 needs to jointly serve as a structure for dividing the block storage area of the semiconductor structure 100 into a plurality of finger storage areas with the first gate slit structure 160 formed in the first gate slit structure forming step S106, that is to say, the common body constituted by the isolation structure 130 and the first gate slit structure 160 needs to have good electrical isolation performance, therefore, please continue to refer to Figure 2 and Figure 3g Before the above-mentioned first gate slit structure forming step S106, the following steps are further included:

[0087] Etching back step S108: etching back the plurality of gate layers 3 through the first gate slit cut 160' to remove the conductive material between the first gate slit cut 160' and the isolation structure 130.

[0088] It is to be further noted that, please refer to Figure 6 the structure schematic diagram of a semiconductor structure 400 according to another embodiment of the present application and the mask layout diagram corresponding to the isolation structure 430 and the first gate slit structure 460 in the semiconductor structure 400.

[0089] As Figure 6As shown in the mask layout corresponding to the isolation structure 430 and the first gate slit structure 460 designed by the inventors, the first pattern M-430 and the second pattern M-460 are in contact, and the first pattern M-430 and the second pattern M-460 do not have overlapping parts, so that during preparation of the first gate slit groove (not shown), the entire bottom surface of the first gate slit groove can also be ensured to be planar, and further, after the semiconductor structure 400 is subjected to the gate replacement process through the first gate slit groove, it can also be ensured that the conductive material will not be left in the substrate, ensuring that the semiconductor structure 400 has excellent electrical isolation, effectively avoiding the occurrence of leakage.

[0090] Further, in the above-mentioned embodiments according to the present application, the isolation structure 430 and the first gate slit groove are not separated by a certain distance, that is, after the above-mentioned replacement step S107, the isolation structure 430 and the first gate slit groove do not have conductive material therebetween, so that in these embodiments, without the need for the etch-back step S108, the common body formed by the isolation structure 430 and the first gate slit structure 460 can be ensured to have good electrical isolation performance.

[0091] Further, please continue to refer to Figure 2 After the above-mentioned first gate slit structure forming step S106, the following step is further included:

[0092] Cutting step S109: cutting the substrate 110 through the marking structure 140 and removing the marking structure 140.

[0093] It should be noted that during preparation of the semiconductor structure 100, the structures required by the semiconductor structure 100 are usually prepared simultaneously on a larger area wafer, and each semiconductor structure 100 has a scribe line therebetween. After all the structures required by the semiconductor structure 100 are prepared, the substrate 110 needs to be cut by the marking structure 140 located in the above-mentioned scribe line and used to mark the position of each semiconductor structure 100, so as to obtain independent semiconductor structures 100 (also known as dies), that is, the above-mentioned cutting step S109.

[0094] According to the foregoing, the embodiment of the present application provides a preparation method of a semiconductor structure 100, comprising: forming a first stack structure 120 on a substrate 110; forming an isolation cutting groove 130' and a mark cutting groove 140' by using a first mask, the isolation cutting groove 130' and the mark cutting groove 140' penetrating through the first stack structure 120 along a first direction Y perpendicular to the substrate 110 and extending into the substrate 110; and then filling a medium material into the isolation cutting groove 130' and the mark cutting groove 140' to form an isolation structure 130 and a mark structure 140. The present application effectively reduces the process cost of preparing the semiconductor structure 100 by using one mask to form the isolation cutting groove 130' and the mark cutting groove 140' at the same time, and the whole bottom surface of the isolation cutting groove 130' is a plane, which ensures that the semiconductor structure 100 has excellent electrical isolation and effectively avoids the occurrence of electric leakage.

[0095] Next, refer to Figure 7 , Figure 7 A cross-sectional structure schematic diagram of the semiconductor structure 100 provided by the embodiment according to the present application is shown.

[0096] As Figure 7 shown, the semiconductor structure 100 at least comprises a substrate 110, a storage stack structure 6 and a separation structure 7. Next, the above components are described in detail in combination with Figure 7 .

[0097] The substrate 110 comprises a substrate 111 and a stop layer 112 located on the substrate 111.

[0098] Specifically, the exemplary material of the substrate 111 can be monocrystalline silicon (Si), monocrystalline germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials, such as group III-V compound gallium arsenide, etc.

[0099] Specifically, the stop layer 112 can be a laminated structure, and the stop layer 112 can comprise a plurality of first laminations (not marked) and a second lamination (not marked) located between the plurality of first laminations, wherein the first lamination and the second lamination are stop layers to each other to jointly control the progress of etching.

[0100] The storage stack structure 6 is arranged on the substrate 110, specifically, on the stop layer 112, and the storage stack structure 6 comprises a plurality of gate layers 3 and a plurality of dielectric layers 1 electrically isolating the plurality of gate layers 3 which are alternately stacked in a first direction Y, wherein the first direction Y is the thickness direction of the substrate 110.

[0101] Specifically, the gate layer 3 is configured to enable a controller coupled to the semiconductor structure 100 to control the corresponding memory cell through the gate layer 3, and an exemplary material of the gate layer 3 includes tungsten (W) or other suitable conductive material, and an exemplary material of the dielectric layer 1 includes oxide or other suitable insulating dielectric material.

[0102] The separation structure 7 at least includes an isolation structure 130 extending into the substrate 110 along the first direction Y, and an exemplary material of the isolation structure 130 includes oxide or other suitable insulating dielectric material.

[0103] It should be noted that, in the process of forming the semiconductor structure 100 of the embodiment of the present application, in order to reduce the process cost, the isolation structure 130 and a mark structure (not shown in the figure) are simultaneously formed in one process by using one mask, wherein the mark structure is located in a scribe line (Scribe Line) beside the semiconductor structure 100, and is used to mark the position of each semiconductor structure 100 (also referred to as a die), and therefore, due to the need of the positioning function of the mark structure, the isolation structure 130 needs to be extended into the stop layer 112 along the first direction Y together with the mark structure.

[0104] Further, please continue to refer to Figure 7 The memory stack structure 6 includes a first stack structure 120 and a second stack structure 150 arranged on the substrate 110 in sequence, and specifically, in the embodiment of the present application, the first stack structure 120 is a bottom select gate (BSG) stack structure, and the isolation structure 130 penetrates the first stack structure 120 along the first direction Y and is used as a bottom select gate cut (BSG CUT) of the semiconductor structure 100.

[0105] It should be understood that, in other variants according to the present application, the isolation structure 130 can also be other structures in the semiconductor structure 100 for isolation or support, and the above-mentioned other structures for isolation or support will also penetrate the first stack structure 120, or will penetrate a structure which has a thickness and a position similar to the first stack structure 120, and the present application does not limit this.

[0106] Further, please continue to refer to Figure 7In the embodiment of the present application, the separation structure 7 further comprises a first gate slit structure 160, the first gate slit structure 160 and the isolation structure 130 are arranged along a second direction X2 parallel to the substrate 110, and the first gate slit structure 160 passes through the second stack structure 150 and the first stack structure 120 along a first direction Y. Specifically, an exemplary material of the first gate slit structure 160 comprises tungsten (W).

[0107] It should be noted that in the 3D NAND flash memory, each die can contain a plurality of block storage areas (Blocks) arranged in an array in a large-size block area (Giant Block) of each die, each block storage area (Block) is the smallest erasable unit of the 3D NAND flash memory, and each block storage area (Block) can be further divided into a plurality of finger storage areas (Fingers).

[0108] Now back to Figure 7 In the embodiment of the present application, the separation structure 7 is a structure for dividing the block storage area (Block) of the semiconductor structure 100 into a plurality of finger storage areas (Fingers). Specifically, in the embodiment of the present application, the semiconductor structure 100 further comprises a second gate slit structure (not shown) passing through the second stack structure 150 and the first stack structure 120 along the first direction Y and extending along the second direction X2, the second gate slit structure is a structure for dividing the large-size block area (Giant Block) of the semiconductor structure 100 into a plurality of block storage areas (Blocks).

[0109] It should be noted that in the process of forming the semiconductor structure 100 of the embodiment of the present application, the patterns in the photo mask used to form the first gate slit structure 160 and the isolation structure 130 are designed separately (as shown in the foregoing Figure 3e Therefore, the entire bottom surface of the first gate slit structure 160 is planar, which ensures that the semiconductor structure 100 has excellent electrical isolation and effectively avoids the occurrence of electrical leakage.

[0110] Further, please continue to refer to Figure 7 In the embodiment of the present application, due to the characteristics of the above-mentioned photo mask pattern design, there is a gap between the isolation structure 130 and the first gate slit structure 160. Specifically, since the etch-back step S108 described above needs to be performed in the process of forming the semiconductor structure 100 of the embodiment of the present application, as Figure 7 shown in the foregoing, the gap comprises a void 8 and a dielectric material, wherein the dielectric material comes from the dielectric layer 1, and the void 8 is formed in the etch-back step S108.

[0111] It should be noted that in the variants according to the present application, the pattern in the mask used to form the isolation structure and the first gate slit structure is designed to be in contact and without overlapping part, so in these variants, the isolation structure is in contact with the first gate slit structure, and the entire bottom surface of the first gate slit structure is also ensured to be planar, so as to ensure that the semiconductor structure has excellent electrical isolation and effectively avoids the occurrence of electric leakage.

[0112] Further, please refer to Figure 8 the top view structural schematic diagram of the semiconductor structure provided by the embodiment according to the present application is shown. As Figure 8 shown, the isolation structure 130 has a first width L1 in the third direction X1, and the first gate slit structure 160 has a second width L2 in the third direction X1, wherein the third direction X1 is parallel to the substrate 110 and perpendicular to the second direction X2.

[0113] It should be noted that in the embodiment of the present application, since the first gate slit structure 160 is filled with conductive material (such as tungsten as described above) in some embodiments, the wider width of the first gate slit structure 160 will be detrimental to the semiconductor structure 100 having better electrical isolation, therefore, as Figure 8 shown, in the present embodiment, the first width L1 is greater than the second width L2.

[0114] According to the foregoing, the embodiment of the present application provides a semiconductor structure, including a substrate 110, a storage stack structure 6 and a separation structure 7, wherein the storage stack structure 6 is arranged on the substrate 110, and the separation structure 7 includes an isolation structure 130, the isolation structure 130 extends into the substrate 110 along a first direction Y, the present application uses one mask to form the isolation structure 130 and a mark structure marking the position of each semiconductor structure 100 at the same time, thereby reducing the process cost, and the entire bottom surface of the isolation structure 130 and the first gate slit structure 160 in the separation structure 7 is planar, so as to ensure that the semiconductor structure 100 has excellent electrical isolation and effectively avoids the occurrence of electric leakage.

[0115] Please refer to Figure 9 , Figure 9 the structural schematic diagram of the memory 500 provided by the embodiment according to the present application is shown. The memory 500 can be a three-dimensional memory such as a 3D NAND, 3D NOR memory.

[0116] Specifically, the memory 500 includes a semiconductor structure 501 and a peripheral circuit 502, where the semiconductor structure 501 can be the semiconductor structure 100 in the above embodiments, and the peripheral circuit 502 can be a complementary metal oxide semiconductor (CMOS) circuit. The peripheral circuit 502 is electrically connected with the semiconductor structure 501 to perform signal transmission with the semiconductor structure 501. The peripheral circuit 502 can be used for logic operation and control and detection of the switching state of each memory cell in the semiconductor structure 501 through metal wires, to realize data storage and reading and other operations.

[0117] Referring to Figure 10 , Figure 10 A structural schematic diagram of a memory system 600 according to an embodiment of the present application is shown. The memory system 600 includes a memory 601 and a controller 602, where the memory 601 can be any of the memories in the above embodiments, and can include the semiconductor structure described above, and the controller 602 is electrically connected with the memory 601 to control the memory 601 to perform data operations, and the memory 601 can perform data storage operations based on the control of the controller 602.

[0118] In some embodiments, the memory system can be implemented as a universal flash storage (UFS) device, a solid state disk (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro-SD, a secure digital card in the form of SD, mini-SD and micro-SD, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0119] In addition to the above embodiments, the present application can have other embodiments. Any technical solution formed by equivalent replacement or equivalent replacement falls within the protection scope of the present application.

[0120] In summary, although the preferred embodiments of the present application have been disclosed as above, the above preferred embodiments are not intended to limit the present application, and any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present application, and therefore the protection scope of the present application is defined by the scope of the claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises: forming a first stack structure on a substrate; forming an isolation trench and a mark trench through the first stack structure and extending into the substrate along a first direction perpendicular to the substrate using a first mask; and filling a dielectric material into the isolation trench and the mark trench to form an isolation structure and a mark structure; forming a second stack structure on the first stack structure, the first stack structure and the second stack structure collectively constituting a memory stack structure, the memory stack structure comprising a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked along the first direction; forming a first gate slit trench through the second stack structure and the first stack structure along the first direction and extending into the substrate using a second mask; replacing the plurality of sacrificial layers with a plurality of gate layers through the first gate slit trench, the plurality of gate layers comprising a conductive material; etching back the plurality of gate layers through the first gate slit trench to remove the conductive material between the first gate slit trench and the isolation structure.

2. The production method according to claim 1, characterized by, The isolation structure has a first top surface parallel to the substrate, and the mark structure has a second top surface parallel to the substrate, wherein the first top surface is flush with the second top surface.

3. The production method according to claim 1, characterized by, The method further comprises, after the step of filling a dielectric material into the isolation trench and the mark trench to form an isolation structure and a mark structure: filling the dielectric material into the first gate slit trench to form a first gate slit structure.

4. The production method according to claim 3, characterized by, An entire bottom surface of the first gate slit trench is planar.

5. The preparation method according to claim 3, characterized in that, The method further comprises, after the step of filling the dielectric material into the first gate slit trench to form a first gate slit structure: cutting the substrate through the mark structure and removing the mark structure.

6. A semiconductor structure, characterized by The semiconductor structure comprises: a substrate; a memory stack structure disposed on the substrate; and a separation structure comprising an isolation structure extending into the substrate along a first direction perpendicular to the substrate and a first gate slit structure arranged along a second direction parallel to the substrate, the isolation structure and the first gate slit structure having a gap therebetween.

7. The semiconductor structure of claim 6, wherein, The substrate comprises a substrate and a stop layer between the substrate and the memory stack structure, wherein the isolation structure extends into the stop layer along the first direction.

8. The semiconductor structure of claim 6, wherein, An entire bottom surface of the first gate slit structure is planar.

9. The semiconductor structure of claim 6, wherein, The memory stack structure comprises a plurality of dielectric layers and a plurality of gate layers alternately stacked along the first direction, the plurality of dielectric layers comprising a dielectric material, wherein the gap comprises a void and the dielectric material.

10. The semiconductor structure of claim 6, wherein, The memory stack structure comprises a first stack structure and a second stack structure disposed on the substrate in sequence, wherein the isolation structure passes through the first stack structure along the first direction, and the first gate slit structure passes through the second stack structure and the first stack structure along the first direction.

11. The semiconductor structure of claim 9, wherein, The first stack structure is a bottom select gate stack structure, and the isolation structure is a bottom select gate trench.

12. The semiconductor structure of claim 6, wherein, The semiconductor structure further includes a second gate slit structure passing through the memory stack structure along the first direction and extending along the second direction, wherein the second gate slit structure is used to divide the semiconductor structure into a plurality of block memory areas, and the partition structure is used to divide each of the block memory areas into a plurality of finger memory areas.

13. The semiconductor structure of claim 6, wherein, The isolation structure has a first width in a third direction, and the first gate slit structure has a second width in the third direction, wherein the first width is greater than the second width, and the third direction is parallel to the substrate and perpendicular to the second direction.

14. A memory, comprising: Comprising: The semiconductor structure of any one of claims 6 to 13; and, A peripheral circuit electrically connected with the semiconductor structure.

15. A storage system, characterized by Comprising: The memory of claim 14; and, A controller electrically connected with the memory to control the memory.

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