Method for manufacturing memory device, memory device, and memory system

Abstract

The present application relates to a manufacturing method of a memory device, a memory device and a memory system. The manufacturing method comprises: providing a semiconductor structure comprising a stack layer, the stack layer comprising alternately stacked sacrificial layers and dielectric layers; removing the sacrificial layers in the stack layer, and filling a conductive material in the voids formed after removing the sacrificial layers to form gate layers; and forming a plurality of contact holes, each of the contact holes penetrating through a plurality of layers in the stack layer to reach the gate layers at a respective predetermined depth. The manufacturing method of the memory device of the present application replaces the sacrificial layers-dielectric layers with a lower etching selectivity in the stack structure with gate layers-dielectric layers with a higher etching selectivity, and then obtains a plurality of openings accurately reaching the gate layers at the respective predetermined depth by etching the gate layers-dielectric layers in the stack layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a manufacturing method of a semiconductor device, and in particular, to a manufacturing method of a memory device and a system including the same. BACKGROUND

[0002] With the continuous development of 3D NAND technology, the number of layers of a memory device can be vertically stacked more and more, from 24 layers, 32 layers, 64 layers to more than 400 layers of high-order stacked structure, which can greatly improve the storage density and reduce the price of unit storage cell. For example, the three-dimensional memory of 3D NAND flash includes a core area and a stair step area. Among them, the core area is used to form a plurality of memory strings, each memory string includes a plurality of memory cells, and the stair step area is used to lead out a contact structure from each layer of word line. The core area also includes a contact structure led out from the top end of the memory string. Through these contact structures, the peripheral circuit connected therewith can control the memory cells to perform programming, reading and erasing operations, etc. through the contact structures connected therewith.

[0003] When forming the contact structure in the stair step area, etching is needed to be performed on the stacked layers to obtain a plurality of openings reaching respective predetermined depths of the gate layers, and then a plurality of contact structures electrically connected with the gate layers of the predetermined depths are formed through the plurality of openings. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a manufacturing method of a memory device capable of obtaining a plurality of openings accurately reaching respective predetermined depths of gate layers, and a memory device and a memory system having contact structures accurately electrically connected with the gate layers of the predetermined depths.

[0005] The technical solution adopted by the present application to solve the above technical problem is to provide a manufacturing method of a memory device, comprising the following steps: providing a semiconductor structure, the semiconductor structure comprising a stacked layer, the stacked layer comprising sacrificial layers and dielectric layers alternately stacked; removing the sacrificial layers in the stacked layer, and filling a conductive material in the voids formed after removing the sacrificial layers to form gate layers; and forming a plurality of contact holes, each of the contact holes penetrating through a plurality of layers in the stacked layer to reach the gate layers of a respective predetermined depth.

[0006] In an embodiment of the present application, the steps of removing the sacrificial layers in the stacked layer, and filling a conductive material in the voids formed after removing the sacrificial layers to form gate layers comprise: forming a gate line slot penetrating through the stacked layer in a first direction; removing the sacrificial layers in the stacked layer through the gate line slot; and filling a conductive material in the voids formed after removing the sacrificial layers to form gate layers.

[0007] In an embodiment of the present application, before removing the sacrificial layers in the stack, further comprising forming a second dielectric layer on top of the stack.

[0008] In an embodiment of the present application, before forming the plurality of contact holes, further comprising: forming a hard mask layer on the stack; covering a first photoresist on the hard mask layer; patterning the hard mask layer through the first photoresist to form a plurality of openings reaching a top gate layer in the gate layers.

[0009] In an embodiment of the present application, forming the plurality of contact holes comprises: coating a second photoresist on the hard mask layer; and repeatedly performing the steps of trimming the second photoresist in the first direction, exposing a predetermined number of the openings, and etching a predetermined number of layers of the stack through the exposed openings to form the plurality of contact holes using the plurality of openings.

[0010] In an embodiment of the present application, further comprising forming a contact structure in the plurality of contact holes.

[0011] In an embodiment of the present application, forming a contact structure in the plurality of contact holes comprises: forming an insulating layer on the sidewalls and the bottom of the contact hole; removing the insulating layer on the bottom of the contact hole to expose the gate layer; and filling a conductive material on the inside of the insulating layer of the contact hole, the conductive material being in electrical contact with the exposed gate layer.

[0012] To solve the above problems, another aspect of the present application provides a memory device manufactured according to the manufacturing method as described above, comprising: a stack structure comprising gate layers and dielectric layers alternately stacked; and a plurality of contact structures, each of the contact structures penetrating through a plurality of layers of the stack structure to reach a respective predetermined depth of the gate layers.

[0013] In an embodiment of the present application, the memory device further comprises at least one gate line slot extending in the first direction and penetrating through the stack structure.

[0014] In an embodiment of the present application, the memory device further comprises a semiconductor layer, the stack structure covering the semiconductor layer.

[0015] To solve the above problems, another aspect of the present application provides a memory system, comprising a memory device as described above configured to store data, and a memory controller coupled to the memory device and configured to control the memory device.

[0016] In an embodiment of the present application, the memory system further comprises a host coupled to the memory controller.

[0017] The manufacturing method of the memory device of the present application replaces the etching selectivity lower sacrificial layer-dielectric layer in the stack structure with the etching selectivity higher gate layer-dielectric layer, and then obtains multiple openings of the gate layer reaching the respective predetermined depths by etching the gate layer-dielectric layer in the stack structure. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to make the above objectives, features and advantages of the present application more apparent, the specific embodiments of the present application are described in detail below with the accompanying drawings.

[0019] Figure 1 is an exemplary flow chart of the manufacturing method of the memory device of an embodiment of the present application;

[0020] Figures 2A-2J is a cross-sectional structure schematic diagram of the memory device in the manufacturing method of an embodiment of the present application;

[0021] Figures 3A-3C is a top view schematic diagram of the memory device in the manufacturing method of an embodiment of the present application;

[0022] Figures 4A-4C is a cross-sectional structure schematic diagram of the memory device of an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the above objectives, features and advantages of the present application more apparent, the specific embodiments of the present application are described in detail below with the accompanying drawings.

[0024] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced without the specific details.

[0025] As shown in the present application and claims, unless otherwise clearly indicated by the context, the words "one", "a", "an" and / or "the" do not exclude a plurality. The mere fact that a method comprises several steps or elements does not prevent the method from being a single method or a single element.

[0026] In the detailed description of the embodiments of the present application, the cross-sectional views of the device structure are partially enlarged without the general scale for the convenience of illustration, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual manufacture.

[0027] For purposes of the description hereinafter, spatial terms, such as "below," "lower," "bottom," "above," "upper," and the like, can be used with reference to the illustrated embodiment. It will be understood that the spatial terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as below other elements or below other features would then be oriented upward from the base plane. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors can be interpreted accordingly. It will also be understood that when a layer is referred to as being "on" another layer, it can be directly on the other layer or intervening layers can also be present. The relative terms "lower" and "upper" can be used to describe one surface's relationship to another surface as illustrated in the figures. It should be noted that as used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] In the context of the present application, a structure described as having a first feature "on" a second feature can include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features can not be in direct contact.

[0029] In addition, it should be noted that the use of "first", "second", and the like, herein does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another, and is more for convenience of specific reference only and does not imply a limitation of the application.

[0030] As used herein, the term "three-dimensional (3D) memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," e.g., NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertically" means nominally perpendicular to a lateral surface of the substrate.

[0031] As used herein, a "substrate" refers to a material on which subsequent layers of material are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can comprise a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0032] The term "layer" as used in this application refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any pair of horizontal planes that are between a top surface and a bottom surface of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, wherein it can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (where contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0033] Flowcharts have been used herein to illustrate operations performed by systems in accordance with embodiments of the present application. It should be understood that the operations previously or hereafter are not necessarily performed in the order shown. Rather, various steps can be processed in reverse order, or at the same time, or added to or removed from these processes.

[0034] In the fabrication process of a memory device (e.g., 3D NAND), in order to connect the contact structure with the word line of a predetermined depth, it is necessary to first form a contact hole that reaches the predetermined word line layer accurately by using an etching process, and then fill the contact hole to form a contact structure. With the increase of the number of layers of 3D NAND, very high requirements are put forward for the etching of the contact hole, which makes it difficult to make the contact hole accurately reach the predetermined word line layer, for example, the contact hole does not reach the depth of the predetermined word line layer, or exceeds the depth of the predetermined word line layer, thereby causing the contact structure to be unable to connect with the word line layer, resulting in the failure of the device.

[0035] Figure 1 is an exemplary flowchart of a method of fabricating a memory device according to an embodiment of the present application. Referring to Figure 1 The fabrication method of the embodiment includes the following steps:

[0036] Step S110: providing a semiconductor structure, the semiconductor structure including a stack layer, the stack layer including alternately stacked sacrificial layers and dielectric layers;

[0037] Step S120: removing the sacrificial layers in the stack layer, and filling a conductive material in the voids formed after the removal of the sacrificial layers to form gate layers;

[0038] Step S130: forming a plurality of contact holes, each contact hole penetrating through a plurality of layers in the stack layer to reach a respective predetermined depth of the gate layers.

[0039] Figures 2A-2J3A-3C and 4A-4C are schematic cross-sectional views of a memory device according to an embodiment of this application. The following description, in conjunction with the accompanying drawings, will illustrate the cross-sectional structure. Figures 2A-4C Steps S110-S130 are described in detail.

[0040] refer to Figure 2A As shown, in step S110, a semiconductor structure 100 is provided, which includes a stacked layer 110, comprising alternately stacked sacrificial layers 111 and dielectric layers 112. The materials of the sacrificial layer 111 and dielectric layer 112 include silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and combinations thereof. The sacrificial layer 111 and dielectric layer 112 have different etching selectivity ratios. For example, the sacrificial layer 111 and dielectric layer 112 can be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polycrystalline or amorphous silicon, or a combination of silicon oxide or silicon nitride and amorphous carbon. The methods for forming the sacrificial layer 111 and dielectric layer 112 include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), thermal oxidation, evaporation, sputtering, and various other methods.

[0041] In some embodiments of this application, the semiconductor structure 100 further includes a semiconductor layer 120. A stacked layer 110 is formed on the semiconductor layer 120. The bottom of the stacked layer 110, which is in contact with the semiconductor layer 120, is a dielectric layer 112.

[0042] In some embodiments, the semiconductor layer 120 may be a substrate. The substrate may be a silicon substrate (Si), a germanium substrate (Ge), a silicon germanide substrate (SiGe), silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The aforementioned materials may be doped or undoped, such as being doped with p-type or n-type dopants. In some embodiments, the substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. It may also be a stacked structure, such as Si / SiGe. Other epitaxial structures may also be included, such as silicon-germanium-on-insulator (SGOI), etc.

[0043] In some embodiments of this application, the substrate material is, for example, silicon. The sacrificial layer 111 and the dielectric layer 112 are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, silicon nitride and silicon oxide can be alternately deposited on the substrate sequentially using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods to form a stacked layer 110.

[0044] refer toFigure 2A As shown, a first region 130 and a second region 140 are adjacently distributed along the first direction D1. This application does not limit the size and position of the first region 130 and the second region 140.

[0045] refer to Figure 2A As shown, the first region 130 and the second region 140 include a channel structure 113 penetrating the stacked layer 110. The channel structure 113 may include a memory layer and a channel layer. Overall, the channel structure 113 includes a channel aperture, and the memory layer and the channel layer are sequentially disposed from the outside to the inside along the radial direction of the channel aperture. The memory layer may include a barrier layer, a charge trapping layer, and a tunneling layer sequentially disposed from the outside to the inside along the radial direction of the channel aperture. A filler layer may also be provided within the channel layer. The filler layer can act as a support. The material of the filler layer may be silicon oxide. The filler layer may be solid or hollow without affecting the device reliability. The vertical channel structure can be formed using one or more thin film deposition processes, such as ALD, CVD, PVD, or any combination thereof.

[0046] In embodiments where the memory device is 3D NAND, the first region 130 includes a word line connection region, and the second region 140 includes a core memory region. The channel structure in the second region 140 constitutes a memory string. The channel structure in the first region 130 is a virtual channel structure, serving a supporting function. In some embodiments, the channel structure in the first region 130 may differ from the channel structure in the second region 140. For example, the channel structure in the first region 130 may have a fill layer but no memory layer or channel layer.

[0047] In some embodiments disclosed in this application, a second dielectric layer is formed above the stacked layers. (See reference...) Figure 2B As shown, a first dielectric layer 150 is provided on top of the stacked layer 110, and a second dielectric layer 160 covers the first dielectric layer 150 and covers the channel structure 113. In some embodiments, the material of the second dielectric layer 160 includes one or more of silicon oxide (SiO2), silicon oxynitride, aluminum oxide (Al2O3), and titanium nitride. For example, the material of the second dielectric layer 160 is silicon oxide (SiO2). The deposition method for forming the second dielectric layer 160 includes various methods such as chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). Referring to FIG3, in this embodiment, the second dielectric layer 160 uses the same material as the first dielectric layer 150 to avoid internal stress caused by the difference in thermal expansion coefficients in subsequent processes. Figures 2C-4C The same pattern is used for identification.

[0048] The second dielectric layer is formed on top of the stack, which can avoid damage to the channel structure 113 caused by subsequent process steps, such as chemical mechanical polishing (CMP).

[0049] Referring to Figure 2A and Figure 2B As shown in FIG. 1, in step S120, the sacrificial layer 111 in the stack 110 is removed, and a conductive material is filled in the void formed after the removal of the sacrificial layer 111 to form the gate layer 114.

[0050] In some embodiments of the present application, the step of removing the sacrificial layer in the stack and filling a conductive material in the void formed after the removal of the sacrificial layer to form the gate layer includes: forming a gate line slot through the stack in the first direction D1; removing the sacrificial layer in the stack through the gate line slot; and filling a conductive material in the void formed after the removal of the sacrificial layer to form the gate layer.

[0051] The specific process is as follows:

[0052] A gate line slot (not shown in the figure) is formed through the stack in the first direction D1, the sacrificial layer 111 in the stack 110 is removed through the gate line slot, and a conductive material is filled in the void formed after the removal of the sacrificial layer 111 to form the gate layer 114. In some embodiments of the present application, the gate line slot can reach the semiconductor layer 120 in a direction perpendicular to the semiconductor layer 120. The gate line slot has an elongated shape, also known as a slit. The sacrificial layer 111 in the stack 110 can be completely removed through the gate line slot, at which time the sacrificial layer 111 functions as a gate sacrificial layer, and a conductive material is filled in the void formed after the removal of the sacrificial layer 111 through a semiconductor process to form the gate layer 114. In this way, a structure is formed in the stack 110 in which the gate layer 114 and the dielectric layer 112 are alternately stacked. For example, a wet etching process is used to remove the sacrificial layer 111. The material of the gate layer 114 can be a conductive material such as tungsten, cobalt, copper, nickel, etc., or can be polysilicon, doped silicon, or any combination thereof. In a 3D NAND, the gate layer 114 can function as a word line of a three-dimensional memory.

[0053] In some embodiments of the present application, in the case where the second dielectric layer 160 does not exist on top of the stack, a second dielectric layer 160 is formed on the first dielectric layer 150 above the stack before the removal of the sacrificial layer in the stack to protect the channel structure 113 from damage. Figures 2C to 2J As shown in FIG. 1, in step S130, a plurality of contact holes are formed, each of which penetrates through a plurality of layers in the stack to reach the gate layer at a respective predetermined depth.

[0054] In an embodiment of the present application, the step of forming the plurality of contact holes comprises the steps of: forming a hard mask layer on the stack; covering a first photoresist on the hard mask layer; and patterning the hard mask layer through the first photoresist to form a plurality of openings reaching the top gate layer in the gate stack.

[0055] Referring to Figure 2C As shown, first, a hard mask layer 170 is formed on the surface of the second dielectric layer 160 located above the stack 110. The material of the hard mask layer 170 includes aluminum oxide (Al203), silicon oxynitride (SiON), silicon nitride (SiN), silicon oxide (SiO2), or the like. The deposition method for forming the hard mask layer 170 includes chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the like. x N y As shown, first, a hard mask layer 170 is formed on the surface of the second dielectric layer 160 located above the stack 110. The material of the hard mask layer 170 includes aluminum oxide (Al203), silicon oxynitride (SiON), silicon nitride (SiN), silicon oxide (SiO2), or the like. The deposition method for forming the hard mask layer 170 includes chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the like.

[0056] Referring to Figure 2D and 3A As shown, first, a hard mask layer 170 is formed on the surface of the second dielectric layer 160 located above the stack 110. The material of the hard mask layer 170 includes aluminum oxide (Al203), silicon oxynitride (SiON), silicon nitride (SiN), silicon oxide (SiO2), or the like. The deposition method for forming the hard mask layer 170 includes chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the like. Figure 3A is a top view of a memory device, Figure 2D is Figure 3A is a cross-sectional view at the dotted line in FIG. 11. Next, a first photoresist layer 180 is covered on the hard mask layer 170. The first photoresist layer 180 covers the first region 130 and the second region 140. The first photoresist layer 180 is patterned to form a mask for etching the plurality of openings.

[0057] Referring to Figure 2E As shown, then, the hard mask layer 170 is patterned with the patterned first photoresist 180 as a mask to form a plurality of openings 190 reaching the top gate layer 114a in the gate stack 114. After the plurality of openings 190 are formed, the first photoresist 180 is removed.

[0058] In an embodiment of the present application, the step of forming the plurality of contact holes comprises: coating a second photoresist on the hard mask layer; and repeatedly performing the steps of trimming the second photoresist in a first direction, exposing a predetermined number of openings, and etching a predetermined number of layers of the stack through the exposed openings to form the plurality of contact holes with the plurality of openings.

[0059] Figures 2F to 2J The manufacturing process of the foregoing steps is exemplarily shown. Referring to Figure 2F and 3B As shown, first, a second photoresist 210 is coated on the hard mask layer 170. It is to be noted that, when the second photoresist 210 is coated, preferably, the second photoresist 210 covers the entire surface of the hard mask layer 170. Figure 2F The reason why the second photoresist 210 does not cover the leftmost opening 190 is shown in Figure 2FThe second photoresist 210 is shown trimmed to expose the leftmost column of openings 190.

[0060] In the trim-etch steps that are performed in a loop, Figure 2F The first step in the loop is shown, where the second photoresist 210 is trimmed in the first direction Dl to expose a predetermined number of openings 190. The exposed openings 190a are shown in Figure 3B The top view of the semiconductor device 100 is shown with the leftmost column of openings 190 exposed.

[0061] Referring to Figure 2G The exposed openings 190a are shown etching through the predetermined number of layers of the stack below. In Figure 2G In the embodiment shown, the predetermined number of layers is two, namely one layer of gate material 114 (here, the top gate material layer 114a) and one layer of dielectric material 112 (here, the top dielectric layer 112a). After etching, the exposed openings 190a have a depth that extends down to the gate material layer 114b. It is noted that the exposed openings 190a reach the gate material layer 114a by etching the top gate material layer 114a and the top dielectric layer 112a, but not the gate material layer 114b. Due to the etching process, the top surface of the gate material layer 114b reached by the openings 190a can have some thickness etched away, so the exposed openings 190a can reach the interior of the gate material layer 114b, but not penetrate the gate material layer 114b. This description applies to other opening structures in this application.

[0062] The application does not limit the number of predetermined layers.

[0063] Referring to Figure 2H The exposed openings 190a are shown etching through the predetermined number of layers of the stack below. In Figure 2H The top view of the semiconductor device 100 is shown with the leftmost column of openings 190 exposed.

[0064] Referring to Figure 2I The exposed openings 190a are shown etching through the predetermined number of layers of the stack below. In

[0065] Figures 2F-2I The first step in the loop is shown, where the second photoresist 210 is trimmed in the first direction Dl to expose a predetermined number of openings 190. The exposed openings 190a are shown inFigure 2J The plurality of first contact holes 220 are shown. Among them, the leftmost first contact hole 220a reaches the bottom gate layer 114d of the stack layer 110 in depth, and the rightmost first contact hole 220b reaches the top gate layer 114a of the stack layer 110 in depth. And from left to right, the depths of the plurality of contact holes 220 decrease in turn, each reaching the gate layer 114 at its predetermined depth, and the plurality of contact holes 220 form a series of contact hole structures with gradually decreasing depths along the first direction D1. Figure 2J The leftmost first contact hole 220a in the embodiment reaches the bottom gate layer 114d of the stack layer 110 in depth, and the rightmost first contact hole 220b reaches the top gate layer 114a of the stack layer 110 in depth. And from left to right, the depths of the plurality of contact holes 220 decrease in turn, each reaching the gate layer 114 at its predetermined depth, and the plurality of contact holes 220 form a series of contact hole structures with gradually decreasing depths along the first direction D1.

[0066] The present application replaces the etch-selective lower sacrificial layer-dielectric layer in the stack structure with the etch-selective higher gate layer-dielectric layer by removing the sacrificial layer in the stack and filling the gate layer in the gap formed by removing the sacrificial layer before etching the plurality of contact holes. When etching the contact holes, the gate layer is more difficult to etch than the sacrificial layer, avoiding the over-etching problem that occurs when etching the sacrificial layer-dielectric layer, so that the contact holes accurately reach the predetermined gate layer.

[0067] Referring to Figures 4A-4C As shown, after forming the plurality of contact holes 220, the second photoresist 210 and the hard mask layer 170 are removed.

[0068] In some embodiments of the present application, after forming the plurality of contact holes 220, a contact structure is formed in the plurality of contact holes 220. The step of forming a contact structure in the plurality of contact holes includes: forming an insulating layer on the side wall and bottom of the contact hole; removing the insulating layer on the bottom of the contact hole to expose the gate layer; filling a conductive material inside the insulating layer of the contact hole, the conductive material being in electrical contact with the exposed gate layer.

[0069] Referring to Figure 4A As shown, first, an insulating layer 221 is formed on the side wall and bottom of the plurality of contact holes 220. Among them, the material of the insulating layer 221 includes oxide.

[0070] Referring to Figure 4B As shown, then, the insulating layer 221 on the bottom of the plurality of contact holes 220 is removed, leaving the insulating layer 221 on the side wall, exposing the gate layer 114 below the plurality of contact holes 220.

[0071] Referring to Figure 4B And 4C As shown, then, the insulating layer 221 on the bottom of the plurality of contact holes 220 is removed, leaving the insulating layer 221 on the side wall, exposing the gate layer 114 below the plurality of contact holes 220. As shown, then, the insulating layer 221 on the bottom of the plurality of contact holes 220 is removed, leaving the insulating layer 221 on the side wall, exposing the gate layer 114 below the plurality of contact holes 220.

[0072] It is to be noted that the manufacturing method of the memory device of the present application is also applicable to form a unidirectional staircase contact structure, and is also applicable to other types of staircase contact structures, thereby achieving similar effects to those conventionally formed on a stack layer. For example, the effects similar to a staircase divide scheme (SDS) are achieved by a zoned staircase contact structure, and the effects similar to a chop formed staircase structure are achieved. In the zoned staircase contact structure, the contact structure 230 reaches different depths in a staircase manner not only in the first direction D1, but also in a second direction D2 (a direction perpendicular to the paper in FIG. 4) perpendicular to the first direction D1. In the chop formed staircase contact structure, the contact structure 230 reaches different depths in a chop formed manner in the first direction D1. Figure 2A

[0073] The present application replaces the sacrificial layer-dielectric layer with a high etching selectivity in the stack structure with a gate layer-dielectric layer with a low etching selectivity, and then etches a plurality of openings to obtain a plurality of contact structures, thereby enabling the contact structures to accurately electrically connect with the gate layer at a predetermined depth. The electrical connection failure caused by over-etching or under-etching is avoided.

[0074] In addition, compared with the process step sequence of first forming a plurality of openings, then replacing the sacrificial layer in the stack structure with a gate layer, and finally forming a plurality of contact structures through the plurality of openings, the process step sequence of the present application of first replacing the sacrificial layer in the stack structure with a gate layer, then forming a plurality of openings each reaching a predetermined depth of the gate layer, and finally forming a plurality of contact structures through the plurality of openings has the advantages of saving the sacrificial material for filling the plurality of openings, and omitting the step of removing the cap oxide layer in the plurality of openings.

[0075] The present application also provides a memory device manufactured by the manufacturing method described above. Referring to FIG. 2, the memory device 200 includes a stack structure 110 and a plurality of contact structures 230. The stack structure 110 includes alternately stacked gate layers 114 and dielectric layers 112, and each contact structure 230 reaches a respective predetermined depth of the gate layer by penetrating through a plurality of layers of the stack structure 110. In some embodiments of the present application, the memory device 200 further includes a semiconductor layer 120, and the stack structure 110 covers the semiconductor layer 120. In other embodiments of the present application, the memory device further includes at least one gate line slot (not shown in the figure) extending along the first direction D1 and penetrating through the stack structure 110. Figure 4C

[0076] ​​The memory device manufactured by the manufacturing method described above has contact structures accurately electrically connected with the respective predetermined depth gate layers, avoiding the electrical connection failure of the contact structures with the predetermined depth gate layers caused by over-etching or under-etching.

[0077] Another aspect of the present application also provides a memory system including a memory device as described above configured to store data, and a memory controller coupled to the memory device and configured to control the memory device. In some embodiments of the present application, the memory system further includes a host coupled to the memory controller.

[0078] Although the present application has been described with reference to the current exemplary embodiments, it will be recognized by those of ordinary skill in the art that various substitutions, modifications and changes can be made to the embodiments without departing from the spirit of the present application. Accordingly, it is intended that the scope of the present application be governed by the following claims and their equivalents.

Claims

1. A method of manufacturing a memory device, characterized by, comprising: providing a semiconductor structure, the semiconductor structure comprising a stack of layers, the stack of layers comprising sacrificial layers and dielectric layers alternately stacked; removing the sacrificial layers in the stack of layers, the gate layers being formed by filling a conductive material in voids formed after removing the sacrificial layers, the etch selectivity ratio of the gate layers to the dielectric layers being greater than the etch selectivity ratio of the sacrificial layers to the dielectric layers; and after forming the gate layers, forming a plurality of contact holes, each of the contact holes penetrating through a number of layers in the stack of layers to reach the gate layers at a respective predetermined depth. the steps of removing the sacrificial layers in the stack of layers and filling a conductive material in voids formed after removing the sacrificial layers to form gate layers comprise:

2. The production method according to claim 1, wherein forming gate line trenches through the stack of layers in a first direction; removing the sacrificial layers in the stack of layers through the gate line trenches; filling a conductive material in voids formed after removing the sacrificial layers to form gate layers. before removing the sacrificial layers in the stack of layers, further comprising forming a second dielectric layer on top of the stack of layers.

3. The production method according to claim 1, wherein before forming the plurality of contact holes, further comprising:

4. The production method according to claim 1, wherein forming a hard mask layer on the stack of layers; covering a first photoresist on the hard mask layer; patterning the hard mask layer through the first photoresist to form a plurality of openings reaching top gate layers in the gate layers. the steps of forming the plurality of contact holes comprise:

5. The production method according to claim 4, wherein applying a second photoresist on the hard mask layer; cyclically performing the steps of trimming the second photoresist in a first direction, exposing a predetermined number of the openings, and etching a predetermined number of layers of the stack of layers through the exposed openings to form the plurality of contact holes using the plurality of openings. further comprising forming contact structures in the plurality of contact holes.

6. The production method according to claim 1, wherein the steps of forming the contact structures in the plurality of contact holes comprise:

7. The production method according to claim 6, wherein forming an insulating layer on the sidewalls and the bottom of the contact holes; removing the insulating layer on the bottom of the contact holes to expose the gate layers; filling a conductive material on the inside of the insulating layer of the contact holes, the conductive material being in electrical contact with the exposed gate layers. comprising:

8. A memory device manufactured according to the manufacturing method as claimed in any one of claims 1 to 7, characterized in that, a stack structure, the stack structure comprising gate layers and dielectric layers alternately stacked; a plurality of contact structures, each of the contact structures penetrating through a number of layers of the stack structure to reach the gate layers at a respective predetermined depth. further comprising at least one gate line trench extending in a first direction and penetrating through the stack structure.

9. The memory device of claim 8, wherein, further comprising a semiconductor layer, the stack structure covering the semiconductor layer.

10. The memory device of claim 8, wherein, comprising the memory device of any one of claims 8-10 configured to store data, and a memory controller coupled to the memory device and configured to control the memory device.

11. A memory system, characterized by comprising: further comprising a host coupled to the memory controller.

12. The memory system of claim 11, wherein, ​

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