A shielding structure of a CMOS sensitive signal pad

Abstract

The application provides a shielding structure of a CMOS sensitive signal PAD, which comprises a sensitive signal PAD, a first shielding structure and a second shielding structure. The sensitive signal PAD comprises a first passivation layer and a first metal layer. The first shielding structure comprises a second passivation layer and a second metal layer. The second shielding structure comprises a third passivation layer and a third metal layer. The first metal layer, the second metal layer and the third metal layer are parallel to each other and are at a first preset height. The first metal layer is apart from the second metal layer by a preset distance. The first metal layer is apart from the third metal layer by a preset distance. The first shielding structure and the second shielding structure replace the left and right shielding PADs, and the distance between the PADs on the left and right sides of the sensitive signal PAD is increased, so that the signal integrity of the sensitive signal PAD is ensured and the area of the chip is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of integrated circuit layout design, and particularly relates to a shielding structure of a CMOS sensitive signal PAD. BACKGROUND

[0002] In the integrated circuit layout design, the layout Figure One Generally, the performance, area and time are compromised, when facing the clock or high-speed differential signal, the performance needs to be considered first, and the signal needs to be shielded according to the situation. For the internal sensitive signal line, the ground line or power line is often used for shielding, and the commonly used shielding methods include left-right shielding and up-down-left-right four-way shielding, which need to be selected according to the actual situation and the sensitivity of the signal line.

[0003] For some sensitive signal PADs (pads) that need to be pulled to the pin through the binding line, shielding treatment is also needed, and the existing method generally adds corresponding power PADs or ground line PADs on the left and right sides of the sensitive signal PAD as shielding, such as Figures 1 to 3 In the prior art, the ground line PAD 11 and the ground line PAD 13 (or the power PAD 11 and the power PAD 13) are arranged on the left and right sides of the sensitive signal PAD 12 to shield the interference on the sensitive signal PAD 12, or to increase the distance between the sensitive signal PAD and the PADs on the left and right sides as much as possible. The above two methods will greatly increase the width of the chip module, and further increase the chip area. If it is a PAD limit layout, that is, the area of the chip is determined by the PAD on the chip, the increased width will also cause the forced increase of the chip area.

[0004] A Chinese invention patent with the publication number CN106206547A discloses an integrated circuit packaging structure and a manufacturing method thereof. The packaging structure prevents electromagnetic chips from being disturbed by a ring-shaped shielding layer, thereby reducing the packaging volume. The ring-shaped shielding layer can be metal. However, the scheme is applied to the electromagnetic chip layout shielding structure in the PCB (printed circuit board) category and cannot be directly applied to the layout shielding structure based on the SOC (System on a Chip) chip. In addition, the electromagnetic chip shielding structure in the scheme is a groove metal structure with a ring-shaped shielding layer. The electromagnetic chip is in the middle, and the metal closed shielding ring is around. In the SOC, the physical parameters such as the number of metal layers and the height of each chip are fixed. If a groove is also set at the bottom to use metal as a shielding layer, on the one hand, it will cause a large parallel area between the signal PAD and the shielding layer, resulting in an increase in parasitic capacitance and affecting the parameters of the signal on the signal PAD. On the other hand, more importantly, when the signal PAD is welded with the lead, a considerable mechanical stress will be generated downward. If there is a large metal block at the bottom, the metal layer is prone to collapse, thereby causing a short circuit and making the real signal of the signal PAD incorrect. In addition, in the CMOS production process, in addition to the metal of the signal PAD, the metal of other levels is not allowed to have a large block. If there is a large block, the large block must be slotted or changed to a plurality of small-width metals in parallel. Otherwise, the edge of the large block is prone to be raised to break through the oxide layer and short-circuit with other levels of metal. In the PCB layout design, there is no limitation on the width of the metal. SUMMARY

[0005] The purpose of the present application is to provide a CMOS sensitive signal PAD shielding structure which guarantees the integrity of the sensitive signal PAD while reducing the chip area.

[0006] In order to achieve the first purpose, the present application provides a CMOS sensitive signal PAD shielding structure, which comprises a sensitive signal PAD, a first shielding structure, and a second shielding structure. The sensitive signal PAD comprises a first passivation layer and a first metal layer. The first shielding structure comprises a second passivation layer and a second metal layer. The second shielding structure comprises a third passivation layer and a third metal layer. The metal of the second metal layer and the metal of the third metal layer are the same as the metal of the first metal layer. The first passivation layer is fixed on the first metal layer. The second passivation layer is fixed on the second metal layer. The third passivation layer is fixed on the third metal layer. The first passivation layer is provided with a window allowing external sensitive signals to be connected to the first metal layer. The first shielding structure and the second shielding structure are both connected to the ground or both connected to the power supply. The first metal layer, the second metal layer, and the third metal layer are parallel to each other and at a first preset height. The first metal layer is separated from the second metal layer by a preset distance. The first metal layer is separated from the third metal layer by a preset distance.

[0007] From the above scheme, the application realizes the protection of the integrity of the sensitive signal through the first shielding structure and the second shielding structure, replaces the left and right shielding PAD, and increases the distance between the PADs on the left and right sides of the sensitive signal PAD, so as to reduce the area of the chip while ensuring the signal integrity of the sensitive signal PAD.

[0008] Further, the sensitive signal PAD includes a first sub-metal layer, the first shielding structure includes a second sub-metal layer, and the second shielding structure includes a third sub-metal layer; the metal of the first sub-metal layer, the metal of the second sub-metal layer, and the metal of the third sub-metal layer are the same as the metal of the first metal layer; the first sub-metal layer is connected to the first metal layer, the second sub-metal layer is connected to the second metal layer, and the third sub-metal layer is connected to the third metal layer; the first sub-metal layer, the second sub-metal layer, and the third sub-metal layer are parallel to each other and are at a second preset height, the second preset height is less than the first height, the first sub-metal layer is separated from the second sub-metal layer by a preset distance, and the first sub-metal layer is separated from the third sub-metal layer by a preset distance.

[0009] Therefore, the demand for shielding signal PADs using the DUP structure can be met.

[0010] Further, the first sub-metal layer is connected to the first metal layer through a through silicon via, the second sub-metal layer is connected to the second metal layer through a through silicon via, and the third sub-metal layer is connected to the third metal layer through a through silicon via.

[0011] Further, the first passivation layer, the second passivation layer, and the third passivation layer are all aluminum pad passivation layers.

[0012] Further, the metal of the first metal layer is copper. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a sectional view of a shielding PAD of a prior art sensitive signal PAD.

[0014] Figure 2 is a top view of a layout of a shielding PAD of a single sensitive signal PAD of the prior art.

[0015] Figure 3 is a top view of a layout of a shielding PAD of multiple sensitive signal PADs of the prior art.

[0016] Figure 4 is a sectional view of a shielding structure of a sensitive signal PAD of the application.

[0017] Figure 5 is a top view of a layout of a shielding structure of a single sensitive signal PAD of the application.

[0018] Figure 6 is a top view of the layout of the shielding structure of the plurality of sensitive signal PADs of the present application.

[0019] The present application is further described below in conjunction with the accompanying drawings and examples. DETAILED DESCRIPTION

[0020] The present application replaces the shielding PAD with a shielding structure, thereby reducing the area of the chip.

[0021] Referring to Figures 4 to 6 , the CMOS sensitive signal shielding PAD includes a sensitive signal PAD 12, a first shielding structure 21, and a second shielding structure 22. The sensitive signal PAD 12 includes a first passivation layer 120 and a first metal layer 121. The first shielding structure 21 includes a second passivation layer 210 and a second metal layer 211. The second shielding structure 22 includes a third passivation layer 220 and a third metal layer 221. The metal of the second metal layer 211 and the metal of the third metal layer 221 are the same as the metal of the first metal layer 121. The first passivation layer 120 is fixed on the first metal layer 121. The first passivation layer 210 is fixed on the second metal layer 211. The third passivation layer 220 is disposed on the third metal layer 221. The first metal layer 121, the second metal layer 211, and the third metal layer 221 are parallel to each other and at a first predetermined height. The first metal layer 121 is separated from the second metal layer 211 by a predetermined distance. The first metal layer 121 is separated from the third metal layer 221 by a predetermined distance. The first predetermined height and the predetermined distance are determined according to the design rules given by the integrated circuit manufacturer. In the absence of short circuit, the first predetermined height and the predetermined distance should be as small as possible to reduce the use of chip area. It should be noted that the first predetermined height and the second predetermined height of the present application are both taken as zero reference surface of the substrate 61.

[0022] Referring to Figure 5 and Figure 6 , Figure 5 and Figure 6 is a layout from a top view. The first passivation layer 120 is provided with a window (i.e. PAD window, not shown in the figure) allowing external sensitive signals to be connected to the first metal layer 121. Through the window, the first metal layer 121 is connected to the GPIO (General-purpose input / output) inside the chip to receive the sensitive signal. According to the specific chip design, the first shielding structure 21 and the second shielding structure 22 are both connected to the ground or the first shielding structure 21 and the second shielding structure 22 are both connected to the power supply, so as to shield the electromagnetic wave signal and prevent the sensitive signal received by the first metal layer 121 from the GPIO from being disturbed.

[0023] Optionally, the first passivation layer 120, the first metal layer 210, and the third passivation layer 220 are all aluminum pad passivation layers, and the metal of the first metal layer 121 is copper.

[0024] In the DUP (Device Under Pad) structure, the sensitive signal PAD can also use more metal layers. In the embodiment, the sensitive signal PAD 12 further includes a first sub-metal layer 122, the first shielding structure 21 further includes a second sub-metal layer 212, and the second shielding structure 22 further includes a third sub-metal layer 222; the metal of the first sub-metal layer 122, the metal of the second sub-metal layer 212, and the metal of the third sub-metal layer 222 are the same as the metal of the first metal layer 121.

[0025] The first sub-metal layer 122 is connected to the first metal layer 121, the second sub-metal layer 212 is connected to the second metal layer 211, and the third sub-metal layer 222 is connected to the third metal layer 221; the first sub-metal layer 122, the second sub-metal layer 212, and the third sub-metal layer 222 are parallel to each other and at a second preset height, which is smaller than the first preset height, i.e., the first sub-metal layer 122, the second sub-metal layer 212, and the third sub-metal layer 222 are respectively below the first metal layer 121, the second metal layer 211, and the third metal layer 221. The first metal layer 121 is separated from the second metal layer 211 by a preset distance, and the first metal layer 121 is separated from the third metal layer 221 by a preset distance. The first sub-metal layer 122 is connected to the first metal layer 121 through the first through silicon via 31, the second sub-metal layer 212 is connected to the second metal layer 211 through the second through silicon via 41, and the third sub-metal layer 222 is connected to the third metal layer 221 through the third through silicon via 51. Similarly, in the case where the first shielding structure 21 and the second shielding structure 22 are both connected to the ground or the first shielding structure 21 and the second shielding structure 22 are both connected to the power supply, the electromagnetic wave signal can be shielded from interfering with the sensitive signal input to the first sub-metal layer 122.

[0026] It can be understood that when a fourth sub-metal layer is further provided below the first sub-metal layer 122 (not shown in the figure), the fourth sub-metal layer can be connected to the first sub-metal layer 122 through a fourth through silicon via 311. Similarly, a fifth sub-metal layer (not shown in the figure) and a sixth sub-metal layer (not shown in the figure) can be respectively provided below the second sub-metal layer 212 and the third sub-metal layer 222, and connected through a fifth through silicon via 411 and a sixth through silicon via 511, respectively, to shield the signal of the fourth sub-metal layer and prevent external electromagnetic wave signals from interfering with the sensitive signal in the fourth sub-metal layer.

[0027] Since the width of the window (PAD window) on the sensitive signal PAD 12 is basically tens of microns (40um to 80um), and the first shielding structure 21 and the second shielding structure 22, which do not need to be set in the window, are in the form of metal shielding lines, the width thereof can be reduced by an order of magnitude (width is 4um to 8um), so that the more the sensitive signal PAD needs to be shielded, the more the first shielding structure 21 and the second shielding structure 22 can greatly reduce the width of the chip, thereby reducing the chip area.

[0028] In summary, the present application realizes the protection of the integrity of the sensitive signal through the first shielding structure and the second shielding structure, instead of the left and right shielding PAD and by increasing the distance between the PADs on the left and right sides of the sensitive signal PAD, while ensuring the signal integrity of the sensitive signal PAD, the chip area is reduced.

Claims

1. A shielding structure for a CMOS sensitive signal PAD, characterized in that, include: The system includes a sensitive signal PAD, a first shielding structure, and a second shielding structure. The sensitive signal PAD includes a first passivation layer and a first metal layer. The first shielding structure and the second shielding structure are implemented as metal shielding lines. The first shielding structure includes a second passivation layer and a second metal layer. The second shielding structure includes a third passivation layer and a third metal layer. The metal of the second metal layer and the metal of the third metal layer are the same as the metal of the first metal layer. The first passivation layer is fixed on the first metal layer, the second passivation layer is fixed on the second metal layer, and the third passivation layer is fixed on the third metal layer; the first passivation layer has a window that allows external sensitive signals to connect to the first metal layer; Both the first shielding structure and the second shielding structure are connected to the ground terminal, or both the first shielding structure and the second shielding structure are connected to the power supply terminal; The first metal layer, the second metal layer, and the third metal layer are parallel to each other and located at a first preset height. The first metal layer and the second metal layer are separated by a preset distance, and the first metal layer and the third metal layer are separated by the preset distance. The sensitive signal PAD includes a first sub-metal layer, the first shielding structure includes a second sub-metal layer, and the second shielding structure includes a third sub-metal layer; the metal of the first sub-metal layer, the metal of the second sub-metal layer, and the metal of the third sub-metal layer are all the same as the metal of the first metal layer. The first sub-metal layer is connected to the first metal layer, the second sub-metal layer is connected to the second metal layer, and the third sub-metal layer is connected to the third sub-metal layer; The first sub-metal layer, the second sub-metal layer, and the third sub-metal layer are parallel to each other and located at a second preset height, the second preset height being less than the first preset height. The first sub-metal layer and the second sub-metal layer are separated by a preset distance, and the first sub-metal layer and the third sub-metal layer are separated by a preset distance. The first sub-metal layer is connected to the first metal layer through a first through-silicon via (TSV), the second sub-metal layer is connected to the second metal layer through a second TSV, and the third sub-metal layer is connected to the third sub-metal layer through a third TSV.

2. The shielding structure of the CMOS sensitive signal PAD as described in claim 1, characterized in that: The first passivation layer, the second passivation layer, and the third passivation layer are all aluminum pad passivation layers.

3. The shielding structure of the CMOS sensitive signal PAD as described in any one of claims 1, characterized in that: The metal of the first metal layer is copper.

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