A heterojunction bipolar light-emitting transistor display and a preparation method thereof

Abstract

The present invention provides a heterojunction bipolar light-emitting transistor display and a manufacturing method thereof, including: a plurality of pixels, a driving backplane, a dielectric layer, and a common electrode. Each of the pixels includes three sub-pixel units, namely a sub-pixel unit R, a sub-pixel unit G, and a sub-pixel unit B. A plurality of regularly arranged vias are provided on the driving backplane, and at least one of the vias is covered by the sub-pixel unit. The driving backplane carries a plurality of pixels and is used to drive the sub-pixel units to emit light. The sub-pixel unit includes an anode, a semiconductor layer, an emitter, two first metal electrodes, a second metal electrode, and an LED light-emitting unit. The present invention uses semiconductor processes to manufacture the heterojunction bipolar light-emitting transistor display, thereby achieving display functions with high resolution, high brightness, high contrast, high-gain driving, and low response time.

Description

Technical Field

[0001] The present invention belongs to the field of triode displays, and particularly relates to a heterojunction bipolar light-emitting triode display and a preparation method thereof. Background Art

[0002] With the development of science and technology, emerging intelligent fields represented by smart phones, tablets, smart homes, and wearable electronic communication devices have been booming, which also puts forward higher requirements for the display structure, such as being thinner, more efficient, and clearer. Similarly, high-performance display technologies rely on electronic technologies and their core power devices.

[0003] Vertical light-emitting triodes, with their excellent material properties, can be used for devices to achieve high picture quality, ultra-thin displays, and large-area plasma displays, breaking through the theoretical performance limits of traditional display devices. Compared with light-emitting diode display devices, vertical light-emitting triodes are expected to give full play to the material advantages of semiconductors to a greater extent and achieve high-definition, high-efficiency, and ultra-thin device characteristics, thus receiving extensive attention and becoming an important development direction of display devices.

[0004] A heterojunction bipolar transistor (HBT) has different semiconductor materials for its emitter and base regions, so that the PN junction between the emitter and the base region forms a heterojunction. Compared with ordinary bipolar transistors, heterojunction bipolar transistors are superior to ordinary bipolar transistors in both high-frequency signals and base transport efficiency and can operate in the range of several hundred GHz. They have extensive applications in modern high-speed circuits, radio frequency systems, mobile phones, and other fields. Summary of the Invention

[0005] The purpose of the present invention is to provide a heterojunction bipolar light-emitting triode display and a preparation method thereof, using semiconductor processes to prepare a heterojunction bipolar light-emitting triode display, so as to achieve display functions of high resolution, high brightness, high contrast, high gain drive, and low response time.

[0006] The specific technical solution of the present invention is as follows:

[0007] A heterojunction bipolar light-emitting triode display, comprising:

[0008] A plurality of pixels, each pixel including three sub-pixel units, namely sub-pixel unit R, sub-pixel unit G, and sub-pixel unit B;

[0009] A driving backplane, on which a number of regularly arranged vias are provided, and the sub-pixel unit covers at least one of the vias; the driving backplane carries a plurality of pixels and is used to drive the sub-pixel units to emit light;

[0010] The sub-pixel unit includes an anode, a semiconductor layer, an emitter, two first metal electrodes, a second metal electrode, and an LED light-emitting unit. Among them, the anode is located on the driving backplane and covers at least one via hole. The semiconductor layer is located on the side of the anode away from the driving backplane. The emitter is located on the side of the semiconductor layer away from the driving backplane. The two first metal electrodes are symmetrically arranged on both sides of the emitter and are both located on the side of the semiconductor layer away from the driving backplane. The second metal electrode is located on the side of the emitter away from the driving backplane. The LED light-emitting unit is located on the side of the second metal electrode away from the driving backplane;

[0011] A dielectric layer, the dielectric layer is filled and coated between each sub-pixel unit, and an electrode groove is formed on the corresponding dielectric layer in each sub-pixel unit. The upper surface of a part of the LED light-emitting unit is exposed at the bottom of the electrode groove in the sub-pixel unit;

[0012] A common electrode, the common electrode is grown on the side of the dielectric layer away from the driving backplane and covers the electrode groove. The common electrode is in contact with the upper surface of the LED light-emitting unit through the electrode groove.

[0013] Preferably, it further includes a glass encapsulation layer. The glass encapsulation layer is bonded to the side of the common electrode away from the driving backplane by UV glue, and the UV glue is located in the peripheral area of the glass encapsulation layer.

[0014] Preferably, the semiconductor layer is an NPN-type semiconductor layer.

[0015] Preferably, the NPN-type semiconductor layer includes an n + GaN layer, an n - GaN layer, and an InGaN layer from bottom to top.

[0016] Preferably, the LED light-emitting unit includes a first bonding metal layer, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a second bonding metal layer. The first bonding metal layer is bonded and grown on the side of the second metal electrode away from the driving backplane. The first semiconductor layer is located on the upper surface of the first bonding metal layer. The light-emitting layer is arranged on the upper surface of the first semiconductor layer; the second semiconductor layer is arranged on the upper surface of the light-emitting layer, and the second bonding metal layer is located on the side of the second semiconductor layer away from the driving backplane.

[0017] Preferably, the light-emitting layer in the sub-pixel unit R is a red multi-quantum well structure light-emitting material; the light-emitting layer in the sub-pixel unit G is a green multi-quantum well structure light-emitting material; the light-emitting layer in the sub-pixel unit B is a blue multi-quantum well structure light-emitting material.

[0018] Preferably, the dielectric layer is a silicon oxide dielectric layer.

[0019] Preferably, the emitter is an n+ AlGaN emitter.

[0020] A method for preparing a heterojunction bipolar light-emitting transistor display, the specific preparation steps are as follows:

[0021] S1: Form a number of regularly arranged vias on the driving backplane, fill the vias with a conductive material, and then form a number of anodes on the upper surface of the driving backplane, and contact the upper surface of the vias;

[0022] S2: Then grow a semiconductor layer on the upper surface of the anode and the driving backplane in sequence;

[0023] S3: Pattern the semiconductor layer so that the semiconductor layer is located on the side of the anode away from the driving backplane;

[0024] S4: Fill and grow a dielectric layer between each sub-pixel unit so that the upper surface of the dielectric layer is flush with the upper surface of the semiconductor layer;

[0025] S5: Use magnetron sputtering technology to coat an emitter and a first metal electrode on the upper surface of the semiconductor layer, and perform patterning and CMP planarization processing on the emitter and the first metal electrode respectively;

[0026] S6: Continue to use magnetron sputtering technology to coat a second metal electrode on the upper surface of the emitter, and perform patterning, then continue to fill the dielectric layer, and perform CMP planarization processing on it so that the dielectric layer is flush with the upper surface of the second metal electrode;

[0027] S7: Use mass transfer and vacuum bonding technology to bond and connect an LED light-emitting unit to the side of the second metal electrode away from the driving backplane, and perform planarization processing;

[0028] S8: Continue to fill and grow a dielectric layer between each sub-pixel unit, and perform patterning on it, form an electrode groove corresponding to each sub-pixel unit, then grow a common electrode on the upper surface of the dielectric layer, and the common electrode contacts the upper surface of the LED light-emitting unit through the electrode groove, and finally bond the glass encapsulation layer on the upper surface of the common electrode with UV glue.

[0029] Advantageous effects: The present invention discloses a heterojunction bipolar light-emitting transistor display and a preparation method thereof, having the following advantages:

[0030] (1) Through semiconductor processes, vertical oxide transistor devices are fabricated on the surface of the driving backplane. The conductance gain of the transistors provides intrinsic amplification for carriers, significantly reducing electrical noise in display devices, thereby achieving high-gain driving for high-resolution displays. This not only realizes display functions with high resolution, high brightness, high contrast, and low response time, but also enables high-gain driving for high-resolution microdisplays, making it possible to quickly and clearly display static images and dynamic videos at low currents.

[0031] (2) By optimizing pixel arrangement methods or schemes, true RGB three-color displays with a pixel density of greater than 1000 ppi are achieved, thereby breaking through the physical limits of existing evaporation patterning and realizing true RGB three-color displays with high pixel density. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the structure of step S1 in Embodiment 1;

[0033] Figure 2 Schematic diagram of the structure of step S2 in Embodiment 1;

[0034] Figure 3 Schematic diagram of the structure of step S3 in Embodiment 1;

[0035] Figure 4 Schematic diagram of the structure of step S4 in Embodiment 1;

[0036] Figure 5 Schematic diagram of the structure of step S5 in Embodiment 1;

[0037] Figure 6 Schematic diagram of the structure of step S6 in Embodiment 1;

[0038] Figure 7 Schematic diagram of the structure of step S7 in Embodiment 1;

[0039] Figure 8 Schematic diagram of the structure of step S8 in Embodiment 1, which is the overall structure diagram of the product;

[0040] Figure 9 Optimized pixel arrangement scheme of the present invention;

[0041] Figure 10 Driving circuit diagram of the present invention;

[0042] In the figure: sub-pixel unit R1-1, sub-pixel unit G1-2, sub-pixel unit B1-3, driving backplane 2, via hole 3, anode 4-1, NPN-type semiconductor layer 4-2, n+AlGaN emitter 4-3, first metal electrode 4-4, second metal electrode 4-5, LED light-emitting unit 4-6, first bonding metal layer 4-61, first semiconductor layer 4-62, light-emitting layer 4-63, second semiconductor layer 4-64, second bonding metal layer 4-65, dielectric layer 5, common electrode 6, glass encapsulation layer 7, UV glue 8. Detailed implementation

[0043] The following makes several improvements and refinements to the present invention in conjunction with the accompanying drawings, and these improvements and refinements should also be regarded as the protection scope of the present invention.

[0044] Example 1:

[0045] A heterojunction bipolar light-emitting transistor display, characterized in that it includes:

[0046] Multiple pixels, each of the pixels includes three sub-pixel units, namely sub-pixel unit R1-1, sub-pixel unit G1-2, and sub-pixel unit B1-3;

[0047] Driving backplane 2, on which a number of regularly arranged via holes 3 are provided, and the sub-pixel unit covers at least one of the via holes 3; the driving backplane 2 carries multiple pixels and is used to drive the sub-pixel unit to emit light;

[0048] The sub-pixel unit includes an anode 4-1, an NPN-type semiconductor layer 4-2, an n+AlGaN emitter 4-3, two first metal electrodes 4-4, a second metal electrode 4-5, and an LED light-emitting unit 4-6. Among them, the anode 4-1 is located on the driving backplane 2 and covers at least one via hole 3. The NPN-type semiconductor layer 4-2 is located on the side of the anode 4-1 away from the driving backplane 2. The n+AlGaN emitter 4-3 is located on the side of the NPN-type semiconductor layer 4-2 away from the driving backplane 2. The two first metal electrodes 4-4 are symmetrically arranged on both sides of the n+AlGaN emitter 4-3 and are both located on the side of the NPN-type semiconductor layer 4-2 away from the driving backplane 2. The second metal electrode 4-5 is located on the side of the n+AlGaN emitter 4-3 away from the driving backplane 2. The LED light-emitting unit 4-6 is located on the side of the second metal electrode 4-5 away from the driving backplane 2. The NPN-type semiconductor layer 4-2 sequentially includes an n+GaN layer, an n-GaN layer, and an InGaN layer from bottom to top;

[0049] A dielectric layer 5, the dielectric layer 5 is filled and coated between each sub-pixel unit, and electrode grooves are formed on the corresponding dielectric layer 5 in each sub-pixel unit. Part of the upper surface of the LED light-emitting unit 4-6 is exposed at the bottom of the electrode groove in the sub-pixel unit. In this embodiment, the dielectric layer is a silicon oxide dielectric layer;

[0050] A common electrode 6, the common electrode 6 is grown on the side of the dielectric layer 5 away from the driving backplane 2 and covers the electrode groove. The common electrode 6 is in contact with the upper surface of the LED light-emitting unit 4-6 through the electrode groove;

[0051] A glass encapsulation layer 7, the glass encapsulation layer 7 is bonded to the side of the common electrode 6 away from the driving backplane 2 through a UV glue 8, and the UV glue 8 is located in the peripheral area of the glass encapsulation layer 7.

[0052] The LED light-emitting unit 4-6 includes a first bonding metal layer 4-61, a first semiconductor layer 4-62, a light-emitting layer 4-63, a second semiconductor layer 4-64 and a second bonding metal layer 4-65. The first bonding metal layer 4-61 is bonded and grown on the side of the second metal electrode 4-5 away from the driving backplane 2. The first semiconductor layer 4-62 is located on the upper surface of the first bonding metal layer 4-61. The light-emitting layer 4-63 is disposed on the upper surface of the first semiconductor layer 4-62. The second semiconductor layer 4-64 is disposed on the upper surface of the light-emitting layer 4-63. The second bonding metal layer 4-65 is located on the side of the second semiconductor layer 4-64 away from the driving backplane 2. Among them, the light-emitting layer 4-63 in the sub-pixel unit R1-1 is a red multi-quantum well structure light-emitting material; the light-emitting layer 4-63 in the sub-pixel unit G1-2 is a green multi-quantum well structure light-emitting material; the light-emitting layer 4-63 in the sub-pixel unit B1-3 is a blue multi-quantum well structure light-emitting material.

[0053] The specific preparation steps of the heterojunction bipolar light-emitting transistor display in Embodiment 1 are as follows:

[0054] S1: Form a plurality of regularly arranged vias 3 on the driving backplane 2, fill conductive materials in the vias 3, and then form a plurality of anodes 4-1 on the upper surface of the driving backplane 2 and in contact with the upper surface of the vias 3;

[0055] S2: Then, an NPN-type semiconductor layer 4-2 is sequentially grown on the upper surfaces of the anode 4-1 and the driving backplane 2;

[0056] S3: Perform patterning on the NPN-type semiconductor layer 4-2 so that the NPN-type semiconductor layer 4-2 is located on the side of the anode 4-1 away from the driving backplane 2;

[0057] S4: Fill the growth medium layer 5 between each sub-pixel unit so that the upper surface of the medium layer 5 is flush with the upper surface of the NPN-type semiconductor layer 4-2;

[0058] S5: Use magnetron sputtering technology to deposit an n+AlGaN emitter 4-3 and a first metal electrode 4-4 on the upper surface of the NPN-type semiconductor layer 4-2, and perform patterning and CMP planarization processes on the n+AlGaN emitter 4-3 and the first metal electrode 4-4 respectively;

[0059] S6: Continue to use magnetron sputtering technology to deposit a second metal electrode 4-5 on the upper surface of the n+AlGaN emitter 4-3, and perform patterning. Subsequently, continue to fill the medium layer 5 and perform CMP planarization on it so that the medium layer 5 is flush with the upper surface of the second metal electrode 4-5;

[0060] S7: Use the mass transfer and vacuum bonding technology to bond and connect the LED light-emitting unit 4-6 to the side of the second metal electrode 4-5 away from the driving backplane 2, and perform planarization;

[0061] S8: Continue to fill the growth medium layer 5 between each sub-pixel unit and perform patterning on it to form an electrode groove corresponding to each sub-pixel unit. Subsequently, grow a common electrode 6 on the upper surface of the medium layer 5, and the common electrode 6 contacts the upper surface of the LED light-emitting unit 4-6 through the electrode groove. Finally, bond the glass encapsulation layer 7 to the upper surface of the common electrode 6 using UV glue 8.

[0062] In the present invention, the anode 4-1 is made of a metal oxide, including indium tin oxide, indium zinc oxide, or aluminum zinc oxide.

[0063] In the present invention, in the LED light-emitting unit, the material of the first bonding metal layer 4-61 is P-pad, the materials of the first semiconductor layer 4-62 and the second semiconductor layer 4-64 are n-GaN, the material of the light-emitting layer 4-63 is MQW (multi-quantum well light-emitting material), and the material of the second bonding metal layer 4-65 is N-pad.

[0064] Currently, most OLED display bodies use evaporation of different OLED materials to achieve OLED patterning. This method has no problem when the pixel density ppi is lower than 700. However, when the pixel density ppi is greater than 800, the existing manufacturing technology will enter a physical bottleneck. To achieve high pixel density display, an optimized pixel arrangement needs to be adopted.

[0065] The optimized pixel arrangement scheme in the present invention is as follows:

[0066] As Figure 9As shown, a pixel includes two sub-pixel units G, one sub-pixel unit R, and one sub-pixel unit B. In terms of spatial distribution, the four vertices of a square pixel unit respectively include sub-pixel units G located at two diagonal vertices, and sub-pixel units R and B located at the other two vertices. The side length of the square pixel unit is equal to the pixel pitch. Four concentrated sub-pixel units R form a group, four concentrated sub-pixel units B form a group, and four concentrated sub-pixel units G form a group. Each group shares one mask opening.

[0067] Figure 9 The pixel optimization solution shown in combination with a high-resolution driving backplane can achieve a high-resolution true RGB display panel with 1000 ppi or more, thereby breaking through the physical limit of the existing evaporation patterning and realizing a true RGB three-color display with a high pixel density.

[0068] As Figure 10 Shown is the driving circuit diagram of the present invention. As can be seen from the figure, the gate of the junction MOS transistor Add1 is connected to the address line, the drain is connected to the data line, and the source is grounded after being connected to the capacitor C1. The capacitor C1 is connected to the base of the heterojunction bipolar transistor Mpix1. The collector of the heterojunction bipolar transistor Mpix1 is connected to the power supply line, and the emitter of the heterojunction bipolar transistor Mpix1 is connected to the light-emitting diode and then grounded. When the voltage value of the capacitor C1 reaches a certain value, the emitter of the heterojunction bipolar transistor is forward-biased, thereby turning on the emitter of the heterojunction bipolar transistor, and then the light-emitting diode is turned on.

[0069] The above description is only for the purpose of illustration and is the preferred implementation mode of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the premise of the present invention, several improvements and refinements can still be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A heterojunction bipolar light-emitting transistor display, characterized in that, Comprising: A plurality of pixels, each pixel including three sub - pixel units, namely sub - pixel unit R, sub - pixel unit G, and sub - pixel unit B; A driving backplane, on which a number of regularly arranged vias are provided, and the sub - pixel units cover at least one of the vias; the driving backplane bears a plurality of pixels and is used to drive the sub - pixel units to emit light; The sub - pixel unit includes an anode, a semiconductor layer, an emitter, two first metal electrodes, a second metal electrode, and an LED light - emitting unit. Among them, the anode is located on the driving backplane and covers at least one via. The semiconductor layer is located on the side of the anode away from the driving backplane. The emitter is located on the side of the semiconductor layer away from the driving backplane. The two first metal electrodes are symmetrically arranged on both sides of the emitter and are both located on the side of the semiconductor layer away from the driving backplane. The second metal electrode is located on the side of the emitter away from the driving backplane. The LED light - emitting unit is located on the side of the second metal electrode away from the driving backplane; The semiconductor layer is an NPN - type semiconductor layer, and the NPN - type semiconductor layer sequentially includes an n + GaN layer, an n - GaN layer, and an InGaN layer from bottom to top; The emitter is an n + AlGaN emitter; A dielectric layer, which is filled and coated between each sub - pixel unit. Electrode grooves are formed on the corresponding dielectric layer in each sub - pixel unit, and the upper surface of part of the LED light - emitting unit is exposed at the bottom of the electrode groove in the sub - pixel unit; A common electrode, which is grown on the side of the dielectric layer away from the driving backplane and covers the electrode groove. The common electrode is in contact with the upper surface of the LED light - emitting unit through the electrode groove.

2. The heterojunction bipolar light-emitting transistor display according to claim 1, wherein It further includes a glass encapsulation layer, which is bonded to the side of the common electrode away from the driving backplane through UV glue, and the UV glue is located in the peripheral area of the glass encapsulation layer.

3. The heterojunction bipolar light-emitting transistor display according to claim 1, characterized in that, The LED light - emitting unit includes a first bonding metal layer, a first semiconductor layer, a light - emitting layer, a second semiconductor layer, and a second bonding metal layer. The first bonding metal layer is bonded and grown on the side of the second metal electrode away from the driving backplane. The first semiconductor layer is located on the upper surface of the first bonding metal layer. The light - emitting layer is arranged on the upper surface of the first semiconductor layer. The second semiconductor layer is arranged on the upper surface of the light - emitting layer. The second bonding metal layer is located on the side of the second semiconductor layer away from the driving backplane.

4. The heterojunction bipolar light-emitting transistor display according to claim 3, wherein, The light - emitting layer in the sub - pixel unit R is a red multi - quantum well structure light - emitting material; the light - emitting layer in the sub - pixel unit G is a green multi - quantum well structure light - emitting material; the light - emitting layer in the sub - pixel unit B is a blue multi - quantum well structure light - emitting material.

5. The heterojunction bipolar light-emitting transistor display according to claim 1, wherein, The dielectric layer is a silicon oxide dielectric layer.

6. A method for preparing a heterojunction bipolar light-emitting transistor display, characterized in that The specific preparation steps of the heterojunction bipolar light - emitting triode display according to any one of claims 1 - 5 are as follows: S1: Form a number of regularly arranged vias on the driving backplane, fill the vias with conductive materials, and then form a number of anodes on the upper surface of the driving backplane and make contact with the upper surface of the vias; S2: Then grow and form a semiconductor layer on the upper surface of the anode and the driving backplane in sequence; S3: Pattern the semiconductor layer such that the semiconductor layer is located on the side of the anode away from the driving backplane; S4: Fill the growth medium layer between each sub-pixel unit so that the upper surface of the medium layer is flush with the upper surface of the semiconductor layer; S5: Deposit an emitter and a first metal electrode on the upper surface of the semiconductor layer using magnetron sputtering technology, and perform patterning and CMP planarization processes on the emitter and the first metal electrode respectively; S6: Continue to deposit a second metal electrode on the upper surface of the emitter using magnetron sputtering technology and perform patterning, then continue to fill the medium layer and perform CMP planarization on it so that the medium layer is flush with the upper surface of the second metal electrode; S7: Use mass transfer and vacuum bonding technology to bond and connect with the LED light-emitting unit on the side of the second metal electrode away from the driving backplane, and perform planarization; S8: Continue to fill the growth medium layer between each sub-pixel unit and pattern it, form an electrode groove corresponding to each sub-pixel unit, then grow a common electrode on the upper surface of the medium layer, and the common electrode contacts the upper surface of the LED light-emitting unit through the electrode groove. Finally, bond the glass encapsulation layer on the upper surface of the common electrode using UV glue.

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