Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: the first gate has a size along the first direction greater than the size of the second gate along the first direction; forming a first source-drain layer in the first fin on both sides of the first gate structure; forming a second source-drain layer in the second fin on both sides of the second gate structure, the first source-drain layer has a depth along the direction perpendicular to the substrate surface greater than the depth of the second source-drain layer along the direction perpendicular to the substrate surface, which is conducive to providing greater stress for the channel of the device on the first region, while not affecting the short channel effect of the device on the first region, nor exacerbating the short channel effect of the device on the second region, thereby improving the overall performance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In the existing semiconductor field, a fin field effect transistor (FinFET) is an emerging multi-gate device, which has stronger short channel inhibition capability and stronger working current compared with a planar metal-oxide semiconductor field effect transistor (MOSFET), and is widely used in various semiconductor devices. However, with the further development of semiconductor technology, the transistor scale is reduced to several nanometers, and the size of the FinFET itself has been reduced to the limit. Whether it is fin distance, short channel effect, or leakage and material limit, the transistor manufacturing becomes precarious, and even the physical structure cannot be completed.

[0003] A gate-all-around (GAA) device becomes a new direction of research and development in the industry. The feature of this technology is to realize the four-side wrapping of the gate to the channel, and the source and the drain no longer contact the substrate, but use multiple linear or flat plate-shaped, sheet-shaped, etc. The source and the drain are distributed transversely and perpendicularly to the gate to realize the basic structure and function of the MOSFET. Such design solves various problems caused by the reduction of the gate distance size to a great extent, including the capacitance effect, etc. In addition, the channel is wrapped by the gate on four sides, so the channel current is smoother than the three-side wrapping of the FinFET.

[0004] However, as an important direction of development in the industry, the gate-all-around device still needs to be further improved. SUMMARY

[0005] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical scheme of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a base, the base comprising a first region and a second region; a plurality of first fins on the first region, the first fins comprising a plurality of first channel layers on the first region and a second trench between adjacent first channel layers; a plurality of second fins on the second region, the second fins comprising a plurality of second channel layers on the second region and a fourth trench between adjacent second channel layers, the first fins and the second fins extending in a first direction; a plurality of first gate structures across the surface of the first fins, the first gate structures comprising first gates, the first gate structures being located on part of the top surface and part of the sidewall surface of the first fins; a plurality of second gate structures across the surface of the second fins, the second gate structures comprising second gates, the second gate structures being located on part of the top surface and part of the sidewall surface of the second fins, the size of the first gate in the first direction being greater than the size of the second gate in the first direction; a first source-drain layer in the first fins on both sides of the first gate structure; a second source-drain layer in the second fins on both sides of the second gate structure, the depth of the first source-drain layer in the direction perpendicular to the surface of the substrate being greater than the depth of the second source-drain layer in the direction perpendicular to the surface of the substrate.

[0007] Optionally, the first source-drain layer is located in a first opening in the first fin; and the second source-drain layer is located in a second opening in the second fin.

[0008] Optionally, the depth of the first opening in the direction perpendicular to the surface of the substrate ranges from 500 angstroms to 3000 angstroms; and the depth of the second opening in the direction perpendicular to the surface of the substrate ranges from 400 angstroms to 2500 angstroms.

[0009] Optionally, the material of the first source-drain layer comprises germanium-silicon or silicon carbide; and the material of the second source-drain layer comprises germanium-silicon or silicon carbide.

[0010] Accordingly, the technical scheme of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate comprising a base, the base comprising a first region and a second region; forming a plurality of first fins on the first region, the first fins comprising a plurality of first channel layers on the first region and a second trench between adjacent first channel layers; forming a plurality of second fins on the second region, the second fins comprising a plurality of second channel layers on the second region and a fourth trench between adjacent second channel layers, the first fins and the second fins extending along a first direction; forming a plurality of first gate structures across surfaces of the first fins, the first gate structures comprising first gates, the first gate structures being located on part of top surfaces and part of sidewall surfaces of the first fins, the first gates also being located in the second trenches; forming a plurality of second gate structures across surfaces of the second fins, the second gate structures comprising second gates, the second gate structures being located on part of top surfaces and part of sidewall surfaces of the second fins, the second gates also being located in the fourth trenches, a size of the first gates along the first direction being greater than a size of the second gates along the first direction; forming first source-drain layers in the first fins on both sides of the first gate structures; forming second source-drain layers in the second fins on both sides of the second gate structures, a depth of the first source-drain layers along a direction perpendicular to a surface of the substrate being greater than a depth of the second source-drain layers along the direction perpendicular to the surface of the substrate.

[0011] Optionally, the method for forming the first fin, the second fin, the first source-drain layer, the second source-drain layer, the first gate and the second gate comprises: forming a plurality of initial first fins extending along a first direction on the first region, the initial first fins comprising a plurality of first composite layers stacked on the first region, the first composite layers comprising a first sacrificial layer and a first channel layer on a surface of the first sacrificial layer; forming a plurality of initial second fins extending along the first direction on the second region, the initial second fins comprising a plurality of second composite layers stacked on the second region, the second composite layers comprising a second sacrificial layer and a second channel layer on a surface of the second sacrificial layer; forming a plurality of first dummy gate structures across surfaces of the initial first fins, the first dummy gate structures comprising a first dummy gate, the first dummy gate structures being located on part of top surfaces and part of sidewall surfaces of the initial first fins, a dimension of the first dummy gate along the first direction being greater than a dimension of the second dummy gate along the first direction; forming a plurality of second dummy gate structures across surfaces of the initial second fins, the second dummy gate structures comprising a second dummy gate, the second dummy gate structures being located on part of top surfaces and part of sidewall surfaces of the initial second fins; forming the first source-drain layer in the initial first fins on both sides of the first dummy gate structure; forming the second source-drain layer in the initial second fins on both sides of the second dummy gate structure; forming an interlayer dielectric layer on sidewalls of the substrate surface, the first source-drain layer surface, the second source-drain layer surface, the first dummy gate structure and the second dummy gate structure, the interlayer dielectric layer exposing top surfaces of the first dummy gate and the second dummy gate; after forming the interlayer dielectric layer, removing the first dummy gate, forming a first trench in the interlayer dielectric layer; removing the first sacrificial layer exposed by a bottom of the first trench, forming a second trench between two adjacent first channel layers exposed by the bottom of the first trench, forming the first fin with the second trench and the first channel layer; after forming the interlayer dielectric layer, removing the second dummy gate, forming a third trench in the interlayer dielectric layer; removing the second sacrificial layer exposed by a bottom of the third trench, forming a fourth trench between two adjacent second channel layers exposed by the bottom of the third trench, forming the second fin with the fourth trench and the second channel layer; forming the first gate in the first trench and the second trench, forming the first gate structure with the first dummy gate structure; forming the second gate in the third trench and the fourth trench, forming the second gate structure with the second dummy gate structure.

[0012] Optionally, the initial first fin further comprises a first bottom structure between the first region and the first composite layer; the initial second fin further comprises a second bottom structure between the second region and the second composite layer.

[0013] Optionally, the method for forming the initial first fin and the initial second fin comprises: forming a plurality of layers of composite material layers on the substrate, the composite material layers comprising a layer of sacrificial material and a layer of channel material on the surface of the layer of sacrificial material; forming a first pattern layer on a portion of the surface of the composite material layers on the first region; etching the composite material layers and the substrate using the first pattern layer as a mask to form the initial first fin; forming a second pattern layer on a portion of the surface of the composite material layers on the second region; etching the composite material layers and the substrate using the second pattern layer as a mask to form the initial second fin.

[0014] Optionally, the material of the layer of sacrificial material is different from the material of the layer of channel material; the material of the layer of sacrificial material comprises germanium-silicon, and the material of the layer of channel material comprises silicon.

[0015] Optionally, the method for forming the first source-drain layer and the second source-drain layer further comprises: forming a first opening in the initial first fin on both sides of the first dummy gate structure; forming a second opening in the initial second fin on both sides of the second dummy gate structure, the depth of the first opening in the direction perpendicular to the surface of the substrate being greater than the depth of the second opening in the direction perpendicular to the surface of the substrate; forming the first source-drain layer in the first opening; and forming the second source-drain layer in the second opening.

[0016] Optionally, the method for forming the first source-drain layer and the second source-drain layer further comprises: forming a first epitaxial layer in the first opening and doping a first doping ion in the first epitaxial layer to form the first source-drain layer; and forming a second epitaxial layer in the second opening and doping a second doping ion in the second epitaxial layer to form the second source-drain layer.

[0017] Optionally, the method for forming the first opening comprises: etching the initial first fin using the first dummy gate structure as a mask to form an initial first opening in the initial first fin, the bottom of the initial first opening exposing the first bottom structure; after forming the initial first opening, etching the first sacrificial layer to form a first recess between two adjacent first channel layers, the first sacrificial layer sidewall exposed by the first recess being recessed relative to the first channel layer sidewall; forming an initial first barrier layer in the sidewall of the first dummy gate structure, the sidewall of the initial first opening, and the first recess, the initial first barrier layer filling the first recess; etching the bottom of the initial first opening using the initial first barrier layer as a mask to expose the first bottom structure and form a third opening in the first bottom structure; after forming the third opening, etching the initial first barrier layer until the sidewall of the first dummy gate structure and the sidewall of the first channel layer are exposed to form the first barrier layer and the first opening.

[0018] Optionally, a size of the initial first barrier layer along the first direction ranges from 2 nm to 8 nm.

[0019] Optionally, a forming method of the initial first barrier layer comprises: forming a barrier material layer on the substrate, the barrier material layer also being located on the sidewalls and top surfaces of the first dummy gate structure and filling the first recess; and etching back the barrier material layer until the top surface of the first dummy gate structure, the bottom of the initial first opening and the surface of the substrate are exposed.

[0020] Optionally, the second opening is formed before the barrier material is formed, and a forming method of the second opening comprises: etching the initial second fin with the second dummy gate structure as a mask to form the second opening in the initial second fin, the bottom of the second opening exposing the second bottom structure.

[0021] Optionally, after the second opening is formed, the method further comprises: etching the second sacrificial layer to form a second recess between two adjacent second channel layers, and a sidewall of the second sacrificial layer exposed by the second recess is recessed relative to a sidewall of the second channel layer.

[0022] Optionally, the barrier material layer also fills the second recess and is located on the sidewalls and top surfaces of the first dummy gate structure and the second dummy gate structure.

[0023] Optionally, after the barrier material layer is formed and before the first barrier layer is formed, the method further comprises: forming an auxiliary material layer on the substrate, the auxiliary material layer filling the second opening and being located on the sidewalls and top surfaces of the first dummy gate structure and the second dummy gate structure; and removing the auxiliary material layer on the first region until the barrier material layer on the first region is exposed.

[0024] Optionally, a material of the auxiliary material layer is different from a material of the barrier material layer, and the material of the auxiliary material layer comprises amorphous carbon.

[0025] Optionally, after the third opening is formed and before the second source-drain layer is formed, the method further comprises: forming a first mask layer on the first region, the first mask layer being located in the initial first opening and the third opening; removing the auxiliary material layer on the second region to expose the barrier material layer on the second region; etching back the barrier material layer on the second region until the sidewalls of the second dummy gate structure, the sidewalls of the second channel layer and the second opening are exposed to form a second barrier layer in the second recess.

[0026] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0027] The semiconductor structure provided by the technical scheme of the present application includes: a first source-drain layer in a first fin portion on both sides of the first gate structure; and a second source-drain layer in a second fin portion on both sides of the second gate structure, wherein the depth of the first source-drain layer along the direction perpendicular to the substrate surface is greater than the depth of the second source-drain layer along the direction perpendicular to the substrate surface. Since the size of the first source-drain layer along the direction perpendicular to the substrate surface is relatively large, the volume of the first source-drain layer is increased, which is beneficial to provide greater stress for the channel of the device in the first region and improve the performance of the device. Meanwhile, since the channel of the device in the first region is relatively long, the short channel effect of the device in the first region will not be affected. On the other hand, the depth of the second source-drain layer along the direction perpendicular to the substrate surface is relatively shallow, which will not aggravate the short channel effect of the device in the second region, thereby improving the performance of the device as a whole.

[0028] The forming method of the semiconductor structure provided by the technical scheme of the present application includes: forming a first source-drain layer in an initial first fin portion on both sides of the first gate structure; and forming a second source-drain layer in a second fin portion on both sides of the second gate structure, wherein the depth of the first source-drain layer along the direction perpendicular to the substrate surface is greater than the depth of the second source-drain layer along the direction perpendicular to the substrate surface. The technical scheme of the present application provides a forming method of a long channel device and a short channel device coexisting structure. Since the size of the first source-drain layer along the direction perpendicular to the substrate surface is relatively large, the volume of the first source-drain layer is increased, which is beneficial to provide greater stress for the channel of the device in the first region and improve the performance of the device. Meanwhile, since the channel of the device in the first region is relatively long, the short channel effect of the device in the first region will not be affected. On the other hand, the depth of the second source-drain layer along the direction perpendicular to the substrate surface is relatively shallow, which will not aggravate the short channel effect of the device in the second region, thereby improving the performance of the device as a whole.

[0029] Further, the initial first barrier layer is used as a mask to form the third opening and is also used to form a first barrier layer, which is used to block the mutual diffusion of ions in the first source-drain layer and ions in the first gate, thereby improving the performance of the device.

[0030] Further, the second barrier layer is used to block the mutual diffusion of ions in the second source-drain layer and ions in the second gate, thereby improving the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figures 1 to 3 is a schematic diagram of a semiconductor structure forming process;

[0032] Figures 4 to 18 is a structural schematic diagram of each step of the forming method of the semiconductor structure in an embodiment of the present application. DETAILED DESCRIPTION

[0033] It should be noted that the "surface", "top" in the specification are used to describe the relative position relationship in space, and are not limited to whether they are in direct contact.

[0034] As described in the background, the performance of the semiconductor structure formed by using the existing surround gate device technology needs to be improved. Now a semiconductor structure is described and analyzed.

[0035] Figures 1 to 3 is a schematic diagram of a semiconductor structure forming process.

[0036] Please refer to Figure 1 and Figure 2 , Figure 1 is a top view, Figure 2 is a schematic diagram of the cross-sectional structure along the XY direction of Figure 1 , a substrate is provided, the substrate includes a base 101, a fin 102 located on the base 101, the fin 102 includes a bottom structure 103 located on the base 101, a plurality of layers of overlapping sacrificial layers 104 located on the bottom structure, and a channel layer 105 located between two adjacent layers of sacrificial layers 104, and the substrate further includes an isolation region 106 located on the base 101, the top surface of the isolation region 106 and the top surface of the bottom structure 103 are flush; a pseudo gate structure 107 is formed across the fin, the pseudo gate structure 107 includes a pseudo gate 108 and a sidewall 109 located on the sidewall of the pseudo gate.

[0037] Please refer to Figure 3 , Figure 3 the view direction of Figure 2 , the fin 102 is etched with the pseudo gate structure 107 as a mask, an opening (not labeled in the figure) is formed in the fin 102, and the opening exposes the bottom structure 103; an epitaxial layer (not labeled in the figure) is formed in the opening, and N-type or P-type doping ions are implanted in the epitaxial layer to form a source-drain region 113.

[0038] In the method, the source-drain region 113 is located in the fin 102, and the material of the source-drain region 113 includes a silicon carbide material or a germanium-silicon material, etc. The channel layer 105 between the source-drain regions 113 and below the dummy gate structure 107 is used to form a channel of a device. The source-drain region 113 generates a tensile stress or a compressive stress on the channel, so as to reduce the conductivity effective mass and scattering probability of the current carriers in the channel direction, thereby improving the speed of an NMOS device or a PMOS device. The source-drain region 113 is formed by forming an epitaxial layer in the opening, and then implanting doped ions in the epitaxial layer. If the depth of the opening is too large, it is easy to cause a short channel effect of the device, and if the depth of the opening is too small, the source-drain region 113 cannot generate a large enough stress due to too small volume, thereby affecting the overall performance of the device.

[0039] To solve the above problems, the present application provides a method for forming a semiconductor structure. The first source-drain layer is formed in the first fin on both sides of the first gate structure. The second source-drain layer is formed in the second fin on both sides of the second gate structure. The depth of the first source-drain layer in the direction perpendicular to the substrate surface is greater than the depth of the second source-drain layer in the direction perpendicular to the substrate surface. The technical scheme of the present application provides a method for forming a coexistence structure of long channel devices and short channel devices. Since the size of the first source-drain layer in the direction perpendicular to the substrate surface is large, the volume of the first source-drain layer is increased, which is beneficial to providing a larger stress for the channel of the device in the first region, thereby improving the performance of the device. At the same time, since the channel of the device in the first region is long, the short channel effect of the device in the first region is not affected. On the other hand, the depth of the second source-drain layer in the direction perpendicular to the substrate surface is shallow, which does not aggravate the short channel effect of the device in the second region, thereby improving the overall performance of the device.

[0040] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0041] Figures 4 to 18 is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present application.

[0042] Please refer to Figure 4 , a substrate is provided, and the substrate includes a base 200, and the base 200 includes a first region I and a second region II.

[0043] The first region and the second region are used to form devices with different channel lengths. Subsequently, a plurality of first fins are formed on the first region, the first fins including a plurality of first channel layers on the first region and a second trench between adjacent first channel layers; a plurality of second fins are formed on the second region, the second fins including a plurality of second channel layers on the second region and a fourth trench between adjacent second channel layers, the first fins and the second fins extending along a first direction; a plurality of first gate structures are formed across surfaces of the first fins, the first gate structures including first gates, the first gate structures being located on part of top surfaces and part of sidewall surfaces of the first fins, the first gates also being located in the second trenches; a plurality of second gate structures are formed across surfaces of the second fins, the second gate structures including second gates, the second gate structures being located on part of top surfaces and part of sidewall surfaces of the second fins, the second gates also being located in the fourth trenches, the first gates having a size along the first direction that is greater than a size of the second gates along the first direction; first source / drain layers are formed in the first fins on both sides of the first gate structures; and second source / drain layers are formed in the second fins on both sides of the second gate structures, the first source / drain layers having a depth along a direction perpendicular to the substrate surface that is greater than a depth of the second source / drain layers along the direction perpendicular to the substrate surface. In this embodiment, a gate-last process is used, i.e., the first source / drain layers and the second source / drain layers are formed before the first gate structures and the second gate structures are formed. In other embodiments, a gate-last process can also be used.

[0044] In this embodiment, the substrate further includes a plurality of initial first fins 201 on the first region I and a plurality of initial second fins 202 on the second region II, the initial first fins 201 including a plurality of layers of first composite layers on the first region I, the first composite layers including first sacrificial layers 203 and first channel layers 204 on surfaces of the first sacrificial layers 203, the initial second fins 202 including a plurality of layers of second composite layers on the second region II, the second composite layers including second sacrificial layers 205 and second channel layers 206 on surfaces of the second sacrificial layers 205, the initial first fins 201 and the initial second fins 202 extending along a first direction.

[0045] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate 200 can also be a silicon-on-insulator (SOI) structure or a germanium-on-insulator structure.

[0046] In the embodiment, the initial first fin 201 further comprises a first bottom structure 207 between the first region I and the first composite layer 202; and the initial second fin 202 further comprises a second bottom structure 208 between the second region II and the second composite layer 206.

[0047] The method for forming the initial first fin 201 and the initial second fin 202 comprises: forming a plurality of layers of composite material (not shown in the figure) on the substrate, the composite material comprising a layer of sacrificial material (not shown in the figure) and a layer of channel material (not shown in the figure) on the surface of the layer of sacrificial material; forming a first pattern layer 209 on part of the surface of the layer of composite material on the first region I, the first pattern layer 209 exposing part of the layer of composite material; etching the layer of composite material and the substrate using the first pattern layer 209 as a mask to form the initial first fin 201; forming a second pattern layer 210 on part of the surface of the layer of composite material on the second region II, the second pattern layer 210 exposing part of the layer of composite material; etching the layer of composite material and the substrate using the second pattern layer 210 as a mask to form the initial second fin 202. The first pattern layer 209 is used as a mask to form the initial first fin 201 and to protect the top surface of the initial first fin 201 from damage in subsequent etching processes; and the second pattern layer 210 is used as a mask to form the initial second fin 202 and to protect the top surface of the initial second fin 202 from damage in subsequent etching processes.

[0048] The material of the layer of sacrificial material is different from the material of the layer of channel material; the material of the layer of sacrificial material comprises germanium-silicon, and the material of the layer of channel material comprises silicon. In the embodiment, the material of the layer of sacrificial material is germanium-silicon, and the material of the layer of channel material is silicon.

[0049] In the embodiment, specifically, the method for forming the first fin, the second fin, the first source-drain layer, the second source-drain layer, the first gate and the second gate is as follows: Figures 6 to 18 .

[0050] Please refer to Figure 5, forming a plurality of first dummy gate structures across the surface of the initial first fin 202, the first dummy gate structure comprising a first dummy gate 211, the first dummy gate structure being located on a portion of the top surface and a portion of the sidewall surface of the initial first fin 201; forming a plurality of second dummy gate structures across the surface of the initial second fin 202, the second dummy gate structure comprising a second dummy gate 212, the second dummy gate structure being located on a portion of the top surface and a portion of the sidewall surface of the initial second fin 202, the first dummy gate 211 having a dimension along the first direction greater than the dimension of the second dummy gate 212 along the first direction.

[0051] The first region I is used to form a long channel device, and the second region II is used to form a short channel device.

[0052] In the embodiment, the material of the first dummy gate 211 is polysilicon; the material of the second dummy gate 212 is polysilicon. In other embodiments, the material of the first dummy gate 211 can also be amorphous silicon, silicon carbide, etc.; the material of the second dummy gate 212 can also be amorphous silicon, silicon carbide, etc.

[0053] In the embodiment, the first dummy gate structure further comprises: a first sidewall 213 located on the sidewall of the first dummy gate 211; a first protective layer 214 located on the top surface of the first dummy gate 211. The second dummy gate structure further comprises: a second sidewall 215 located on the sidewall of the second dummy gate 212; a second protective layer 216 located on the top surface of the second dummy gate 212.

[0054] Subsequently, a first opening is formed in the initial first fin 201 on both sides of the first dummy gate structure, and the forming method of the first opening is described in detail in the following Figures 6 to 14 .

[0055] As described in the following Figure 6 , the initial first fin 201 is etched with the first dummy gate structure as a mask to form an initial first opening 217 in the initial first fin 201, and the bottom of the initial first opening 217 exposes the first bottom structure 207; after the initial first opening 217 is formed, the first sacrificial layer 203 is etched to form a first recess 218 between the two adjacent first channel layers 204, and the sidewall of the first sacrificial layer 203 exposed by the first recess 218 is recessed relative to the sidewall of the first channel layer 204.

[0056] Subsequently, an initial first barrier layer is formed in the first dummy gate structure sidewall, the initial first opening 217 sidewall, and the first recess 218, and the initial first barrier layer fills the first recess 218. The forming method of the initial first barrier layer includes forming a barrier material layer on the substrate, the barrier material layer is also located on the first dummy gate structure sidewall and the top surface, and fills the first recess 218; etching back the barrier material layer until the first dummy gate structure top surface, the initial first opening bottom and the substrate surface are exposed. The forming method of the initial first barrier layer, please refer to Figures 7 to 9 .

[0057] In the embodiment, the second opening is formed before the barrier material is formed, and the forming method of the second opening includes: etching the initial second fin 202 with the second dummy gate structure as a mask to form the second opening in the initial second fin 202, and the second opening bottom exposes the second bottom structure 208. The forming method of the second opening, please refer to Figure 6 .

[0058] Please continue to refer to Figure 6 The first opening is formed in the initial second fin 202 on both sides of the second dummy gate structure, and the depth of the first opening in the direction perpendicular to the substrate surface is greater than the depth of the second opening 219 in the direction perpendicular to the substrate surface.

[0059] The depth of the second opening 219 in the direction perpendicular to the substrate surface ranges from 400 angstroms to 4000 angstroms. Specifically, in the embodiment, the depth of the second opening 219 in the direction perpendicular to the substrate surface is the same as the depth of the initial first opening 217 in the direction perpendicular to the substrate surface.

[0060] In the embodiment, after the second opening 219 is formed before the barrier material is formed, the second sacrificial layer 205 is also etched, and a second recess 220 is formed between the two adjacent second channel layers 206, and the second sacrificial layer 205 sidewall exposed by the second recess 220 is recessed relative to the second channel layer 206 sidewall.

[0061] Specifically, in the embodiment, the initial first opening 217 and the second opening 219 are formed at the same time in the same process, which saves the process and reduces the production cost. In other embodiments, the initial first opening 217 and the second opening 219 can not be formed at the same time.

[0062] The forming process of the first recess 218 comprises a wet etching process; the forming process of the second recess comprises a wet etching process. In this embodiment, the second recess 220 and the first recess 218 are formed by the wet etching process and are formed simultaneously in the same process, which saves the process and reduces the production cost. In other embodiments, the second recess 220 and the first recess 218 can not be formed simultaneously.

[0063] Please refer to Figure 7 A barrier material layer 221 is formed on the substrate, the barrier material layer 221 is also located on the side wall and top surface of the first dummy gate structure, and fills the first recess 218 (as shown in Figure 6 ).

[0064] The barrier material layer 221 is also located on the side wall and top surface of the second dummy gate structure, and fills the second recess 220 (as shown in Figure 6 ).

[0065] The material of the barrier material layer 221 comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the barrier material layer 221 is silicon nitride. The barrier material layer 221 is used for subsequent formation of an initial first barrier layer, a first barrier layer, and a second barrier layer.

[0066] Please refer to Figure 8 After the formation of the barrier material layer 221, an auxiliary material layer 222 is also formed on the substrate before the formation of the first barrier layer, the auxiliary material layer 222 fills the second opening 219 (as shown in Figure 7 ), and is located on the side wall and top of the first dummy gate structure and the second dummy gate structure.

[0067] The material of the auxiliary material layer 222 is different from the material of the barrier material layer 221, and the material of the auxiliary material layer 222 comprises amorphous carbon. In this embodiment, the auxiliary material layer 222 is amorphous carbon. The material of the auxiliary material layer 222 is different from the material of the barrier material layer 221, so that in the subsequent etching process for removing the auxiliary material layer 222, an etching process with a large selectivity ratio for the auxiliary material layer 222 and the barrier material layer 221 is selected, reducing the etching damage of the etching process to the barrier material layer 221.

[0068] The first region I is used to form long channel devices, and the second region II is used to form short channel devices. The second opening 219 has a smaller size in the first direction than the initial first opening 217, and thus the second opening 219 is more easily filled. In this embodiment, the auxiliary material layer 222 is used to protect the devices on the second region II from damage during subsequent etching on the first region I, and thus the initial first opening 217 does not need to be filled, thereby saving material. In other embodiments, the material of the auxiliary material layer can also fill the initial first opening 217. The auxiliary material layer is subsequently removed on the second region II to expose the surface of the barrier material layer 221 on the second region II. The auxiliary material layer is subsequently used to protect the devices on the first region I from damage during etching on the second region II.

[0069] Referring to Figure 9 , the auxiliary material layer 222 on the first region I is removed until the barrier material layer 221 on the first region I is exposed; the barrier material layer 221 is etched back until the top surface of the first dummy gate structure, the bottom of the initial first opening 217, and the surface of the substrate are exposed.

[0070] Specifically, the barrier material layer 221 on the first region I is etched back to form the initial barrier layer 223.

[0071] The initial first barrier layer 223 has a size in the first direction ranging from 2 nm to 8 nm.

[0072] Referring to Figure 10 , the initial first barrier layer 223 is used as a mask to etch the bottom of the initial first opening 217 to expose the first bottom structure 207, and a third opening 224 is formed in the first bottom structure 207.

[0073] The third opening 224 has a depth in the direction perpendicular to the substrate ranging from 500 angstroms to 4000 angstroms. In this embodiment, the depth determines the difference in depth of the first opening in the direction perpendicular to the substrate and the second opening in the direction perpendicular to the substrate. The significance of selecting the depth range value is to avoid the depth of the third opening 224 being too large, thereby exacerbating the channel effect of the devices on the first region I.

[0074] Subsequently, after forming the third opening 224, the initial first barrier layer is etched until the sidewall of the first dummy gate structure and the sidewall of the first channel layer are exposed, forming a first barrier layer and the first opening; a first source / drain layer is formed in the first opening; and a second source / drain layer is formed in the second opening.

[0075] Referring to Figure 11 , after forming the third opening 223, before forming the second source-drain layer, the method further comprises: forming a first mask layer 225 on the first region I, the first mask layer 225 being located in the initial first opening 217 (as shown in Figure 10 ) and the third opening 224 (as shown in Figure 10 ); removing the auxiliary material layer 222 on the second region II to expose the barrier material layer 221 on the second region II.

[0076] In this embodiment, the material of the first mask layer 225 is photoresist. The first mask layer 225 is used to protect the device on the first region I from damage in the subsequent etching process.

[0077] Referring to Figure 12 , etching back the barrier material layer 221 on the second region II until the second dummy gate structure sidewall, the second channel layer 206 sidewall and the second opening 219 are exposed, and a second barrier layer 226 is formed in the second recess 220.

[0078] In this embodiment, the second barrier layer 226 is formed first, and then the first barrier layer is formed. In other embodiments, the first barrier layer can also be formed first, and then the second barrier layer is formed.

[0079] The size of the second barrier layer 226 in the first direction ranges from 3 nanometers to 8 nanometers.

[0080] The second barrier layer 226 is used to block the mutual diffusion between the ions in the second gate and the ions in the second source-drain layer formed subsequently, thereby reducing the impact on the device performance.

[0081] Referring to Figure 13 , a second source-drain layer 227 is formed in the second opening 219 (as shown in Figure 12 ).

[0082] The forming method of the second source-drain layer 227 comprises: forming a second epitaxial layer (not labeled in the figure) in the second opening 219, and doping a second doping ion in the second epitaxial layer to form the second source-drain layer 227.

[0083] The material of the second source-drain layer 227 comprises germanium-silicon or silicon carbide; and the second doping ion is N-type or P-type ion. In this embodiment, the second region II is used to form an NMOS device, and the material of the second source-drain layer 227 is silicon carbide; and the second doping ion is N-type ion.

[0084] In the embodiment, the second source-drain layer 227 is formed first, and then the first source-drain layer is formed. In other embodiments, the first source-drain layer can be formed first, and then the second source-drain layer is formed.

[0085] In the embodiment, after the second source-drain layer 227 is formed, the first mask layer 225 is removed; after the first mask layer 225 is removed, a second mask layer 228 is formed on the second region II, and the second mask layer 228 is also located on the sidewall and surface of the second dummy gate structure and the surface of the second source-drain layer 227.

[0086] In the embodiment, the material of the second mask layer 228 is photoresist. The second mask layer 228 is used to protect the device on the second region II from damage in the subsequent etching process.

[0087] Please refer to Figure 14 After the third opening 224 is formed, the initial first barrier layer 222 is etched until the sidewall of the first dummy gate structure and the sidewall of the first channel layer 204 are exposed, forming the first barrier layer 229 and the first opening 230.

[0088] Specifically, in the embodiment, after the second mask layer 228 is formed, the initial first barrier layer 222 is etched until the sidewall of the first dummy gate structure and the sidewall of the first channel layer 204 are exposed, forming the first barrier layer 229 and the first opening 230.

[0089] The size of the first barrier layer 229 in the first direction ranges from 2 nanometers to 6 nanometers.

[0090] The first barrier layer 229 is used to block the mutual diffusion of ions in the subsequently formed first source-drain layer and ions in the first gate, thereby improving the performance of the device.

[0091] The depth of the first opening 230 in the direction perpendicular to the surface of the substrate ranges from 480 angstroms to 4800 angstroms.

[0092] The depth of the first opening 230 in the direction perpendicular to the surface of the substrate is greater than the depth of the second opening 219 in the direction perpendicular to the surface of the substrate.

[0093] Subsequently, a first source-drain layer is formed in the first opening 230. Since the first source-drain layer has a large size in the direction perpendicular to the substrate surface, i.e. the volume occupied by the first source-drain layer is increased, it is beneficial to provide a larger stress to the channel of the device in the first region I, and improve the performance of the device. Meanwhile, since the channel of the device in the first region I is long, it will not affect the short channel effect of the device in the first region I. In addition, the second opening 219 has a shallow depth in the direction perpendicular to the substrate surface relative to the first opening 230, and the position of the second source-drain layer 227 will not aggravate the short channel effect of the device in the second region II. That is, the first source-drain layer in the first region I and the second source-drain layer 227 in the second region II have different positions in the substrate, thereby improving the performance of the device as a whole.

[0094] Please refer to Figure 15 A first source-drain layer 231 is formed in the first opening 230.

[0095] The method for forming the first source-drain layer 231 includes: forming a first epitaxial layer (not shown in the figure) in the first opening 230, and doping a first doping ion in the first epitaxial layer to form the first source-drain layer 231.

[0096] The material of the first source-drain layer 231 includes germanium-silicon or silicon carbide; and the first doping ion is an N-type or P-type ion. In this embodiment, the first region I is used to form an NMOS device, and the material of the first source-drain layer 231 is silicon carbide; and the first doping ion is an N-type ion.

[0097] Please refer to Figure 16 An interlayer dielectric layer 232 is formed on the substrate surface, the surface of the first source-drain layer 231, the surface of the second source-drain layer 227, the sidewall and surface of the first dummy gate structure, and the sidewall and surface of the second dummy gate structure, and the interlayer dielectric layer 232 exposes the top surface of the first dummy gate 211 and the second dummy gate 212.

[0098] The method for forming the interlayer dielectric layer 232 includes: forming an interlayer dielectric material layer (not shown in the figure) on the substrate surface, the surface of the first source-drain layer 231, the surface of the second source-drain layer 227, the sidewall and surface of the first dummy gate structure, and the sidewall and surface of the second dummy gate structure; and planarizing the interlayer dielectric material layer until the top surface of the first dummy gate 211 and the second dummy gate 212 is exposed to form the interlayer dielectric layer 232.

[0099] The interlayer dielectric layer 232 is used to isolate the metal interconnection lines and the devices in the subsequent device manufacturing process, reduce the parasitic capacitance between the metal and the substrate, and improve the parasitic field effect transistor formed by the metal across different regions.

[0100] Please refer to Figure 17 After forming the interlayer dielectric layer 232, the first dummy gate 211 is removed, and a first trench 233 is formed in the interlayer dielectric layer 232; the first sacrificial layer 203 exposed at the bottom of the first trench 233 is removed, and a second trench 234 is formed between the two adjacent first channel layers 204 exposed at the bottom of the first trench 233, so as to form a first fin with the second trench 234 and the first channel layer 204; after forming the interlayer dielectric layer 232, the second dummy gate 212 is removed, and a third trench 235 is formed in the interlayer dielectric layer 231; the second sacrificial layer 205 exposed at the bottom of the third trench 235 is removed, and a fourth trench 236 is formed between the two adjacent second channel layers 206 exposed at the bottom of the third trench 235, so as to form a second fin with the fourth trench 236 and the second channel layer 206.

[0101] The process of removing the first dummy gate 211 includes a wet etching process; the process of removing the second dummy gate 212 includes a wet etching process. In this embodiment, in order to save the process and reduce the production cost, the first dummy gate 211 and the second dummy gate 212 are removed in the same process. In other embodiments, the first dummy gate 211 and the second dummy gate 212 can be removed in different processes.

[0102] The process of forming the second trench 234 includes a wet etching process; the process of forming the fourth trench 236 includes a wet etching process. In this embodiment, in order to save the process and reduce the production cost, the second trench 234 and the fourth trench 236 are formed in the same process. In other embodiments, the second trench 234 and the fourth trench 236 can not be formed at the same time.

[0103] Please refer to Figure 18 The first gate 237 is formed in the first trench 233 and the second trench 234, so as to form a first gate structure with the first dummy gate structure; the second gate 238 is formed in the third trench 235 and the fourth trench 236, so as to form a second gate structure with the second dummy gate structure.

[0104] The first gate structure includes the first gate 237; the second gate structure includes the second gate 238.

[0105] The material of the first gate 237 includes metal; the material of the metal includes tungsten, copper or aluminum.

[0106] The material of the second gate 238 comprises metal; the material of the metal comprises tungsten, copper or aluminum. In the embodiment, the material of the first gate 237 and the second gate 238 is tungsten, and the first gate 237 and the second gate 238 are formed in the same process, which saves the process and reduces the production cost. In other embodiments, the first gate 237 and the second gate 238 can not be formed at the same time.

[0107] Correspondingly, an embodiment of the present application further provides a semiconductor structure formed by the above method, please continue to refer to Figure 18 , comprising: a substrate, the substrate comprises a base 200, the base 200 comprises a first region I and a second region II; a plurality of first fins on the first region I, the first fin comprises a plurality of first channel layers 204 on the first region I and a second trench 234 (as shown in Figure 17 ) between adjacent first channels 204; a plurality of second fins on the second region II, the second fin comprises a plurality of second channel layers 206 on the second region II and a fourth trench 236 (as shown in Figure 17 ) between adjacent second channel layers 206, the first fin and the second fin extend along a first direction; a plurality of first gate structures across the surface of the first fin, the first gate structure comprises a first gate 237, the first gate structure is located on part of the top surface and part of the sidewall surface of the first fin, and the first gate 237 is also located in the second trench 234; a plurality of second gate structures across the surface of the second fin, the second gate structure comprises a second gate 238, the second gate structure is located on part of the top surface and part of the sidewall surface of the second fin, and the second gate 238 is also located in the fourth trench 236, the size of the first gate 237 in the first direction is greater than the size of the second gate 238 in the first direction; the depth of the first source-drain layer 231 in the direction perpendicular to the surface of the substrate is greater than the depth of the second source-drain layer 227 in the direction perpendicular to the surface of the substrate.

[0108] Since the first source-drain layer 231 has a large size along the direction perpendicular to the substrate surface, i.e. the volume of the first source-drain layer 231 is increased, it is beneficial to provide greater stress for the channel of the device in the first region I, and improve the performance of the device. At the same time, since the channel of the device in the first region I is long, it will not affect the short channel effect of the device in the first region I. In addition, compared with the first source-drain layer 231, the second source-drain layer 227 has a shallow depth along the direction perpendicular to the substrate surface, and the position of the second source-drain layer 227 will not aggravate the short channel effect of the device in the second region II. That is, the first source-drain layer 231 in the first region I and the second source-drain layer 227 in the second region II have different positions in the substrate, thereby improving the performance of the device as a whole.

[0109] The first source-drain layer 231 is located in a first opening 230 (as shown in FIG. 2) in the first fin; and the second source-drain layer 227 is located in a second opening 219 (as shown in FIG. 2) in the second fin. Figure 14 Figure 12

[0110] The material of the first source-drain layer 231 includes germanium-silicon or silicon carbide; and the material of the second source-drain layer 227 includes germanium-silicon or silicon carbide.

[0111] The depth of the first opening 230 along the direction perpendicular to the substrate surface ranges from 500 angstroms to 5000 angstroms; and the depth of the second opening 219 along the direction perpendicular to the substrate surface ranges from 400 angstroms to 4000 angstroms.

[0112] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.​​

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate comprising a base, the base comprising a first region and a second region; a plurality of first fins on the first region, the first fins comprising a plurality of first channel layers on the first region and a second trench between adjacent ones of the first channel layers; a plurality of second fins on the second region, the second fins comprising a plurality of second channel layers on the second region and a fourth trench between adjacent ones of the second channel layers, the first fins and the second fins both extending along a first direction; a plurality of first gate structures across surfaces of the first fins, the first gate structures comprising first gates, the first gate structures being on portions of top surfaces and portions of sidewall surfaces of the first fins, the first gates also being in the second trenches; a plurality of second gate structures across surfaces of the second fins, the second gate structures comprising second gates, the second gate structures being on portions of top surfaces and portions of sidewall surfaces of the second fins, the second gates also being in the fourth trenches, the first gates having a dimension along the first direction that is greater than a dimension along the first direction of the second gates; first source-drain layers in the first fins on both sides of the first gate structures; second source-drain layers in the second fins on both sides of the second gate structures, the first source-drain layers having a depth along a direction perpendicular to surfaces of the substrate that is greater than a depth along the direction perpendicular to the surfaces of the substrate of the second source-drain layers.

2. The semiconductor structure of claim 1, wherein, the first source-drain layers are in first openings in the first fins; the second source-drain layers are in second openings in the second fins.

3. The semiconductor structure of claim 2, wherein, the first openings have a depth along the direction perpendicular to the surfaces of the substrate that ranges from 500 angstroms to 3000 angstroms; the second openings have a depth along the direction perpendicular to the surfaces of the substrate that ranges from 400 angstroms to 2500 angstroms.

4. The semiconductor structure of claim 1, wherein, the first source-drain layers comprise germanium-silicon or silicon carbide; the second source-drain layers comprise germanium-silicon or silicon carbide.

5. A method of forming a semiconductor structure, characterized by, Comprising: providing a substrate comprising a base, the base comprising a first region and a second region; forming a plurality of first fins on the first region, the first fins comprising a plurality of first channel layers on the first region and a second trench between adjacent ones of the first channel layers; forming a plurality of second fins on the second region, the second fins comprising a plurality of second channel layers on the second region and a fourth trench between adjacent ones of the second channel layers, the first fins and the second fins both extending along a first direction; forming a plurality of first gate structures across surfaces of the first fins, the first gate structures comprising first gates, the first gate structures being on portions of top surfaces and portions of sidewall surfaces of the first fins, the first gates also being in the second trenches; forming a plurality of second gate structures across the second fin surface, the second gate structures including a second gate, the second gate structures located on a portion of a top surface and a portion of a sidewall surface of the second fin, the second gate also located within the fourth trench, a dimension of the first gate in the first direction being greater than a dimension of the second gate in the first direction; forming a first source drain layer within the first fin on both sides of the first gate structure; forming a second source drain layer within the second fin on both sides of the second gate structure, a depth of the first source drain layer in a direction perpendicular to the substrate surface being greater than a depth of the second source drain layer in the direction perpendicular to the substrate surface.

6. The method of forming a semiconductor structure of claim 5, wherein, The forming method of the first fin, the second fin, the first source-drain layer, the second source-drain layer, the first gate and the second gate comprises: forming a plurality of initial first fins extending along a first direction on the first region, the initial first fin comprising a plurality of first composite layers stacked on the first region, the first composite layer comprising a first sacrificial layer and a first channel layer on the surface of the first sacrificial layer; forming a plurality of initial second fins extending along the first direction on the second region, the initial second fin comprising a plurality of second composite layers stacked on the second region, the second composite layer comprising a second sacrificial layer and a second channel layer on the surface of the second sacrificial layer; forming a plurality of first dummy gate structures across the surface of the initial first fin, the first dummy gate structure comprising a first dummy gate, the first dummy gate structure being located on part of the top surface and part of the sidewall surface of the initial first fin; forming a plurality of second dummy gate structures across the surface of the initial second fin, the second dummy gate structure comprising a second dummy gate, the second dummy gate structure being located on part of the top surface and part of the sidewall surface of the initial second fin, the size of the first dummy gate along the first direction being greater than the size of the second dummy gate along the first direction; forming a first source-drain layer in the initial first fin on both sides of the first dummy gate structure; forming a second source-drain layer in the initial second fin on both sides of the second dummy gate structure; forming an interlayer dielectric layer on the surface of the substrate, the surface of the first source-drain layer, the surface of the second source-drain layer, the sidewall of the first dummy gate structure and the sidewall of the second dummy gate structure, the interlayer dielectric layer exposing the top surface of the first dummy gate and the top surface of the second dummy gate; after forming the interlayer dielectric layer, removing the first dummy gate to form a first trench in the interlayer dielectric layer; removing the first sacrificial layer exposed by the bottom of the first trench, forming a second trench between the two adjacent first channel layers exposed by the bottom of the first trench, and forming a first fin with the second trench and the first channel layer; after forming the interlayer dielectric layer, removing the second dummy gate to form a third trench in the interlayer dielectric layer; removing the second sacrificial layer exposed by the bottom of the third trench, forming a fourth trench between the two adjacent second channel layers exposed by the bottom of the third trench, and forming a second fin with the fourth trench and the second channel layer; forming a first gate in the first trench and the second trench, and forming a first gate structure with the first dummy gate structure; forming a second gate in the third trench and the fourth trench, and forming a second gate structure with the second dummy gate structure.

7. The method of forming a semiconductor structure of claim 6, wherein, The initial first fin further comprises a first bottom structure between the first region and the first composite layer; and the initial second fin further comprises a second bottom structure between the second region and the second composite layer.

8. The method of forming a semiconductor structure of claim 7, wherein, The method for forming the initial first fin and the initial second fin comprises: forming a plurality of layers of composite material layers on the substrate, the composite material layers comprising a layer of sacrificial material and a layer of channel material on the surface of the layer of sacrificial material; forming a first pattern layer on the surface of the composite material layer on the first region; etching the composite material layer and the substrate using the first pattern layer as a mask to form the initial first fin; forming a second pattern layer on the surface of the composite material layer on the second region; etching the composite material layer and the substrate using the second pattern layer as a mask to form the initial second fin.

9. The method of forming a semiconductor structure of claim 8, wherein, The material of the layer of sacrificial material is different from the material of the layer of channel material; the material of the layer of sacrificial material comprises germanium silicon, and the material of the layer of channel material comprises silicon.

10. The method of forming a semiconductor structure of claim 7, wherein, The method for forming the first source-drain layer and the second source-drain layer further comprises: forming a first opening in the initial first fin on both sides of the first dummy gate structure; forming a second opening in the initial second fin on both sides of the second dummy gate structure, the depth of the first opening in the vertical direction of the substrate surface being greater than the depth of the second opening in the vertical direction of the substrate surface; forming the first source-drain layer in the first opening; and forming the second source-drain layer in the second opening.

11. The method of forming a semiconductor structure of claim 10, wherein, The method for forming the first source-drain layer and the second source-drain layer further comprises: forming a first epitaxial layer in the first opening and doping the first epitaxial layer with first doping ions to form the first source-drain layer; and forming a second epitaxial layer in the second opening and doping the second epitaxial layer with second doping ions to form the second source-drain layer.

12. The method of forming a semiconductor structure of claim 10, wherein, The method for forming the first opening comprises: etching the initial first fin using the first dummy gate structure as a mask to form an initial first opening in the initial first fin, the bottom of the initial first opening exposing the first bottom structure; after forming the initial first opening, etching the first sacrificial layer to form a first recess between two adjacent first channel layers, the first sacrificial layer sidewall exposed by the first recess being recessed relative to the first channel layer sidewall; forming an initial first barrier layer in the first dummy gate structure sidewall, the initial first opening sidewall, and the first recess, the initial first barrier layer filling the first recess; etching the bottom of the initial first opening using the initial first barrier layer as a mask to expose the first bottom structure and form a third opening in the first bottom structure; after forming the third opening, etching the initial first barrier layer until the first dummy gate structure sidewall and the first channel layer sidewall are exposed to form the first barrier layer and the first opening.

13. The method of forming a semiconductor structure of claim 12, wherein, The initial first barrier layer has a size in the first direction ranging from 2 nanometers to 8 nanometers.

14. The method of forming a semiconductor structure of claim 12, wherein, The forming method of the initial first barrier layer comprises: forming a barrier material layer on the substrate, the barrier material layer also being located on the sidewall and top surface of the first dummy gate structure and filling the first recess; and etching back the barrier material layer until the top surface of the first dummy gate structure, the bottom of the initial first opening and the surface of the substrate are exposed.

15. The method of forming a semiconductor structure of claim 14, wherein, The second opening is formed before the barrier material layer is formed, and the forming method of the second opening comprises: etching the initial second fin with the second dummy gate structure as a mask to form the second opening in the initial second fin, the bottom of the second opening exposing the second bottom structure.

16. The method of forming a semiconductor structure of claim 15, wherein, Before the barrier material layer is formed and after the second opening is formed, the method further comprises: etching the second sacrificial layer to form a second recess between two adjacent second channel layers, the sidewall of the second sacrificial layer exposed by the second recess being recessed relative to the sidewall of the second channel layer.

17. The method of forming a semiconductor structure of claim 16, wherein, The barrier material layer is also located on the sidewall and top surface of the second dummy gate structure and fills the second recess.

18. The method of forming a semiconductor structure of claim 17, wherein, After the barrier material layer is formed and before the first barrier layer is formed, the method further comprises: forming an auxiliary material layer on the substrate, the auxiliary material layer filling the second opening and being located on the sidewall and top of the first dummy gate structure and the second dummy gate structure; and removing the auxiliary material layer on the first region until the barrier material layer on the first region is exposed.

19. The method of forming a semiconductor structure of claim 18, wherein, The material of the auxiliary material layer is different from that of the barrier material layer, and the material of the auxiliary material layer comprises amorphous carbon.

20. The method of forming a semiconductor structure of claim 18, wherein, After the third opening is formed and before the second source-drain layer is formed, the method further comprises: forming a first mask layer on the first region, the first mask layer being located in the initial first opening and the third opening; removing the auxiliary material layer on the second region to expose the barrier material layer on the second region; etching back the barrier material layer on the second region until the sidewall of the second dummy gate structure, the sidewall of the second channel layer and the second opening are exposed, thereby forming a second barrier layer in the second recess.

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