Semiconductor device and method for manufacturing the same

Abstract

Embodiments relate to semiconductor devices and methods for manufacturing the same. The semiconductor device of the embodiment includes a semiconductor portion, first to third electrodes, and a control electrode. The first electrode is provided on the back surface of the semiconductor portion, and the second electrode is provided on the front surface of the semiconductor portion. The third electrode and the control electrode are provided within a trench of the semiconductor portion. The control electrode includes a first control portion and a second control portion. The semiconductor device further includes first to third insulating films. The first insulating film is provided between the control electrode and the semiconductor portion. The second insulating film covers the first control portion and the second control portion, and the third insulating film is provided between the second electrode and the second insulating film. The third insulating film includes a portion extending between the first control portion and the second control portion, and the third electrode is located between the first electrode and the extending portion of the third insulating film.

Description

[0001] Related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2021-35045 (filing date: March 5, 2021), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] In semiconductor devices used for power control, such as MOSFETs, it is desirable to have fast switching speeds and reduced switching losses. For example, in MOSFETs with a trench gate structure, a structure in which a field plate, which is at the same potential as the source electrode, is placed inside the gate trench along with the gate electrode is widely used. This trench gate structure increases parasitic capacitance between the gate and source, slowing switching speeds. Summary of the Invention

[0005] Embodiments provide a semiconductor device with improved switching speed and a method for manufacturing the same.

[0006] A semiconductor device according to an embodiment includes a semiconductor portion, a first electrode, a second electrode, a third electrode, a control electrode, and first to fourth insulating films. The semiconductor portion includes a first semiconductor layer of the first conductivity type, a second semiconductor layer of the second conductivity type, and a third semiconductor layer of the first conductivity type. The first electrode is provided on the back surface of the semiconductor portion, and the second electrode is provided on the front surface of the semiconductor portion. The first semiconductor layer extends between the first and second electrodes, and the second semiconductor layer is provided between the first and second electrodes. The third semiconductor layer is provided between the second semiconductor layer and the second electrode. The control electrode is provided between the semiconductor portion and the second electrode. The semiconductor portion has a trench extending from the front surface into the first semiconductor layer, and the control electrode is provided within the trench. The control electrode includes a first control portion and a second control portion arranged in a first direction along the boundary between the first and second semiconductor layers. The first insulating film is provided between the first or second control portion of the control electrode and the second semiconductor layer of the semiconductor portion. The second insulating film is provided between the first and second control portions of the control electrode and covers the first and second control portions. The third insulating film includes a first portion located between the first control portion and the second electrode, a second portion located between the second control portion and the second electrode, and a third portion located between the first portion and the second portion and extending between the first control portion and the second control portion. The second insulating film is provided between the control electrode and the third insulating film. The third electrode is provided within the trench, extending in the second direction from the first electrode toward the second electrode, between the first electrode and the third portion of the third insulating film, and at a level between the control electrode and the first electrode in the second direction. The fourth insulating film is provided between the first semiconductor layer of the semiconductor portion and the third electrode. The fourth insulating film extends along the inner surface of the trench, with the first control portion and the second control portion of the control electrode provided between the second electrode and the fourth insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic cross-sectional view showing a semiconductor device according to an embodiment.

[0008] Figure 2 (a) and (b) are other schematic cross-sectional views showing the semiconductor device according to the embodiment.

[0009] Figure 3 (a) to (c) are other schematic cross-sectional views showing the semiconductor device according to the embodiment.

[0010] Figure 4 (a)~ Figure 13 (b) is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment.

[0011] Figure 14 (a) and (b) are schematic cross-sectional views showing the manufacturing process of a modified example of the embodiment.

[0012] Figure 15 This is a schematic cross-sectional view of a semiconductor device showing a modification of the embodiment. DETAILED DESCRIPTION

[0013] The following describes the embodiments with reference to the accompanying drawings. Identical parts in the drawings are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate. The following describes different parts. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratios between parts, and other aspects are not necessarily the same as in reality. Furthermore, even when depicting identical parts, their dimensions and ratios may differ depending on the drawing.

[0014] Furthermore, the arrangement and configuration of each component are described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be described as upward and the opposite direction as downward.

[0015] Figure 1 Schematic cross-sectional view of a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, a MOSFET. The semiconductor device 1 has a trench gate structure. The semiconductor device 1 includes a semiconductor portion 10, a first electrode 20, a second electrode 30, and a control electrode 40 (see FIG. 1 ). Figure 2 ) and a third electrode 50. The semiconductor portion 10 is made of silicon, for example.

[0016] The semiconductor portion 10 has, for example, a back surface provided with a first electrode 20 and a surface opposite thereto. The second electrode 30 is provided on the surface side of the semiconductor portion 10. The first electrode 20 is a drain electrode. The first electrode 20 is provided on the back surface of the semiconductor portion 10. The second electrode 30 is a source electrode.

[0017] The semiconductor portion 10 includes a first semiconductor layer 11 of the first conductivity type, a second semiconductor layer 13 of the second conductivity type, a third semiconductor layer 15 of the first conductivity type, a fourth semiconductor layer 17 of the second conductivity type, and a fifth semiconductor layer 19 of the first conductivity type. For example, the first conductivity type is n-type and the second conductivity type is p-type.

[0018] The first semiconductor layer 11 is a so-called drift layer and extends between the first electrode 20 and the second electrode 30 .

[0019] The second semiconductor layer 13 is a so-called p-type diffusion layer and is provided between the first semiconductor layer 11 and the second electrode 30 .

[0020] The third semiconductor layer 15 is a so-called n-type source layer. It is provided between the second semiconductor layer 13 and the second electrode 30. The third semiconductor layer 15 contains a higher concentration of first conductivity-type impurities than the first conductivity-type impurities in the first semiconductor layer 11 and is electrically connected to the second electrode 30.

[0021] The fourth semiconductor layer 17 is a so-called p-type contact layer. It is provided between the second semiconductor layer 13 and the second electrode 30. The fourth semiconductor layer 17 contains a higher concentration of second conductivity-type impurities than the second conductivity-type impurities in the second semiconductor layer 13 and is electrically connected to the second electrode 30. In this example, the fourth semiconductor layer 17 is provided in the second semiconductor layer 13. The second semiconductor layer 13 is electrically connected to the second electrode 30 via the fourth semiconductor layer 17.

[0022] The fifth semiconductor layer 19 is a so-called n-type drain layer. It is provided between the first semiconductor layer 11 and the first electrode 20. The fifth semiconductor layer 19 contains a higher concentration of first conductivity-type impurities than the first semiconductor layer 11 and is electrically connected to the first electrode 20.

[0023] The control electrode 40 is a gate electrode. It is located between the first electrode 20 and the second electrode 30 and is disposed within the trench TR provided in the semiconductor portion 10. The third electrode 50 is a so-called field plate. The third electrode 50 is electrically connected to the source electrode 30 and is disposed within the trench TR together with the control electrode 40.

[0024] like Figure 1 As shown, the control electrode 40 is provided at the same level as the second semiconductor layer 13 in the direction from the first electrode 20 toward the second electrode 30, for example, in the Z direction. The control electrode 40 includes a first control portion 40A and a second control portion 40B. The first control portion 40A and the second control portion 40B are arranged in the trench TR in a direction along the boundary between the first semiconductor layer 11 and the second semiconductor layer 13, for example, in the X direction.

[0025] The trench TR extends in a direction from the second electrode 30 toward the first electrode 20, and has a depth from the surface side of the semiconductor portion 10 to the first semiconductor layer 11. The third electrode 50 is provided, for example, so as to be located in the first semiconductor layer 11. The distance from the third electrode 50 to the first electrode 20 is shorter than the distance from the control electrode 40 to the first electrode 20.

[0026] The length LE of the third electrode 50 in the Z direction is longer than the distance LD between the fifth semiconductor layer 19 and the third electrode 50 . Furthermore, the length LE of the third electrode 50 in the Z direction is longer than the length LG of the control electrode 40 in the Z direction.

[0027] like Figure 1 As shown, the semiconductor device 1 further includes a first insulating film 41 , a second insulating film 43 , a third insulating film 45 , a fourth insulating film 55 , and a fifth insulating film 57 .

[0028] The first insulating film 41 is a so-called gate insulating film. It is provided between the semiconductor portion 10 and the control electrode 40 to electrically insulate the control electrode 40 from the semiconductor portion 10. The second semiconductor layer 13 is provided opposite the control electrode 40 via the first insulating film 41. The third semiconductor layer 15 is in contact with the first insulating film 41 between the second semiconductor layer 13 and the second electrode 30.

[0029] A plurality of trenches TR are provided, for example, arranged in the X direction. The second semiconductor layer 13 is provided between the plurality of trenches TR and faces the first control portion 40A and the second control portion 40B of the control electrode 40 via the first insulating film 41 .

[0030] The second insulating film 43 is provided so as to cover the first control portion 40A and the second control portion 40B of the control electrode 40 inside the trench TR.

[0031] The third insulating film 45 is provided between the second electrode 30 and the control electrode 40 to electrically insulate the control electrode 40 from the second electrode 30. The second insulating film 43 is located between the control electrode 40 and the third insulating film 45. The third insulating film 45 includes a first portion located between the first control portion 40A of the control electrode 40 and the second electrode 30, a second portion located between the second control portion 40B and the second electrode 30, and a third portion extending between the first control portion 40A and the second control portion 40B.

[0032] The second insulating film 43 and the third insulating film 45 function as interlayer insulating films that electrically insulate the control electrode 40 from the second electrode 30 .

[0033] The fourth insulating film 55 is provided between the semiconductor portion 10 and the third electrode 50 to electrically insulate the third electrode 50 from the semiconductor portion 10. The third electrode 50 is located in the first semiconductor layer 11, for example, and the fourth insulating film 55 is located between the first semiconductor layer 11 and the third electrode 50.

[0034] The fourth insulating film 55 is provided, for example, in contact with the control electrode 40. The portion of the fourth insulating film 55 in contact with the control electrode 40 has a width in the X direction that is greater than the width in the X direction of the first control portion 40A and the width in the X direction of the second control portion 40B of the control electrode 40. The third insulating film 45 faces the fourth insulating film 55 with the second insulating film 43 interposed therebetween.

[0035] The fifth insulating film 57 is provided between the third portion of the third insulating film 45 and the third electrode 50. The second insulating film 43 includes a portion located between the third portion of the third insulating film 45 and the fifth insulating film 57. The portion of the second insulating film 43 located between the third portion of the third insulating film 45 and the fifth insulating film 57 extends between a portion of the fourth insulating film 55 that is in contact with the first control unit 40A and a portion of the fourth insulating film 55 that is in contact with the second control unit 40B.

[0036] like Figure 1 As shown, the second electrode 30 includes a first metal layer 31, a second metal layer 33, and a third metal layer 35. The first metal layer 31 is provided on the third insulating film 45. The second metal layer 33 and the third metal layer 35 are sequentially stacked on the first metal layer 31.

[0037] The first metal layer 31 functions as a so-called barrier layer that suppresses the diffusion of metal atoms into the semiconductor portion 10. The second metal layer 33 fills the contact trench CT (see FIG. 1 ) extending from the third insulating film 45 to the semiconductor portion 10. Figure 12 The second metal layer 33 is provided as a so-called buried layer. The third metal layer 35 is provided as a so-called bonding layer and is connected to a conductor such as a metal wire.

[0038] The second electrode 30 includes a contact portion 30cp extending from the upper surface of the third insulating film 45 into the semiconductor portion 10. The contact portion 30cp is formed in the contact trench CT (see FIG. Figure 12 The inner surface of (b) is in contact with and electrically connected to the third semiconductor layer 15 and the fourth semiconductor layer 17 .

[0039] In the embodiment, the third electrode 50 has a first end on the first electrode 20 side and a second end on the second electrode 30 side. The second end of the third electrode 50 is located, for example, below the level of the boundary between the control electrode 40 and the fourth insulating film 55 in the Z direction. For example, when viewed in the X direction, the third electrode 50 is positioned so as not to overlap with the control electrode 40. However, the embodiment is not limited thereto; the second end of the third electrode 50 may also be located between the first control portion 40A and the second control portion 40B of the control electrode 40.

[0040] Figure 2 (a) and (b) are other schematic cross-sectional views showing the semiconductor device 1 according to the embodiment. Figure 2(a) is along Figure 2 (b) is a cross-sectional view of the line AA shown in FIG. Figure 2 (b) is along Figure 2 Cross-sectional view of line BB shown in (a).

[0041] like Figure 2 As shown in (a), the trench TR extends in the Y direction. Multiple control electrodes 40 are provided, and for example, two control electrodes 40 are provided within the trench TR. The first control portion 40A and the second control portion 40B of the control electrode 40 each extend in the Y direction and are integrated at the ends of the control electrode 40 in the Y direction.

[0042] like Figure 2 As shown in (b), a sixth insulating film 59 is provided between the integrated portion of the control electrode 40 and the third electrode 50. The sixth insulating film 59 is provided between the fifth insulating film 57 and the control electrode 40. The sixth insulating film 59 is made of a material different from that of the fifth insulating film 57. For example, the sixth insulating film 59 is made of silicate glass (BPSG) containing boron (B) and phosphorus (P).

[0043] The third electrode 50 includes, for example, extensions 50ea, 50eb, and 50ec located at the same level as the control electrodes 40 in the Z direction. The extensions 50ea and 50ec are provided at both ends of the trench TR in the Y direction. The extension 50eb is provided between the two control electrodes 40. The third electrode 50 is electrically connected to the second electrode 30 in the extension 50eb, for example.

[0044] The semiconductor device 1 further includes a wiring 60. The wiring 60 is provided on the third insulating film 45. The wiring 60 is provided separately from the second electrode 30 and is electrically connected to the control electrode 40. The wiring 60 is provided so as to be electrically insulated from the second electrode 30.

[0045] like Figure 2 As shown in (b), the wiring 60 includes a first metal layer 61, a second metal layer 63, and a third metal layer 65. The wiring 60 has, for example, the same stacked structure as the second electrode 30. The first metal layer 61 is a so-called barrier layer. The second metal layer 63 is a so-called buried layer, and the third metal layer 65 is a so-called bonding layer.

[0046] Figure 3 (a) to (c) are other schematic cross-sectional views showing the semiconductor device 1 according to the embodiment. Figure 3 (a) is along Figure 2 (b) is a cross-sectional view of the CC line shown in FIG. Figure 3 (b) is along Figure 2 (b) is a cross-sectional view of the D-D line shown in FIG. Figure 3 (c) is along Figure 2 (b) is a cross-sectional view taken along line EE.

[0047] like Figure 3 As shown in (a), the second electrode 30 further includes a contact portion 30cf extending through the third insulating film 45 and the second insulating film 43 and reaching the third electrode 50. The contact portion 30cf is in contact with and electrically connected to the extension portion 50eb of the third electrode 50. The second electrode 30 is electrically connected to the third electrode 50 via the contact portion 30cf.

[0048] like Figure 3 As shown in FIG. 5( b ), the wiring 60 includes a contact portion 60cg extending through the third insulating film 45 and the second insulating film 43 and reaching the control electrode 40. The contact portion 60cg is in contact with and electrically connected to the control electrode 40 at a portion where the first control unit 40A and the second control unit 40B are integrated.

[0049] A fifth insulating film 57 and a sixth insulating film 59 are provided between the control electrode 40 and the third electrode 50. Providing a double-layered insulating film in this manner increases the distance between the control electrode 40 and the third electrode 50. This improves the dielectric strength between the control electrode 40 and the third electrode 50 and reduces parasitic capacitance.

[0050] like Figure 3 As shown in (c), the extension portion 50ec of the third electrode 50 is not electrically connected to the second electrode 30. A wiring 60 is provided above the extension portion 50ec via the second insulating film 43, the third insulating film 45, and the fifth insulating film 57. The third electrode 50 is electrically insulated from the wiring 60 by the second insulating film 43, the third insulating film 45, and the fifth insulating film 57. A wiring 60 is also provided above the extension portion 50ea of ​​the third electrode 50 via the second insulating film 43, the third insulating film 45, and the fifth insulating film 57 (see FIG. Figure 2 (b)).

[0051] Next, refer to Figure 4 (a)~ Figure 13 (b) of the present invention will describe a method for manufacturing the semiconductor device 1 according to the embodiment. Figure 4 (a)~ Figure 13 (b) is a schematic cross-sectional view showing the manufacturing process of the semiconductor device 1 .

[0052] like Figure 4As shown in (a), a semiconductor wafer including a semiconductor substrate 100 of a first conductivity type and a first semiconductor layer 11 is prepared. The semiconductor substrate 100 is, for example, an n-type silicon substrate. The first semiconductor layer 11 is, for example, an n-type silicon layer, and is epitaxially grown on the semiconductor substrate 100. The first semiconductor layer 11 contains a first conductivity type impurity at a lower concentration than the first conductivity type impurity concentration in the semiconductor substrate 100.

[0053] Next, a trench TR is formed in the first semiconductor layer 11. The trench TR is formed by selectively etching the first semiconductor layer 11 using, for example, anisotropic RIE (Reactive Ion Etching). The first semiconductor layer 11 is selectively etched using, for example, an etching mask (not shown).

[0054] like Figure 4 As shown in FIG. 1 (b), a fourth insulating film 55 is formed on the first semiconductor layer 11. The fourth insulating film 55 is formed to cover the inner surface of the trench TR. The fourth insulating film 55 is formed so that a first space SP1 remains within the trench TR. The fourth insulating film 55 is formed using, for example, CVD (Chemical Vapor Deposition). The fourth insulating film 55 is, for example, a silicon oxide film.

[0055] Alternatively, the fourth insulating film 55 may have a two-layer structure including a silicon oxide film formed by thermally oxidizing the first semiconductor layer 11 and a silicon oxide film formed by CVD.

[0056] like Figure 5 As shown in (a), a conductive film 105 is formed on the fourth insulating film 55. The conductive film 105 is buried in the first space SP1 (refer to Figure 4 The conductive film 105 is formed by the method of (b). The conductive film 105 is, for example, a polysilicon film. The conductive film 105 is formed by, for example, CVD to have conductivity.

[0057] like Figure 5 As shown in (b), the conductive film 105 is etched so that a portion thereof remains in the trench TR. For example, the conductive film 105 is removed by wet etching. The portion of the conductive film 105 remaining in the trench TR is the third electrode 50. In the trench TR, the second space SP2 is formed above the third electrode 50.

[0058] In addition, the extension portions 50ea, 50eb, and 50ec of the third electrode 50 remain in the trench TR (see Figure 2 The conductive film 105 is removed by the method of (b). That is, after removing the other portions formed on the first semiconductor layer 11, the portion remaining inside the trench TR is selectively removed using an etching mask (not shown).

[0059] like Figure 6 As shown in (a), a fifth insulating film 57 is formed on the third electrode 50. The fifth insulating film 57 is formed, for example, by thermally oxidizing the third electrode 50 through the second space SP2. The fifth insulating film 57 is, for example, a silicon oxide film.

[0060] like Figure 6 As shown in FIG. 5 ( b ), a sixth insulating film 59 is formed on the fourth insulating film 55 and the fifth insulating film 57. The sixth insulating film 59 is formed so as to fill the second space SP2. The sixth insulating film 59 is formed using, for example, CVD.

[0061] The sixth insulating film 59 is, for example, BPSG. Using BPSG for the sixth insulating film 59 allows for uniform filling of the second space SP2. For example, BPSG has a softening point below 1000°C. Therefore, BPSG can be softened by heat treatment, removing seams and gaps in the sixth insulating film 59 formed within the second space SP2.

[0062] like Figure 7 As shown in (a), the portion filled with the second space SP2 is left and the sixth insulating film 59 is removed. For example, CMP (Chemical Mechanical Polishing) is used to remove the sixth insulating film 59. At this time, the fourth insulating film 55CMP functions as a stopper.

[0063] like Figure 7 As shown in (b), a third space SP3 is formed in the upper portion of the trench TR. The third space SP3 is formed by partially removing the fourth insulating film 55 and the sixth insulating film 59 using isotropic dry etching, for example (see FIG. 2 ). Figure 7 (b)).

[0064] For example, if seams or gaps exist in the sixth insulating film 59, it is difficult to uniformly etch the fourth insulating film 55 and the sixth insulating film 59, making it difficult to control the depth of the third space SP3. In the embodiment, BPSG is used in the sixth insulating film 59 to eliminate seams and gaps, making etching control easier. The third space SP3 is formed to expose the first semiconductor layer 11.

[0065] like Figure 8 As shown in (a), the sixth insulating film 59 remaining on the fifth insulating film 57 is removed. For example, the sixth insulating film 59 is removed by wet etching. For example, by using a diluted solution of hydrofluoric acid as an etching solution, the sixth insulating film 59 can be selectively removed. The fourth insulating film 55 and the fifth insulating film 57 are exposed on the bottom surface of the third space SP3. In addition, the sixth insulating film 59 is selectively removed using an etching mask not shown so that a portion of it remains at the end of the third space SP3 in the extension direction (Y direction) of the trench TR (refer to FIG. Figure 2 (b)).

[0066] like Figure 8 As shown in (b), a first insulating film 41 is formed on the first semiconductor layer 11. The first insulating film 41 is formed, for example, by thermally oxidizing the first semiconductor layer 11. The first insulating film 41 is, for example, a silicon oxide film. Furthermore, during the process of forming the first insulating film 41 by thermal oxidation, the third electrode 50 is also oxidized, and the thickness of the fifth insulating film 57 in the Z direction also increases.

[0067] When the sixth insulating film 59 is made of BPSG, for example, boron and phosphorus diffuse into undesired portions during the thermal oxidation process of forming the first insulating film 41. Figure 8 In the process shown in (a), by selectively removing the sixth insulating film 59, diffusion of such impurities can be prevented.

[0068] like Figure 9 As shown in (a), a conductive film 110 is formed and buried in the third space SP3. The conductive film 110 is, for example, a polycrystalline silicon film containing first conductivity type impurities such as phosphorus (P) or arsenic (As). The conductive film 110 is formed, for example, using CVD. The conductive film 110 can also be made conductive by doping first conductivity type impurities during the CVD process. Alternatively, after forming the polycrystalline silicon film that becomes the conductive film 110, the first conductivity type impurities can be diffused into the polycrystalline silicon.

[0069] like Figure 9 As shown in (b), the portion filled with the third space SP3 is left and the conductive film 110 is removed. For example, CMP is used to remove the conductive film 110. The first insulating film 41 on the upper surface of the first semiconductor layer 11 functions as a CMP stopper.

[0070] like Figure 10 As shown in (a), a second semiconductor layer 13 is formed on the first semiconductor layer 11. The second semiconductor layer 13 is formed by activating and diffusing the second conductive type impurity ion-implanted through the first insulating film 41 on the first semiconductor layer 11 through a heat treatment. As the second conductive type impurity, for example, boron (B) is ion-implanted into the first semiconductor layer 11. The boundary between the first semiconductor layer 11 and the second semiconductor layer 13 is set to be located above the boundary between the fourth insulating film 55 and the conductive film 110 in the Z direction, for example.

[0071] like Figure 10 As shown in (b), an etching mask 115 is formed on the second semiconductor layer 13 and the conductive film 110. The etching mask 115 has an opening 115s on the conductive film 110. The etching mask 115 is formed using, for example, photolithography.

[0072] like Figure 11 As shown in FIG. 1A and FIG. 2A , a first control portion 40A and a second control portion 40B of the control electrode 40 are formed in the trench TR. The first control portion 40A and the second control portion 40B are formed by selectively etching the conductive film 110. For example, the conductive film 110 is selectively removed by wet etching using an etching mask 115. The fourth insulating film 55 and the fifth insulating film 57 are exposed in the space between the first control portion 40A and the second control portion 40B.

[0073] The first control unit 40A and the second control unit 40B are each formed to have a flat upper surface. The length LG of the first control unit 40A and the second control unit 40B in the Z direction is, for example, 0.4 to 1.5 micrometers (μm). Furthermore, the width WG of the first control unit 40A and the second control unit 40B in the X direction is, for example, 0.1 to 0.5 μm.

[0074] like Figure 11 As shown in (b), the third semiconductor layer 15 is formed on the second semiconductor layer 13. The third semiconductor layer 15 is formed by ion-implanting first conductivity type impurities such as phosphorus (P) into the second semiconductor layer 13 through the first insulating film 41 and activating them by heat treatment.

[0075] like Figure 12 As shown in (a), a second insulating film 43 and a third insulating film 45 are formed on the control electrode 40 and the first insulating film 41. The second insulating film 43 covers the first control portion 40A and the second control portion 40B of the control electrode 40, and also covers the fourth insulating film 55 and the fifth insulating film 57 exposed in the space between the first control portion 40A and the second control portion 40B. In addition, the second insulating film 43 also covers the third semiconductor layer 15 via the first insulating film 41. The second insulating film 43 is, for example, a silicon oxide film and is formed using CVD.

[0076] The third insulating film 45 is formed on the second insulating film 43 so as to fill the space between the first control section 40A and the second control section 40B. The third insulating film 45 includes a portion extending between the first control section 40A and the second control section 40B. The third insulating film 45 is made of, for example, BPSG. The third insulating film 45 is formed using, for example, CVD.

[0077] like Figure 12 As shown in (b), a contact trench CT is formed extending from the upper surface of the third insulating film 45 into the second semiconductor layer 13. The contact trench CT is formed, for example, by selectively etching the third insulating film 45, the second insulating film 43, the first insulating film 41, and the third semiconductor layer 15 using anisotropic RIE and an etching mask (not shown). The contact trench CT is formed, for example, so as to have a bottom surface in the second semiconductor layer 13.

[0078] Furthermore, a fourth semiconductor layer 17 is formed in the second semiconductor layer 13. The fourth semiconductor layer 17 is formed by ion-implanting a second-conductivity-type impurity, such as boron (B), into the second semiconductor layer 13 through the contact trench CT and then activating the second-conductivity-type impurity by heat treatment. The fourth semiconductor layer 17 is provided, for example, at a position away from the third semiconductor layer 15. Alternatively, the fourth semiconductor layer 17 may be formed so as to be in contact with the third semiconductor layer 15.

[0079] like Figure 13 As shown in (a), the contact trench CT is extended, for example, in the X direction. This exposes a portion of the upper surface of the third semiconductor layer 15. The contact trench CT is extended, for example, by etching the first insulating film 41, the second insulating film 43, and the third insulating film 45 on the third semiconductor layer 15.

[0080] like Figure 13 As shown in (b), the second electrode 30 is formed on the third insulating film 45. The second electrode 30 includes a first metal layer 31, a second metal layer 33, and a third metal layer 35. The second electrode 30 is formed so as to be embedded in the contact trench CT.

[0081] The first metal layer 31 is formed to cover the upper surface of the third insulating film 45 and the inner surface of the contact trench CT. The first metal layer 31 is, for example, a titanium nitride layer (TiN). The first metal layer 31 is formed using, for example, reactive sputtering.

[0082] The second metal layer 33 is formed on the first metal layer 31. The second metal layer 33 is formed so as to fill the contact trench CT. The second metal layer 33 is, for example, a tungsten layer (W) and is formed using CVD.

[0083] The third metal layer 35 is formed on the second metal layer 33. The third metal layer 35 is, for example, an aluminum layer (Al), and is formed using a sputtering method.

[0084] Next, the back side of the semiconductor substrate 100 is ground to form a fifth semiconductor layer 19 of a predetermined thickness. Furthermore, a first electrode 20 is formed on the back side of the fifth semiconductor layer 19 to complete the semiconductor device 1. The first electrode 20 is a metal layer containing, for example, nickel or aluminum.

[0085] The above-mentioned manufacturing method is an example, and the embodiment is not limited thereto. For example, the third insulating film 45 may be a silicon oxide film.

[0086] For example, the first insulating film 41, the second insulating film 43, and the third insulating film 45 are silicon oxide films having different manufacturing methods. The first insulating film 41 is, for example, an oxide film formed by thermal oxidation and having a high film density with the least unbonded silicon bonds. The second insulating film 43 and the third insulating film 45 are formed using one of CVD, HDP (High Density Plasma), and HARP (High Aspect Ratio Process), respectively. Silicon oxide films using these manufacturing methods, for example, contain unbonded silicon bonds terminated by hydrogen atoms. Therefore, the second insulating film 43 and the third insulating film 45 have a lower film density than the silicon oxide film formed by thermal oxidation. As a result, the first insulating film 41, the second insulating film 43, and the third insulating film 45 become silicon oxide films with different film densities from each other.

[0087] For example, the film density of the second insulating film 43 is lower than the film density of the first insulating film 41 and higher than the third insulating film 45. In addition, the film density of the third insulating film 45 can also be formed to be lower than the film density of the first insulating film 41 and the same as the film density of the second insulating film 43, or higher than the film density of the second insulating film 43. The difference in "film density" can be detected using, for example, RBS (Rutherford Back scattering) or XRR (X-ray Reflection). In addition, the difference in "film density" can also be detected by the difference in contrast of HAADF-STEM (High Angle Annular Dark-Field Scanning Transmission Electron Microscopy) images.

[0088] When the BPSG film is used as the third insulating film 45 , it is possible to getter (capture) mobile ions such as sodium (Na) in the silicon oxide film, thereby improving the reliability of the semiconductor device 1 .

[0089] For example, the fourth insulating film 55 is formed thicker at the bottom of the trench TR near the first electrode 20 to achieve a higher dielectric breakdown voltage. If the fourth insulating film 55 is formed using, for example, thermal oxidation, the warping of the wafer due to stress in the film increases. To avoid this, the fourth insulating film 55 is formed using, for example, a silicon oxide film formed using CVD, or a two-layer structure consisting of a silicon oxide film formed by thermal oxidation and a silicon oxide film formed by CVD. However, a silicon oxide film formed using CVD contains Na ions, and the thicker the film, the greater the amount of Na contained in the film.

[0090] The semiconductor device 1 of the embodiment includes a third insulating film 45 (BPSG film) extending between the first control portion 40A and the second control portion 40B of the control electrode 40. This BPSG film is provided in close proximity to the fourth insulating film 55 via the second insulating film 43. This improves the gettering efficiency of the BPSG film for Na ions, suppressing the migration of Na ions from the fourth insulating film 55 to the gate insulating film. Consequently, it is possible to suppress characteristic variations in the semiconductor device 1 and improve reliability.

[0091] Figure 14 (a) and (b) are schematic cross-sectional views showing a manufacturing method according to a modified example of the embodiment. Figure 9 (a)~ Figure 11 The manufacturing process shown in (a) is implemented Figure 14 The manufacturing process shown in (a) and (b).

[0092] like Figure 14 As shown in (a), a conductive film 110 is formed. The conductive film 110 is formed to cover the first insulating film 41 and to be exposed in the third space SP3 (see Figure 9 The fourth insulating film 55 and the fifth insulating film 57 of (a) are provided. The conductive film 110 is, for example, a polysilicon film having conductivity. The conductive film 110 is formed so as to leave a fourth space SP4 in the upper portion of the trench TR.

[0093] like Figure 14 As shown in (b), the portion formed on the wall surface of the trench TR remains, and the conductive film 110 is selectively removed. For example, the conductive film 110 is removed using anisotropic RIE. The portion of the conductive film 110 remaining on the wall surface of the trench TR becomes the first control portion 40A and the second control portion 40B of the control electrode 40. The first control portion 40A and the second control portion 40B are each formed to face the first semiconductor layer 11 via the first insulating film 41. In addition, the first control portion 40A and the second control portion 40B are formed to have upper ends inclined relative to the wall surface of the trench TR.

[0094] Furthermore, a second semiconductor layer 13 is formed on the first semiconductor layer 11. The second semiconductor layer 13 is formed by activating and diffusing the second conductivity-type impurities ion-implanted through the first insulating film 41 on the first semiconductor layer 11 through a heat treatment. The boundary between the first semiconductor layer 11 and the second semiconductor layer 13 is formed to be located above the level of the boundary between each of the first control portion 40A and the second control portion 40B and the fourth insulating film 55. The second semiconductor layer 13 is formed to face the first control portion 40A and the second control portion 40B across the first insulating film 41.

[0095] Figure 151 is a schematic cross-sectional view showing a semiconductor device 2 according to a modification of the embodiment. The semiconductor device 2 has the same trench gate structure as the semiconductor device 1.

[0096] like Figure 15 As shown, the second electrode 30 of the semiconductor device 2 includes a first metal layer 31, a second metal layer 34 and a third metal layer 35. The first metal layer 31 is provided on the third insulating film 45 and covers the contact trench CT (see Figure 13 (a)) of the inner surface.

[0097] Second metal layer 34 is provided so as to fill contact trench CT. Second metal layer 34 is, for example, a tungsten layer formed using CVD. Second metal layer 34 is removed, leaving the portion filling contact trench CT. Third metal layer 35 is provided over first metal layer 31 and second metal layer 34. In this example, third metal layer 35 is in contact with first metal layer 31 provided over third insulating film 45.

[0098] In the semiconductor devices 1 and 2 of the embodiments, the upper end of the third electrode 50 is positioned below the level of the lower end of the control electrode 40. This increases the distance from the control electrode 40 to the third electrode 50. This reduces the parasitic capacitance between the gate and the source, thereby increasing the switching speed.

[0099] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: a semiconductor portion comprising a first semiconductor layer of the first conductivity type, a second semiconductor layer of the second conductivity type, and a third semiconductor layer of the first conductivity type; a first electrode provided on the back side of the semiconductor portion; a second electrode provided on a surface side of the semiconductor portion, the first semiconductor layer extending between the first electrode and the second electrode, the second semiconductor layer provided between the first semiconductor layer and the second electrode, and the third semiconductor layer provided between the second semiconductor layer and the second electrode; a control electrode provided in the semiconductor portion, comprising a first control portion and a second control portion arranged in a first direction intersecting a second direction from the first electrode toward the second electrode; and a connecting portion integrating the first control portion and the second control portion; a first insulating film provided between the first control portion or the second control portion of the control electrode and the second semiconductor layer; a second insulating film provided between the first control portion and the second control portion and covering the first control portion and the second control portion; a third insulating film comprising: a first portion located between the first control portion and the second electrode; a second portion located between the second control portion and the second electrode; and a third portion located between the first portion and the second portion and extending between the first control portion and the second control portion, wherein the second insulating film is provided between the control electrode and the third insulating film; a third electrode provided in the semiconductor portion, extending in the second direction, and having a portion located between the first electrode and the third portion of the third insulating film and a portion located between the first electrode and the connecting portion of the control electrode; a fourth insulating film located between the first semiconductor layer and the third electrode, wherein the first control portion and the second control portion of the control electrode are located between the second electrode and the fourth insulating film; a fifth insulating film provided between the third portion of the third insulating film and the third electrode and between the connecting portion of the control electrode and the third electrode; and A sixth insulating film is provided between the connection portion of the control electrode and the fifth insulating film and includes a material different from that of the fifth insulating film.

2. The semiconductor device according to claim 1, wherein A distance from the third electrode to the first electrode is shorter than a distance from the control electrode to the first electrode.

3. The semiconductor device according to claim 1 or 2, wherein The second insulating film has a portion located between the third electrode and the third insulating film, The portion of the second insulating film extends in the fourth insulating film.

4. The semiconductor device according to claim 1 or 2, wherein The third insulating film is silicate glass containing boron and phosphorus.

5. The semiconductor device according to claim 1 or 2, wherein The first control portion and the second control portion of the control electrode are each provided to have a first width in the first direction and to be in contact with the fourth insulating film. The fourth insulating film has a second width in the first direction at a portion in contact with the control electrode, and the second width is wider than the first width.

6. A method for manufacturing a semiconductor device having a trench gate structure, the semiconductor device comprising a gate electrode having a first control portion and a second control portion, and a field plate, the method comprising: The process of forming trenches on a semiconductor wafer; forming a field plate insulating film covering an inner surface of the trench while leaving a first space inside the trench; forming a first conductive film embedded in the first space; removing the first conductive film while leaving a portion of the first conductive film located at the bottom of the trench, thereby forming the field plate at the bottom of the trench; forming a first intermediate insulating film on the field plate by thermally oxidizing the field plate in a second space formed in the field plate insulating film by removing the first conductive film; forming a second interlayer insulating film on the first interlayer insulating film so as to fill the second space; forming a third space in which a portion of the semiconductor wafer is exposed by partially removing each of the second interlayer insulating film and the field plate insulating film at an upper portion of the trench; a step of removing a remaining portion of the second interlayer insulating film exposed in the third space; forming a gate insulating film by thermally oxidizing the portion of the semiconductor wafer exposed in the third space; forming a second conductive film covering the gate insulating film, the field plate insulating film, and the first intermediate insulating film in the third space; as well as A step of selectively removing a portion of the second conductive film formed on the first interlayer insulating film to form the first control portion and the second control portion of the gate electrode.

7. The method according to claim 6, wherein: The gate electrode is formed to have a connection portion connecting the first control portion and the second control portion, The remaining portion of the second interlayer insulating film is removed so as to remain between the connecting portion of the gate electrode and the first interlayer insulating film.

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