GaN-based LED epitaxial wafer, epitaxial growth method and LED chip

Abstract

This invention provides a GaN-based LED epitaxial wafer, an epitaxial growth method, and an LED chip. The epitaxial wafer incorporates a three-dimensional nucleation layer, comprising a first three-dimensional nucleation layer, a three-dimensional nucleation temperature transition layer, and a second three-dimensional nucleation layer stacked sequentially. The temperature during the growth of the first three-dimensional nucleation layer is lower than the temperatures during the growth of the three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer. The temperature during the growth of the three-dimensional nucleation temperature transition layer gradually increases. Specifically, the lower temperature of the first three-dimensional nucleation layer effectively reduces the nucleus density. The three-dimensional nucleation temperature transition layer allows the longitudinal growth of the nuclei to exceed the lateral growth, developing into GaN islands. The higher growth temperature of the second three-dimensional nucleation layer intensifies the lateral growth of the GaN islands, gradually leading to their fusion, reducing the nucleus density, decreasing line defects, and improving the crystal quality of GaN.

Description

Technical Field

[0001] This invention relates to the field of LED technology, and in particular to a GaN-based LED epitaxial wafer, an epitaxial growth method, and an LED chip. Background Technology

[0002] In recent years, with the rapid improvement of luminous efficacy, GaN-based LEDs have been widely used in general lighting, display and other fields.

[0003] Group III nitride semiconductor materials mainly include GaN, InN, AlN, and ternary or quaternary alloys composed of them. Compared with the previous two generations of semiconductor materials, Group III nitride semiconductor materials have the characteristics of high electron saturation drift velocity, low dielectric constant, high breakdown field strength, and high thermal conductivity. These excellent optical and electrical properties make III-V nitride materials promising in optoelectronic devices such as light-emitting diodes (LEDs), laser diodes (LDs), and ultraviolet photodetectors, and they have been widely used. Crucially, Group III nitride semiconductor materials all possess direct band gaps, giving them extremely high luminous efficiency. By controlling the alloy composition, the band gap can be continuously varied from 0.7 eV for InN to 3.4 eV for GaN and then to 6.2 eV for AlN. These unique advantages enable Group III nitride light-emitting devices to cover a wide wavelength range from infrared to near-ultraviolet, making them ideal semiconductor light-emitting materials.

[0004] The quality of GaN crystal is a crucial factor affecting the luminous efficiency and reliability of GaN-based LEDs. Since GaN is the foundation for InGaN quantum well growth, dislocations in GaN propagate into the quantum well, impacting luminous efficiency. Therefore, obtaining high-quality GaN is fundamental to improving InGaN crystal quality. Due to the significant lattice mismatch between GaN and the substrate, a two-step method is typically used to grow GaN epitaxial layers: first, a GaN buffer layer is grown at a low temperature, followed by a high-temperature GaN layer. While this two-step method can improve GaN crystal quality to some extent, the high-temperature growth leads to excessively rapid coalescence of island-like GaN epitaxial layers, resulting in numerous line defects. Summary of the Invention

[0005] Based on this, the purpose of this invention is to provide a GaN-based LED epitaxial wafer, an epitaxial growth method, and an LED chip, with the aim of reducing line defects caused by the merging of island-shaped GaN epitaxial layers and improving the crystal quality of GaN.

[0006] According to an embodiment of the present invention, a GaN-based LED epitaxial wafer includes a three-dimensional nucleation layer, which comprises a first three-dimensional nucleation layer, a three-dimensional nucleation temperature transition layer, and a second three-dimensional nucleation layer stacked sequentially. The temperature at which the first three-dimensional nucleation layer is grown is lower than the temperature at which the three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown. The temperature at which the first three-dimensional nucleation layer and the second three-dimensional nucleation layer are grown is constant, while the temperature at which the three-dimensional nucleation temperature transition layer is grown gradually increases.

[0007] Furthermore, a Ga source is introduced during the growth of the three-dimensional nucleation layer, wherein the Ga source flow rate is gradually increased during the growth of the first three-dimensional nucleation layer.

[0008] Furthermore, the thickness ratio of the first three-dimensional nucleation layer, the three-dimensional nucleation temperature transition layer, and the second three-dimensional nucleation layer is 1-2:1-2:1-3.

[0009] Furthermore, the thickness of the three-dimensional nucleation layer is 0.5 μm to 5 μm.

[0010] According to an embodiment of the present invention, an epitaxial growth method for an LED epitaxial wafer is used to prepare the above-mentioned GaN-based LED epitaxial wafer. The epitaxial growth method includes:

[0011] Provide a substrate required for growth;

[0012] A buffer layer, a three-dimensional nucleation layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially stacked on the substrate.

[0013] During the growth of the three-dimensional nucleation layer, a first three-dimensional nucleation layer, a three-dimensional nucleation temperature transition layer, and a second three-dimensional nucleation layer are sequentially deposited on the buffer layer.

[0014] The temperature at which the first three-dimensional nucleation layer is grown is lower than the temperature at which the three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown. The temperature at which the first three-dimensional nucleation layer and the second three-dimensional nucleation layer are grown is constant, while the temperature at which the three-dimensional nucleation temperature transition layer is grown gradually increases.

[0015] Furthermore, the growth temperature of the three-dimensional nucleation layer is 950℃~1080℃, and the growth pressure is 0 torr~500 torr.

[0016] Furthermore, during the growth of the first three-dimensional nucleation layer, the growth temperature is controlled at a first temperature. During the growth of the three-dimensional nucleation temperature transition layer, the growth temperature is controlled to gradually increase from the first temperature to 20°C to 50°C, and then to a second temperature. During the growth of the second three-dimensional nucleation layer, the growth temperature is controlled at the second temperature.

[0017] Furthermore, during the growth of the first three-dimensional nucleation layer, the Ga source flow rate is gradually increased to a first flow rate, and the three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown at the first flow rate.

[0018] Furthermore, the Ga source flow rate is 600 slm to 1200 slm.

[0019] An LED chip according to an embodiment of the present invention includes the above-described GaN-based LED epitaxial wafer.

[0020] Compared with existing technologies: By setting a three-dimensional nucleation layer in a GaN-based LED epitaxial wafer, the three-dimensional nucleation layer includes a first three-dimensional nucleation layer, a three-dimensional nucleation temperature transition layer, and a second three-dimensional nucleation layer stacked sequentially. The temperature during the growth of the first three-dimensional nucleation layer is lower than the temperature during the growth of the three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer. The temperature during the growth of the three-dimensional nucleation temperature transition layer gradually increases. Specifically, the lower temperature of the first three-dimensional nucleation layer can effectively reduce the nucleus density of the nucleation layer. The three-dimensional nucleation temperature transition layer can make the longitudinal growth of the nuclei higher than the lateral growth, developing into GaN islands. The higher growth temperature of the second three-dimensional nucleation layer will intensify the lateral growth of the GaN islands, gradually causing the GaN islands to fuse, reducing the nucleus density, reducing the generation of line defects, and improving the crystal quality of GaN. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of the GaN-based LED epitaxial wafer in Embodiment 1 of the present invention;

[0022] Figure 2 This is a schematic diagram of the three-dimensional nucleation layer in Embodiment 1 of the present invention;

[0023] Figure 3 This is a flowchart of the epitaxial growth method for GaN-based LED epitaxial wafers in Embodiment 2 of the present invention. Detailed Implementation

[0024] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0025] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0027] Example 1

[0028] Please see Figure 1 and Figure 2 , Figure 1 The image shown is a GaN-based LED epitaxial wafer according to Embodiment 1 of the present invention. Figure 2 The diagram shows a three-dimensional nucleation layer. The GaN-based LED epitaxial wafer includes a substrate 10 and a buffer layer 20, a three-dimensional nucleation layer 30, an undoped GaN layer 40, an N-type GaN layer 50, a multiple quantum well layer 60, an electron blocking layer 70, and a P-type GaN layer 80 that are epitaxially grown sequentially on the substrate 10.

[0029] The three-dimensional nucleation layer 30 is a GaN layer, comprising a first three-dimensional nucleation layer 301, a three-dimensional nucleation temperature transition layer 302, and a second three-dimensional nucleation layer 303 stacked sequentially, and the thickness ratio of the first three-dimensional nucleation layer 301, the three-dimensional nucleation temperature transition layer 302, and the second three-dimensional nucleation layer 303 is 1~2:1~2:1~3.

[0030] By way of example and not limitation, in some preferred embodiments of this embodiment, the thickness of the buffer layer 20 is 10nm to 50nm, for example, 12nm, 14nm, 16nm, etc.; the thickness of the three-dimensional nucleation layer 30 is 0.5um to 5um, for example, 1um, 2um, 3um, etc.; the thickness of the undoped GaN layer 40 is 2μm to 3μm, for example, 2.2um, 2.4um, 2.6um, etc.; the thickness of the N-type GaN layer 50 is 2um to 3um, for example, 2.2um, 2.4um, 2.6um, etc.; the thickness of the multiple quantum well layer 60 is 42nm to 240nm, for example, 100nm, 120nm, 140nm, etc.; the thickness of the electron blocking layer 70 is 10nm to 40nm, for example, 15nm, 20nm, 35nm, etc.; and the thickness of the P-type GaN layer 80 is 10nm to 50nm, for example, 15nm, 20nm, 25nm, etc.

[0031] Specifically, the multiple quantum well layer 60 consists of alternating stacked InGaN quantum well layers and AlGaN quantum barrier layers. As an example and not a limitation, in some preferred embodiments of this embodiment, the thickness of a single InGaN quantum well layer is 2nm to 5nm, for example, 2.5nm, 3nm, 3.5nm, etc.; the thickness of a single AlGaN quantum barrier layer is 5nm to 15nm, for example, 9.5nm, 10nm, 11nm, etc. The number of stacking cycles of the quantum well layer and the quantum barrier layer 506 in the multiple quantum well layer 60 is 6 to 12, for example, 9, that is, there are 9 quantum well layers and 9 quantum barrier layers 506.

[0032] Example 2

[0033] Please see Figure 3 The figure shows an epitaxial growth method for GaN-based LED epitaxial wafers according to Embodiment 2 of the present invention. The method specifically includes steps S201 to S209, wherein:

[0034] Step S201: Provide a substrate required for growth.

[0035] The substrate can be selected from one of the following: sapphire substrate, SiO2 sapphire composite substrate, silicon substrate, silicon carbide substrate, gallium nitride substrate, and zinc oxide substrate.

[0036] Specifically, sapphire substrates are selected because they have mature manufacturing processes, low prices, are easy to clean and process, and have good stability at high temperatures.

[0037] In this embodiment, an A7 MOCVD (Metal-organic Chemical Vapor Deposition) equipment was used. One of the following gases—high-purity H2 (hydrogen), high-purity N2 (nitrogen), or a mixture of high-purity H2 and high-purity N2—was used as the carrier gas. High-purity NH3 was used as the N source, trimethylgallium (TMGa) and triethylgallium (TEGa) were used as gallium sources, trimethylindium (TMIn) was used as the indium source, trimethylaluminum (TMAl) was used as the aluminum source, silane (SiH4) was used as the N-type dopant, and magnesium dicthene (CP2Mg) was used as the P-type dopant for epitaxial growth.

[0038] Step S202: Grow a buffer layer with a thickness of 10 nm to 50 nm.

[0039] It should be noted that the material of the buffer layer can be AlN or GaN. In this embodiment, an AlN buffer layer with a thickness of 15nm is selected to be deposited in the PVD of the applied material. The AlN buffer layer is used to control crystal defects, improve the quality of subsequent crystal growth, and alleviate the stress caused by lattice mismatch and thermal mismatch between the substrate and the epitaxial layer.

[0040] Step S203: Pre-treat the sapphire substrate with the deposited buffer layer.

[0041] Specifically, the sapphire substrate with the AlN buffer layer deposited is transferred into the MOCVD equipment and pretreated in H2 atmosphere for 1 min to 10 min at a temperature of 1000℃ to 1200℃. Then, the sapphire substrate is nitrided to improve the crystal quality of the AlN buffer layer and effectively improve the crystal quality of the subsequently deposited GaN epitaxial layer.

[0042] Step S204: Grow a three-dimensional nucleation layer with a thickness of 0.5 μm to 5 μm.

[0043] It should be noted that the three-dimensional nucleation layer includes a first three-dimensional nucleation layer, a three-dimensional nucleation temperature transition layer, and a second three-dimensional nucleation layer, which are sequentially stacked on the buffer layer. During the growth of the three-dimensional nucleation layer, a Ga source is introduced with a Ga source flow rate of 600 slm to 1200 slm. During the growth of the first three-dimensional nucleation layer, the Ga source flow rate is gradually increased to a first flow rate, and the three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown at the first flow rate.

[0044] Specifically, the growth temperature of the three-dimensional nucleation layer is 950℃~1080℃, and the growth pressure is 50 torr~500 torr. During the growth of the first three-dimensional nucleation layer, the growth temperature is controlled at the first temperature. During the growth of the three-dimensional nucleation temperature transition layer, the growth temperature is controlled to gradually increase from the first temperature to the second temperature by 20℃~50℃. During the growth of the second three-dimensional nucleation layer, the growth temperature is controlled at the second temperature. The lower temperature of the first three-dimensional nucleation layer can effectively reduce the nucleus density. The three-dimensional nucleation temperature transition layer can make the longitudinal growth of the nuclei higher than the lateral growth, developing into GaN islands. The higher growth temperature of the second three-dimensional nucleation layer will intensify the lateral growth of the GaN islands, gradually causing the GaN islands to merge, reducing the nucleus density, and reducing the generation of line defects.

[0045] In this embodiment, the thickness of the three-dimensional nucleation layer is 2.5 μm. The thickness ratio of the first three-dimensional nucleation layer, the three-dimensional nucleation temperature transition layer, and the second three-dimensional nucleation layer is 1:1:1, that is, the thickness of the first three-dimensional nucleation layer, the three-dimensional nucleation temperature transition layer, and the second three-dimensional nucleation layer is 0.83 μm. During the growth of the three-dimensional nucleation layer, the growth pressure is 150 torr. During the growth of the first three-dimensional nucleation layer, the growth temperature is controlled at 1050°C. During the growth of the three-dimensional nucleation temperature transition layer, the growth temperature is gradually increased by 30°C from 1050°C to 1080°C. During the growth of the second three-dimensional nucleation layer, the growth temperature is controlled at 1080°C. At the same time, during the growth of the first three-dimensional nucleation layer, the Ga source flow rate is gradually increased from 600 slm to 1000 slm. The three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown at a Ga source flow rate of 1000 slm.

[0046] Step S205: Grow an undoped GaN layer with a thickness of 1 μm to 5 μm.

[0047] Specifically, the growth temperature of the undoped GaN layer is 1050℃~1200℃, and the growth pressure is 100 torr~600 torr. In this embodiment, the growth temperature of the undoped GaN layer is 1100℃, the growth pressure is 150 torr, and the growth thickness is 2μm~3μm. At this thickness, not only is the GaN crystal quality better, but the Ga source is also saved, thus reducing production costs.

[0048] Step S206: Grow an N-type GaN layer with a thickness of 2µm to 3µm.

[0049] Specifically, the growth temperature of the N-type GaN layer is 1050℃~1200℃, and the growth pressure is 100 torr~600 torr. During the growth process, Si is doped at a concentration of 1E19 atoms / cm². 3 ~5E19 atoms / cm3 , which ensures the quality of the N-type GaN crystal and the sheet resistance of the N-type GaN layer. In this embodiment, the growth temperature of the N-type GaN layer is 1120 °C, the growth pressure is 100 torr, and the Si doping concentration is 2.5E19 atoms / cm 3 , providing sufficient electrons for the light-emitting diode to ensure that there are enough electrons to recombine with holes.

[0050] Step S207: Grow a multi-quantum well layer with a growth thickness of 42 nm to 240 nm.

[0051] Among them, the multi-quantum well layer is an alternately stacked InGaN quantum well layer and an AlGaN quantum barrier layer, with the stacking period number of 6 to 12. The growth temperature of the InGaN quantum well layer is 790 °C to 810 °C, the thickness is 2 nm to 5 nm, the growth pressure is 50 torr to 300 torr, the growth temperature of the AlGaN quantum barrier layer is 800 °C to 900 °C, the thickness is 5 nm to 15 nm, the growth pressure is 50 torr to 300 torr, and the Al component is 0.01 to 0.1.

[0052] Specifically, the multi-quantum well layer is an alternately stacked InGaN quantum well layer and an AlGaN quantum barrier layer, with the stacking period number of 10. The growth temperature of the InGaN quantum well is 795 °C, the thickness is 3.5 nm, the pressure is 200 torr, the In component is 0.22, the growth temperature of the AlGaN quantum barrier layer is 855 °C, the thickness is 9.8 nm, the growth pressure is 200 torr, and the Al component is 0.05. The multi-quantum well active region is the region where electrons and holes recombine. A reasonable structural design can significantly increase the overlap degree of the electron and hole wave functions, thereby improving the light-emitting efficiency of the LED device.

[0053] Step S208: Grow an electron blocking layer with a growth thickness of 10 nm to 40 nm.

[0054] Among them, the electron blocking layer is an Al x In y Ga 1-x-y N layer, the growth temperature is 900 °C to 1000 °C, the growth pressure is 100 torr to 300 torr, where 0.005 < x < 0.1 for the Al component and 0.01 < y < 0.2 for the In component concentration..

[0055] Specifically, the electron blocking layer is an AlInGaN with a thickness of 15 nm, where the Al component concentration gradually changes from 0.01 to 0.05 along the growth direction of the epitaxial layer, the In component concentration is 0.01, the growth temperature is 965 °C, and the growth pressure is 200 torr. It can effectively limit electron overflow and reduce the hole blocking, improving the injection efficiency of holes into the quantum well.

[0056] Step S209: Grow a P-type GaN layer with a thickness of 10 nm to 50 nm.

[0057] The growth temperature of the p-type GaN layer is 900℃~1050℃, the growth pressure is 100 torr~600 torr, and the Mg doping concentration is 1E19 atoms / cm³. 3 ~1E21 atoms / cm 3 .

[0058] Specifically, the p-type GaN layer was grown at a temperature of 985℃, a thickness of 15nm, a growth pressure of 200 torr, and a Mg doping concentration of 2E+20 atoms / cm². 3 Excessive Mg doping concentration can damage crystal quality, while low doping concentration can affect hole concentration. Meanwhile, for LED structures containing V-shaped pits, the higher growth temperature of the P-type GaN layer is beneficial for merging the V-shaped pits, resulting in a smooth LED epitaxial wafer.

[0059] The chip prepared in this embodiment showed a 1% improvement in photoelectric efficiency when tested at 120mA / 60mA current, and good performance in other electrical aspects.

[0060] In summary, the epitaxial growth method for LED epitaxial wafers in this embodiment of the invention involves setting a three-dimensional nucleation layer in a GaN-based LED epitaxial wafer. The three-dimensional nucleation layer includes a first three-dimensional nucleation layer, a three-dimensional nucleation temperature transition layer, and a second three-dimensional nucleation layer stacked sequentially. The temperature during the growth of the first three-dimensional nucleation layer is lower than the temperature during the growth of the three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer. The temperature during the growth of the three-dimensional nucleation temperature transition layer gradually increases. Specifically, the lower temperature of the first three-dimensional nucleation layer can effectively reduce the nucleus density. The three-dimensional nucleation temperature transition layer allows the longitudinal growth of the nuclei to be higher than the lateral growth, developing into GaN islands. The higher growth temperature of the second three-dimensional nucleation layer intensifies the lateral growth of the GaN islands, gradually causing the GaN islands to fuse, reducing the nucleus density, decreasing the generation of line defects, and improving the crystal quality of GaN.

[0061] Example 3

[0062] In this embodiment, a buffer layer, a three-dimensional nucleation layer, an undoped GaN layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate. The thickness of the three-dimensional nucleation layer is 2.5 μm. The thickness ratio of the first three-dimensional nucleation layer, the three-dimensional nucleation temperature transition layer, and the second three-dimensional nucleation layer is 1:1:1.5. During the growth of the three-dimensional nucleation layer, the growth pressure is 150 torr. During the growth of the first three-dimensional nucleation layer, the growth temperature is controlled at 1050°C. During the growth of the three-dimensional nucleation temperature transition layer, the growth temperature is gradually increased by 30°C from 1050°C to 1080°C. During the growth of the second three-dimensional nucleation layer, the growth temperature is controlled at 1080°C. Simultaneously, during the growth of the first three-dimensional nucleation layer, the Ga source flow rate is gradually increased from 600 slm to 1000 slm. The three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown at a Ga source flow rate of 1000 slm.

[0063] The chip prepared in this embodiment showed a 0.8% improvement in photoelectric efficiency when tested at 120mA / 60mA current, and good performance in other electrical aspects.

[0064] Example 4

[0065] In this embodiment, a buffer layer, a three-dimensional nucleation layer, an undoped GaN layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate. The thickness of the three-dimensional nucleation layer is 2.5 μm. The thickness ratio of the first three-dimensional nucleation layer, the three-dimensional nucleation temperature transition layer, and the second three-dimensional nucleation layer is 1:1:1. During the growth of the three-dimensional nucleation layer, the growth pressure is 150 torr. During the growth of the first three-dimensional nucleation layer, the growth temperature is controlled at 1060°C. During the growth of the three-dimensional nucleation temperature transition layer, the growth temperature is gradually increased by 20°C from 1060°C to 1080°C. During the growth of the second three-dimensional nucleation layer, the growth temperature is controlled at 1080°C. Simultaneously, during the growth of the first three-dimensional nucleation layer, the Ga source flow rate is gradually increased from 600 slm to 1000 slm. The three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown at a Ga source flow rate of 1000 slm.

[0066] The chip prepared in this embodiment showed a 0.8% improvement in photoelectric efficiency when tested at 120mA / 60mA current, and good performance in other electrical aspects.

[0067] Example 5

[0068] In this embodiment, a buffer layer, a three-dimensional nucleation layer, an undoped GaN layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate. The thickness of the three-dimensional nucleation layer is 2.5 μm. The thickness ratio of the first three-dimensional nucleation layer, the three-dimensional nucleation temperature transition layer, and the second three-dimensional nucleation layer is 1:1:1. During the growth of the three-dimensional nucleation layer, the growth pressure is 250 torr. During the growth of the first three-dimensional nucleation layer, the growth temperature is controlled at 1060°C. During the growth of the three-dimensional nucleation temperature transition layer, the growth temperature is gradually increased by 20°C from 1060°C to 1080°C. During the growth of the second three-dimensional nucleation layer, the growth temperature is controlled at 1080°C. Simultaneously, during the growth of the first three-dimensional nucleation layer, the Ga source flow rate is gradually increased from 600 slm to 1000 slm. The three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown at a Ga source flow rate of 1000 slm.

[0069] The chip prepared in this embodiment showed a 0.5% improvement in photoelectric efficiency when tested at 120mA / 60mA current, and good performance in other electrical aspects.

[0070] Example 6

[0071] In this embodiment, a buffer layer, a three-dimensional nucleation layer, an undoped GaN layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate. The thickness of the three-dimensional nucleation layer is 2.5 μm. The thickness ratio of the first three-dimensional nucleation layer, the three-dimensional nucleation temperature transition layer, and the second three-dimensional nucleation layer is 1:1:1. During the growth of the three-dimensional nucleation layer, the growth pressure is 100 torr. During the growth of the first three-dimensional nucleation layer, the growth temperature is controlled at 1020°C. During the growth of the three-dimensional nucleation temperature transition layer, the growth temperature is gradually increased by 50°C from 1020°C to 1070°C. During the growth of the second three-dimensional nucleation layer, the growth temperature is controlled at 1070°C. Simultaneously, during the growth of the first three-dimensional nucleation layer, the Ga source flow rate is gradually increased from 600 slm to 1000 slm. The three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown at a Ga source flow rate of 1000 slm.

[0072] The chip prepared in this embodiment showed a 1.5% improvement in photoelectric efficiency when tested at 120mA / 60mA current, and good performance in other electrical aspects.

[0073] Example 7

[0074] In this embodiment, a buffer layer, a three-dimensional nucleation layer, an undoped GaN layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate. The thickness of the three-dimensional nucleation layer is 2.5 μm. The thickness ratio of the first three-dimensional nucleation layer, the three-dimensional nucleation temperature transition layer, and the second three-dimensional nucleation layer is 1:1:1. During the growth of the three-dimensional nucleation layer, the growth pressure is 100 torr. During the growth of the first three-dimensional nucleation layer, the growth temperature is controlled at 950°C. During the growth of the three-dimensional nucleation temperature transition layer, the growth temperature is gradually increased by 50°C from 950°C to 1000°C. During the growth of the second three-dimensional nucleation layer, the growth temperature is controlled at 1000°C. Simultaneously, during the growth of the first three-dimensional nucleation layer, the Ga source flow rate is gradually increased from 600 slm to 1000 slm. The three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown at a Ga source flow rate of 1000 slm.

[0075] The chip prepared in this embodiment showed a 1.7% improvement in photoelectric efficiency when tested at 120mA / 60mA current, and good performance in other electrical aspects.

[0076] The photoelectric efficiency of existing GaN-based LED chips is compared with that of the GaN-based LED chip proposed in this invention, as shown in Table 1:

[0077] Table 1

[0078]

[0079] As can be seen from the table, the GaN-based LED chip proposed in this invention has a significantly improved photoelectric efficiency compared with existing GaN-based LED chips.

[0080] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A GaN-based LED epitaxial wafer, characterized in that, The material includes a three-dimensional nucleation layer, which comprises a first three-dimensional nucleation layer, a three-dimensional nucleation temperature transition layer, and a second three-dimensional nucleation layer stacked sequentially. The temperature at which the first three-dimensional nucleation layer is grown is lower than the temperature at which the three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown. The temperature at which the first three-dimensional nucleation layer and the second three-dimensional nucleation layer are grown is constant, while the temperature at which the three-dimensional nucleation temperature transition layer is grown gradually increases. A Ga source is introduced during the growth of the three-dimensional nucleation layer, wherein the Ga source flow rate is gradually increased during the growth of the first three-dimensional nucleation layer.

2. The GaN-based LED epitaxial wafer according to claim 1, characterized in that, The thickness ratio of the first three-dimensional nucleation layer, the three-dimensional nucleation temperature transition layer, and the second three-dimensional nucleation layer is 1~2:1~2:1~3.

3. The GaN-based LED epitaxial wafer according to claim 1, characterized in that, The thickness of the three-dimensional nucleation layer is 0.5 μm to 5 μm.

4. A method for epitaxial growth of LED epitaxial wafers, characterized in that, The epitaxial growth method for preparing the GaN-based LED epitaxial wafer according to any one of claims 1-3 includes: Provide a substrate required for growth; A buffer layer, a three-dimensional nucleation layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially stacked on the substrate. During the growth of the three-dimensional nucleation layer, a first three-dimensional nucleation layer, a three-dimensional nucleation temperature transition layer, and a second three-dimensional nucleation layer are sequentially deposited on the buffer layer. The temperature at which the first three-dimensional nucleation layer is grown is lower than the temperature at which the three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown. The temperature at which the first three-dimensional nucleation layer and the second three-dimensional nucleation layer are grown is constant, while the temperature at which the three-dimensional nucleation temperature transition layer is grown gradually increases.

5. The epitaxial growth method for LED epitaxial wafers according to claim 4, characterized in that, The growth temperature of the three-dimensional nucleation layer is 950℃~1080℃, and the growth pressure is 50 torr~500 torr.

6. The epitaxial growth method for LED epitaxial wafers according to claim 4, characterized in that, During the growth of the first three-dimensional nucleation layer, the growth temperature is controlled at a first temperature. During the growth of the three-dimensional nucleation temperature transition layer, the growth temperature is controlled to gradually increase from the first temperature to 20°C~50°C, and then to a second temperature. During the growth of the second three-dimensional nucleation layer, the growth temperature is controlled at the second temperature.

7. The epitaxial growth method for LED epitaxial wafers according to claim 4, characterized in that, During the growth of the first three-dimensional nucleation layer, the Ga source flow rate is gradually increased to a first flow rate, and the three-dimensional nucleation temperature transition layer and the second three-dimensional nucleation layer are grown at the first flow rate.

8. The epitaxial growth method for LED epitaxial wafers according to claim 7, characterized in that, The Ga source flow rate is 600 slm to 1200 slm.

9. An LED chip, characterized in that, Includes the GaN-based LED epitaxial wafer as described in any one of claims 1-3.

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